1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * PWM controller driver for Amlogic Meson SoCs.
4 *
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
7 * two periods (low and high). The counter then has to be set to switch after
8 * N cycles for the first half period.
9 * The hardware has no "polarity" setting. This driver reverses the period
10 * cycles (the low length is inverted with the high length) for
11 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12 * from the hardware.
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
16 *
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
18 * controller starting on page 543:
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
20 * An updated version of this IP block is found in S922X (G12B) SoCs. The
21 * datasheet contains the description for this IP block revision starting at
22 * page 1084:
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
24 *
25 * Copyright (c) 2016 BayLibre, SAS.
26 * Author: Neil Armstrong <narmstrong@baylibre.com>
27 * Copyright (C) 2014 Amlogic, Inc.
28 */
29
30 #include <linux/bitfield.h>
31 #include <linux/bits.h>
32 #include <linux/clk.h>
33 #include <linux/clk-provider.h>
34 #include <linux/err.h>
35 #include <linux/io.h>
36 #include <linux/kernel.h>
37 #include <linux/math64.h>
38 #include <linux/module.h>
39 #include <linux/of.h>
40 #include <linux/platform_device.h>
41 #include <linux/pwm.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44
45 #define REG_PWM_A 0x0
46 #define REG_PWM_B 0x4
47 #define PWM_LOW_MASK GENMASK(15, 0)
48 #define PWM_HIGH_MASK GENMASK(31, 16)
49
50 #define REG_MISC_AB 0x8
51 #define MISC_B_CLK_EN_SHIFT 23
52 #define MISC_A_CLK_EN_SHIFT 15
53 #define MISC_CLK_DIV_WIDTH 7
54 #define MISC_B_CLK_DIV_SHIFT 16
55 #define MISC_A_CLK_DIV_SHIFT 8
56 #define MISC_B_CLK_SEL_SHIFT 6
57 #define MISC_A_CLK_SEL_SHIFT 4
58 #define MISC_CLK_SEL_MASK 0x3
59 #define MISC_B_EN BIT(1)
60 #define MISC_A_EN BIT(0)
61
62 #define MESON_NUM_PWMS 2
63 #define MESON_MAX_MUX_PARENTS 4
64
65 static struct meson_pwm_channel_data {
66 u8 reg_offset;
67 u8 clk_sel_shift;
68 u8 clk_div_shift;
69 u8 clk_en_shift;
70 u32 pwm_en_mask;
71 } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72 {
73 .reg_offset = REG_PWM_A,
74 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
75 .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
76 .clk_en_shift = MISC_A_CLK_EN_SHIFT,
77 .pwm_en_mask = MISC_A_EN,
78 },
79 {
80 .reg_offset = REG_PWM_B,
81 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
82 .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
83 .clk_en_shift = MISC_B_CLK_EN_SHIFT,
84 .pwm_en_mask = MISC_B_EN,
85 }
86 };
87
88 struct meson_pwm_channel {
89 unsigned long rate;
90 unsigned int hi;
91 unsigned int lo;
92
93 struct clk_mux mux;
94 struct clk_divider div;
95 struct clk_gate gate;
96 struct clk *clk;
97 };
98
99 struct meson_pwm_data {
100 const char * const *parent_names;
101 unsigned int num_parents;
102 };
103
104 struct meson_pwm {
105 struct pwm_chip chip;
106 const struct meson_pwm_data *data;
107 struct meson_pwm_channel channels[MESON_NUM_PWMS];
108 void __iomem *base;
109 /*
110 * Protects register (write) access to the REG_MISC_AB register
111 * that is shared between the two PWMs.
112 */
113 spinlock_t lock;
114 };
115
to_meson_pwm(struct pwm_chip * chip)116 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
117 {
118 return container_of(chip, struct meson_pwm, chip);
119 }
120
meson_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)121 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
122 {
123 struct meson_pwm *meson = to_meson_pwm(chip);
124 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
125 struct device *dev = chip->dev;
126 int err;
127
128 err = clk_prepare_enable(channel->clk);
129 if (err < 0) {
130 dev_err(dev, "failed to enable clock %s: %d\n",
131 __clk_get_name(channel->clk), err);
132 return err;
133 }
134
135 return 0;
136 }
137
meson_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)138 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
139 {
140 struct meson_pwm *meson = to_meson_pwm(chip);
141 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
142
143 clk_disable_unprepare(channel->clk);
144 }
145
meson_pwm_calc(struct meson_pwm * meson,struct pwm_device * pwm,const struct pwm_state * state)146 static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
147 const struct pwm_state *state)
148 {
149 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
150 unsigned int cnt, duty_cnt;
151 unsigned long fin_freq;
152 u64 duty, period, freq;
153
154 duty = state->duty_cycle;
155 period = state->period;
156
157 /*
158 * Note this is wrong. The result is an output wave that isn't really
159 * inverted and so is wrongly identified by .get_state as normal.
160 * Fixing this needs some care however as some machines might rely on
161 * this.
162 */
163 if (state->polarity == PWM_POLARITY_INVERSED)
164 duty = period - duty;
165
166 freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period);
167 if (freq > ULONG_MAX)
168 freq = ULONG_MAX;
169
170 fin_freq = clk_round_rate(channel->clk, freq);
171 if (fin_freq == 0) {
172 dev_err(meson->chip.dev, "invalid source clock frequency\n");
173 return -EINVAL;
174 }
175
176 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
177
178 cnt = div_u64(fin_freq * period, NSEC_PER_SEC);
179 if (cnt > 0xffff) {
180 dev_err(meson->chip.dev, "unable to get period cnt\n");
181 return -EINVAL;
182 }
183
184 dev_dbg(meson->chip.dev, "period=%llu cnt=%u\n", period, cnt);
185
186 if (duty == period) {
187 channel->hi = cnt;
188 channel->lo = 0;
189 } else if (duty == 0) {
190 channel->hi = 0;
191 channel->lo = cnt;
192 } else {
193 duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC);
194
195 dev_dbg(meson->chip.dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
196
197 channel->hi = duty_cnt;
198 channel->lo = cnt - duty_cnt;
199 }
200
201 channel->rate = fin_freq;
202
203 return 0;
204 }
205
meson_pwm_enable(struct meson_pwm * meson,struct pwm_device * pwm)206 static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
207 {
208 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
209 struct meson_pwm_channel_data *channel_data;
210 unsigned long flags;
211 u32 value;
212 int err;
213
214 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
215
216 err = clk_set_rate(channel->clk, channel->rate);
217 if (err)
218 dev_err(meson->chip.dev, "setting clock rate failed\n");
219
220 spin_lock_irqsave(&meson->lock, flags);
221
222 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
223 FIELD_PREP(PWM_LOW_MASK, channel->lo);
224 writel(value, meson->base + channel_data->reg_offset);
225
226 value = readl(meson->base + REG_MISC_AB);
227 value |= channel_data->pwm_en_mask;
228 writel(value, meson->base + REG_MISC_AB);
229
230 spin_unlock_irqrestore(&meson->lock, flags);
231 }
232
meson_pwm_disable(struct meson_pwm * meson,struct pwm_device * pwm)233 static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
234 {
235 unsigned long flags;
236 u32 value;
237
238 spin_lock_irqsave(&meson->lock, flags);
239
240 value = readl(meson->base + REG_MISC_AB);
241 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
242 writel(value, meson->base + REG_MISC_AB);
243
244 spin_unlock_irqrestore(&meson->lock, flags);
245 }
246
meson_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)247 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
248 const struct pwm_state *state)
249 {
250 struct meson_pwm *meson = to_meson_pwm(chip);
251 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
252 int err = 0;
253
254 if (!state->enabled) {
255 if (state->polarity == PWM_POLARITY_INVERSED) {
256 /*
257 * This IP block revision doesn't have an "always high"
258 * setting which we can use for "inverted disabled".
259 * Instead we achieve this by setting mux parent with
260 * highest rate and minimum divider value, resulting
261 * in the shortest possible duration for one "count"
262 * and "period == duty_cycle". This results in a signal
263 * which is LOW for one "count", while being HIGH for
264 * the rest of the (so the signal is HIGH for slightly
265 * less than 100% of the period, but this is the best
266 * we can achieve).
267 */
268 channel->rate = ULONG_MAX;
269 channel->hi = ~0;
270 channel->lo = 0;
271
272 meson_pwm_enable(meson, pwm);
273 } else {
274 meson_pwm_disable(meson, pwm);
275 }
276 } else {
277 err = meson_pwm_calc(meson, pwm, state);
278 if (err < 0)
279 return err;
280
281 meson_pwm_enable(meson, pwm);
282 }
283
284 return 0;
285 }
286
meson_pwm_cnt_to_ns(struct pwm_chip * chip,struct pwm_device * pwm,u32 cnt)287 static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm,
288 u32 cnt)
289 {
290 struct meson_pwm *meson = to_meson_pwm(chip);
291 struct meson_pwm_channel *channel;
292 unsigned long fin_freq;
293
294 /* to_meson_pwm() can only be used after .get_state() is called */
295 channel = &meson->channels[pwm->hwpwm];
296
297 fin_freq = clk_get_rate(channel->clk);
298 if (fin_freq == 0)
299 return 0;
300
301 return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq);
302 }
303
meson_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)304 static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
305 struct pwm_state *state)
306 {
307 struct meson_pwm *meson = to_meson_pwm(chip);
308 struct meson_pwm_channel_data *channel_data;
309 struct meson_pwm_channel *channel;
310 u32 value;
311
312 if (!state)
313 return 0;
314
315 channel = &meson->channels[pwm->hwpwm];
316 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
317
318 value = readl(meson->base + REG_MISC_AB);
319 state->enabled = value & channel_data->pwm_en_mask;
320
321 value = readl(meson->base + channel_data->reg_offset);
322 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
323 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
324
325 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi);
326 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
327
328 state->polarity = PWM_POLARITY_NORMAL;
329
330 return 0;
331 }
332
333 static const struct pwm_ops meson_pwm_ops = {
334 .request = meson_pwm_request,
335 .free = meson_pwm_free,
336 .apply = meson_pwm_apply,
337 .get_state = meson_pwm_get_state,
338 .owner = THIS_MODULE,
339 };
340
341 static const char * const pwm_meson8b_parent_names[] = {
342 "xtal", NULL, "fclk_div4", "fclk_div3"
343 };
344
345 static const struct meson_pwm_data pwm_meson8b_data = {
346 .parent_names = pwm_meson8b_parent_names,
347 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
348 };
349
350 /*
351 * Only the 2 first inputs of the GXBB AO PWMs are valid
352 * The last 2 are grounded
353 */
354 static const char * const pwm_gxbb_ao_parent_names[] = {
355 "xtal", "clk81"
356 };
357
358 static const struct meson_pwm_data pwm_gxbb_ao_data = {
359 .parent_names = pwm_gxbb_ao_parent_names,
360 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
361 };
362
363 static const char * const pwm_axg_ee_parent_names[] = {
364 "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
365 };
366
367 static const struct meson_pwm_data pwm_axg_ee_data = {
368 .parent_names = pwm_axg_ee_parent_names,
369 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
370 };
371
372 static const char * const pwm_axg_ao_parent_names[] = {
373 "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5"
374 };
375
376 static const struct meson_pwm_data pwm_axg_ao_data = {
377 .parent_names = pwm_axg_ao_parent_names,
378 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
379 };
380
381 static const char * const pwm_g12a_ao_ab_parent_names[] = {
382 "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5"
383 };
384
385 static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
386 .parent_names = pwm_g12a_ao_ab_parent_names,
387 .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
388 };
389
390 static const char * const pwm_g12a_ao_cd_parent_names[] = {
391 "xtal", "g12a_ao_clk81",
392 };
393
394 static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
395 .parent_names = pwm_g12a_ao_cd_parent_names,
396 .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
397 };
398
399 static const struct of_device_id meson_pwm_matches[] = {
400 {
401 .compatible = "amlogic,meson8b-pwm",
402 .data = &pwm_meson8b_data
403 },
404 {
405 .compatible = "amlogic,meson-gxbb-pwm",
406 .data = &pwm_meson8b_data
407 },
408 {
409 .compatible = "amlogic,meson-gxbb-ao-pwm",
410 .data = &pwm_gxbb_ao_data
411 },
412 {
413 .compatible = "amlogic,meson-axg-ee-pwm",
414 .data = &pwm_axg_ee_data
415 },
416 {
417 .compatible = "amlogic,meson-axg-ao-pwm",
418 .data = &pwm_axg_ao_data
419 },
420 {
421 .compatible = "amlogic,meson-g12a-ee-pwm",
422 .data = &pwm_meson8b_data
423 },
424 {
425 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
426 .data = &pwm_g12a_ao_ab_data
427 },
428 {
429 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
430 .data = &pwm_g12a_ao_cd_data
431 },
432 {},
433 };
434 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
435
meson_pwm_init_channels(struct meson_pwm * meson)436 static int meson_pwm_init_channels(struct meson_pwm *meson)
437 {
438 struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {};
439 struct device *dev = meson->chip.dev;
440 unsigned int i;
441 char name[255];
442 int err;
443
444 for (i = 0; i < meson->data->num_parents; i++) {
445 mux_parent_data[i].index = -1;
446 mux_parent_data[i].name = meson->data->parent_names[i];
447 }
448
449 for (i = 0; i < meson->chip.npwm; i++) {
450 struct meson_pwm_channel *channel = &meson->channels[i];
451 struct clk_parent_data div_parent = {}, gate_parent = {};
452 struct clk_init_data init = {};
453
454 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
455
456 init.name = name;
457 init.ops = &clk_mux_ops;
458 init.flags = 0;
459 init.parent_data = mux_parent_data;
460 init.num_parents = meson->data->num_parents;
461
462 channel->mux.reg = meson->base + REG_MISC_AB;
463 channel->mux.shift =
464 meson_pwm_per_channel_data[i].clk_sel_shift;
465 channel->mux.mask = MISC_CLK_SEL_MASK;
466 channel->mux.flags = 0;
467 channel->mux.lock = &meson->lock;
468 channel->mux.table = NULL;
469 channel->mux.hw.init = &init;
470
471 err = devm_clk_hw_register(dev, &channel->mux.hw);
472 if (err) {
473 dev_err(dev, "failed to register %s: %d\n", name, err);
474 return err;
475 }
476
477 snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i);
478
479 init.name = name;
480 init.ops = &clk_divider_ops;
481 init.flags = CLK_SET_RATE_PARENT;
482 div_parent.index = -1;
483 div_parent.hw = &channel->mux.hw;
484 init.parent_data = &div_parent;
485 init.num_parents = 1;
486
487 channel->div.reg = meson->base + REG_MISC_AB;
488 channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift;
489 channel->div.width = MISC_CLK_DIV_WIDTH;
490 channel->div.hw.init = &init;
491 channel->div.flags = 0;
492 channel->div.lock = &meson->lock;
493
494 err = devm_clk_hw_register(dev, &channel->div.hw);
495 if (err) {
496 dev_err(dev, "failed to register %s: %d\n", name, err);
497 return err;
498 }
499
500 snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i);
501
502 init.name = name;
503 init.ops = &clk_gate_ops;
504 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
505 gate_parent.index = -1;
506 gate_parent.hw = &channel->div.hw;
507 init.parent_data = &gate_parent;
508 init.num_parents = 1;
509
510 channel->gate.reg = meson->base + REG_MISC_AB;
511 channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift;
512 channel->gate.hw.init = &init;
513 channel->gate.flags = 0;
514 channel->gate.lock = &meson->lock;
515
516 err = devm_clk_hw_register(dev, &channel->gate.hw);
517 if (err) {
518 dev_err(dev, "failed to register %s: %d\n", name, err);
519 return err;
520 }
521
522 channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL);
523 if (IS_ERR(channel->clk)) {
524 err = PTR_ERR(channel->clk);
525 dev_err(dev, "failed to register %s: %d\n", name, err);
526 return err;
527 }
528 }
529
530 return 0;
531 }
532
meson_pwm_probe(struct platform_device * pdev)533 static int meson_pwm_probe(struct platform_device *pdev)
534 {
535 struct meson_pwm *meson;
536 int err;
537
538 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
539 if (!meson)
540 return -ENOMEM;
541
542 meson->base = devm_platform_ioremap_resource(pdev, 0);
543 if (IS_ERR(meson->base))
544 return PTR_ERR(meson->base);
545
546 spin_lock_init(&meson->lock);
547 meson->chip.dev = &pdev->dev;
548 meson->chip.ops = &meson_pwm_ops;
549 meson->chip.npwm = MESON_NUM_PWMS;
550
551 meson->data = of_device_get_match_data(&pdev->dev);
552
553 err = meson_pwm_init_channels(meson);
554 if (err < 0)
555 return err;
556
557 err = devm_pwmchip_add(&pdev->dev, &meson->chip);
558 if (err < 0) {
559 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
560 return err;
561 }
562
563 return 0;
564 }
565
566 static struct platform_driver meson_pwm_driver = {
567 .driver = {
568 .name = "meson-pwm",
569 .of_match_table = meson_pwm_matches,
570 },
571 .probe = meson_pwm_probe,
572 };
573 module_platform_driver(meson_pwm_driver);
574
575 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
576 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
577 MODULE_LICENSE("Dual BSD/GPL");
578