xref: /openbmc/qemu/include/hw/pci/pci_bridge.h (revision 4565917b)
1 /*
2  * QEMU PCI bridge
3  *
4  * Copyright (c) 2004 Fabrice Bellard
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  *
20  * split out pci bus specific stuff from pci.[hc] to pci_bridge.[hc]
21  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
22  *                    VA Linux Systems Japan K.K.
23  *
24  */
25 
26 #ifndef QEMU_PCI_BRIDGE_H
27 #define QEMU_PCI_BRIDGE_H
28 
29 #include "hw/pci/pci_device.h"
30 #include "hw/pci/pci_bus.h"
31 #include "hw/cxl/cxl.h"
32 #include "qom/object.h"
33 
34 typedef struct PCIBridgeWindows PCIBridgeWindows;
35 
36 /*
37  * Aliases for each of the address space windows that the bridge
38  * can forward. Mapped into the bridge's parent's address space,
39  * as subregions.
40  */
41 struct PCIBridgeWindows {
42     MemoryRegion alias_pref_mem;
43     MemoryRegion alias_mem;
44     MemoryRegion alias_io;
45     /*
46      * When bridge control VGA forwarding is enabled, bridges will
47      * provide positive decode on the PCI VGA defined I/O port and
48      * MMIO ranges.  When enabled forwarding is only qualified on the
49      * I/O and memory enable bits in the bridge command register.
50      */
51     MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS];
52 };
53 
54 #define TYPE_PCI_BRIDGE "base-pci-bridge"
55 OBJECT_DECLARE_SIMPLE_TYPE(PCIBridge, PCI_BRIDGE)
56 #define IS_PCI_BRIDGE(dev) object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)
57 
58 struct PCIBridge {
59     /*< private >*/
60     PCIDevice parent_obj;
61     /*< public >*/
62 
63     /* private member */
64     PCIBus sec_bus;
65     /*
66      * Memory regions for the bridge's address spaces.  These regions are not
67      * directly added to system_memory/system_io or its descendants.
68      * Bridge's secondary bus points to these, so that devices
69      * under the bridge see these regions as its address spaces.
70      * The regions are as large as the entire address space -
71      * they don't take into account any windows.
72      */
73     MemoryRegion address_space_mem;
74     MemoryRegion address_space_io;
75 
76     PCIBridgeWindows windows;
77 
78     pci_map_irq_fn map_irq;
79     const char *bus_name;
80 
81     /* SLT is RO for PCIE to PCIE bridges, but old QEMU versions had it RW */
82     bool pcie_writeable_slt_bug;
83 };
84 
85 #define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr"
86 #define PCI_BRIDGE_DEV_PROP_MSI        "msi"
87 #define PCI_BRIDGE_DEV_PROP_SHPC       "shpc"
88 typedef struct CXLHost CXLHost;
89 
90 typedef struct PXBDev {
91     /*< private >*/
92     PCIDevice parent_obj;
93     /*< public >*/
94 
95     uint8_t bus_nr;
96     uint16_t numa_node;
97     bool bypass_iommu;
98 } PXBDev;
99 
100 typedef struct PXBPCIEDev {
101     /*< private >*/
102     PXBDev parent_obj;
103 } PXBPCIEDev;
104 
105 #define TYPE_PXB_DEV "pxb"
106 OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV)
107 
108 typedef struct PXBCXLDev {
109     /*< private >*/
110     PXBPCIEDev parent_obj;
111     /*< public >*/
112 
113     bool hdm_for_passthrough;
114     CXLHost *cxl_host_bridge; /* Pointer to a CXLHost */
115 } PXBCXLDev;
116 
117 #define TYPE_PXB_CXL_DEV "pxb-cxl"
118 OBJECT_DECLARE_SIMPLE_TYPE(PXBCXLDev, PXB_CXL_DEV)
119 
120 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
121                           uint16_t svid, uint16_t ssid,
122                           Error **errp);
123 
124 PCIDevice *pci_bridge_get_device(PCIBus *bus);
125 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br);
126 
127 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type);
128 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type);
129 
130 void pci_bridge_update_mappings(PCIBridge *br);
131 void pci_bridge_write_config(PCIDevice *d,
132                              uint32_t address, uint32_t val, int len);
133 void pci_bridge_disable_base_limit(PCIDevice *dev);
134 void pci_bridge_reset(DeviceState *qdev);
135 
136 void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename);
137 void pci_bridge_exitfn(PCIDevice *pci_dev);
138 
139 void pci_bridge_dev_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
140                             Error **errp);
141 void pci_bridge_dev_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
142                               Error **errp);
143 void pci_bridge_dev_unplug_request_cb(HotplugHandler *hotplug_dev,
144                                       DeviceState *dev, Error **errp);
145 
146 /*
147  * before qdev initialization(qdev_init()), this function sets bus_name and
148  * map_irq callback which are necessary for pci_bridge_initfn() to
149  * initialize bus.
150  */
151 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
152                         pci_map_irq_fn map_irq);
153 
154 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
155 #define  PCI_BRIDGE_CTL_VGA_16BIT       0x10    /* VGA 16-bit decode */
156 #define  PCI_BRIDGE_CTL_DISCARD         0x100   /* Primary discard timer */
157 #define  PCI_BRIDGE_CTL_SEC_DISCARD     0x200   /* Secondary discard timer */
158 #define  PCI_BRIDGE_CTL_DISCARD_STATUS  0x400   /* Discard timer status */
159 #define  PCI_BRIDGE_CTL_DISCARD_SERR    0x800   /* Discard timer SERR# enable */
160 
161 typedef struct PCIBridgeQemuCap {
162     uint8_t id;     /* Standard PCI capability header field */
163     uint8_t next;   /* Standard PCI capability header field */
164     uint8_t len;    /* Standard PCI vendor-specific capability header field */
165     uint8_t type;   /* Red Hat vendor-specific capability type.
166                        Types are defined with REDHAT_PCI_CAP_ prefix */
167 
168     uint32_t bus_res;   /* Minimum number of buses to reserve */
169     uint64_t io;        /* IO space to reserve */
170     uint32_t mem;       /* Non-prefetchable memory to reserve */
171     /* At most one of the following two fields may be set to a value
172      * different from -1 */
173     uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) */
174     uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */
175 } PCIBridgeQemuCap;
176 
177 #define REDHAT_PCI_CAP_TYPE_OFFSET      3
178 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
179 
180 /*
181  * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a
182  * capability in PCI configuration space to reserve on firmware init.
183  */
184 typedef struct PCIResReserve {
185     uint32_t bus;
186     uint64_t io;
187     uint64_t mem_non_pref;
188     uint64_t mem_pref_32;
189     uint64_t mem_pref_64;
190 } PCIResReserve;
191 
192 #define REDHAT_PCI_CAP_RES_RESERVE_BUS_RES     4
193 #define REDHAT_PCI_CAP_RES_RESERVE_IO          8
194 #define REDHAT_PCI_CAP_RES_RESERVE_MEM         16
195 #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_32 20
196 #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_64 24
197 #define REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE    32
198 
199 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
200                                PCIResReserve res_reserve, Error **errp);
201 
202 #endif /* QEMU_PCI_BRIDGE_H */
203