1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for Sysam AMCORE (MCF5307 based) board
4 *
5 * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
6 *
7 * This file copies memory testdram() from sandburst/common/sb_common.c
8 */
9
10 #include <common.h>
11 #include <asm/immap.h>
12 #include <asm/io.h>
13 #include <dm.h>
14 #include <dm/platform_data/serial_coldfire.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
init_lcd(void)18 void init_lcd(void)
19 {
20 /* setup for possible K0108 lcd connected on the parallel port */
21 sim_t *sim = (sim_t *)(MMAP_SIM);
22
23 out_be16(&sim->par, 0x300);
24
25 gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
26
27 out_be16(&gpio->paddr, 0xfcff);
28 out_be16(&gpio->padat, 0x0c00);
29 }
30
checkboard(void)31 int checkboard(void)
32 {
33 puts("Board: ");
34 puts("AMCORE v.001(alpha)\n");
35
36 init_lcd();
37
38 return 0;
39 }
40
41 /*
42 * in dram_init we are here executing from flash
43 * case 1:
44 * is with no ACR/flash cache enabled
45 * nop = 40ns (scope measured)
46 */
fudelay(int usec)47 void fudelay(int usec)
48 {
49 while (usec--)
50 asm volatile ("nop");
51 }
52
dram_init(void)53 int dram_init(void)
54 {
55 u32 dramsize, RC;
56
57 sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
58
59 /*
60 * SDRAM MT48LC4M32B2 details
61 * Memory block 0: 16 MB of SDRAM at address $00000000
62 * Port size: 32-bit port
63 *
64 * Memory block 0 wired as follows:
65 * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
66 * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
67 *
68 * Ensure that there is a delay of at least 100 microseconds from
69 * processor reset to the following code so that the SDRAM is ready
70 * for commands.
71 */
72 fudelay(100);
73
74 /*
75 * DCR
76 * set proper RC as per specification
77 */
78 RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
79 RC = (RC * 15) >> 4;
80
81 /* 0x8000 is the faster option */
82 out_be16(&dc->dcr, 0x8200 | RC);
83
84 /*
85 * DACR0, page mode continuous, CMD on A20 0x0300
86 */
87 out_be32(&dc->dacr0, 0x00003304);
88
89 dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
90 out_be32(&dc->dmr0, dramsize|1);
91
92 /* issue a PRECHARGE ALL */
93 out_be32(&dc->dacr0, 0x0000330c);
94 out_be32((u32 *)0x00000004, 0xbeaddeed);
95 /* issue AUTOREFRESH */
96 out_be32(&dc->dacr0, 0x0000b304);
97 /* let refresh occur */
98 fudelay(1);
99
100 out_be32(&dc->dacr0, 0x0000b344);
101 out_be32((u32 *)0x00000c00, 0xbeaddeed);
102
103 gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
104 CONFIG_SYS_SDRAM_SIZE);
105
106 return 0;
107 }
108
109 static struct coldfire_serial_platdata mcf5307_serial_plat = {
110 .base = CONFIG_SYS_UART_BASE,
111 .port = 0,
112 .baudrate = CONFIG_BAUDRATE,
113 };
114
115 U_BOOT_DEVICE(coldfire_serial) = {
116 .name = "serial_coldfire",
117 .platdata = &mcf5307_serial_plat,
118 };
119