1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu_ras.h"
24 #include "amdgpu.h"
25 #include "amdgpu_mca.h"
26
27 #define smnMCMP0_STATUST0 0x03830408
28 #define smnMCMP1_STATUST0 0x03b30408
29 #define smnMCMPIO_STATUST0 0x0c930408
30
31
mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
33 void *ras_error_status)
34 {
35 amdgpu_mca_query_ras_error_count(adev,
36 smnMCMP0_STATUST0,
37 ras_error_status);
38 }
39
mca_v3_0_ras_block_match(struct amdgpu_ras_block_object * block_obj,enum amdgpu_ras_block block,uint32_t sub_block_index)40 static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
41 enum amdgpu_ras_block block, uint32_t sub_block_index)
42 {
43 if (!block_obj)
44 return -EINVAL;
45
46 if ((block_obj->ras_comm.block == block) &&
47 (block_obj->ras_comm.sub_block_index == sub_block_index)) {
48 return 0;
49 }
50
51 return -EINVAL;
52 }
53
54 static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = {
55 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
56 .query_ras_error_address = NULL,
57 };
58
59 struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
60 .ras_block = {
61 .hw_ops = &mca_v3_0_mp0_hw_ops,
62 .ras_block_match = mca_v3_0_ras_block_match,
63 },
64 };
65
mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)66 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
67 void *ras_error_status)
68 {
69 amdgpu_mca_query_ras_error_count(adev,
70 smnMCMP1_STATUST0,
71 ras_error_status);
72 }
73
74 static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
75 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
76 .query_ras_error_address = NULL,
77 };
78
79 struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
80 .ras_block = {
81 .hw_ops = &mca_v3_0_mp1_hw_ops,
82 .ras_block_match = mca_v3_0_ras_block_match,
83 },
84 };
85
mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)86 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
87 void *ras_error_status)
88 {
89 amdgpu_mca_query_ras_error_count(adev,
90 smnMCMPIO_STATUST0,
91 ras_error_status);
92 }
93
94 static const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
95 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
96 .query_ras_error_address = NULL,
97 };
98
99 struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
100 .ras_block = {
101 .hw_ops = &mca_v3_0_mpio_hw_ops,
102 .ras_block_match = mca_v3_0_ras_block_match,
103 },
104 };
105