1 /* 2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __NVKM_CLK_GK20A_H__ 25 #define __NVKM_CLK_GK20A_H__ 26 27 #define KHZ (1000) 28 #define MHZ (KHZ * 1000) 29 30 #define MASK(w) ((1 << (w)) - 1) 31 32 #define GK20A_CLK_GPC_MDIV 1000 33 34 #define SYS_GPCPLL_CFG_BASE 0x00137000 35 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 36 #define GPCPLL_CFG_ENABLE BIT(0) 37 #define GPCPLL_CFG_IDDQ BIT(1) 38 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 39 #define GPCPLL_CFG_LOCK BIT(17) 40 41 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 42 #define GPCPLL_CFG2_SETUP2_SHIFT 16 43 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 44 45 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 46 #define GPCPLL_CFG3_VCO_CTRL_SHIFT 0 47 #define GPCPLL_CFG3_VCO_CTRL_WIDTH 9 48 #define GPCPLL_CFG3_VCO_CTRL_MASK \ 49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT) 50 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 51 #define GPCPLL_CFG3_PLL_STEPB_WIDTH 8 52 53 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 54 #define GPCPLL_COEFF_M_SHIFT 0 55 #define GPCPLL_COEFF_M_WIDTH 8 56 #define GPCPLL_COEFF_N_SHIFT 8 57 #define GPCPLL_COEFF_N_WIDTH 8 58 #define GPCPLL_COEFF_N_MASK \ 59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT) 60 #define GPCPLL_COEFF_P_SHIFT 16 61 #define GPCPLL_COEFF_P_WIDTH 6 62 63 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 64 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 65 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 66 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 67 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 68 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 69 70 #define GPC_BCAST_GPCPLL_CFG_BASE 0x00132800 71 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCAST_GPCPLL_CFG_BASE + 0xa0) 72 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 73 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 74 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 75 76 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 77 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 78 79 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 80 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 81 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 82 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 83 #define GPC2CLK_OUT_VCODIV_WIDTH 6 84 #define GPC2CLK_OUT_VCODIV_SHIFT 8 85 #define GPC2CLK_OUT_VCODIV1 0 86 #define GPC2CLK_OUT_VCODIV2 2 87 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 88 GPC2CLK_OUT_VCODIV_SHIFT) 89 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 90 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 91 #define GPC2CLK_OUT_BYPDIV31 0x3c 92 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 93 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 96 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 97 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 98 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 99 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 100 101 /* All frequencies in Khz */ 102 struct gk20a_clk_pllg_params { 103 u32 min_vco, max_vco; 104 u32 min_u, max_u; 105 u32 min_m, max_m; 106 u32 min_n, max_n; 107 u32 min_pl, max_pl; 108 }; 109 110 struct gk20a_pll { 111 u32 m; 112 u32 n; 113 u32 pl; 114 }; 115 116 struct gk20a_clk { 117 struct nvkm_clk base; 118 const struct gk20a_clk_pllg_params *params; 119 struct gk20a_pll pll; 120 u32 parent_rate; 121 122 u32 (*div_to_pl)(u32); 123 u32 (*pl_to_div)(u32); 124 }; 125 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base) 126 127 u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *); 128 int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *); 129 void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *); 130 void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *); 131 132 static inline bool gk20a_pllg_is_enabled(struct gk20a_clk * clk)133 gk20a_pllg_is_enabled(struct gk20a_clk *clk) 134 { 135 struct nvkm_device *device = clk->base.subdev.device; 136 u32 val; 137 138 val = nvkm_rd32(device, GPCPLL_CFG); 139 return val & GPCPLL_CFG_ENABLE; 140 } 141 142 static inline u32 gk20a_pllg_n_lo(struct gk20a_clk * clk,struct gk20a_pll * pll)143 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll) 144 { 145 return DIV_ROUND_UP(pll->m * clk->params->min_vco, 146 clk->parent_rate / KHZ); 147 } 148 149 int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *, 150 const struct gk20a_clk_pllg_params *, struct gk20a_clk *); 151 void gk20a_clk_fini(struct nvkm_clk *); 152 int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src); 153 int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *); 154 int gk20a_clk_prog(struct nvkm_clk *); 155 void gk20a_clk_tidy(struct nvkm_clk *); 156 157 int gk20a_clk_setup_slide(struct gk20a_clk *); 158 159 #endif 160