1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qemu/timer.h"
24 #include "qemu/log.h"
25 #include "qemu/module.h"
26 #include "qemu/queue.h"
27 #include "migration/vmstate.h"
28 #include "hw/qdev-properties.h"
29 #include "trace.h"
30 #include "qapi/error.h"
31
32 #include "hcd-xhci.h"
33
34 //#define DEBUG_XHCI
35 //#define DEBUG_DATA
36
37 #ifdef DEBUG_XHCI
38 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
39 #else
40 #define DPRINTF(...) do {} while (0)
41 #endif
42 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
43 __func__, __LINE__, _msg); abort(); } while (0)
44
45 #define TRB_LINK_LIMIT 32
46 #define COMMAND_LIMIT 256
47 #define TRANSFER_LIMIT 256
48
49 #define LEN_CAP 0x40
50 #define LEN_OPER (0x400 + 0x10 * XHCI_MAXPORTS)
51 #define LEN_RUNTIME ((XHCI_MAXINTRS + 1) * 0x20)
52 #define LEN_DOORBELL ((XHCI_MAXSLOTS + 1) * 0x20)
53
54 #define OFF_OPER LEN_CAP
55 #define OFF_RUNTIME 0x1000
56 #define OFF_DOORBELL 0x2000
57
58 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
59 #error Increase OFF_RUNTIME
60 #endif
61 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
62 #error Increase OFF_DOORBELL
63 #endif
64 #if (OFF_DOORBELL + LEN_DOORBELL) > XHCI_LEN_REGS
65 # error Increase XHCI_LEN_REGS
66 #endif
67
68 /* bit definitions */
69 #define USBCMD_RS (1<<0)
70 #define USBCMD_HCRST (1<<1)
71 #define USBCMD_INTE (1<<2)
72 #define USBCMD_HSEE (1<<3)
73 #define USBCMD_LHCRST (1<<7)
74 #define USBCMD_CSS (1<<8)
75 #define USBCMD_CRS (1<<9)
76 #define USBCMD_EWE (1<<10)
77 #define USBCMD_EU3S (1<<11)
78
79 #define USBSTS_HCH (1<<0)
80 #define USBSTS_HSE (1<<2)
81 #define USBSTS_EINT (1<<3)
82 #define USBSTS_PCD (1<<4)
83 #define USBSTS_SSS (1<<8)
84 #define USBSTS_RSS (1<<9)
85 #define USBSTS_SRE (1<<10)
86 #define USBSTS_CNR (1<<11)
87 #define USBSTS_HCE (1<<12)
88
89
90 #define PORTSC_CCS (1<<0)
91 #define PORTSC_PED (1<<1)
92 #define PORTSC_OCA (1<<3)
93 #define PORTSC_PR (1<<4)
94 #define PORTSC_PLS_SHIFT 5
95 #define PORTSC_PLS_MASK 0xf
96 #define PORTSC_PP (1<<9)
97 #define PORTSC_SPEED_SHIFT 10
98 #define PORTSC_SPEED_MASK 0xf
99 #define PORTSC_SPEED_FULL (1<<10)
100 #define PORTSC_SPEED_LOW (2<<10)
101 #define PORTSC_SPEED_HIGH (3<<10)
102 #define PORTSC_SPEED_SUPER (4<<10)
103 #define PORTSC_PIC_SHIFT 14
104 #define PORTSC_PIC_MASK 0x3
105 #define PORTSC_LWS (1<<16)
106 #define PORTSC_CSC (1<<17)
107 #define PORTSC_PEC (1<<18)
108 #define PORTSC_WRC (1<<19)
109 #define PORTSC_OCC (1<<20)
110 #define PORTSC_PRC (1<<21)
111 #define PORTSC_PLC (1<<22)
112 #define PORTSC_CEC (1<<23)
113 #define PORTSC_CAS (1<<24)
114 #define PORTSC_WCE (1<<25)
115 #define PORTSC_WDE (1<<26)
116 #define PORTSC_WOE (1<<27)
117 #define PORTSC_DR (1<<30)
118 #define PORTSC_WPR (1<<31)
119
120 #define CRCR_RCS (1<<0)
121 #define CRCR_CS (1<<1)
122 #define CRCR_CA (1<<2)
123 #define CRCR_CRR (1<<3)
124
125 #define IMAN_IP (1<<0)
126 #define IMAN_IE (1<<1)
127
128 #define ERDP_EHB (1<<3)
129
130 #define TRB_SIZE 16
131 typedef struct XHCITRB {
132 uint64_t parameter;
133 uint32_t status;
134 uint32_t control;
135 dma_addr_t addr;
136 bool ccs;
137 } XHCITRB;
138
139 enum {
140 PLS_U0 = 0,
141 PLS_U1 = 1,
142 PLS_U2 = 2,
143 PLS_U3 = 3,
144 PLS_DISABLED = 4,
145 PLS_RX_DETECT = 5,
146 PLS_INACTIVE = 6,
147 PLS_POLLING = 7,
148 PLS_RECOVERY = 8,
149 PLS_HOT_RESET = 9,
150 PLS_COMPILANCE_MODE = 10,
151 PLS_TEST_MODE = 11,
152 PLS_RESUME = 15,
153 };
154
155 #define CR_LINK TR_LINK
156
157 #define TRB_C (1<<0)
158 #define TRB_TYPE_SHIFT 10
159 #define TRB_TYPE_MASK 0x3f
160 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
161
162 #define TRB_EV_ED (1<<2)
163
164 #define TRB_TR_ENT (1<<1)
165 #define TRB_TR_ISP (1<<2)
166 #define TRB_TR_NS (1<<3)
167 #define TRB_TR_CH (1<<4)
168 #define TRB_TR_IOC (1<<5)
169 #define TRB_TR_IDT (1<<6)
170 #define TRB_TR_TBC_SHIFT 7
171 #define TRB_TR_TBC_MASK 0x3
172 #define TRB_TR_BEI (1<<9)
173 #define TRB_TR_TLBPC_SHIFT 16
174 #define TRB_TR_TLBPC_MASK 0xf
175 #define TRB_TR_FRAMEID_SHIFT 20
176 #define TRB_TR_FRAMEID_MASK 0x7ff
177 #define TRB_TR_SIA (1<<31)
178
179 #define TRB_TR_DIR (1<<16)
180
181 #define TRB_CR_SLOTID_SHIFT 24
182 #define TRB_CR_SLOTID_MASK 0xff
183 #define TRB_CR_EPID_SHIFT 16
184 #define TRB_CR_EPID_MASK 0x1f
185
186 #define TRB_CR_BSR (1<<9)
187 #define TRB_CR_DC (1<<9)
188
189 #define TRB_LK_TC (1<<1)
190
191 #define TRB_INTR_SHIFT 22
192 #define TRB_INTR_MASK 0x3ff
193 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
194
195 #define EP_TYPE_MASK 0x7
196 #define EP_TYPE_SHIFT 3
197
198 #define EP_STATE_MASK 0x7
199 #define EP_DISABLED (0<<0)
200 #define EP_RUNNING (1<<0)
201 #define EP_HALTED (2<<0)
202 #define EP_STOPPED (3<<0)
203 #define EP_ERROR (4<<0)
204
205 #define SLOT_STATE_MASK 0x1f
206 #define SLOT_STATE_SHIFT 27
207 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
208 #define SLOT_ENABLED 0
209 #define SLOT_DEFAULT 1
210 #define SLOT_ADDRESSED 2
211 #define SLOT_CONFIGURED 3
212
213 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
214 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
215
216 #define get_field(data, field) \
217 (((data) >> field##_SHIFT) & field##_MASK)
218
219 #define set_field(data, newval, field) do { \
220 uint32_t val_ = *data; \
221 val_ &= ~(field##_MASK << field##_SHIFT); \
222 val_ |= ((newval) & field##_MASK) << field##_SHIFT; \
223 *data = val_; \
224 } while (0)
225
226 typedef enum EPType {
227 ET_INVALID = 0,
228 ET_ISO_OUT,
229 ET_BULK_OUT,
230 ET_INTR_OUT,
231 ET_CONTROL,
232 ET_ISO_IN,
233 ET_BULK_IN,
234 ET_INTR_IN,
235 } EPType;
236
237 typedef struct XHCITransfer {
238 XHCIEPContext *epctx;
239 USBPacket packet;
240 QEMUSGList sgl;
241 bool running_async;
242 bool running_retry;
243 bool complete;
244 bool int_req;
245 unsigned int iso_pkts;
246 unsigned int streamid;
247 bool in_xfer;
248 bool iso_xfer;
249 bool timed_xfer;
250
251 unsigned int trb_count;
252 XHCITRB *trbs;
253
254 TRBCCode status;
255
256 unsigned int pkts;
257 unsigned int pktsize;
258 unsigned int cur_pkt;
259
260 uint64_t mfindex_kick;
261
262 QTAILQ_ENTRY(XHCITransfer) next;
263 } XHCITransfer;
264
265 struct XHCIStreamContext {
266 dma_addr_t pctx;
267 unsigned int sct;
268 XHCIRing ring;
269 };
270
271 struct XHCIEPContext {
272 XHCIState *xhci;
273 unsigned int slotid;
274 unsigned int epid;
275
276 XHCIRing ring;
277 uint32_t xfer_count;
278 QTAILQ_HEAD(, XHCITransfer) transfers;
279 XHCITransfer *retry;
280 EPType type;
281 dma_addr_t pctx;
282 unsigned int max_psize;
283 uint32_t state;
284 uint32_t kick_active;
285
286 /* streams */
287 unsigned int max_pstreams;
288 bool lsa;
289 unsigned int nr_pstreams;
290 XHCIStreamContext *pstreams;
291
292 /* iso xfer scheduling */
293 unsigned int interval;
294 int64_t mfindex_last;
295 QEMUTimer *kick_timer;
296 };
297
298 typedef struct XHCIEvRingSeg {
299 uint32_t addr_low;
300 uint32_t addr_high;
301 uint32_t size;
302 uint32_t rsvd;
303 } XHCIEvRingSeg;
304
305 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
306 unsigned int epid, unsigned int streamid);
307 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
308 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
309 unsigned int epid);
310 static void xhci_xfer_report(XHCITransfer *xfer);
311 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
312 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
313 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx);
314
315 static const char *TRBType_names[] = {
316 [TRB_RESERVED] = "TRB_RESERVED",
317 [TR_NORMAL] = "TR_NORMAL",
318 [TR_SETUP] = "TR_SETUP",
319 [TR_DATA] = "TR_DATA",
320 [TR_STATUS] = "TR_STATUS",
321 [TR_ISOCH] = "TR_ISOCH",
322 [TR_LINK] = "TR_LINK",
323 [TR_EVDATA] = "TR_EVDATA",
324 [TR_NOOP] = "TR_NOOP",
325 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
326 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
327 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
328 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
329 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
330 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
331 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
332 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
333 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
334 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
335 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
336 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
337 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
338 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
339 [CR_NOOP] = "CR_NOOP",
340 [ER_TRANSFER] = "ER_TRANSFER",
341 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
342 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
343 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
344 [ER_DOORBELL] = "ER_DOORBELL",
345 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
346 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
347 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
348 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
349 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
350 };
351
352 static const char *TRBCCode_names[] = {
353 [CC_INVALID] = "CC_INVALID",
354 [CC_SUCCESS] = "CC_SUCCESS",
355 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
356 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
357 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
358 [CC_TRB_ERROR] = "CC_TRB_ERROR",
359 [CC_STALL_ERROR] = "CC_STALL_ERROR",
360 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
361 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
362 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
363 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
364 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
365 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
366 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
367 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
368 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
369 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
370 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
371 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
372 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
373 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
374 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
375 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
376 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
377 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
378 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
379 [CC_STOPPED] = "CC_STOPPED",
380 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
381 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
382 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
383 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
384 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
385 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
386 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
387 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
388 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
389 };
390
391 static const char *ep_state_names[] = {
392 [EP_DISABLED] = "disabled",
393 [EP_RUNNING] = "running",
394 [EP_HALTED] = "halted",
395 [EP_STOPPED] = "stopped",
396 [EP_ERROR] = "error",
397 };
398
lookup_name(uint32_t index,const char ** list,uint32_t llen)399 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
400 {
401 if (index >= llen || list[index] == NULL) {
402 return "???";
403 }
404 return list[index];
405 }
406
trb_name(XHCITRB * trb)407 static const char *trb_name(XHCITRB *trb)
408 {
409 return lookup_name(TRB_TYPE(*trb), TRBType_names,
410 ARRAY_SIZE(TRBType_names));
411 }
412
event_name(XHCIEvent * event)413 static const char *event_name(XHCIEvent *event)
414 {
415 return lookup_name(event->ccode, TRBCCode_names,
416 ARRAY_SIZE(TRBCCode_names));
417 }
418
ep_state_name(uint32_t state)419 static const char *ep_state_name(uint32_t state)
420 {
421 return lookup_name(state, ep_state_names,
422 ARRAY_SIZE(ep_state_names));
423 }
424
xhci_get_flag(XHCIState * xhci,enum xhci_flags bit)425 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
426 {
427 return xhci->flags & (1 << bit);
428 }
429
xhci_set_flag(XHCIState * xhci,enum xhci_flags bit)430 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
431 {
432 xhci->flags |= (1 << bit);
433 }
434
xhci_mfindex_get(XHCIState * xhci)435 static uint64_t xhci_mfindex_get(XHCIState *xhci)
436 {
437 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
438 return (now - xhci->mfindex_start) / 125000;
439 }
440
xhci_mfwrap_update(XHCIState * xhci)441 static void xhci_mfwrap_update(XHCIState *xhci)
442 {
443 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
444 uint32_t mfindex, left;
445 int64_t now;
446
447 if ((xhci->usbcmd & bits) == bits) {
448 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
449 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
450 left = 0x4000 - mfindex;
451 timer_mod(xhci->mfwrap_timer, now + left * 125000);
452 } else {
453 timer_del(xhci->mfwrap_timer);
454 }
455 }
456
xhci_mfwrap_timer(void * opaque)457 static void xhci_mfwrap_timer(void *opaque)
458 {
459 XHCIState *xhci = opaque;
460 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
461
462 xhci_event(xhci, &wrap, 0);
463 xhci_mfwrap_update(xhci);
464 }
465
xhci_die(XHCIState * xhci)466 static void xhci_die(XHCIState *xhci)
467 {
468 xhci->usbsts |= USBSTS_HCE;
469 DPRINTF("xhci: asserted controller error\n");
470 }
471
xhci_addr64(uint32_t low,uint32_t high)472 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
473 {
474 if (sizeof(dma_addr_t) == 4) {
475 return low;
476 } else {
477 return low | (((dma_addr_t)high << 16) << 16);
478 }
479 }
480
xhci_mask64(uint64_t addr)481 static inline dma_addr_t xhci_mask64(uint64_t addr)
482 {
483 if (sizeof(dma_addr_t) == 4) {
484 return addr & 0xffffffff;
485 } else {
486 return addr;
487 }
488 }
489
xhci_dma_read_u32s(XHCIState * xhci,dma_addr_t addr,uint32_t * buf,size_t len)490 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
491 uint32_t *buf, size_t len)
492 {
493 int i;
494
495 assert((len % sizeof(uint32_t)) == 0);
496
497 if (dma_memory_read(xhci->as, addr, buf, len,
498 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
499 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
500 __func__);
501 memset(buf, 0xff, len);
502 xhci_die(xhci);
503 return;
504 }
505
506 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
507 buf[i] = le32_to_cpu(buf[i]);
508 }
509 }
510
xhci_dma_write_u32s(XHCIState * xhci,dma_addr_t addr,const uint32_t * buf,size_t len)511 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
512 const uint32_t *buf, size_t len)
513 {
514 int i;
515 uint32_t tmp[5];
516 uint32_t n = len / sizeof(uint32_t);
517
518 assert((len % sizeof(uint32_t)) == 0);
519 assert(n <= ARRAY_SIZE(tmp));
520
521 for (i = 0; i < n; i++) {
522 tmp[i] = cpu_to_le32(buf[i]);
523 }
524 if (dma_memory_write(xhci->as, addr, tmp, len,
525 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
526 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
527 __func__);
528 xhci_die(xhci);
529 return;
530 }
531 }
532
xhci_lookup_port(XHCIState * xhci,struct USBPort * uport)533 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
534 {
535 int index;
536
537 if (!uport->dev) {
538 return NULL;
539 }
540 switch (uport->dev->speed) {
541 case USB_SPEED_LOW:
542 case USB_SPEED_FULL:
543 case USB_SPEED_HIGH:
544 index = uport->index + xhci->numports_3;
545 break;
546 case USB_SPEED_SUPER:
547 index = uport->index;
548 break;
549 default:
550 return NULL;
551 }
552 return &xhci->ports[index];
553 }
554
xhci_intr_update(XHCIState * xhci,int v)555 static void xhci_intr_update(XHCIState *xhci, int v)
556 {
557 int level = 0;
558
559 if (v == 0) {
560 if (xhci->intr[0].iman & IMAN_IP &&
561 xhci->intr[0].iman & IMAN_IE &&
562 xhci->usbcmd & USBCMD_INTE) {
563 level = 1;
564 }
565 if (xhci->intr_raise) {
566 if (xhci->intr_raise(xhci, 0, level)) {
567 xhci->intr[0].iman &= ~IMAN_IP;
568 }
569 }
570 }
571 if (xhci->intr_update) {
572 xhci->intr_update(xhci, v,
573 xhci->intr[v].iman & IMAN_IE);
574 }
575 }
576
xhci_intr_raise(XHCIState * xhci,int v)577 static void xhci_intr_raise(XHCIState *xhci, int v)
578 {
579 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
580
581 xhci->intr[v].erdp_low |= ERDP_EHB;
582 xhci->intr[v].iman |= IMAN_IP;
583 xhci->usbsts |= USBSTS_EINT;
584
585 if (pending) {
586 return;
587 }
588 if (!(xhci->intr[v].iman & IMAN_IE)) {
589 return;
590 }
591
592 if (!(xhci->usbcmd & USBCMD_INTE)) {
593 return;
594 }
595 if (xhci->intr_raise) {
596 if (xhci->intr_raise(xhci, v, true)) {
597 xhci->intr[v].iman &= ~IMAN_IP;
598 }
599 }
600 }
601
xhci_running(XHCIState * xhci)602 static inline int xhci_running(XHCIState *xhci)
603 {
604 return !(xhci->usbsts & USBSTS_HCH);
605 }
606
xhci_write_event(XHCIState * xhci,XHCIEvent * event,int v)607 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
608 {
609 XHCIInterrupter *intr = &xhci->intr[v];
610 XHCITRB ev_trb;
611 dma_addr_t addr;
612
613 ev_trb.parameter = cpu_to_le64(event->ptr);
614 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
615 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
616 event->flags | (event->type << TRB_TYPE_SHIFT);
617 if (intr->er_pcs) {
618 ev_trb.control |= TRB_C;
619 }
620 ev_trb.control = cpu_to_le32(ev_trb.control);
621
622 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
623 event_name(event), ev_trb.parameter,
624 ev_trb.status, ev_trb.control);
625
626 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
627 if (dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE,
628 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
629 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
630 __func__);
631 xhci_die(xhci);
632 }
633
634 intr->er_ep_idx++;
635 if (intr->er_ep_idx >= intr->er_size) {
636 intr->er_ep_idx = 0;
637 intr->er_pcs = !intr->er_pcs;
638 }
639 }
640
xhci_event(XHCIState * xhci,XHCIEvent * event,int v)641 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
642 {
643 XHCIInterrupter *intr;
644 dma_addr_t erdp;
645 unsigned int dp_idx;
646
647 if (xhci->numintrs == 1 ||
648 (xhci->intr_mapping_supported && !xhci->intr_mapping_supported(xhci))) {
649 v = 0;
650 }
651
652 if (v >= xhci->numintrs) {
653 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
654 return;
655 }
656 intr = &xhci->intr[v];
657
658 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
659 if (erdp < intr->er_start ||
660 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
661 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
662 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
663 v, intr->er_start, intr->er_size);
664 xhci_die(xhci);
665 return;
666 }
667
668 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
669 assert(dp_idx < intr->er_size);
670
671 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) {
672 DPRINTF("xhci: ER %d full, send ring full error\n", v);
673 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
674 xhci_write_event(xhci, &full, v);
675 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) {
676 DPRINTF("xhci: ER %d full, drop event\n", v);
677 } else {
678 xhci_write_event(xhci, event, v);
679 }
680
681 xhci_intr_raise(xhci, v);
682 }
683
xhci_ring_init(XHCIState * xhci,XHCIRing * ring,dma_addr_t base)684 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
685 dma_addr_t base)
686 {
687 ring->dequeue = base;
688 ring->ccs = 1;
689 }
690
xhci_ring_fetch(XHCIState * xhci,XHCIRing * ring,XHCITRB * trb,dma_addr_t * addr)691 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
692 dma_addr_t *addr)
693 {
694 uint32_t link_cnt = 0;
695
696 while (1) {
697 TRBType type;
698 if (dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE,
699 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
700 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
701 __func__);
702 return 0;
703 }
704 trb->addr = ring->dequeue;
705 trb->ccs = ring->ccs;
706 le64_to_cpus(&trb->parameter);
707 le32_to_cpus(&trb->status);
708 le32_to_cpus(&trb->control);
709
710 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
711 trb->parameter, trb->status, trb->control);
712
713 if ((trb->control & TRB_C) != ring->ccs) {
714 return 0;
715 }
716
717 type = TRB_TYPE(*trb);
718
719 if (type != TR_LINK) {
720 if (addr) {
721 *addr = ring->dequeue;
722 }
723 ring->dequeue += TRB_SIZE;
724 return type;
725 } else {
726 if (++link_cnt > TRB_LINK_LIMIT) {
727 trace_usb_xhci_enforced_limit("trb-link");
728 return 0;
729 }
730 ring->dequeue = xhci_mask64(trb->parameter);
731 if (trb->control & TRB_LK_TC) {
732 ring->ccs = !ring->ccs;
733 }
734 }
735 }
736 }
737
xhci_ring_chain_length(XHCIState * xhci,const XHCIRing * ring)738 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
739 {
740 XHCITRB trb;
741 int length = 0;
742 dma_addr_t dequeue = ring->dequeue;
743 bool ccs = ring->ccs;
744 /* hack to bundle together the two/three TDs that make a setup transfer */
745 bool control_td_set = 0;
746 uint32_t link_cnt = 0;
747
748 do {
749 TRBType type;
750 if (dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE,
751 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
752 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
753 __func__);
754 return -1;
755 }
756 le64_to_cpus(&trb.parameter);
757 le32_to_cpus(&trb.status);
758 le32_to_cpus(&trb.control);
759
760 if ((trb.control & TRB_C) != ccs) {
761 return -length;
762 }
763
764 type = TRB_TYPE(trb);
765
766 if (type == TR_LINK) {
767 if (++link_cnt > TRB_LINK_LIMIT) {
768 return -length;
769 }
770 dequeue = xhci_mask64(trb.parameter);
771 if (trb.control & TRB_LK_TC) {
772 ccs = !ccs;
773 }
774 continue;
775 }
776
777 length += 1;
778 dequeue += TRB_SIZE;
779
780 if (type == TR_SETUP) {
781 control_td_set = 1;
782 } else if (type == TR_STATUS) {
783 control_td_set = 0;
784 }
785
786 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
787 return length;
788 }
789
790 /*
791 * According to the xHCI spec, Transfer Ring segments should have
792 * a maximum size of 64 kB (see chapter "6 Data Structures")
793 */
794 } while (length < TRB_LINK_LIMIT * 65536 / TRB_SIZE);
795
796 qemu_log_mask(LOG_GUEST_ERROR, "%s: exceeded maximum transfer ring size!\n",
797 __func__);
798
799 return -1;
800 }
801
xhci_er_reset(XHCIState * xhci,int v)802 static void xhci_er_reset(XHCIState *xhci, int v)
803 {
804 XHCIInterrupter *intr = &xhci->intr[v];
805 XHCIEvRingSeg seg;
806 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
807
808 if (intr->erstsz == 0 || erstba == 0) {
809 /* disabled */
810 intr->er_start = 0;
811 intr->er_size = 0;
812 return;
813 }
814 /* cache the (sole) event ring segment location */
815 if (intr->erstsz != 1) {
816 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
817 xhci_die(xhci);
818 return;
819 }
820 if (dma_memory_read(xhci->as, erstba, &seg, sizeof(seg),
821 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
822 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
823 __func__);
824 xhci_die(xhci);
825 return;
826 }
827
828 le32_to_cpus(&seg.addr_low);
829 le32_to_cpus(&seg.addr_high);
830 le32_to_cpus(&seg.size);
831 if (seg.size < 16 || seg.size > 4096) {
832 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
833 xhci_die(xhci);
834 return;
835 }
836 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
837 intr->er_size = seg.size;
838
839 intr->er_ep_idx = 0;
840 intr->er_pcs = 1;
841
842 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
843 v, intr->er_start, intr->er_size);
844 }
845
xhci_run(XHCIState * xhci)846 static void xhci_run(XHCIState *xhci)
847 {
848 trace_usb_xhci_run();
849 xhci->usbsts &= ~USBSTS_HCH;
850 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
851 }
852
xhci_stop(XHCIState * xhci)853 static void xhci_stop(XHCIState *xhci)
854 {
855 trace_usb_xhci_stop();
856 xhci->usbsts |= USBSTS_HCH;
857 xhci->crcr_low &= ~CRCR_CRR;
858 }
859
xhci_alloc_stream_contexts(unsigned count,dma_addr_t base)860 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
861 dma_addr_t base)
862 {
863 XHCIStreamContext *stctx;
864 unsigned int i;
865
866 stctx = g_new0(XHCIStreamContext, count);
867 for (i = 0; i < count; i++) {
868 stctx[i].pctx = base + i * 16;
869 stctx[i].sct = -1;
870 }
871 return stctx;
872 }
873
xhci_reset_streams(XHCIEPContext * epctx)874 static void xhci_reset_streams(XHCIEPContext *epctx)
875 {
876 unsigned int i;
877
878 for (i = 0; i < epctx->nr_pstreams; i++) {
879 epctx->pstreams[i].sct = -1;
880 }
881 }
882
xhci_alloc_streams(XHCIEPContext * epctx,dma_addr_t base)883 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
884 {
885 assert(epctx->pstreams == NULL);
886 epctx->nr_pstreams = 2 << epctx->max_pstreams;
887 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
888 }
889
xhci_free_streams(XHCIEPContext * epctx)890 static void xhci_free_streams(XHCIEPContext *epctx)
891 {
892 assert(epctx->pstreams != NULL);
893
894 g_free(epctx->pstreams);
895 epctx->pstreams = NULL;
896 epctx->nr_pstreams = 0;
897 }
898
xhci_epmask_to_eps_with_streams(XHCIState * xhci,unsigned int slotid,uint32_t epmask,XHCIEPContext ** epctxs,USBEndpoint ** eps)899 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
900 unsigned int slotid,
901 uint32_t epmask,
902 XHCIEPContext **epctxs,
903 USBEndpoint **eps)
904 {
905 XHCISlot *slot;
906 XHCIEPContext *epctx;
907 USBEndpoint *ep;
908 int i, j;
909
910 assert(slotid >= 1 && slotid <= xhci->numslots);
911
912 slot = &xhci->slots[slotid - 1];
913
914 for (i = 2, j = 0; i <= 31; i++) {
915 if (!(epmask & (1u << i))) {
916 continue;
917 }
918
919 epctx = slot->eps[i - 1];
920 ep = xhci_epid_to_usbep(epctx);
921 if (!epctx || !epctx->nr_pstreams || !ep) {
922 continue;
923 }
924
925 if (epctxs) {
926 epctxs[j] = epctx;
927 }
928 eps[j++] = ep;
929 }
930 return j;
931 }
932
xhci_free_device_streams(XHCIState * xhci,unsigned int slotid,uint32_t epmask)933 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
934 uint32_t epmask)
935 {
936 USBEndpoint *eps[30];
937 int nr_eps;
938
939 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
940 if (nr_eps) {
941 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
942 }
943 }
944
xhci_alloc_device_streams(XHCIState * xhci,unsigned int slotid,uint32_t epmask)945 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
946 uint32_t epmask)
947 {
948 XHCIEPContext *epctxs[30];
949 USBEndpoint *eps[30];
950 int i, r, nr_eps, req_nr_streams, dev_max_streams;
951
952 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
953 eps);
954 if (nr_eps == 0) {
955 return CC_SUCCESS;
956 }
957
958 req_nr_streams = epctxs[0]->nr_pstreams;
959 dev_max_streams = eps[0]->max_streams;
960
961 for (i = 1; i < nr_eps; i++) {
962 /*
963 * HdG: I don't expect these to ever trigger, but if they do we need
964 * to come up with another solution, ie group identical endpoints
965 * together and make an usb_device_alloc_streams call per group.
966 */
967 if (epctxs[i]->nr_pstreams != req_nr_streams) {
968 FIXME("guest streams config not identical for all eps");
969 return CC_RESOURCE_ERROR;
970 }
971 if (eps[i]->max_streams != dev_max_streams) {
972 FIXME("device streams config not identical for all eps");
973 return CC_RESOURCE_ERROR;
974 }
975 }
976
977 /*
978 * max-streams in both the device descriptor and in the controller is a
979 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
980 * streams the guest will ask for 5 rounded up to the next power of 2 which
981 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
982 *
983 * For redirected devices however this is an issue, as there we must ask
984 * the real xhci controller to alloc streams, and the host driver for the
985 * real xhci controller will likely disallow allocating more streams then
986 * the device can handle.
987 *
988 * So we limit the requested nr_streams to the maximum number the device
989 * can handle.
990 */
991 if (req_nr_streams > dev_max_streams) {
992 req_nr_streams = dev_max_streams;
993 }
994
995 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
996 if (r != 0) {
997 DPRINTF("xhci: alloc streams failed\n");
998 return CC_RESOURCE_ERROR;
999 }
1000
1001 return CC_SUCCESS;
1002 }
1003
xhci_find_stream(XHCIEPContext * epctx,unsigned int streamid,uint32_t * cc_error)1004 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1005 unsigned int streamid,
1006 uint32_t *cc_error)
1007 {
1008 XHCIStreamContext *sctx;
1009 dma_addr_t base;
1010 uint32_t ctx[2], sct;
1011
1012 assert(streamid != 0);
1013 if (epctx->lsa) {
1014 if (streamid >= epctx->nr_pstreams) {
1015 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1016 return NULL;
1017 }
1018 sctx = epctx->pstreams + streamid;
1019 } else {
1020 fprintf(stderr, "xhci: FIXME: secondary streams not implemented yet");
1021 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1022 return NULL;
1023 }
1024
1025 if (sctx->sct == -1) {
1026 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1027 sct = (ctx[0] >> 1) & 0x07;
1028 if (epctx->lsa && sct != 1) {
1029 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1030 return NULL;
1031 }
1032 sctx->sct = sct;
1033 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1034 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1035 }
1036 return sctx;
1037 }
1038
xhci_set_ep_state(XHCIState * xhci,XHCIEPContext * epctx,XHCIStreamContext * sctx,uint32_t state)1039 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1040 XHCIStreamContext *sctx, uint32_t state)
1041 {
1042 XHCIRing *ring = NULL;
1043 uint32_t ctx[5];
1044 uint32_t ctx2[2];
1045
1046 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1047 ctx[0] &= ~EP_STATE_MASK;
1048 ctx[0] |= state;
1049
1050 /* update ring dequeue ptr */
1051 if (epctx->nr_pstreams) {
1052 if (sctx != NULL) {
1053 ring = &sctx->ring;
1054 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1055 ctx2[0] &= 0xe;
1056 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1057 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1058 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1059 }
1060 } else {
1061 ring = &epctx->ring;
1062 }
1063 if (ring) {
1064 ctx[2] = ring->dequeue | ring->ccs;
1065 ctx[3] = (ring->dequeue >> 16) >> 16;
1066
1067 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1068 epctx->pctx, state, ctx[3], ctx[2]);
1069 }
1070
1071 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1072 if (epctx->state != state) {
1073 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1074 ep_state_name(epctx->state),
1075 ep_state_name(state));
1076 }
1077 epctx->state = state;
1078 }
1079
xhci_ep_kick_timer(void * opaque)1080 static void xhci_ep_kick_timer(void *opaque)
1081 {
1082 XHCIEPContext *epctx = opaque;
1083 xhci_kick_epctx(epctx, 0);
1084 }
1085
xhci_alloc_epctx(XHCIState * xhci,unsigned int slotid,unsigned int epid)1086 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1087 unsigned int slotid,
1088 unsigned int epid)
1089 {
1090 XHCIEPContext *epctx;
1091
1092 epctx = g_new0(XHCIEPContext, 1);
1093 epctx->xhci = xhci;
1094 epctx->slotid = slotid;
1095 epctx->epid = epid;
1096
1097 QTAILQ_INIT(&epctx->transfers);
1098 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1099
1100 return epctx;
1101 }
1102
xhci_init_epctx(XHCIEPContext * epctx,dma_addr_t pctx,uint32_t * ctx)1103 static void xhci_init_epctx(XHCIEPContext *epctx,
1104 dma_addr_t pctx, uint32_t *ctx)
1105 {
1106 dma_addr_t dequeue;
1107
1108 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1109
1110 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1111 epctx->pctx = pctx;
1112 epctx->max_psize = ctx[1]>>16;
1113 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1114 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1115 epctx->lsa = (ctx[0] >> 15) & 1;
1116 if (epctx->max_pstreams) {
1117 xhci_alloc_streams(epctx, dequeue);
1118 } else {
1119 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1120 epctx->ring.ccs = ctx[2] & 1;
1121 }
1122
1123 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1124 }
1125
xhci_enable_ep(XHCIState * xhci,unsigned int slotid,unsigned int epid,dma_addr_t pctx,uint32_t * ctx)1126 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1127 unsigned int epid, dma_addr_t pctx,
1128 uint32_t *ctx)
1129 {
1130 XHCISlot *slot;
1131 XHCIEPContext *epctx;
1132
1133 trace_usb_xhci_ep_enable(slotid, epid);
1134 assert(slotid >= 1 && slotid <= xhci->numslots);
1135 assert(epid >= 1 && epid <= 31);
1136
1137 slot = &xhci->slots[slotid-1];
1138 if (slot->eps[epid-1]) {
1139 xhci_disable_ep(xhci, slotid, epid);
1140 }
1141
1142 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1143 slot->eps[epid-1] = epctx;
1144 xhci_init_epctx(epctx, pctx, ctx);
1145
1146 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1147 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1148
1149 epctx->mfindex_last = 0;
1150
1151 epctx->state = EP_RUNNING;
1152 ctx[0] &= ~EP_STATE_MASK;
1153 ctx[0] |= EP_RUNNING;
1154
1155 return CC_SUCCESS;
1156 }
1157
xhci_ep_alloc_xfer(XHCIEPContext * epctx,uint32_t length)1158 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx,
1159 uint32_t length)
1160 {
1161 uint32_t limit = epctx->nr_pstreams + 16;
1162 XHCITransfer *xfer;
1163
1164 if (epctx->xfer_count >= limit) {
1165 return NULL;
1166 }
1167
1168 xfer = g_new0(XHCITransfer, 1);
1169 xfer->epctx = epctx;
1170 xfer->trbs = g_new(XHCITRB, length);
1171 xfer->trb_count = length;
1172 usb_packet_init(&xfer->packet);
1173
1174 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next);
1175 epctx->xfer_count++;
1176
1177 return xfer;
1178 }
1179
xhci_ep_free_xfer(XHCITransfer * xfer)1180 static void xhci_ep_free_xfer(XHCITransfer *xfer)
1181 {
1182 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next);
1183 xfer->epctx->xfer_count--;
1184
1185 usb_packet_cleanup(&xfer->packet);
1186 g_free(xfer->trbs);
1187 g_free(xfer);
1188 }
1189
xhci_ep_nuke_one_xfer(XHCITransfer * t,TRBCCode report)1190 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1191 {
1192 int killed = 0;
1193
1194 if (report && (t->running_async || t->running_retry)) {
1195 t->status = report;
1196 xhci_xfer_report(t);
1197 }
1198
1199 if (t->running_async) {
1200 usb_cancel_packet(&t->packet);
1201 t->running_async = 0;
1202 killed = 1;
1203 }
1204 if (t->running_retry) {
1205 if (t->epctx) {
1206 t->epctx->retry = NULL;
1207 timer_del(t->epctx->kick_timer);
1208 }
1209 t->running_retry = 0;
1210 killed = 1;
1211 }
1212 g_free(t->trbs);
1213
1214 t->trbs = NULL;
1215 t->trb_count = 0;
1216
1217 return killed;
1218 }
1219
xhci_ep_nuke_xfers(XHCIState * xhci,unsigned int slotid,unsigned int epid,TRBCCode report)1220 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1221 unsigned int epid, TRBCCode report)
1222 {
1223 XHCISlot *slot;
1224 XHCIEPContext *epctx;
1225 XHCITransfer *xfer;
1226 int killed = 0;
1227 USBEndpoint *ep = NULL;
1228 assert(slotid >= 1 && slotid <= xhci->numslots);
1229 assert(epid >= 1 && epid <= 31);
1230
1231 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1232
1233 slot = &xhci->slots[slotid-1];
1234
1235 if (!slot->eps[epid-1]) {
1236 return 0;
1237 }
1238
1239 epctx = slot->eps[epid-1];
1240
1241 for (;;) {
1242 xfer = QTAILQ_FIRST(&epctx->transfers);
1243 if (xfer == NULL) {
1244 break;
1245 }
1246 killed += xhci_ep_nuke_one_xfer(xfer, report);
1247 if (killed) {
1248 report = 0; /* Only report once */
1249 }
1250 xhci_ep_free_xfer(xfer);
1251 }
1252
1253 ep = xhci_epid_to_usbep(epctx);
1254 if (ep) {
1255 usb_device_ep_stopped(ep->dev, ep);
1256 }
1257 return killed;
1258 }
1259
xhci_disable_ep(XHCIState * xhci,unsigned int slotid,unsigned int epid)1260 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1261 unsigned int epid)
1262 {
1263 XHCISlot *slot;
1264 XHCIEPContext *epctx;
1265
1266 trace_usb_xhci_ep_disable(slotid, epid);
1267 assert(slotid >= 1 && slotid <= xhci->numslots);
1268 assert(epid >= 1 && epid <= 31);
1269
1270 slot = &xhci->slots[slotid-1];
1271
1272 if (!slot->eps[epid-1]) {
1273 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1274 return CC_SUCCESS;
1275 }
1276
1277 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1278
1279 epctx = slot->eps[epid-1];
1280
1281 if (epctx->nr_pstreams) {
1282 xhci_free_streams(epctx);
1283 }
1284
1285 /* only touch guest RAM if we're not resetting the HC */
1286 if (xhci->dcbaap_low || xhci->dcbaap_high) {
1287 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1288 }
1289
1290 timer_free(epctx->kick_timer);
1291 g_free(epctx);
1292 slot->eps[epid-1] = NULL;
1293
1294 return CC_SUCCESS;
1295 }
1296
xhci_stop_ep(XHCIState * xhci,unsigned int slotid,unsigned int epid)1297 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1298 unsigned int epid)
1299 {
1300 XHCISlot *slot;
1301 XHCIEPContext *epctx;
1302
1303 trace_usb_xhci_ep_stop(slotid, epid);
1304 assert(slotid >= 1 && slotid <= xhci->numslots);
1305
1306 if (epid < 1 || epid > 31) {
1307 DPRINTF("xhci: bad ep %d\n", epid);
1308 return CC_TRB_ERROR;
1309 }
1310
1311 slot = &xhci->slots[slotid-1];
1312
1313 if (!slot->eps[epid-1]) {
1314 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1315 return CC_EP_NOT_ENABLED_ERROR;
1316 }
1317
1318 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1319 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1320 "data might be lost\n");
1321 }
1322
1323 epctx = slot->eps[epid-1];
1324
1325 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1326
1327 if (epctx->nr_pstreams) {
1328 xhci_reset_streams(epctx);
1329 }
1330
1331 return CC_SUCCESS;
1332 }
1333
xhci_reset_ep(XHCIState * xhci,unsigned int slotid,unsigned int epid)1334 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1335 unsigned int epid)
1336 {
1337 XHCISlot *slot;
1338 XHCIEPContext *epctx;
1339
1340 trace_usb_xhci_ep_reset(slotid, epid);
1341 assert(slotid >= 1 && slotid <= xhci->numslots);
1342
1343 if (epid < 1 || epid > 31) {
1344 DPRINTF("xhci: bad ep %d\n", epid);
1345 return CC_TRB_ERROR;
1346 }
1347
1348 slot = &xhci->slots[slotid-1];
1349
1350 if (!slot->eps[epid-1]) {
1351 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1352 return CC_EP_NOT_ENABLED_ERROR;
1353 }
1354
1355 epctx = slot->eps[epid-1];
1356
1357 if (epctx->state != EP_HALTED) {
1358 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1359 epid, epctx->state);
1360 return CC_CONTEXT_STATE_ERROR;
1361 }
1362
1363 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1364 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1365 "data might be lost\n");
1366 }
1367
1368 if (!xhci->slots[slotid-1].uport ||
1369 !xhci->slots[slotid-1].uport->dev ||
1370 !xhci->slots[slotid-1].uport->dev->attached) {
1371 return CC_USB_TRANSACTION_ERROR;
1372 }
1373
1374 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1375
1376 if (epctx->nr_pstreams) {
1377 xhci_reset_streams(epctx);
1378 }
1379
1380 return CC_SUCCESS;
1381 }
1382
xhci_set_ep_dequeue(XHCIState * xhci,unsigned int slotid,unsigned int epid,unsigned int streamid,uint64_t pdequeue)1383 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1384 unsigned int epid, unsigned int streamid,
1385 uint64_t pdequeue)
1386 {
1387 XHCISlot *slot;
1388 XHCIEPContext *epctx;
1389 XHCIStreamContext *sctx;
1390 dma_addr_t dequeue;
1391
1392 assert(slotid >= 1 && slotid <= xhci->numslots);
1393
1394 if (epid < 1 || epid > 31) {
1395 DPRINTF("xhci: bad ep %d\n", epid);
1396 return CC_TRB_ERROR;
1397 }
1398
1399 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1400 dequeue = xhci_mask64(pdequeue);
1401
1402 slot = &xhci->slots[slotid-1];
1403
1404 if (!slot->eps[epid-1]) {
1405 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1406 return CC_EP_NOT_ENABLED_ERROR;
1407 }
1408
1409 epctx = slot->eps[epid-1];
1410
1411 if (epctx->state != EP_STOPPED) {
1412 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1413 return CC_CONTEXT_STATE_ERROR;
1414 }
1415
1416 if (epctx->nr_pstreams) {
1417 uint32_t err;
1418 sctx = xhci_find_stream(epctx, streamid, &err);
1419 if (sctx == NULL) {
1420 return err;
1421 }
1422 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1423 sctx->ring.ccs = dequeue & 1;
1424 } else {
1425 sctx = NULL;
1426 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1427 epctx->ring.ccs = dequeue & 1;
1428 }
1429
1430 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1431
1432 return CC_SUCCESS;
1433 }
1434
xhci_xfer_create_sgl(XHCITransfer * xfer,int in_xfer)1435 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1436 {
1437 XHCIState *xhci = xfer->epctx->xhci;
1438 int i;
1439
1440 xfer->int_req = false;
1441 qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as);
1442 for (i = 0; i < xfer->trb_count; i++) {
1443 XHCITRB *trb = &xfer->trbs[i];
1444 dma_addr_t addr;
1445 unsigned int chunk = 0;
1446
1447 if (trb->control & TRB_TR_IOC) {
1448 xfer->int_req = true;
1449 }
1450
1451 switch (TRB_TYPE(*trb)) {
1452 case TR_DATA:
1453 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1454 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1455 goto err;
1456 }
1457 /* fallthrough */
1458 case TR_NORMAL:
1459 case TR_ISOCH:
1460 addr = xhci_mask64(trb->parameter);
1461 chunk = trb->status & 0x1ffff;
1462 if (trb->control & TRB_TR_IDT) {
1463 if (chunk > 8 || in_xfer) {
1464 DPRINTF("xhci: invalid immediate data TRB\n");
1465 goto err;
1466 }
1467 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1468 } else {
1469 qemu_sglist_add(&xfer->sgl, addr, chunk);
1470 }
1471 break;
1472 }
1473 }
1474
1475 return 0;
1476
1477 err:
1478 qemu_sglist_destroy(&xfer->sgl);
1479 xhci_die(xhci);
1480 return -1;
1481 }
1482
xhci_xfer_unmap(XHCITransfer * xfer)1483 static void xhci_xfer_unmap(XHCITransfer *xfer)
1484 {
1485 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1486 qemu_sglist_destroy(&xfer->sgl);
1487 }
1488
xhci_xfer_report(XHCITransfer * xfer)1489 static void xhci_xfer_report(XHCITransfer *xfer)
1490 {
1491 uint32_t edtla = 0;
1492 unsigned int left;
1493 bool reported = 0;
1494 bool shortpkt = 0;
1495 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1496 XHCIState *xhci = xfer->epctx->xhci;
1497 int i;
1498
1499 left = xfer->packet.actual_length;
1500
1501 for (i = 0; i < xfer->trb_count; i++) {
1502 XHCITRB *trb = &xfer->trbs[i];
1503 unsigned int chunk = 0;
1504
1505 switch (TRB_TYPE(*trb)) {
1506 case TR_SETUP:
1507 chunk = trb->status & 0x1ffff;
1508 if (chunk > 8) {
1509 chunk = 8;
1510 }
1511 break;
1512 case TR_DATA:
1513 case TR_NORMAL:
1514 case TR_ISOCH:
1515 chunk = trb->status & 0x1ffff;
1516 if (chunk > left) {
1517 chunk = left;
1518 if (xfer->status == CC_SUCCESS) {
1519 shortpkt = 1;
1520 }
1521 }
1522 left -= chunk;
1523 edtla += chunk;
1524 break;
1525 case TR_STATUS:
1526 reported = 0;
1527 shortpkt = 0;
1528 break;
1529 }
1530
1531 if (!reported && ((trb->control & TRB_TR_IOC) ||
1532 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1533 (xfer->status != CC_SUCCESS && left == 0))) {
1534 event.slotid = xfer->epctx->slotid;
1535 event.epid = xfer->epctx->epid;
1536 event.length = (trb->status & 0x1ffff) - chunk;
1537 event.flags = 0;
1538 event.ptr = trb->addr;
1539 if (xfer->status == CC_SUCCESS) {
1540 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1541 } else {
1542 event.ccode = xfer->status;
1543 }
1544 if (TRB_TYPE(*trb) == TR_EVDATA) {
1545 event.ptr = trb->parameter;
1546 event.flags |= TRB_EV_ED;
1547 event.length = edtla & 0xffffff;
1548 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1549 edtla = 0;
1550 }
1551 xhci_event(xhci, &event, TRB_INTR(*trb));
1552 reported = 1;
1553 if (xfer->status != CC_SUCCESS) {
1554 return;
1555 }
1556 }
1557
1558 switch (TRB_TYPE(*trb)) {
1559 case TR_SETUP:
1560 reported = 0;
1561 shortpkt = 0;
1562 break;
1563 }
1564
1565 }
1566 }
1567
xhci_stall_ep(XHCITransfer * xfer)1568 static void xhci_stall_ep(XHCITransfer *xfer)
1569 {
1570 XHCIEPContext *epctx = xfer->epctx;
1571 XHCIState *xhci = epctx->xhci;
1572 uint32_t err;
1573 XHCIStreamContext *sctx;
1574
1575 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1576 /* never halt isoch endpoints, 4.10.2 */
1577 return;
1578 }
1579
1580 if (epctx->nr_pstreams) {
1581 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1582 if (sctx == NULL) {
1583 return;
1584 }
1585 sctx->ring.dequeue = xfer->trbs[0].addr;
1586 sctx->ring.ccs = xfer->trbs[0].ccs;
1587 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1588 } else {
1589 epctx->ring.dequeue = xfer->trbs[0].addr;
1590 epctx->ring.ccs = xfer->trbs[0].ccs;
1591 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1592 }
1593 }
1594
xhci_setup_packet(XHCITransfer * xfer)1595 static int xhci_setup_packet(XHCITransfer *xfer)
1596 {
1597 USBEndpoint *ep;
1598 int dir;
1599
1600 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1601
1602 if (xfer->packet.ep) {
1603 ep = xfer->packet.ep;
1604 } else {
1605 ep = xhci_epid_to_usbep(xfer->epctx);
1606 if (!ep) {
1607 DPRINTF("xhci: slot %d has no device\n",
1608 xfer->epctx->slotid);
1609 return -1;
1610 }
1611 }
1612
1613 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1614 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1615 xfer->trbs[0].addr, false, xfer->int_req);
1616 if (usb_packet_map(&xfer->packet, &xfer->sgl)) {
1617 qemu_sglist_destroy(&xfer->sgl);
1618 return -1;
1619 }
1620 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1621 xfer->packet.pid, ep->dev->addr, ep->nr);
1622 return 0;
1623 }
1624
xhci_try_complete_packet(XHCITransfer * xfer)1625 static int xhci_try_complete_packet(XHCITransfer *xfer)
1626 {
1627 if (xfer->packet.status == USB_RET_ASYNC) {
1628 trace_usb_xhci_xfer_async(xfer);
1629 xfer->running_async = 1;
1630 xfer->running_retry = 0;
1631 xfer->complete = 0;
1632 return 0;
1633 } else if (xfer->packet.status == USB_RET_NAK) {
1634 trace_usb_xhci_xfer_nak(xfer);
1635 xfer->running_async = 0;
1636 xfer->running_retry = 1;
1637 xfer->complete = 0;
1638 return 0;
1639 } else {
1640 xfer->running_async = 0;
1641 xfer->running_retry = 0;
1642 xfer->complete = 1;
1643 xhci_xfer_unmap(xfer);
1644 }
1645
1646 if (xfer->packet.status == USB_RET_SUCCESS) {
1647 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1648 xfer->status = CC_SUCCESS;
1649 xhci_xfer_report(xfer);
1650 return 0;
1651 }
1652
1653 /* error */
1654 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1655 switch (xfer->packet.status) {
1656 case USB_RET_NODEV:
1657 case USB_RET_IOERROR:
1658 xfer->status = CC_USB_TRANSACTION_ERROR;
1659 xhci_xfer_report(xfer);
1660 xhci_stall_ep(xfer);
1661 break;
1662 case USB_RET_STALL:
1663 xfer->status = CC_STALL_ERROR;
1664 xhci_xfer_report(xfer);
1665 xhci_stall_ep(xfer);
1666 break;
1667 case USB_RET_BABBLE:
1668 xfer->status = CC_BABBLE_DETECTED;
1669 xhci_xfer_report(xfer);
1670 xhci_stall_ep(xfer);
1671 break;
1672 default:
1673 DPRINTF("%s: FIXME: status = %d\n", __func__,
1674 xfer->packet.status);
1675 FIXME("unhandled USB_RET_*");
1676 }
1677 return 0;
1678 }
1679
xhci_fire_ctl_transfer(XHCIState * xhci,XHCITransfer * xfer)1680 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1681 {
1682 XHCITRB *trb_setup, *trb_status;
1683 uint8_t bmRequestType;
1684
1685 trb_setup = &xfer->trbs[0];
1686 trb_status = &xfer->trbs[xfer->trb_count-1];
1687
1688 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1689 xfer->epctx->epid, xfer->streamid);
1690
1691 /* at most one Event Data TRB allowed after STATUS */
1692 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1693 trb_status--;
1694 }
1695
1696 /* do some sanity checks */
1697 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1698 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1699 TRB_TYPE(*trb_setup));
1700 return -1;
1701 }
1702 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1703 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1704 TRB_TYPE(*trb_status));
1705 return -1;
1706 }
1707 if (!(trb_setup->control & TRB_TR_IDT)) {
1708 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1709 return -1;
1710 }
1711 if ((trb_setup->status & 0x1ffff) != 8) {
1712 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1713 (trb_setup->status & 0x1ffff));
1714 return -1;
1715 }
1716
1717 bmRequestType = trb_setup->parameter;
1718
1719 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1720 xfer->iso_xfer = false;
1721 xfer->timed_xfer = false;
1722
1723 if (xhci_setup_packet(xfer) < 0) {
1724 return -1;
1725 }
1726 xfer->packet.parameter = trb_setup->parameter;
1727
1728 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1729 xhci_try_complete_packet(xfer);
1730 return 0;
1731 }
1732
xhci_calc_intr_kick(XHCIState * xhci,XHCITransfer * xfer,XHCIEPContext * epctx,uint64_t mfindex)1733 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1734 XHCIEPContext *epctx, uint64_t mfindex)
1735 {
1736 uint64_t asap = ((mfindex + epctx->interval - 1) &
1737 ~(epctx->interval-1));
1738 uint64_t kick = epctx->mfindex_last + epctx->interval;
1739
1740 assert(epctx->interval != 0);
1741 xfer->mfindex_kick = MAX(asap, kick);
1742 }
1743
xhci_calc_iso_kick(XHCIState * xhci,XHCITransfer * xfer,XHCIEPContext * epctx,uint64_t mfindex)1744 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1745 XHCIEPContext *epctx, uint64_t mfindex)
1746 {
1747 if (xfer->trbs[0].control & TRB_TR_SIA) {
1748 uint64_t asap = ((mfindex + epctx->interval - 1) &
1749 ~(epctx->interval-1));
1750 if (asap >= epctx->mfindex_last &&
1751 asap <= epctx->mfindex_last + epctx->interval * 4) {
1752 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1753 } else {
1754 xfer->mfindex_kick = asap;
1755 }
1756 } else {
1757 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1758 & TRB_TR_FRAMEID_MASK) << 3;
1759 xfer->mfindex_kick |= mfindex & ~0x3fff;
1760 if (xfer->mfindex_kick + 0x100 < mfindex) {
1761 xfer->mfindex_kick += 0x4000;
1762 }
1763 }
1764 }
1765
xhci_check_intr_iso_kick(XHCIState * xhci,XHCITransfer * xfer,XHCIEPContext * epctx,uint64_t mfindex)1766 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1767 XHCIEPContext *epctx, uint64_t mfindex)
1768 {
1769 if (xfer->mfindex_kick > mfindex) {
1770 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1771 (xfer->mfindex_kick - mfindex) * 125000);
1772 xfer->running_retry = 1;
1773 } else {
1774 epctx->mfindex_last = xfer->mfindex_kick;
1775 timer_del(epctx->kick_timer);
1776 xfer->running_retry = 0;
1777 }
1778 }
1779
1780
xhci_submit(XHCIState * xhci,XHCITransfer * xfer,XHCIEPContext * epctx)1781 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1782 {
1783 uint64_t mfindex;
1784
1785 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid);
1786
1787 xfer->in_xfer = epctx->type>>2;
1788
1789 switch(epctx->type) {
1790 case ET_INTR_OUT:
1791 case ET_INTR_IN:
1792 xfer->pkts = 0;
1793 xfer->iso_xfer = false;
1794 xfer->timed_xfer = true;
1795 mfindex = xhci_mfindex_get(xhci);
1796 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1797 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1798 if (xfer->running_retry) {
1799 return -1;
1800 }
1801 break;
1802 case ET_BULK_OUT:
1803 case ET_BULK_IN:
1804 xfer->pkts = 0;
1805 xfer->iso_xfer = false;
1806 xfer->timed_xfer = false;
1807 break;
1808 case ET_ISO_OUT:
1809 case ET_ISO_IN:
1810 xfer->pkts = 1;
1811 xfer->iso_xfer = true;
1812 xfer->timed_xfer = true;
1813 mfindex = xhci_mfindex_get(xhci);
1814 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1815 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1816 if (xfer->running_retry) {
1817 return -1;
1818 }
1819 break;
1820 default:
1821 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
1822 return -1;
1823 }
1824
1825 if (xhci_setup_packet(xfer) < 0) {
1826 return -1;
1827 }
1828 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1829 xhci_try_complete_packet(xfer);
1830 return 0;
1831 }
1832
xhci_fire_transfer(XHCIState * xhci,XHCITransfer * xfer,XHCIEPContext * epctx)1833 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1834 {
1835 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1836 xfer->epctx->epid, xfer->streamid);
1837 return xhci_submit(xhci, xfer, epctx);
1838 }
1839
xhci_kick_ep(XHCIState * xhci,unsigned int slotid,unsigned int epid,unsigned int streamid)1840 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1841 unsigned int epid, unsigned int streamid)
1842 {
1843 XHCIEPContext *epctx;
1844
1845 assert(slotid >= 1 && slotid <= xhci->numslots);
1846 assert(epid >= 1 && epid <= 31);
1847
1848 if (!xhci->slots[slotid-1].enabled) {
1849 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1850 return;
1851 }
1852 epctx = xhci->slots[slotid-1].eps[epid-1];
1853 if (!epctx) {
1854 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1855 epid, slotid);
1856 return;
1857 }
1858
1859 if (epctx->kick_active) {
1860 return;
1861 }
1862 xhci_kick_epctx(epctx, streamid);
1863 }
1864
xhci_slot_ok(XHCIState * xhci,int slotid)1865 static bool xhci_slot_ok(XHCIState *xhci, int slotid)
1866 {
1867 return (xhci->slots[slotid - 1].uport &&
1868 xhci->slots[slotid - 1].uport->dev &&
1869 xhci->slots[slotid - 1].uport->dev->attached);
1870 }
1871
xhci_kick_epctx(XHCIEPContext * epctx,unsigned int streamid)1872 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
1873 {
1874 XHCIState *xhci = epctx->xhci;
1875 XHCIStreamContext *stctx = NULL;
1876 XHCITransfer *xfer;
1877 XHCIRing *ring;
1878 USBEndpoint *ep = NULL;
1879 uint64_t mfindex;
1880 unsigned int count = 0;
1881 int length;
1882 int i;
1883
1884 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid);
1885 assert(!epctx->kick_active);
1886
1887 /* If the device has been detached, but the guest has not noticed this
1888 yet the 2 above checks will succeed, but we must NOT continue */
1889 if (!xhci_slot_ok(xhci, epctx->slotid)) {
1890 return;
1891 }
1892
1893 if (epctx->retry) {
1894 xfer = epctx->retry;
1895
1896 trace_usb_xhci_xfer_retry(xfer);
1897 assert(xfer->running_retry);
1898 if (xfer->timed_xfer) {
1899 /* time to kick the transfer? */
1900 mfindex = xhci_mfindex_get(xhci);
1901 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1902 if (xfer->running_retry) {
1903 return;
1904 }
1905 xfer->timed_xfer = 0;
1906 xfer->running_retry = 1;
1907 }
1908 if (xfer->iso_xfer) {
1909 /* retry iso transfer */
1910 if (xhci_setup_packet(xfer) < 0) {
1911 return;
1912 }
1913 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1914 assert(xfer->packet.status != USB_RET_NAK);
1915 xhci_try_complete_packet(xfer);
1916 } else {
1917 /* retry nak'ed transfer */
1918 if (xhci_setup_packet(xfer) < 0) {
1919 return;
1920 }
1921 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1922 if (xfer->packet.status == USB_RET_NAK) {
1923 xhci_xfer_unmap(xfer);
1924 return;
1925 }
1926 xhci_try_complete_packet(xfer);
1927 }
1928 assert(!xfer->running_retry);
1929 if (xfer->complete) {
1930 /* update ring dequeue ptr */
1931 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
1932 xhci_ep_free_xfer(epctx->retry);
1933 }
1934 epctx->retry = NULL;
1935 }
1936
1937 if (epctx->state == EP_HALTED) {
1938 DPRINTF("xhci: ep halted, not running schedule\n");
1939 return;
1940 }
1941
1942
1943 if (epctx->nr_pstreams) {
1944 uint32_t err;
1945 stctx = xhci_find_stream(epctx, streamid, &err);
1946 if (stctx == NULL) {
1947 return;
1948 }
1949 ring = &stctx->ring;
1950 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
1951 } else {
1952 ring = &epctx->ring;
1953 streamid = 0;
1954 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
1955 }
1956 if (!ring->dequeue) {
1957 return;
1958 }
1959
1960 epctx->kick_active++;
1961 while (1) {
1962 length = xhci_ring_chain_length(xhci, ring);
1963 if (length <= 0) {
1964 if (epctx->type == ET_ISO_OUT || epctx->type == ET_ISO_IN) {
1965 /* 4.10.3.1 */
1966 XHCIEvent ev = { ER_TRANSFER };
1967 ev.ccode = epctx->type == ET_ISO_IN ?
1968 CC_RING_OVERRUN : CC_RING_UNDERRUN;
1969 ev.slotid = epctx->slotid;
1970 ev.epid = epctx->epid;
1971 ev.ptr = epctx->ring.dequeue;
1972 xhci_event(xhci, &ev, xhci->slots[epctx->slotid-1].intr);
1973 }
1974 break;
1975 }
1976 xfer = xhci_ep_alloc_xfer(epctx, length);
1977 if (xfer == NULL) {
1978 break;
1979 }
1980
1981 for (i = 0; i < length; i++) {
1982 TRBType type;
1983 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
1984 if (!type) {
1985 xhci_die(xhci);
1986 xhci_ep_free_xfer(xfer);
1987 epctx->kick_active--;
1988 return;
1989 }
1990 }
1991 xfer->streamid = streamid;
1992
1993 if (epctx->epid == 1) {
1994 xhci_fire_ctl_transfer(xhci, xfer);
1995 } else {
1996 xhci_fire_transfer(xhci, xfer, epctx);
1997 }
1998 if (!xhci_slot_ok(xhci, epctx->slotid)) {
1999 /* surprise removal -> stop processing */
2000 break;
2001 }
2002 if (xfer->complete) {
2003 /* update ring dequeue ptr */
2004 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
2005 xhci_ep_free_xfer(xfer);
2006 xfer = NULL;
2007 }
2008
2009 if (epctx->state == EP_HALTED) {
2010 break;
2011 }
2012 if (xfer != NULL && xfer->running_retry) {
2013 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2014 epctx->retry = xfer;
2015 xhci_xfer_unmap(xfer);
2016 break;
2017 }
2018 if (count++ > TRANSFER_LIMIT) {
2019 trace_usb_xhci_enforced_limit("transfers");
2020 break;
2021 }
2022 }
2023 epctx->kick_active--;
2024
2025 ep = xhci_epid_to_usbep(epctx);
2026 if (ep) {
2027 usb_device_flush_ep_queue(ep->dev, ep);
2028 }
2029 }
2030
xhci_enable_slot(XHCIState * xhci,unsigned int slotid)2031 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2032 {
2033 trace_usb_xhci_slot_enable(slotid);
2034 assert(slotid >= 1 && slotid <= xhci->numslots);
2035 xhci->slots[slotid-1].enabled = 1;
2036 xhci->slots[slotid-1].uport = NULL;
2037 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2038
2039 return CC_SUCCESS;
2040 }
2041
xhci_disable_slot(XHCIState * xhci,unsigned int slotid)2042 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2043 {
2044 int i;
2045
2046 trace_usb_xhci_slot_disable(slotid);
2047 assert(slotid >= 1 && slotid <= xhci->numslots);
2048
2049 for (i = 1; i <= 31; i++) {
2050 if (xhci->slots[slotid-1].eps[i-1]) {
2051 xhci_disable_ep(xhci, slotid, i);
2052 }
2053 }
2054
2055 xhci->slots[slotid-1].enabled = 0;
2056 xhci->slots[slotid-1].addressed = 0;
2057 xhci->slots[slotid-1].uport = NULL;
2058 xhci->slots[slotid-1].intr = 0;
2059 return CC_SUCCESS;
2060 }
2061
xhci_lookup_uport(XHCIState * xhci,uint32_t * slot_ctx)2062 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2063 {
2064 USBPort *uport;
2065 char path[32];
2066 int i, pos, port;
2067
2068 port = (slot_ctx[1]>>16) & 0xFF;
2069 if (port < 1 || port > xhci->numports) {
2070 return NULL;
2071 }
2072 port = xhci->ports[port-1].uport->index+1;
2073 pos = snprintf(path, sizeof(path), "%d", port);
2074 for (i = 0; i < 5; i++) {
2075 port = (slot_ctx[0] >> 4*i) & 0x0f;
2076 if (!port) {
2077 break;
2078 }
2079 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2080 }
2081
2082 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2083 if (strcmp(uport->path, path) == 0) {
2084 return uport;
2085 }
2086 }
2087 return NULL;
2088 }
2089
xhci_address_slot(XHCIState * xhci,unsigned int slotid,uint64_t pictx,bool bsr)2090 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2091 uint64_t pictx, bool bsr)
2092 {
2093 XHCISlot *slot;
2094 USBPort *uport;
2095 USBDevice *dev;
2096 dma_addr_t ictx, octx, dcbaap;
2097 uint64_t poctx;
2098 uint32_t ictl_ctx[2];
2099 uint32_t slot_ctx[4];
2100 uint32_t ep0_ctx[5];
2101 int i;
2102 TRBCCode res;
2103
2104 assert(slotid >= 1 && slotid <= xhci->numslots);
2105
2106 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2107 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &poctx, MEMTXATTRS_UNSPECIFIED);
2108 ictx = xhci_mask64(pictx);
2109 octx = xhci_mask64(poctx);
2110
2111 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2112 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2113
2114 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2115
2116 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2117 DPRINTF("xhci: invalid input context control %08x %08x\n",
2118 ictl_ctx[0], ictl_ctx[1]);
2119 return CC_TRB_ERROR;
2120 }
2121
2122 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2123 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2124
2125 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2126 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2127
2128 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2129 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2130
2131 uport = xhci_lookup_uport(xhci, slot_ctx);
2132 if (uport == NULL) {
2133 DPRINTF("xhci: port not found\n");
2134 return CC_TRB_ERROR;
2135 }
2136 trace_usb_xhci_slot_address(slotid, uport->path);
2137
2138 dev = uport->dev;
2139 if (!dev || !dev->attached) {
2140 DPRINTF("xhci: port %s not connected\n", uport->path);
2141 return CC_USB_TRANSACTION_ERROR;
2142 }
2143
2144 for (i = 0; i < xhci->numslots; i++) {
2145 if (i == slotid-1) {
2146 continue;
2147 }
2148 if (xhci->slots[i].uport == uport) {
2149 DPRINTF("xhci: port %s already assigned to slot %d\n",
2150 uport->path, i+1);
2151 return CC_TRB_ERROR;
2152 }
2153 }
2154
2155 slot = &xhci->slots[slotid-1];
2156 slot->uport = uport;
2157 slot->ctx = octx;
2158 slot->intr = get_field(slot_ctx[2], TRB_INTR);
2159
2160 /* Make sure device is in USB_STATE_DEFAULT state */
2161 usb_device_reset(dev);
2162 if (bsr) {
2163 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2164 } else {
2165 USBPacket p;
2166 uint8_t buf[1];
2167
2168 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2169 memset(&p, 0, sizeof(p));
2170 usb_packet_addbuf(&p, buf, sizeof(buf));
2171 usb_packet_setup(&p, USB_TOKEN_OUT,
2172 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2173 0, false, false);
2174 usb_device_handle_control(dev, &p,
2175 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2176 slotid, 0, 0, NULL);
2177 assert(p.status != USB_RET_ASYNC);
2178 usb_packet_cleanup(&p);
2179 }
2180
2181 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2182
2183 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2184 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2185 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2186 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2187
2188 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2189 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2190
2191 xhci->slots[slotid-1].addressed = 1;
2192 return res;
2193 }
2194
2195
xhci_configure_slot(XHCIState * xhci,unsigned int slotid,uint64_t pictx,bool dc)2196 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2197 uint64_t pictx, bool dc)
2198 {
2199 dma_addr_t ictx, octx;
2200 uint32_t ictl_ctx[2];
2201 uint32_t slot_ctx[4];
2202 uint32_t islot_ctx[4];
2203 uint32_t ep_ctx[5];
2204 int i;
2205 TRBCCode res;
2206
2207 trace_usb_xhci_slot_configure(slotid);
2208 assert(slotid >= 1 && slotid <= xhci->numslots);
2209
2210 ictx = xhci_mask64(pictx);
2211 octx = xhci->slots[slotid-1].ctx;
2212
2213 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2214 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2215
2216 if (dc) {
2217 for (i = 2; i <= 31; i++) {
2218 if (xhci->slots[slotid-1].eps[i-1]) {
2219 xhci_disable_ep(xhci, slotid, i);
2220 }
2221 }
2222
2223 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2224 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2225 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2226 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2227 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2228 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2229
2230 return CC_SUCCESS;
2231 }
2232
2233 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2234
2235 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2236 DPRINTF("xhci: invalid input context control %08x %08x\n",
2237 ictl_ctx[0], ictl_ctx[1]);
2238 return CC_TRB_ERROR;
2239 }
2240
2241 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2242 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2243
2244 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2245 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2246 return CC_CONTEXT_STATE_ERROR;
2247 }
2248
2249 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2250
2251 for (i = 2; i <= 31; i++) {
2252 if (ictl_ctx[0] & (1<<i)) {
2253 xhci_disable_ep(xhci, slotid, i);
2254 }
2255 if (ictl_ctx[1] & (1<<i)) {
2256 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2257 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2258 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2259 ep_ctx[3], ep_ctx[4]);
2260 xhci_disable_ep(xhci, slotid, i);
2261 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2262 if (res != CC_SUCCESS) {
2263 return res;
2264 }
2265 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2266 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2267 ep_ctx[3], ep_ctx[4]);
2268 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2269 }
2270 }
2271
2272 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2273 if (res != CC_SUCCESS) {
2274 for (i = 2; i <= 31; i++) {
2275 if (ictl_ctx[1] & (1u << i)) {
2276 xhci_disable_ep(xhci, slotid, i);
2277 }
2278 }
2279 return res;
2280 }
2281
2282 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2283 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2284 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2285 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2286 SLOT_CONTEXT_ENTRIES_SHIFT);
2287 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2288 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2289
2290 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2291
2292 return CC_SUCCESS;
2293 }
2294
2295
xhci_evaluate_slot(XHCIState * xhci,unsigned int slotid,uint64_t pictx)2296 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2297 uint64_t pictx)
2298 {
2299 dma_addr_t ictx, octx;
2300 uint32_t ictl_ctx[2];
2301 uint32_t iep0_ctx[5];
2302 uint32_t ep0_ctx[5];
2303 uint32_t islot_ctx[4];
2304 uint32_t slot_ctx[4];
2305
2306 trace_usb_xhci_slot_evaluate(slotid);
2307 assert(slotid >= 1 && slotid <= xhci->numslots);
2308
2309 ictx = xhci_mask64(pictx);
2310 octx = xhci->slots[slotid-1].ctx;
2311
2312 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2313 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2314
2315 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2316
2317 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2318 DPRINTF("xhci: invalid input context control %08x %08x\n",
2319 ictl_ctx[0], ictl_ctx[1]);
2320 return CC_TRB_ERROR;
2321 }
2322
2323 if (ictl_ctx[1] & 0x1) {
2324 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2325
2326 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2327 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2328
2329 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2330
2331 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2332 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2333 /* update interrupter target field */
2334 xhci->slots[slotid-1].intr = get_field(islot_ctx[2], TRB_INTR);
2335 set_field(&slot_ctx[2], xhci->slots[slotid-1].intr, TRB_INTR);
2336
2337 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2338 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2339
2340 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2341 }
2342
2343 if (ictl_ctx[1] & 0x2) {
2344 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2345
2346 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2347 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2348 iep0_ctx[3], iep0_ctx[4]);
2349
2350 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2351
2352 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2353 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2354
2355 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2356 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2357
2358 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2359 }
2360
2361 return CC_SUCCESS;
2362 }
2363
xhci_reset_slot(XHCIState * xhci,unsigned int slotid)2364 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2365 {
2366 uint32_t slot_ctx[4];
2367 dma_addr_t octx;
2368 int i;
2369
2370 trace_usb_xhci_slot_reset(slotid);
2371 assert(slotid >= 1 && slotid <= xhci->numslots);
2372
2373 octx = xhci->slots[slotid-1].ctx;
2374
2375 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2376
2377 for (i = 2; i <= 31; i++) {
2378 if (xhci->slots[slotid-1].eps[i-1]) {
2379 xhci_disable_ep(xhci, slotid, i);
2380 }
2381 }
2382
2383 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2384 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2385 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2386 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2387 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2388 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2389
2390 return CC_SUCCESS;
2391 }
2392
xhci_get_slot(XHCIState * xhci,XHCIEvent * event,XHCITRB * trb)2393 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2394 {
2395 unsigned int slotid;
2396 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2397 if (slotid < 1 || slotid > xhci->numslots) {
2398 DPRINTF("xhci: bad slot id %d\n", slotid);
2399 event->ccode = CC_TRB_ERROR;
2400 return 0;
2401 } else if (!xhci->slots[slotid-1].enabled) {
2402 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2403 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2404 return 0;
2405 }
2406 return slotid;
2407 }
2408
2409 /* cleanup slot state on usb device detach */
xhci_detach_slot(XHCIState * xhci,USBPort * uport)2410 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2411 {
2412 int slot, ep;
2413
2414 for (slot = 0; slot < xhci->numslots; slot++) {
2415 if (xhci->slots[slot].uport == uport) {
2416 break;
2417 }
2418 }
2419 if (slot == xhci->numslots) {
2420 return;
2421 }
2422
2423 for (ep = 0; ep < 31; ep++) {
2424 if (xhci->slots[slot].eps[ep]) {
2425 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2426 }
2427 }
2428 xhci->slots[slot].uport = NULL;
2429 }
2430
xhci_get_port_bandwidth(XHCIState * xhci,uint64_t pctx)2431 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2432 {
2433 dma_addr_t ctx;
2434
2435 DPRINTF("xhci_get_port_bandwidth()\n");
2436
2437 ctx = xhci_mask64(pctx);
2438
2439 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2440
2441 /* TODO: actually implement real values here. This is 80% for all ports. */
2442 if (stb_dma(xhci->as, ctx, 0, MEMTXATTRS_UNSPECIFIED) != MEMTX_OK ||
2443 dma_memory_set(xhci->as, ctx + 1, 80, xhci->numports,
2444 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
2445 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory write failed!\n",
2446 __func__);
2447 return CC_TRB_ERROR;
2448 }
2449
2450 return CC_SUCCESS;
2451 }
2452
rotl(uint32_t v,unsigned count)2453 static uint32_t rotl(uint32_t v, unsigned count)
2454 {
2455 count &= 31;
2456 return (v << count) | (v >> (32 - count));
2457 }
2458
2459
xhci_nec_challenge(uint32_t hi,uint32_t lo)2460 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2461 {
2462 uint32_t val;
2463 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2464 val += rotl(lo + 0x49434878, hi & 0x1F);
2465 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2466 return ~val;
2467 }
2468
xhci_process_commands(XHCIState * xhci)2469 static void xhci_process_commands(XHCIState *xhci)
2470 {
2471 XHCITRB trb;
2472 TRBType type;
2473 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2474 dma_addr_t addr;
2475 unsigned int i, slotid = 0, count = 0;
2476
2477 DPRINTF("xhci_process_commands()\n");
2478 if (!xhci_running(xhci)) {
2479 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2480 return;
2481 }
2482
2483 xhci->crcr_low |= CRCR_CRR;
2484
2485 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2486 event.ptr = addr;
2487 switch (type) {
2488 case CR_ENABLE_SLOT:
2489 for (i = 0; i < xhci->numslots; i++) {
2490 if (!xhci->slots[i].enabled) {
2491 break;
2492 }
2493 }
2494 if (i >= xhci->numslots) {
2495 DPRINTF("xhci: no device slots available\n");
2496 event.ccode = CC_NO_SLOTS_ERROR;
2497 } else {
2498 slotid = i+1;
2499 event.ccode = xhci_enable_slot(xhci, slotid);
2500 }
2501 break;
2502 case CR_DISABLE_SLOT:
2503 slotid = xhci_get_slot(xhci, &event, &trb);
2504 if (slotid) {
2505 event.ccode = xhci_disable_slot(xhci, slotid);
2506 }
2507 break;
2508 case CR_ADDRESS_DEVICE:
2509 slotid = xhci_get_slot(xhci, &event, &trb);
2510 if (slotid) {
2511 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2512 trb.control & TRB_CR_BSR);
2513 }
2514 break;
2515 case CR_CONFIGURE_ENDPOINT:
2516 slotid = xhci_get_slot(xhci, &event, &trb);
2517 if (slotid) {
2518 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2519 trb.control & TRB_CR_DC);
2520 }
2521 break;
2522 case CR_EVALUATE_CONTEXT:
2523 slotid = xhci_get_slot(xhci, &event, &trb);
2524 if (slotid) {
2525 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2526 }
2527 break;
2528 case CR_STOP_ENDPOINT:
2529 slotid = xhci_get_slot(xhci, &event, &trb);
2530 if (slotid) {
2531 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2532 & TRB_CR_EPID_MASK;
2533 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2534 }
2535 break;
2536 case CR_RESET_ENDPOINT:
2537 slotid = xhci_get_slot(xhci, &event, &trb);
2538 if (slotid) {
2539 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2540 & TRB_CR_EPID_MASK;
2541 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2542 }
2543 break;
2544 case CR_SET_TR_DEQUEUE:
2545 slotid = xhci_get_slot(xhci, &event, &trb);
2546 if (slotid) {
2547 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2548 & TRB_CR_EPID_MASK;
2549 unsigned int streamid = (trb.status >> 16) & 0xffff;
2550 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2551 epid, streamid,
2552 trb.parameter);
2553 }
2554 break;
2555 case CR_RESET_DEVICE:
2556 slotid = xhci_get_slot(xhci, &event, &trb);
2557 if (slotid) {
2558 event.ccode = xhci_reset_slot(xhci, slotid);
2559 }
2560 break;
2561 case CR_GET_PORT_BANDWIDTH:
2562 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2563 break;
2564 case CR_NOOP:
2565 event.ccode = CC_SUCCESS;
2566 break;
2567 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2568 if (xhci->nec_quirks) {
2569 event.type = 48; /* NEC reply */
2570 event.length = 0x3034;
2571 } else {
2572 event.ccode = CC_TRB_ERROR;
2573 }
2574 break;
2575 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2576 if (xhci->nec_quirks) {
2577 uint32_t chi = trb.parameter >> 32;
2578 uint32_t clo = trb.parameter;
2579 uint32_t val = xhci_nec_challenge(chi, clo);
2580 event.length = val & 0xFFFF;
2581 event.epid = val >> 16;
2582 slotid = val >> 24;
2583 event.type = 48; /* NEC reply */
2584 } else {
2585 event.ccode = CC_TRB_ERROR;
2586 }
2587 break;
2588 default:
2589 trace_usb_xhci_unimplemented("command", type);
2590 event.ccode = CC_TRB_ERROR;
2591 break;
2592 }
2593 event.slotid = slotid;
2594 xhci_event(xhci, &event, 0);
2595
2596 if (count++ > COMMAND_LIMIT) {
2597 trace_usb_xhci_enforced_limit("commands");
2598 return;
2599 }
2600 }
2601 }
2602
xhci_port_have_device(XHCIPort * port)2603 static bool xhci_port_have_device(XHCIPort *port)
2604 {
2605 if (!port->uport->dev || !port->uport->dev->attached) {
2606 return false; /* no device present */
2607 }
2608 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2609 return false; /* speed mismatch */
2610 }
2611 return true;
2612 }
2613
xhci_port_notify(XHCIPort * port,uint32_t bits)2614 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2615 {
2616 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2617 port->portnr << 24 };
2618
2619 if ((port->portsc & bits) == bits) {
2620 return;
2621 }
2622 trace_usb_xhci_port_notify(port->portnr, bits);
2623 port->portsc |= bits;
2624 if (!xhci_running(port->xhci)) {
2625 return;
2626 }
2627 xhci_event(port->xhci, &ev, 0);
2628 }
2629
xhci_port_update(XHCIPort * port,int is_detach)2630 static void xhci_port_update(XHCIPort *port, int is_detach)
2631 {
2632 uint32_t pls = PLS_RX_DETECT;
2633
2634 assert(port);
2635 port->portsc = PORTSC_PP;
2636 if (!is_detach && xhci_port_have_device(port)) {
2637 port->portsc |= PORTSC_CCS;
2638 switch (port->uport->dev->speed) {
2639 case USB_SPEED_LOW:
2640 port->portsc |= PORTSC_SPEED_LOW;
2641 pls = PLS_POLLING;
2642 break;
2643 case USB_SPEED_FULL:
2644 port->portsc |= PORTSC_SPEED_FULL;
2645 pls = PLS_POLLING;
2646 break;
2647 case USB_SPEED_HIGH:
2648 port->portsc |= PORTSC_SPEED_HIGH;
2649 pls = PLS_POLLING;
2650 break;
2651 case USB_SPEED_SUPER:
2652 port->portsc |= PORTSC_SPEED_SUPER;
2653 port->portsc |= PORTSC_PED;
2654 pls = PLS_U0;
2655 break;
2656 }
2657 }
2658 set_field(&port->portsc, pls, PORTSC_PLS);
2659 trace_usb_xhci_port_link(port->portnr, pls);
2660 xhci_port_notify(port, PORTSC_CSC);
2661 }
2662
xhci_port_reset(XHCIPort * port,bool warm_reset)2663 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2664 {
2665 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2666
2667 if (!xhci_port_have_device(port)) {
2668 return;
2669 }
2670
2671 usb_device_reset(port->uport->dev);
2672
2673 switch (port->uport->dev->speed) {
2674 case USB_SPEED_SUPER:
2675 if (warm_reset) {
2676 port->portsc |= PORTSC_WRC;
2677 }
2678 /* fall through */
2679 case USB_SPEED_LOW:
2680 case USB_SPEED_FULL:
2681 case USB_SPEED_HIGH:
2682 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2683 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2684 port->portsc |= PORTSC_PED;
2685 break;
2686 }
2687
2688 port->portsc &= ~PORTSC_PR;
2689 xhci_port_notify(port, PORTSC_PRC);
2690 }
2691
xhci_reset(DeviceState * dev)2692 static void xhci_reset(DeviceState *dev)
2693 {
2694 XHCIState *xhci = XHCI(dev);
2695 int i;
2696
2697 trace_usb_xhci_reset();
2698 if (!(xhci->usbsts & USBSTS_HCH)) {
2699 DPRINTF("xhci: reset while running!\n");
2700 }
2701
2702 xhci->usbcmd = 0;
2703 xhci->usbsts = USBSTS_HCH;
2704 xhci->dnctrl = 0;
2705 xhci->crcr_low = 0;
2706 xhci->crcr_high = 0;
2707 xhci->dcbaap_low = 0;
2708 xhci->dcbaap_high = 0;
2709 xhci->config = 0;
2710
2711 for (i = 0; i < xhci->numslots; i++) {
2712 xhci_disable_slot(xhci, i+1);
2713 }
2714
2715 for (i = 0; i < xhci->numports; i++) {
2716 xhci_port_update(xhci->ports + i, 0);
2717 }
2718
2719 for (i = 0; i < xhci->numintrs; i++) {
2720 xhci->intr[i].iman = 0;
2721 xhci->intr[i].imod = 0;
2722 xhci->intr[i].erstsz = 0;
2723 xhci->intr[i].erstba_low = 0;
2724 xhci->intr[i].erstba_high = 0;
2725 xhci->intr[i].erdp_low = 0;
2726 xhci->intr[i].erdp_high = 0;
2727
2728 xhci->intr[i].er_ep_idx = 0;
2729 xhci->intr[i].er_pcs = 1;
2730 xhci->intr[i].ev_buffer_put = 0;
2731 xhci->intr[i].ev_buffer_get = 0;
2732 }
2733
2734 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2735 xhci_mfwrap_update(xhci);
2736 }
2737
xhci_cap_read(void * ptr,hwaddr reg,unsigned size)2738 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2739 {
2740 XHCIState *xhci = ptr;
2741 uint32_t ret;
2742
2743 switch (reg) {
2744 case 0x00: /* HCIVERSION, CAPLENGTH */
2745 ret = 0x01000000 | LEN_CAP;
2746 break;
2747 case 0x04: /* HCSPARAMS 1 */
2748 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2749 | (xhci->numintrs<<8) | xhci->numslots;
2750 break;
2751 case 0x08: /* HCSPARAMS 2 */
2752 ret = 0x0000000f;
2753 break;
2754 case 0x0c: /* HCSPARAMS 3 */
2755 ret = 0x00000000;
2756 break;
2757 case 0x10: /* HCCPARAMS */
2758 if (sizeof(dma_addr_t) == 4) {
2759 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2760 } else {
2761 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2762 }
2763 break;
2764 case 0x14: /* DBOFF */
2765 ret = OFF_DOORBELL;
2766 break;
2767 case 0x18: /* RTSOFF */
2768 ret = OFF_RUNTIME;
2769 break;
2770
2771 /* extended capabilities */
2772 case 0x20: /* Supported Protocol:00 */
2773 ret = 0x02000402; /* USB 2.0 */
2774 break;
2775 case 0x24: /* Supported Protocol:04 */
2776 ret = 0x20425355; /* "USB " */
2777 break;
2778 case 0x28: /* Supported Protocol:08 */
2779 ret = (xhci->numports_2 << 8) | (xhci->numports_3 + 1);
2780 break;
2781 case 0x2c: /* Supported Protocol:0c */
2782 ret = 0x00000000; /* reserved */
2783 break;
2784 case 0x30: /* Supported Protocol:00 */
2785 ret = 0x03000002; /* USB 3.0 */
2786 break;
2787 case 0x34: /* Supported Protocol:04 */
2788 ret = 0x20425355; /* "USB " */
2789 break;
2790 case 0x38: /* Supported Protocol:08 */
2791 ret = (xhci->numports_3 << 8) | 1;
2792 break;
2793 case 0x3c: /* Supported Protocol:0c */
2794 ret = 0x00000000; /* reserved */
2795 break;
2796 default:
2797 trace_usb_xhci_unimplemented("cap read", reg);
2798 ret = 0;
2799 }
2800
2801 trace_usb_xhci_cap_read(reg, ret);
2802 return ret;
2803 }
2804
xhci_port_read(void * ptr,hwaddr reg,unsigned size)2805 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2806 {
2807 XHCIPort *port = ptr;
2808 uint32_t ret;
2809
2810 switch (reg) {
2811 case 0x00: /* PORTSC */
2812 ret = port->portsc;
2813 break;
2814 case 0x04: /* PORTPMSC */
2815 case 0x08: /* PORTLI */
2816 ret = 0;
2817 break;
2818 case 0x0c: /* PORTHLPMC */
2819 ret = 0;
2820 qemu_log_mask(LOG_UNIMP, "%s: read from port register PORTHLPMC",
2821 __func__);
2822 break;
2823 default:
2824 qemu_log_mask(LOG_GUEST_ERROR,
2825 "%s: read from port offset 0x%" HWADDR_PRIx,
2826 __func__, reg);
2827 ret = 0;
2828 }
2829
2830 trace_usb_xhci_port_read(port->portnr, reg, ret);
2831 return ret;
2832 }
2833
xhci_port_write(void * ptr,hwaddr reg,uint64_t val,unsigned size)2834 static void xhci_port_write(void *ptr, hwaddr reg,
2835 uint64_t val, unsigned size)
2836 {
2837 XHCIPort *port = ptr;
2838 uint32_t portsc, notify;
2839
2840 trace_usb_xhci_port_write(port->portnr, reg, val);
2841
2842 switch (reg) {
2843 case 0x00: /* PORTSC */
2844 /* write-1-to-start bits */
2845 if (val & PORTSC_WPR) {
2846 xhci_port_reset(port, true);
2847 break;
2848 }
2849 if (val & PORTSC_PR) {
2850 xhci_port_reset(port, false);
2851 break;
2852 }
2853
2854 portsc = port->portsc;
2855 notify = 0;
2856 /* write-1-to-clear bits*/
2857 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2858 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2859 if (val & PORTSC_LWS) {
2860 /* overwrite PLS only when LWS=1 */
2861 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2862 uint32_t new_pls = get_field(val, PORTSC_PLS);
2863 switch (new_pls) {
2864 case PLS_U0:
2865 if (old_pls != PLS_U0) {
2866 set_field(&portsc, new_pls, PORTSC_PLS);
2867 trace_usb_xhci_port_link(port->portnr, new_pls);
2868 notify = PORTSC_PLC;
2869 }
2870 break;
2871 case PLS_U3:
2872 if (old_pls < PLS_U3) {
2873 set_field(&portsc, new_pls, PORTSC_PLS);
2874 trace_usb_xhci_port_link(port->portnr, new_pls);
2875 }
2876 break;
2877 case PLS_RESUME:
2878 /* windows does this for some reason, don't spam stderr */
2879 break;
2880 default:
2881 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2882 __func__, old_pls, new_pls);
2883 break;
2884 }
2885 }
2886 /* read/write bits */
2887 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2888 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2889 port->portsc = portsc;
2890 if (notify) {
2891 xhci_port_notify(port, notify);
2892 }
2893 break;
2894 case 0x04: /* PORTPMSC */
2895 case 0x0c: /* PORTHLPMC */
2896 qemu_log_mask(LOG_UNIMP,
2897 "%s: write 0x%" PRIx64
2898 " (%u bytes) to port register at offset 0x%" HWADDR_PRIx,
2899 __func__, val, size, reg);
2900 break;
2901 case 0x08: /* PORTLI */
2902 qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only PORTLI register",
2903 __func__);
2904 break;
2905 default:
2906 qemu_log_mask(LOG_GUEST_ERROR,
2907 "%s: write 0x%" PRIx64 " (%u bytes) to unknown port "
2908 "register at offset 0x%" HWADDR_PRIx,
2909 __func__, val, size, reg);
2910 break;
2911 }
2912 }
2913
xhci_oper_read(void * ptr,hwaddr reg,unsigned size)2914 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
2915 {
2916 XHCIState *xhci = ptr;
2917 uint32_t ret;
2918
2919 switch (reg) {
2920 case 0x00: /* USBCMD */
2921 ret = xhci->usbcmd;
2922 break;
2923 case 0x04: /* USBSTS */
2924 ret = xhci->usbsts;
2925 break;
2926 case 0x08: /* PAGESIZE */
2927 ret = 1; /* 4KiB */
2928 break;
2929 case 0x14: /* DNCTRL */
2930 ret = xhci->dnctrl;
2931 break;
2932 case 0x18: /* CRCR low */
2933 ret = xhci->crcr_low & ~0xe;
2934 break;
2935 case 0x1c: /* CRCR high */
2936 ret = xhci->crcr_high;
2937 break;
2938 case 0x30: /* DCBAAP low */
2939 ret = xhci->dcbaap_low;
2940 break;
2941 case 0x34: /* DCBAAP high */
2942 ret = xhci->dcbaap_high;
2943 break;
2944 case 0x38: /* CONFIG */
2945 ret = xhci->config;
2946 break;
2947 default:
2948 trace_usb_xhci_unimplemented("oper read", reg);
2949 ret = 0;
2950 }
2951
2952 trace_usb_xhci_oper_read(reg, ret);
2953 return ret;
2954 }
2955
xhci_oper_write(void * ptr,hwaddr reg,uint64_t val,unsigned size)2956 static void xhci_oper_write(void *ptr, hwaddr reg,
2957 uint64_t val, unsigned size)
2958 {
2959 XHCIState *xhci = XHCI(ptr);
2960
2961 trace_usb_xhci_oper_write(reg, val);
2962
2963 switch (reg) {
2964 case 0x00: /* USBCMD */
2965 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2966 xhci_run(xhci);
2967 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2968 xhci_stop(xhci);
2969 }
2970 if (val & USBCMD_CSS) {
2971 /* save state */
2972 xhci->usbsts &= ~USBSTS_SRE;
2973 }
2974 if (val & USBCMD_CRS) {
2975 /* restore state */
2976 xhci->usbsts |= USBSTS_SRE;
2977 }
2978 xhci->usbcmd = val & 0xc0f;
2979 xhci_mfwrap_update(xhci);
2980 if (val & USBCMD_HCRST) {
2981 xhci_reset(DEVICE(xhci));
2982 }
2983 xhci_intr_update(xhci, 0);
2984 break;
2985
2986 case 0x04: /* USBSTS */
2987 /* these bits are write-1-to-clear */
2988 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2989 xhci_intr_update(xhci, 0);
2990 break;
2991
2992 case 0x14: /* DNCTRL */
2993 xhci->dnctrl = val & 0xffff;
2994 break;
2995 case 0x18: /* CRCR low */
2996 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2997 break;
2998 case 0x1c: /* CRCR high */
2999 xhci->crcr_high = val;
3000 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3001 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3002 xhci->crcr_low &= ~CRCR_CRR;
3003 xhci_event(xhci, &event, 0);
3004 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3005 } else {
3006 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3007 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3008 }
3009 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3010 break;
3011 case 0x30: /* DCBAAP low */
3012 xhci->dcbaap_low = val & 0xffffffc0;
3013 break;
3014 case 0x34: /* DCBAAP high */
3015 xhci->dcbaap_high = val;
3016 break;
3017 case 0x38: /* CONFIG */
3018 xhci->config = val & 0xff;
3019 break;
3020 default:
3021 trace_usb_xhci_unimplemented("oper write", reg);
3022 }
3023 }
3024
xhci_runtime_read(void * ptr,hwaddr reg,unsigned size)3025 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3026 unsigned size)
3027 {
3028 XHCIState *xhci = ptr;
3029 uint32_t ret = 0;
3030
3031 if (reg < 0x20) {
3032 switch (reg) {
3033 case 0x00: /* MFINDEX */
3034 ret = xhci_mfindex_get(xhci) & 0x3fff;
3035 break;
3036 default:
3037 trace_usb_xhci_unimplemented("runtime read", reg);
3038 break;
3039 }
3040 } else {
3041 int v = (reg - 0x20) / 0x20;
3042 XHCIInterrupter *intr = &xhci->intr[v];
3043 switch (reg & 0x1f) {
3044 case 0x00: /* IMAN */
3045 ret = intr->iman;
3046 break;
3047 case 0x04: /* IMOD */
3048 ret = intr->imod;
3049 break;
3050 case 0x08: /* ERSTSZ */
3051 ret = intr->erstsz;
3052 break;
3053 case 0x10: /* ERSTBA low */
3054 ret = intr->erstba_low;
3055 break;
3056 case 0x14: /* ERSTBA high */
3057 ret = intr->erstba_high;
3058 break;
3059 case 0x18: /* ERDP low */
3060 ret = intr->erdp_low;
3061 break;
3062 case 0x1c: /* ERDP high */
3063 ret = intr->erdp_high;
3064 break;
3065 }
3066 }
3067
3068 trace_usb_xhci_runtime_read(reg, ret);
3069 return ret;
3070 }
3071
xhci_runtime_write(void * ptr,hwaddr reg,uint64_t val,unsigned size)3072 static void xhci_runtime_write(void *ptr, hwaddr reg,
3073 uint64_t val, unsigned size)
3074 {
3075 XHCIState *xhci = ptr;
3076 XHCIInterrupter *intr;
3077 int v;
3078
3079 trace_usb_xhci_runtime_write(reg, val);
3080
3081 if (reg < 0x20) {
3082 trace_usb_xhci_unimplemented("runtime write", reg);
3083 return;
3084 }
3085 v = (reg - 0x20) / 0x20;
3086 intr = &xhci->intr[v];
3087
3088 switch (reg & 0x1f) {
3089 case 0x00: /* IMAN */
3090 if (val & IMAN_IP) {
3091 intr->iman &= ~IMAN_IP;
3092 }
3093 intr->iman &= ~IMAN_IE;
3094 intr->iman |= val & IMAN_IE;
3095 xhci_intr_update(xhci, v);
3096 break;
3097 case 0x04: /* IMOD */
3098 intr->imod = val;
3099 break;
3100 case 0x08: /* ERSTSZ */
3101 intr->erstsz = val & 0xffff;
3102 break;
3103 case 0x10: /* ERSTBA low */
3104 if (xhci->nec_quirks) {
3105 /* NEC driver bug: it doesn't align this to 64 bytes */
3106 intr->erstba_low = val & 0xfffffff0;
3107 } else {
3108 intr->erstba_low = val & 0xffffffc0;
3109 }
3110 break;
3111 case 0x14: /* ERSTBA high */
3112 intr->erstba_high = val;
3113 xhci_er_reset(xhci, v);
3114 break;
3115 case 0x18: /* ERDP low */
3116 if (val & ERDP_EHB) {
3117 intr->erdp_low &= ~ERDP_EHB;
3118 }
3119 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3120 if (val & ERDP_EHB) {
3121 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
3122 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE;
3123 if (erdp >= intr->er_start &&
3124 erdp < (intr->er_start + TRB_SIZE * intr->er_size) &&
3125 dp_idx != intr->er_ep_idx) {
3126 xhci_intr_raise(xhci, v);
3127 }
3128 }
3129 break;
3130 case 0x1c: /* ERDP high */
3131 intr->erdp_high = val;
3132 break;
3133 default:
3134 trace_usb_xhci_unimplemented("oper write", reg);
3135 }
3136 }
3137
xhci_doorbell_read(void * ptr,hwaddr reg,unsigned size)3138 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3139 unsigned size)
3140 {
3141 /* doorbells always read as 0 */
3142 trace_usb_xhci_doorbell_read(reg, 0);
3143 return 0;
3144 }
3145
xhci_doorbell_write(void * ptr,hwaddr reg,uint64_t val,unsigned size)3146 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3147 uint64_t val, unsigned size)
3148 {
3149 XHCIState *xhci = ptr;
3150 unsigned int epid, streamid;
3151
3152 trace_usb_xhci_doorbell_write(reg, val);
3153
3154 if (!xhci_running(xhci)) {
3155 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3156 return;
3157 }
3158
3159 reg >>= 2;
3160
3161 if (reg == 0) {
3162 if (val == 0) {
3163 xhci_process_commands(xhci);
3164 } else {
3165 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3166 (uint32_t)val);
3167 }
3168 } else {
3169 epid = val & 0xff;
3170 streamid = (val >> 16) & 0xffff;
3171 if (reg > xhci->numslots) {
3172 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3173 } else if (epid == 0 || epid > 31) {
3174 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3175 (int)reg, (uint32_t)val);
3176 } else {
3177 xhci_kick_ep(xhci, reg, epid, streamid);
3178 }
3179 }
3180 }
3181
xhci_cap_write(void * opaque,hwaddr addr,uint64_t val,unsigned width)3182 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3183 unsigned width)
3184 {
3185 /* nothing */
3186 }
3187
3188 static const MemoryRegionOps xhci_cap_ops = {
3189 .read = xhci_cap_read,
3190 .write = xhci_cap_write,
3191 .valid.min_access_size = 1,
3192 .valid.max_access_size = 4,
3193 .impl.min_access_size = 4,
3194 .impl.max_access_size = 4,
3195 .endianness = DEVICE_LITTLE_ENDIAN,
3196 };
3197
3198 static const MemoryRegionOps xhci_oper_ops = {
3199 .read = xhci_oper_read,
3200 .write = xhci_oper_write,
3201 .valid.min_access_size = 4,
3202 .valid.max_access_size = sizeof(dma_addr_t),
3203 .endianness = DEVICE_LITTLE_ENDIAN,
3204 };
3205
3206 static const MemoryRegionOps xhci_port_ops = {
3207 .read = xhci_port_read,
3208 .write = xhci_port_write,
3209 .valid.min_access_size = 4,
3210 .valid.max_access_size = 4,
3211 .endianness = DEVICE_LITTLE_ENDIAN,
3212 };
3213
3214 static const MemoryRegionOps xhci_runtime_ops = {
3215 .read = xhci_runtime_read,
3216 .write = xhci_runtime_write,
3217 .valid.min_access_size = 4,
3218 .valid.max_access_size = sizeof(dma_addr_t),
3219 .endianness = DEVICE_LITTLE_ENDIAN,
3220 };
3221
3222 static const MemoryRegionOps xhci_doorbell_ops = {
3223 .read = xhci_doorbell_read,
3224 .write = xhci_doorbell_write,
3225 .valid.min_access_size = 4,
3226 .valid.max_access_size = 4,
3227 .endianness = DEVICE_LITTLE_ENDIAN,
3228 };
3229
xhci_attach(USBPort * usbport)3230 static void xhci_attach(USBPort *usbport)
3231 {
3232 XHCIState *xhci = usbport->opaque;
3233 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3234
3235 xhci_port_update(port, 0);
3236 }
3237
xhci_detach(USBPort * usbport)3238 static void xhci_detach(USBPort *usbport)
3239 {
3240 XHCIState *xhci = usbport->opaque;
3241 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3242
3243 xhci_detach_slot(xhci, usbport);
3244 xhci_port_update(port, 1);
3245 }
3246
xhci_wakeup(USBPort * usbport)3247 static void xhci_wakeup(USBPort *usbport)
3248 {
3249 XHCIState *xhci = usbport->opaque;
3250 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3251
3252 assert(port);
3253 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3254 return;
3255 }
3256 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3257 xhci_port_notify(port, PORTSC_PLC);
3258 }
3259
xhci_complete(USBPort * port,USBPacket * packet)3260 static void xhci_complete(USBPort *port, USBPacket *packet)
3261 {
3262 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3263
3264 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3265 xhci_ep_nuke_one_xfer(xfer, 0);
3266 return;
3267 }
3268 xhci_try_complete_packet(xfer);
3269 xhci_kick_epctx(xfer->epctx, xfer->streamid);
3270 if (xfer->complete) {
3271 xhci_ep_free_xfer(xfer);
3272 }
3273 }
3274
xhci_child_detach(USBPort * uport,USBDevice * child)3275 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3276 {
3277 USBBus *bus = usb_bus_from_device(child);
3278 XHCIState *xhci = container_of(bus, XHCIState, bus);
3279
3280 xhci_detach_slot(xhci, child->port);
3281 }
3282
3283 static USBPortOps xhci_uport_ops = {
3284 .attach = xhci_attach,
3285 .detach = xhci_detach,
3286 .wakeup = xhci_wakeup,
3287 .complete = xhci_complete,
3288 .child_detach = xhci_child_detach,
3289 };
3290
xhci_find_epid(USBEndpoint * ep)3291 static int xhci_find_epid(USBEndpoint *ep)
3292 {
3293 if (ep->nr == 0) {
3294 return 1;
3295 }
3296 if (ep->pid == USB_TOKEN_IN) {
3297 return ep->nr * 2 + 1;
3298 } else {
3299 return ep->nr * 2;
3300 }
3301 }
3302
xhci_epid_to_usbep(XHCIEPContext * epctx)3303 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx)
3304 {
3305 USBPort *uport;
3306 uint32_t token;
3307
3308 if (!epctx) {
3309 return NULL;
3310 }
3311 uport = epctx->xhci->slots[epctx->slotid - 1].uport;
3312 if (!uport || !uport->dev) {
3313 return NULL;
3314 }
3315 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT;
3316 return usb_ep_get(uport->dev, token, epctx->epid >> 1);
3317 }
3318
xhci_wakeup_endpoint(USBBus * bus,USBEndpoint * ep,unsigned int stream)3319 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3320 unsigned int stream)
3321 {
3322 XHCIState *xhci = container_of(bus, XHCIState, bus);
3323 int slotid;
3324
3325 DPRINTF("%s\n", __func__);
3326 slotid = ep->dev->addr;
3327 if (slotid == 0 || slotid > xhci->numslots ||
3328 !xhci->slots[slotid - 1].enabled) {
3329 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3330 return;
3331 }
3332 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3333 }
3334
3335 static USBBusOps xhci_bus_ops = {
3336 .wakeup_endpoint = xhci_wakeup_endpoint,
3337 };
3338
usb_xhci_init(XHCIState * xhci)3339 static void usb_xhci_init(XHCIState *xhci)
3340 {
3341 XHCIPort *port;
3342 unsigned int i, usbports, speedmask;
3343
3344 xhci->usbsts = USBSTS_HCH;
3345
3346 if (xhci->numports_2 > XHCI_MAXPORTS_2) {
3347 xhci->numports_2 = XHCI_MAXPORTS_2;
3348 }
3349 if (xhci->numports_3 > XHCI_MAXPORTS_3) {
3350 xhci->numports_3 = XHCI_MAXPORTS_3;
3351 }
3352 usbports = MAX(xhci->numports_2, xhci->numports_3);
3353 xhci->numports = xhci->numports_2 + xhci->numports_3;
3354
3355 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque);
3356
3357 for (i = 0; i < usbports; i++) {
3358 speedmask = 0;
3359 if (i < xhci->numports_2) {
3360 port = &xhci->ports[i + xhci->numports_3];
3361 port->portnr = i + 1 + xhci->numports_3;
3362 port->uport = &xhci->uports[i];
3363 port->speedmask =
3364 USB_SPEED_MASK_LOW |
3365 USB_SPEED_MASK_FULL |
3366 USB_SPEED_MASK_HIGH;
3367 assert(i < XHCI_MAXPORTS);
3368 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3369 speedmask |= port->speedmask;
3370 }
3371 if (i < xhci->numports_3) {
3372 port = &xhci->ports[i];
3373 port->portnr = i + 1;
3374 port->uport = &xhci->uports[i];
3375 port->speedmask = USB_SPEED_MASK_SUPER;
3376 assert(i < XHCI_MAXPORTS);
3377 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3378 speedmask |= port->speedmask;
3379 }
3380 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3381 &xhci_uport_ops, speedmask);
3382 }
3383 }
3384
usb_xhci_realize(DeviceState * dev,Error ** errp)3385 static void usb_xhci_realize(DeviceState *dev, Error **errp)
3386 {
3387 int i;
3388
3389 XHCIState *xhci = XHCI(dev);
3390
3391 if (xhci->numintrs > XHCI_MAXINTRS) {
3392 xhci->numintrs = XHCI_MAXINTRS;
3393 }
3394 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3395 xhci->numintrs++;
3396 }
3397 if (xhci->numintrs < 1) {
3398 xhci->numintrs = 1;
3399 }
3400 if (xhci->numslots > XHCI_MAXSLOTS) {
3401 xhci->numslots = XHCI_MAXSLOTS;
3402 }
3403 if (xhci->numslots < 1) {
3404 xhci->numslots = 1;
3405 }
3406 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3407 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3408 } else {
3409 xhci->max_pstreams_mask = 0;
3410 }
3411
3412 usb_xhci_init(xhci);
3413 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3414
3415 memory_region_init(&xhci->mem, OBJECT(dev), "xhci", XHCI_LEN_REGS);
3416 memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci,
3417 "capabilities", LEN_CAP);
3418 memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci,
3419 "operational", 0x400);
3420 memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops,
3421 xhci, "runtime", LEN_RUNTIME);
3422 memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops,
3423 xhci, "doorbell", LEN_DOORBELL);
3424
3425 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3426 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3427 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3428 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3429
3430 for (i = 0; i < xhci->numports; i++) {
3431 XHCIPort *port = &xhci->ports[i];
3432 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3433 port->xhci = xhci;
3434 memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port,
3435 port->name, 0x10);
3436 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3437 }
3438 }
3439
usb_xhci_unrealize(DeviceState * dev)3440 static void usb_xhci_unrealize(DeviceState *dev)
3441 {
3442 int i;
3443 XHCIState *xhci = XHCI(dev);
3444
3445 trace_usb_xhci_exit();
3446
3447 for (i = 0; i < xhci->numslots; i++) {
3448 xhci_disable_slot(xhci, i + 1);
3449 }
3450
3451 if (xhci->mfwrap_timer) {
3452 timer_free(xhci->mfwrap_timer);
3453 xhci->mfwrap_timer = NULL;
3454 }
3455
3456 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3457 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3458 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3459 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3460
3461 for (i = 0; i < xhci->numports; i++) {
3462 XHCIPort *port = &xhci->ports[i];
3463 memory_region_del_subregion(&xhci->mem, &port->mem);
3464 }
3465
3466 usb_bus_release(&xhci->bus);
3467 }
3468
usb_xhci_post_load(void * opaque,int version_id)3469 static int usb_xhci_post_load(void *opaque, int version_id)
3470 {
3471 XHCIState *xhci = opaque;
3472 XHCISlot *slot;
3473 XHCIEPContext *epctx;
3474 dma_addr_t dcbaap, pctx;
3475 uint32_t slot_ctx[4];
3476 uint32_t ep_ctx[5];
3477 int slotid, epid, state;
3478 uint64_t addr;
3479
3480 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3481
3482 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3483 slot = &xhci->slots[slotid-1];
3484 if (!slot->addressed) {
3485 continue;
3486 }
3487 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &addr, MEMTXATTRS_UNSPECIFIED);
3488 slot->ctx = xhci_mask64(addr);
3489
3490 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3491 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3492 if (!slot->uport) {
3493 /* should not happen, but may trigger on guest bugs */
3494 slot->enabled = 0;
3495 slot->addressed = 0;
3496 continue;
3497 }
3498 assert(slot->uport && slot->uport->dev);
3499
3500 for (epid = 1; epid <= 31; epid++) {
3501 pctx = slot->ctx + 32 * epid;
3502 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3503 state = ep_ctx[0] & EP_STATE_MASK;
3504 if (state == EP_DISABLED) {
3505 continue;
3506 }
3507 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3508 slot->eps[epid-1] = epctx;
3509 xhci_init_epctx(epctx, pctx, ep_ctx);
3510 epctx->state = state;
3511 if (state == EP_RUNNING) {
3512 /* kick endpoint after vmload is finished */
3513 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3514 }
3515 }
3516 }
3517 return 0;
3518 }
3519
3520 static const VMStateDescription vmstate_xhci_ring = {
3521 .name = "xhci-ring",
3522 .version_id = 1,
3523 .fields = (const VMStateField[]) {
3524 VMSTATE_UINT64(dequeue, XHCIRing),
3525 VMSTATE_BOOL(ccs, XHCIRing),
3526 VMSTATE_END_OF_LIST()
3527 }
3528 };
3529
3530 static const VMStateDescription vmstate_xhci_port = {
3531 .name = "xhci-port",
3532 .version_id = 1,
3533 .fields = (const VMStateField[]) {
3534 VMSTATE_UINT32(portsc, XHCIPort),
3535 VMSTATE_END_OF_LIST()
3536 }
3537 };
3538
3539 static const VMStateDescription vmstate_xhci_slot = {
3540 .name = "xhci-slot",
3541 .version_id = 1,
3542 .fields = (const VMStateField[]) {
3543 VMSTATE_BOOL(enabled, XHCISlot),
3544 VMSTATE_BOOL(addressed, XHCISlot),
3545 VMSTATE_END_OF_LIST()
3546 }
3547 };
3548
3549 static const VMStateDescription vmstate_xhci_event = {
3550 .name = "xhci-event",
3551 .version_id = 1,
3552 .fields = (const VMStateField[]) {
3553 VMSTATE_UINT32(type, XHCIEvent),
3554 VMSTATE_UINT32(ccode, XHCIEvent),
3555 VMSTATE_UINT64(ptr, XHCIEvent),
3556 VMSTATE_UINT32(length, XHCIEvent),
3557 VMSTATE_UINT32(flags, XHCIEvent),
3558 VMSTATE_UINT8(slotid, XHCIEvent),
3559 VMSTATE_UINT8(epid, XHCIEvent),
3560 VMSTATE_END_OF_LIST()
3561 }
3562 };
3563
xhci_er_full(void * opaque,int version_id)3564 static bool xhci_er_full(void *opaque, int version_id)
3565 {
3566 return false;
3567 }
3568
3569 static const VMStateDescription vmstate_xhci_intr = {
3570 .name = "xhci-intr",
3571 .version_id = 1,
3572 .fields = (const VMStateField[]) {
3573 /* registers */
3574 VMSTATE_UINT32(iman, XHCIInterrupter),
3575 VMSTATE_UINT32(imod, XHCIInterrupter),
3576 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3577 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3578 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3579 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3580 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3581
3582 /* state */
3583 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3584 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3585 VMSTATE_UINT64(er_start, XHCIInterrupter),
3586 VMSTATE_UINT32(er_size, XHCIInterrupter),
3587 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3588
3589 /* event queue (used if ring is full) */
3590 VMSTATE_BOOL(er_full_unused, XHCIInterrupter),
3591 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3592 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3593 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3594 xhci_er_full, 1,
3595 vmstate_xhci_event, XHCIEvent),
3596
3597 VMSTATE_END_OF_LIST()
3598 }
3599 };
3600
3601 const VMStateDescription vmstate_xhci = {
3602 .name = "xhci-core",
3603 .version_id = 1,
3604 .post_load = usb_xhci_post_load,
3605 .fields = (const VMStateField[]) {
3606 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3607 vmstate_xhci_port, XHCIPort),
3608 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3609 vmstate_xhci_slot, XHCISlot),
3610 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3611 vmstate_xhci_intr, XHCIInterrupter),
3612
3613 /* Operational Registers */
3614 VMSTATE_UINT32(usbcmd, XHCIState),
3615 VMSTATE_UINT32(usbsts, XHCIState),
3616 VMSTATE_UINT32(dnctrl, XHCIState),
3617 VMSTATE_UINT32(crcr_low, XHCIState),
3618 VMSTATE_UINT32(crcr_high, XHCIState),
3619 VMSTATE_UINT32(dcbaap_low, XHCIState),
3620 VMSTATE_UINT32(dcbaap_high, XHCIState),
3621 VMSTATE_UINT32(config, XHCIState),
3622
3623 /* Runtime Registers & state */
3624 VMSTATE_INT64(mfindex_start, XHCIState),
3625 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3626 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3627
3628 VMSTATE_END_OF_LIST()
3629 }
3630 };
3631
3632 static const Property xhci_properties[] = {
3633 DEFINE_PROP_BIT("streams", XHCIState, flags,
3634 XHCI_FLAG_ENABLE_STREAMS, true),
3635 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3636 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3637 DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE,
3638 DeviceState *),
3639 };
3640
xhci_class_init(ObjectClass * klass,void * data)3641 static void xhci_class_init(ObjectClass *klass, void *data)
3642 {
3643 DeviceClass *dc = DEVICE_CLASS(klass);
3644
3645 dc->realize = usb_xhci_realize;
3646 dc->unrealize = usb_xhci_unrealize;
3647 device_class_set_legacy_reset(dc, xhci_reset);
3648 device_class_set_props(dc, xhci_properties);
3649 dc->user_creatable = false;
3650 }
3651
3652 static const TypeInfo xhci_info = {
3653 .name = TYPE_XHCI,
3654 .parent = TYPE_DEVICE,
3655 .instance_size = sizeof(XHCIState),
3656 .class_init = xhci_class_init,
3657 };
3658
xhci_register_types(void)3659 static void xhci_register_types(void)
3660 {
3661 type_register_static(&xhci_info);
3662 }
3663
3664 type_init(xhci_register_types)
3665