1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * max98095.c -- MAX98095 ALSA SoC Audio driver
4 *
5 * Copyright 2011 Maxim Integrated Products
6 *
7 * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com)
8 */
9
10 #include <common.h>
11 #include <audio_codec.h>
12 #include <dm.h>
13 #include <div64.h>
14 #include <fdtdec.h>
15 #include <i2c.h>
16 #include <sound.h>
17 #include <asm/gpio.h>
18 #include "i2s.h"
19 #include "max98095.h"
20
21 /* Index 0 is reserved. */
22 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
23 88200, 96000};
24
25 /*
26 * codec mclk clock divider coefficients based on sampling rate
27 *
28 * @param rate sampling rate
29 * @param value address of indexvalue to be stored
30 *
31 * @return 0 for success or negative error code.
32 */
rate_value(int rate,u8 * value)33 static int rate_value(int rate, u8 *value)
34 {
35 int i;
36
37 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
38 if (rate_table[i] >= rate) {
39 *value = i;
40 return 0;
41 }
42 }
43 *value = 1;
44
45 return -EINVAL;
46 }
47
48 /*
49 * Sets hw params for max98095
50 *
51 * @param priv max98095 information pointer
52 * @param rate Sampling rate
53 * @param bits_per_sample Bits per sample
54 *
55 * @return 0 for success or negative error code.
56 */
max98095_hw_params(struct maxim_priv * priv,enum en_max_audio_interface aif_id,unsigned int rate,unsigned int bits_per_sample)57 static int max98095_hw_params(struct maxim_priv *priv,
58 enum en_max_audio_interface aif_id,
59 unsigned int rate, unsigned int bits_per_sample)
60 {
61 u8 regval;
62 int error;
63 unsigned short M98095_DAI_CLKMODE;
64 unsigned short M98095_DAI_FORMAT;
65 unsigned short M98095_DAI_FILTERS;
66
67 if (aif_id == AIF1) {
68 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
69 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
70 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
71 } else {
72 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
73 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
74 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
75 }
76
77 switch (bits_per_sample) {
78 case 16:
79 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0);
80 break;
81 case 24:
82 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS,
83 M98095_DAI_WS);
84 break;
85 default:
86 debug("%s: Illegal bits per sample %d.\n",
87 __func__, bits_per_sample);
88 return -EINVAL;
89 }
90
91 if (rate_value(rate, ®val)) {
92 debug("%s: Failed to set sample rate to %d.\n",
93 __func__, rate);
94 return -EINVAL;
95 }
96 priv->rate = rate;
97
98 error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK,
99 regval);
100
101 /* Update sample rate mode */
102 if (rate < 50000)
103 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
104 M98095_DAI_DHF, 0);
105 else
106 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
107 M98095_DAI_DHF, M98095_DAI_DHF);
108
109 if (error < 0) {
110 debug("%s: Error setting hardware params.\n", __func__);
111 return -EIO;
112 }
113
114 return 0;
115 }
116
117 /*
118 * Configures Audio interface system clock for the given frequency
119 *
120 * @param priv max98095 information
121 * @param freq Sampling frequency in Hz
122 *
123 * @return 0 for success or negative error code.
124 */
max98095_set_sysclk(struct maxim_priv * priv,unsigned int freq)125 static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq)
126 {
127 int error = 0;
128
129 /* Requested clock frequency is already setup */
130 if (freq == priv->sysclk)
131 return 0;
132
133 /* Setup clocks for slave mode, and using the PLL
134 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
135 * 0x02 (when master clk is 20MHz to 40MHz)..
136 * 0x03 (when master clk is 40MHz to 60MHz)..
137 */
138 if ((freq >= 10000000) && (freq < 20000000)) {
139 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10);
140 } else if ((freq >= 20000000) && (freq < 40000000)) {
141 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20);
142 } else if ((freq >= 40000000) && (freq < 60000000)) {
143 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30);
144 } else {
145 debug("%s: Invalid master clock frequency\n", __func__);
146 return -EINVAL;
147 }
148
149 debug("%s: Clock at %uHz\n", __func__, freq);
150
151 if (error < 0)
152 return -EIO;
153
154 priv->sysclk = freq;
155 return 0;
156 }
157
158 /*
159 * Sets Max98095 I2S format
160 *
161 * @param priv max98095 information
162 * @param fmt i2S format - supports a subset of the options defined
163 * in i2s.h.
164 *
165 * @return 0 for success or negative error code.
166 */
max98095_set_fmt(struct maxim_priv * priv,int fmt,enum en_max_audio_interface aif_id)167 static int max98095_set_fmt(struct maxim_priv *priv, int fmt,
168 enum en_max_audio_interface aif_id)
169 {
170 u8 regval = 0;
171 int error = 0;
172 unsigned short M98095_DAI_CLKCFG_HI;
173 unsigned short M98095_DAI_CLKCFG_LO;
174 unsigned short M98095_DAI_FORMAT;
175 unsigned short M98095_DAI_CLOCK;
176
177 if (fmt == priv->fmt)
178 return 0;
179
180 priv->fmt = fmt;
181
182 if (aif_id == AIF1) {
183 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
184 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
185 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
186 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
187 } else {
188 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
189 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
190 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
191 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
192 }
193
194 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
195 case SND_SOC_DAIFMT_CBS_CFS:
196 /* Slave mode PLL */
197 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80);
198 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00);
199 break;
200 case SND_SOC_DAIFMT_CBM_CFM:
201 /* Set to master mode */
202 regval |= M98095_DAI_MAS;
203 break;
204 case SND_SOC_DAIFMT_CBS_CFM:
205 case SND_SOC_DAIFMT_CBM_CFS:
206 default:
207 debug("%s: Clock mode unsupported\n", __func__);
208 return -EINVAL;
209 }
210
211 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
212 case SND_SOC_DAIFMT_I2S:
213 regval |= M98095_DAI_DLY;
214 break;
215 case SND_SOC_DAIFMT_LEFT_J:
216 break;
217 default:
218 debug("%s: Unrecognized format.\n", __func__);
219 return -EINVAL;
220 }
221
222 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
223 case SND_SOC_DAIFMT_NB_NF:
224 break;
225 case SND_SOC_DAIFMT_NB_IF:
226 regval |= M98095_DAI_WCI;
227 break;
228 case SND_SOC_DAIFMT_IB_NF:
229 regval |= M98095_DAI_BCI;
230 break;
231 case SND_SOC_DAIFMT_IB_IF:
232 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
233 break;
234 default:
235 debug("%s: Unrecognized inversion settings.\n", __func__);
236 return -EINVAL;
237 }
238
239 error |= maxim_bic_or(priv, M98095_DAI_FORMAT,
240 M98095_DAI_MAS | M98095_DAI_DLY |
241 M98095_DAI_BCI | M98095_DAI_WCI, regval);
242
243 error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64);
244
245 if (error < 0) {
246 debug("%s: Error setting i2s format.\n", __func__);
247 return -EIO;
248 }
249
250 return 0;
251 }
252
253 /*
254 * resets the audio codec
255 *
256 * @param priv Private data for driver
257 * @return 0 for success or negative error code.
258 */
max98095_reset(struct maxim_priv * priv)259 static int max98095_reset(struct maxim_priv *priv)
260 {
261 int i, ret;
262
263 /*
264 * Gracefully reset the DSP core and the codec hardware in a proper
265 * sequence.
266 */
267 ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0);
268 if (ret != 0) {
269 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
270 return ret;
271 }
272
273 ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0);
274 if (ret != 0) {
275 debug("%s: Failed to reset codec: %d\n", __func__, ret);
276 return ret;
277 }
278
279 /*
280 * Reset to hardware default for registers, as there is not a soft
281 * reset hardware control register.
282 */
283 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
284 ret = maxim_i2c_write(priv, i, 0);
285 if (ret < 0) {
286 debug("%s: Failed to reset: %d\n", __func__, ret);
287 return ret;
288 }
289 }
290
291 return 0;
292 }
293
294 /*
295 * Intialise max98095 codec device
296 *
297 * @param priv max98095 information
298 * @return 0 for success or negative error code.
299 */
max98095_device_init(struct maxim_priv * priv)300 static int max98095_device_init(struct maxim_priv *priv)
301 {
302 unsigned char id;
303 int ret;
304
305 /* reset the codec, the DSP core, and disable all interrupts */
306 ret = max98095_reset(priv);
307 if (ret != 0) {
308 debug("Reset\n");
309 return ret;
310 }
311
312 /* initialize private data */
313 priv->sysclk = -1U;
314 priv->rate = -1U;
315 priv->fmt = -1U;
316
317 ret = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id);
318 if (ret < 0) {
319 debug("%s: Failure reading hardware revision: %d\n",
320 __func__, id);
321 return ret;
322 }
323 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
324
325 return 0;
326 }
327
max98095_setup_interface(struct maxim_priv * priv,enum en_max_audio_interface aif_id)328 static int max98095_setup_interface(struct maxim_priv *priv,
329 enum en_max_audio_interface aif_id)
330 {
331 int error;
332
333 error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV);
334
335 /*
336 * initialize registers to hardware default configuring audio
337 * interface2 to DAC
338 */
339 if (aif_id == AIF1)
340 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
341 M98095_DAI1L_TO_DACL |
342 M98095_DAI1R_TO_DACR);
343 else
344 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
345 M98095_DAI2M_TO_DACL |
346 M98095_DAI2M_TO_DACR);
347
348 error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT,
349 M98095_SPK_SPREADSPECTRUM);
350 error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL);
351 if (aif_id == AIF1)
352 error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG,
353 M98095_S1NORMAL | M98095_SDATA);
354 else
355 error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG,
356 M98095_S2NORMAL | M98095_SDATA);
357
358 /* take the codec out of the shut down */
359 error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN,
360 M98095_SHDNRUN);
361 /*
362 * route DACL and DACR output to HO and Speakers
363 * Ordering: DACL, DACR, DACL, DACR
364 */
365 error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01);
366 error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01);
367 error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01);
368 error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01);
369
370 /* power Enable */
371 error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3);
372
373 /* set Volume */
374 error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15);
375 error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15);
376 error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16);
377 error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16);
378
379 /* Enable DAIs */
380 error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30);
381 if (aif_id == AIF1)
382 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01);
383 else
384 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07);
385
386 if (error < 0)
387 return -EIO;
388
389 return 0;
390 }
391
max98095_do_init(struct maxim_priv * priv,enum en_max_audio_interface aif_id,int sampling_rate,int mclk_freq,int bits_per_sample)392 static int max98095_do_init(struct maxim_priv *priv,
393 enum en_max_audio_interface aif_id,
394 int sampling_rate, int mclk_freq,
395 int bits_per_sample)
396 {
397 int ret = 0;
398
399 ret = max98095_setup_interface(priv, aif_id);
400 if (ret < 0) {
401 debug("%s: max98095 setup interface failed\n", __func__);
402 return ret;
403 }
404
405 ret = max98095_set_sysclk(priv, mclk_freq);
406 if (ret < 0) {
407 debug("%s: max98095 codec set sys clock failed\n", __func__);
408 return ret;
409 }
410
411 ret = max98095_hw_params(priv, aif_id, sampling_rate,
412 bits_per_sample);
413
414 if (ret == 0) {
415 ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S |
416 SND_SOC_DAIFMT_NB_NF |
417 SND_SOC_DAIFMT_CBS_CFS,
418 aif_id);
419 }
420
421 return ret;
422 }
423
max98095_set_params(struct udevice * dev,int interface,int rate,int mclk_freq,int bits_per_sample,uint channels)424 static int max98095_set_params(struct udevice *dev, int interface, int rate,
425 int mclk_freq, int bits_per_sample,
426 uint channels)
427 {
428 struct maxim_priv *priv = dev_get_priv(dev);
429
430 return max98095_do_init(priv, interface, rate, mclk_freq,
431 bits_per_sample);
432 }
433
max98095_probe(struct udevice * dev)434 static int max98095_probe(struct udevice *dev)
435 {
436 struct maxim_priv *priv = dev_get_priv(dev);
437 int ret;
438
439 priv->dev = dev;
440 ret = max98095_device_init(priv);
441 if (ret < 0) {
442 debug("%s: max98095 codec chip init failed\n", __func__);
443 return ret;
444 }
445
446 return 0;
447 }
448
449 static const struct audio_codec_ops max98095_ops = {
450 .set_params = max98095_set_params,
451 };
452
453 static const struct udevice_id max98095_ids[] = {
454 { .compatible = "maxim,max98095" },
455 { }
456 };
457
458 U_BOOT_DRIVER(max98095) = {
459 .name = "max98095",
460 .id = UCLASS_AUDIO_CODEC,
461 .of_match = max98095_ids,
462 .probe = max98095_probe,
463 .ops = &max98095_ops,
464 .priv_auto_alloc_size = sizeof(struct maxim_priv),
465 };
466