1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 Xilinx, Inc.
4 *
5 * Michal Simek <michal.simek@xilinx.com>
6 */
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/psu_init_gpl.h>
10
11 #define PSU_MASK_POLL_TIME 1100000
12
mask_pollonvalue(unsigned long add,u32 mask,u32 value)13 int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value)
14 {
15 int i = 0;
16
17 while ((__raw_readl(add) & mask) != value) {
18 if (i == PSU_MASK_POLL_TIME)
19 return 0;
20 i++;
21 }
22 return 1;
23 }
24
mask_poll(u32 add,u32 mask)25 __weak int mask_poll(u32 add, u32 mask)
26 {
27 int i = 0;
28 unsigned long addr = add;
29
30 while (!(__raw_readl(addr) & mask)) {
31 if (i == PSU_MASK_POLL_TIME)
32 return 0;
33 i++;
34 }
35 return 1;
36 }
37
mask_read(u32 add,u32 mask)38 __weak u32 mask_read(u32 add, u32 mask)
39 {
40 unsigned long addr = add;
41
42 return __raw_readl(addr) & mask;
43 }
44
mask_delay(u32 delay)45 __weak void mask_delay(u32 delay)
46 {
47 udelay(delay);
48 }
49
psu_mask_write(unsigned long offset,unsigned long mask,unsigned long val)50 __weak void psu_mask_write(unsigned long offset, unsigned long mask,
51 unsigned long val)
52 {
53 unsigned long regval = 0;
54
55 regval = readl(offset);
56 regval &= ~(mask);
57 regval |= (val & mask);
58 writel(regval, offset);
59 }
60
prog_reg(unsigned long addr,unsigned long mask,unsigned long shift,unsigned long value)61 __weak void prog_reg(unsigned long addr, unsigned long mask,
62 unsigned long shift, unsigned long value)
63 {
64 int rdata = 0;
65
66 rdata = readl(addr);
67 rdata = rdata & (~mask);
68 rdata = rdata | (value << shift);
69 writel(rdata, addr);
70 }
71
psu_init(void)72 __weak int psu_init(void)
73 {
74 /*
75 * This function is overridden by the one in
76 * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
77 */
78 return -1;
79 }
80