1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
5 */
6
7 #include <common.h>
8 #include <ide.h>
9 #include <netdev.h>
10 #include <pci.h>
11 #include <pci_gt64120.h>
12 #include <pci_msc01.h>
13 #include <rtc.h>
14
15 #include <asm/addrspace.h>
16 #include <asm/io.h>
17 #include <asm/malta.h>
18
19 #include "superio.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 enum core_card {
24 CORE_UNKNOWN,
25 CORE_LV,
26 CORE_FPGA6,
27 };
28
29 enum sys_con {
30 SYSCON_UNKNOWN,
31 SYSCON_GT64120,
32 SYSCON_MSC01,
33 };
34
malta_lcd_puts(const char * str)35 static void malta_lcd_puts(const char *str)
36 {
37 int i;
38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
39
40 /* print up to 8 characters of the string */
41 for (i = 0; i < min((int)strlen(str), 8); i++) {
42 __raw_writel(str[i], reg);
43 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
44 }
45
46 /* fill the rest of the display with spaces */
47 for (; i < 8; i++) {
48 __raw_writel(' ', reg);
49 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
50 }
51 }
52
malta_core_card(void)53 static enum core_card malta_core_card(void)
54 {
55 u32 corid, rev;
56 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
57
58 rev = __raw_readl(reg);
59 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
60
61 switch (corid) {
62 case MALTA_REVISION_CORID_CORE_LV:
63 return CORE_LV;
64
65 case MALTA_REVISION_CORID_CORE_FPGA6:
66 return CORE_FPGA6;
67
68 default:
69 return CORE_UNKNOWN;
70 }
71 }
72
malta_sys_con(void)73 static enum sys_con malta_sys_con(void)
74 {
75 switch (malta_core_card()) {
76 case CORE_LV:
77 return SYSCON_GT64120;
78
79 case CORE_FPGA6:
80 return SYSCON_MSC01;
81
82 default:
83 return SYSCON_UNKNOWN;
84 }
85 }
86
dram_init(void)87 int dram_init(void)
88 {
89 gd->ram_size = CONFIG_SYS_MEM_SIZE;
90
91 return 0;
92 }
93
checkboard(void)94 int checkboard(void)
95 {
96 enum core_card core;
97
98 malta_lcd_puts("U-Boot");
99 puts("Board: MIPS Malta");
100
101 core = malta_core_card();
102 switch (core) {
103 case CORE_LV:
104 puts(" CoreLV");
105 break;
106
107 case CORE_FPGA6:
108 puts(" CoreFPGA6");
109 break;
110
111 default:
112 puts(" CoreUnknown");
113 }
114
115 putc('\n');
116 return 0;
117 }
118
board_eth_init(bd_t * bis)119 int board_eth_init(bd_t *bis)
120 {
121 return pci_eth_init(bis);
122 }
123
_machine_restart(void)124 void _machine_restart(void)
125 {
126 void __iomem *reset_base;
127
128 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
129 __raw_writel(GORESET, reset_base);
130 mdelay(1000);
131 }
132
board_early_init_f(void)133 int board_early_init_f(void)
134 {
135 ulong io_base;
136
137 /* choose correct PCI I/O base */
138 switch (malta_sys_con()) {
139 case SYSCON_GT64120:
140 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
141 break;
142
143 case SYSCON_MSC01:
144 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
145 break;
146
147 default:
148 return -1;
149 }
150
151 set_io_port_base(io_base);
152
153 /* setup FDC37M817 super I/O controller */
154 malta_superio_init();
155
156 return 0;
157 }
158
misc_init_r(void)159 int misc_init_r(void)
160 {
161 rtc_reset();
162
163 return 0;
164 }
165
pci_init_board(void)166 void pci_init_board(void)
167 {
168 pci_dev_t bdf;
169 u32 val32;
170 u8 val8;
171
172 switch (malta_sys_con()) {
173 case SYSCON_GT64120:
174 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
175 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
176 0x10000000, 0x10000000, 128 * 1024 * 1024,
177 0x00000000, 0x00000000, 0x20000);
178 break;
179
180 default:
181 case SYSCON_MSC01:
182 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
183 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
184 MALTA_MSC01_PCIMEM_MAP,
185 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
186 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
187 0x00000000, MALTA_MSC01_PCIIO_SIZE);
188 break;
189 }
190
191 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
192 PCI_DEVICE_ID_INTEL_82371AB_0, 0);
193 if (bdf == -1)
194 panic("Failed to find PIIX4 PCI bridge\n");
195
196 /* setup PCI interrupt routing */
197 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
198 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
199 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
200 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
201
202 /* mux SERIRQ onto SERIRQ pin */
203 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
204 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
205 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
206
207 /* enable SERIRQ - Linux currently depends upon this */
208 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
209 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
210 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
211
212 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
213 PCI_DEVICE_ID_INTEL_82371AB, 0);
214 if (bdf == -1)
215 panic("Failed to find PIIX4 IDE controller\n");
216
217 /* enable bus master & IO access */
218 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
219 pci_write_config_dword(bdf, PCI_COMMAND, val32);
220
221 /* set latency */
222 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
223
224 /* enable IDE/ATA */
225 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
226 PCI_CFG_PIIX4_IDETIM_IDE);
227 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
228 PCI_CFG_PIIX4_IDETIM_IDE);
229 }
230