1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <netdev.h>
8 #include <asm/io.h>
9 #include <asm/arch/fsl_serdes.h>
10 #include <hwconfig.h>
11 #include <fsl_mdio.h>
12 #include <malloc.h>
13 #include <fm_eth.h>
14 #include <i2c.h>
15 #include <miiphy.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <fsl-mc/ldpaa_wriop.h>
18
19 #include "../common/qixis.h"
20
21 #include "ls2080aqds_qixis.h"
22
23 #define MC_BOOT_ENV_VAR "mcinitcmd"
24
25 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
26 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
27 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
28 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
29 */
30
31 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
32 * means that the mapping must be determined dynamically, or that the lane
33 * maps to something other than a board slot.
34 */
35
36 static u8 lane_to_slot_fsm1[] = {
37 0, 0, 0, 0, 0, 0, 0, 0
38 };
39
40 static u8 lane_to_slot_fsm2[] = {
41 0, 0, 0, 0, 0, 0, 0, 0
42 };
43
44 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
45 * housed.
46 */
47
48 static int xqsgii_riser_phy_addr[] = {
49 XQSGMII_CARD_PHY1_PORT0_ADDR,
50 XQSGMII_CARD_PHY2_PORT0_ADDR,
51 XQSGMII_CARD_PHY3_PORT0_ADDR,
52 XQSGMII_CARD_PHY4_PORT0_ADDR,
53 XQSGMII_CARD_PHY3_PORT2_ADDR,
54 XQSGMII_CARD_PHY1_PORT2_ADDR,
55 XQSGMII_CARD_PHY4_PORT2_ADDR,
56 XQSGMII_CARD_PHY2_PORT2_ADDR,
57 };
58
59 static int sgmii_riser_phy_addr[] = {
60 SGMII_CARD_PORT1_PHY_ADDR,
61 SGMII_CARD_PORT2_PHY_ADDR,
62 SGMII_CARD_PORT3_PHY_ADDR,
63 SGMII_CARD_PORT4_PHY_ADDR,
64 };
65
66 /* Slot2 does not have EMI connections */
67 #define EMI_NONE 0xFF
68 #define EMI1_SLOT1 0
69 #define EMI1_SLOT2 1
70 #define EMI1_SLOT3 2
71 #define EMI1_SLOT4 3
72 #define EMI1_SLOT5 4
73 #define EMI1_SLOT6 5
74 #define EMI2 6
75 #define SFP_TX 0
76
77 static const char * const mdio_names[] = {
78 "LS2080A_QDS_MDIO0",
79 "LS2080A_QDS_MDIO1",
80 "LS2080A_QDS_MDIO2",
81 "LS2080A_QDS_MDIO3",
82 "LS2080A_QDS_MDIO4",
83 "LS2080A_QDS_MDIO5",
84 DEFAULT_WRIOP_MDIO2_NAME,
85 };
86
87 struct ls2080a_qds_mdio {
88 u8 muxval;
89 struct mii_dev *realbus;
90 };
91
sgmii_configure_repeater(int serdes_port)92 static void sgmii_configure_repeater(int serdes_port)
93 {
94 struct mii_dev *bus;
95 uint8_t a = 0xf;
96 int i, j, ret;
97 int dpmac_id = 0, dpmac, mii_bus = 0;
98 unsigned short value;
99 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
100 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
101
102 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
103 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
104 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
105 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
106
107 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
108
109 /* Set I2c to Slot 1 */
110 i2c_write(0x77, 0, 0, &a, 1);
111
112 for (dpmac = 0; dpmac < 8; dpmac++) {
113 /* Check the PHY status */
114 switch (serdes_port) {
115 case 1:
116 mii_bus = 0;
117 dpmac_id = dpmac + 1;
118 break;
119 case 2:
120 mii_bus = 1;
121 dpmac_id = dpmac + 9;
122 a = 0xb;
123 i2c_write(0x76, 0, 0, &a, 1);
124 break;
125 }
126
127 ret = miiphy_set_current_dev(dev[mii_bus]);
128 if (ret > 0)
129 goto error;
130
131 bus = mdio_get_current_dev();
132 debug("Reading from bus %s\n", bus->name);
133
134 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
135 3);
136 if (ret > 0)
137 goto error;
138
139 mdelay(10);
140 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
141 &value);
142 if (ret > 0)
143 goto error;
144
145 mdelay(10);
146
147 if ((value & 0xfff) == 0x401) {
148 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
149 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
150 0x1f, 0);
151 continue;
152 }
153
154 for (i = 0; i < 4; i++) {
155 for (j = 0; j < 4; j++) {
156 a = 0x18;
157 i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
158 a = 0x38;
159 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
160 a = 0x4;
161 i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
162
163 i2c_write(i2c_addr[dpmac], 0xf, 1,
164 &ch_a_eq[i], 1);
165 i2c_write(i2c_addr[dpmac], 0x11, 1,
166 &ch_a_ctl2[j], 1);
167
168 i2c_write(i2c_addr[dpmac], 0x16, 1,
169 &ch_b_eq[i], 1);
170 i2c_write(i2c_addr[dpmac], 0x18, 1,
171 &ch_b_ctl2[j], 1);
172
173 a = 0x14;
174 i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
175 a = 0xb5;
176 i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
177 a = 0x20;
178 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
179 mdelay(100);
180 ret = miiphy_read(dev[mii_bus],
181 riser_phy_addr[dpmac],
182 0x11, &value);
183 if (ret > 0)
184 goto error;
185
186 mdelay(100);
187 ret = miiphy_read(dev[mii_bus],
188 riser_phy_addr[dpmac],
189 0x11, &value);
190 if (ret > 0)
191 goto error;
192
193 if ((value & 0xfff) == 0x401) {
194 printf("DPMAC %d :PHY is configured ",
195 dpmac_id);
196 printf("after setting repeater 0x%x\n",
197 value);
198 i = 5;
199 j = 5;
200 } else {
201 printf("DPMAC %d :PHY is failed to ",
202 dpmac_id);
203 printf("configure the repeater 0x%x\n",
204 value);
205 }
206 }
207 }
208 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
209 }
210 error:
211 if (ret)
212 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
213 return;
214 }
215
qsgmii_configure_repeater(int dpmac)216 static void qsgmii_configure_repeater(int dpmac)
217 {
218 uint8_t a = 0xf;
219 int i, j;
220 int i2c_phy_addr = 0;
221 int phy_addr = 0;
222 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
223
224 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
225 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
226 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
227 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
228
229 const char *dev = "LS2080A_QDS_MDIO0";
230 int ret = 0;
231 unsigned short value;
232
233 /* Set I2c to Slot 1 */
234 i2c_write(0x77, 0, 0, &a, 1);
235
236 switch (dpmac) {
237 case 1:
238 case 2:
239 case 3:
240 case 4:
241 i2c_phy_addr = i2c_addr[0];
242 phy_addr = 0;
243 break;
244
245 case 5:
246 case 6:
247 case 7:
248 case 8:
249 i2c_phy_addr = i2c_addr[1];
250 phy_addr = 4;
251 break;
252
253 case 9:
254 case 10:
255 case 11:
256 case 12:
257 i2c_phy_addr = i2c_addr[2];
258 phy_addr = 8;
259 break;
260
261 case 13:
262 case 14:
263 case 15:
264 case 16:
265 i2c_phy_addr = i2c_addr[3];
266 phy_addr = 0xc;
267 break;
268 }
269
270 /* Check the PHY status */
271 ret = miiphy_set_current_dev(dev);
272 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
273 mdelay(10);
274 ret = miiphy_read(dev, phy_addr, 0x11, &value);
275 mdelay(10);
276 ret = miiphy_read(dev, phy_addr, 0x11, &value);
277 mdelay(10);
278 if ((value & 0xf) == 0xf) {
279 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
280 return;
281 }
282
283 for (i = 0; i < 4; i++) {
284 for (j = 0; j < 4; j++) {
285 a = 0x18;
286 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
287 a = 0x38;
288 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
289 a = 0x4;
290 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
291
292 i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
293 i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
294
295 i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
296 i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
297
298 a = 0x14;
299 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
300 a = 0xb5;
301 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
302 a = 0x20;
303 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
304 mdelay(100);
305 ret = miiphy_read(dev, phy_addr, 0x11, &value);
306 if (ret > 0)
307 goto error;
308 mdelay(1);
309 ret = miiphy_read(dev, phy_addr, 0x11, &value);
310 if (ret > 0)
311 goto error;
312 mdelay(10);
313 if ((value & 0xf) == 0xf) {
314 printf("DPMAC %d :PHY is ..... Configured\n",
315 dpmac);
316 return;
317 }
318 }
319 }
320 error:
321 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
322 return;
323 }
324
ls2080a_qds_mdio_name_for_muxval(u8 muxval)325 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
326 {
327 return mdio_names[muxval];
328 }
329
mii_dev_for_muxval(u8 muxval)330 struct mii_dev *mii_dev_for_muxval(u8 muxval)
331 {
332 struct mii_dev *bus;
333 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
334
335 if (!name) {
336 printf("No bus for muxval %x\n", muxval);
337 return NULL;
338 }
339
340 bus = miiphy_get_dev_by_name(name);
341
342 if (!bus) {
343 printf("No bus by name %s\n", name);
344 return NULL;
345 }
346
347 return bus;
348 }
349
ls2080a_qds_enable_SFP_TX(u8 muxval)350 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
351 {
352 u8 brdcfg9;
353
354 brdcfg9 = QIXIS_READ(brdcfg[9]);
355 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
356 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
357 QIXIS_WRITE(brdcfg[9], brdcfg9);
358 }
359
ls2080a_qds_mux_mdio(u8 muxval)360 static void ls2080a_qds_mux_mdio(u8 muxval)
361 {
362 u8 brdcfg4;
363
364 if (muxval <= 5) {
365 brdcfg4 = QIXIS_READ(brdcfg[4]);
366 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
367 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
368 QIXIS_WRITE(brdcfg[4], brdcfg4);
369 }
370 }
371
ls2080a_qds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)372 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
373 int devad, int regnum)
374 {
375 struct ls2080a_qds_mdio *priv = bus->priv;
376
377 ls2080a_qds_mux_mdio(priv->muxval);
378
379 return priv->realbus->read(priv->realbus, addr, devad, regnum);
380 }
381
ls2080a_qds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)382 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
383 int regnum, u16 value)
384 {
385 struct ls2080a_qds_mdio *priv = bus->priv;
386
387 ls2080a_qds_mux_mdio(priv->muxval);
388
389 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
390 }
391
ls2080a_qds_mdio_reset(struct mii_dev * bus)392 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
393 {
394 struct ls2080a_qds_mdio *priv = bus->priv;
395
396 return priv->realbus->reset(priv->realbus);
397 }
398
ls2080a_qds_mdio_init(char * realbusname,u8 muxval)399 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
400 {
401 struct ls2080a_qds_mdio *pmdio;
402 struct mii_dev *bus = mdio_alloc();
403
404 if (!bus) {
405 printf("Failed to allocate ls2080a_qds MDIO bus\n");
406 return -1;
407 }
408
409 pmdio = malloc(sizeof(*pmdio));
410 if (!pmdio) {
411 printf("Failed to allocate ls2080a_qds private data\n");
412 free(bus);
413 return -1;
414 }
415
416 bus->read = ls2080a_qds_mdio_read;
417 bus->write = ls2080a_qds_mdio_write;
418 bus->reset = ls2080a_qds_mdio_reset;
419 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
420
421 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
422
423 if (!pmdio->realbus) {
424 printf("No bus with name %s\n", realbusname);
425 free(bus);
426 free(pmdio);
427 return -1;
428 }
429
430 pmdio->muxval = muxval;
431 bus->priv = pmdio;
432
433 return mdio_register(bus);
434 }
435
436 /*
437 * Initialize the dpmac_info array.
438 *
439 */
initialize_dpmac_to_slot(void)440 static void initialize_dpmac_to_slot(void)
441 {
442 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
443 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
444 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
445 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
446 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
447 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
448 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
449
450 char *env_hwconfig;
451 env_hwconfig = env_get("hwconfig");
452
453 switch (serdes1_prtcl) {
454 case 0x07:
455 case 0x09:
456 case 0x33:
457 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
458 serdes1_prtcl);
459 lane_to_slot_fsm1[0] = EMI1_SLOT1;
460 lane_to_slot_fsm1[1] = EMI1_SLOT1;
461 lane_to_slot_fsm1[2] = EMI1_SLOT1;
462 lane_to_slot_fsm1[3] = EMI1_SLOT1;
463 if (hwconfig_f("xqsgmii", env_hwconfig)) {
464 lane_to_slot_fsm1[4] = EMI1_SLOT1;
465 lane_to_slot_fsm1[5] = EMI1_SLOT1;
466 lane_to_slot_fsm1[6] = EMI1_SLOT1;
467 lane_to_slot_fsm1[7] = EMI1_SLOT1;
468 } else {
469 lane_to_slot_fsm1[4] = EMI1_SLOT2;
470 lane_to_slot_fsm1[5] = EMI1_SLOT2;
471 lane_to_slot_fsm1[6] = EMI1_SLOT2;
472 lane_to_slot_fsm1[7] = EMI1_SLOT2;
473 }
474 break;
475
476 case 0x39:
477 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
478 serdes1_prtcl);
479 if (hwconfig_f("xqsgmii", env_hwconfig)) {
480 lane_to_slot_fsm1[0] = EMI1_SLOT3;
481 lane_to_slot_fsm1[1] = EMI1_SLOT3;
482 lane_to_slot_fsm1[2] = EMI1_SLOT3;
483 lane_to_slot_fsm1[3] = EMI_NONE;
484 } else {
485 lane_to_slot_fsm1[0] = EMI_NONE;
486 lane_to_slot_fsm1[1] = EMI_NONE;
487 lane_to_slot_fsm1[2] = EMI_NONE;
488 lane_to_slot_fsm1[3] = EMI_NONE;
489 }
490 lane_to_slot_fsm1[4] = EMI1_SLOT3;
491 lane_to_slot_fsm1[5] = EMI1_SLOT3;
492 lane_to_slot_fsm1[6] = EMI1_SLOT3;
493 lane_to_slot_fsm1[7] = EMI_NONE;
494 break;
495
496 case 0x4D:
497 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
498 serdes1_prtcl);
499 if (hwconfig_f("xqsgmii", env_hwconfig)) {
500 lane_to_slot_fsm1[0] = EMI1_SLOT3;
501 lane_to_slot_fsm1[1] = EMI1_SLOT3;
502 lane_to_slot_fsm1[2] = EMI_NONE;
503 lane_to_slot_fsm1[3] = EMI_NONE;
504 } else {
505 lane_to_slot_fsm1[0] = EMI_NONE;
506 lane_to_slot_fsm1[1] = EMI_NONE;
507 lane_to_slot_fsm1[2] = EMI_NONE;
508 lane_to_slot_fsm1[3] = EMI_NONE;
509 }
510 lane_to_slot_fsm1[4] = EMI1_SLOT3;
511 lane_to_slot_fsm1[5] = EMI1_SLOT3;
512 lane_to_slot_fsm1[6] = EMI_NONE;
513 lane_to_slot_fsm1[7] = EMI_NONE;
514 break;
515
516 case 0x2A:
517 case 0x4B:
518 case 0x4C:
519 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
520 serdes1_prtcl);
521 break;
522 default:
523 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
524 __func__, serdes1_prtcl);
525 break;
526 }
527
528 switch (serdes2_prtcl) {
529 case 0x07:
530 case 0x08:
531 case 0x09:
532 case 0x49:
533 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
534 serdes2_prtcl);
535 lane_to_slot_fsm2[0] = EMI1_SLOT4;
536 lane_to_slot_fsm2[1] = EMI1_SLOT4;
537 lane_to_slot_fsm2[2] = EMI1_SLOT4;
538 lane_to_slot_fsm2[3] = EMI1_SLOT4;
539
540 if (hwconfig_f("xqsgmii", env_hwconfig)) {
541 lane_to_slot_fsm2[4] = EMI1_SLOT4;
542 lane_to_slot_fsm2[5] = EMI1_SLOT4;
543 lane_to_slot_fsm2[6] = EMI1_SLOT4;
544 lane_to_slot_fsm2[7] = EMI1_SLOT4;
545 } else {
546 /* No MDIO physical connection */
547 lane_to_slot_fsm2[4] = EMI1_SLOT6;
548 lane_to_slot_fsm2[5] = EMI1_SLOT6;
549 lane_to_slot_fsm2[6] = EMI1_SLOT6;
550 lane_to_slot_fsm2[7] = EMI1_SLOT6;
551 }
552 break;
553
554 case 0x47:
555 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
556 serdes2_prtcl);
557 lane_to_slot_fsm2[0] = EMI_NONE;
558 lane_to_slot_fsm2[1] = EMI1_SLOT5;
559 lane_to_slot_fsm2[2] = EMI1_SLOT5;
560 lane_to_slot_fsm2[3] = EMI1_SLOT5;
561
562 if (hwconfig_f("xqsgmii", env_hwconfig)) {
563 lane_to_slot_fsm2[4] = EMI_NONE;
564 lane_to_slot_fsm2[5] = EMI1_SLOT5;
565 lane_to_slot_fsm2[6] = EMI1_SLOT5;
566 lane_to_slot_fsm2[7] = EMI1_SLOT5;
567 }
568 break;
569
570 case 0x57:
571 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
572 serdes2_prtcl);
573 if (hwconfig_f("xqsgmii", env_hwconfig)) {
574 lane_to_slot_fsm2[0] = EMI_NONE;
575 lane_to_slot_fsm2[1] = EMI_NONE;
576 lane_to_slot_fsm2[2] = EMI_NONE;
577 lane_to_slot_fsm2[3] = EMI_NONE;
578 }
579 lane_to_slot_fsm2[4] = EMI_NONE;
580 lane_to_slot_fsm2[5] = EMI_NONE;
581 lane_to_slot_fsm2[6] = EMI1_SLOT5;
582 lane_to_slot_fsm2[7] = EMI1_SLOT5;
583 break;
584
585 default:
586 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
587 __func__ , serdes2_prtcl);
588 break;
589 }
590 }
591
ls2080a_handle_phy_interface_sgmii(int dpmac_id)592 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
593 {
594 int lane, slot;
595 struct mii_dev *bus;
596 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
597 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
598 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
599 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
600 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
601 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
602 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
603
604 int *riser_phy_addr;
605 char *env_hwconfig = env_get("hwconfig");
606
607 if (hwconfig_f("xqsgmii", env_hwconfig))
608 riser_phy_addr = &xqsgii_riser_phy_addr[0];
609 else
610 riser_phy_addr = &sgmii_riser_phy_addr[0];
611
612 if (dpmac_id > WRIOP1_DPMAC9)
613 goto serdes2;
614
615 switch (serdes1_prtcl) {
616 case 0x07:
617 case 0x39:
618 case 0x4D:
619 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
620
621 slot = lane_to_slot_fsm1[lane];
622
623 switch (++slot) {
624 case 1:
625 /* Slot housing a SGMII riser card? */
626 wriop_set_phy_address(dpmac_id, 0,
627 riser_phy_addr[dpmac_id - 1]);
628 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
629 bus = mii_dev_for_muxval(EMI1_SLOT1);
630 wriop_set_mdio(dpmac_id, bus);
631 break;
632 case 2:
633 /* Slot housing a SGMII riser card? */
634 wriop_set_phy_address(dpmac_id, 0,
635 riser_phy_addr[dpmac_id - 1]);
636 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
637 bus = mii_dev_for_muxval(EMI1_SLOT2);
638 wriop_set_mdio(dpmac_id, bus);
639 break;
640 case 3:
641 if (slot == EMI_NONE)
642 return;
643 if (serdes1_prtcl == 0x39) {
644 wriop_set_phy_address(dpmac_id, 0,
645 riser_phy_addr[dpmac_id - 2]);
646 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
647 env_hwconfig))
648 wriop_set_phy_address(dpmac_id, 0,
649 riser_phy_addr[dpmac_id - 3]);
650 } else {
651 wriop_set_phy_address(dpmac_id, 0,
652 riser_phy_addr[dpmac_id - 2]);
653 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
654 env_hwconfig))
655 wriop_set_phy_address(dpmac_id, 0,
656 riser_phy_addr[dpmac_id - 3]);
657 }
658 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
659 bus = mii_dev_for_muxval(EMI1_SLOT3);
660 wriop_set_mdio(dpmac_id, bus);
661 break;
662 case 4:
663 break;
664 case 5:
665 break;
666 case 6:
667 break;
668 }
669 break;
670 default:
671 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
672 __func__ , serdes1_prtcl);
673 break;
674 }
675
676 serdes2:
677 switch (serdes2_prtcl) {
678 case 0x07:
679 case 0x08:
680 case 0x49:
681 case 0x47:
682 case 0x57:
683 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
684 (dpmac_id - 9));
685 slot = lane_to_slot_fsm2[lane];
686
687 switch (++slot) {
688 case 1:
689 break;
690 case 3:
691 break;
692 case 4:
693 /* Slot housing a SGMII riser card? */
694 wriop_set_phy_address(dpmac_id, 0,
695 riser_phy_addr[dpmac_id - 9]);
696 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
697 bus = mii_dev_for_muxval(EMI1_SLOT4);
698 wriop_set_mdio(dpmac_id, bus);
699 break;
700 case 5:
701 if (slot == EMI_NONE)
702 return;
703 if (serdes2_prtcl == 0x47) {
704 wriop_set_phy_address(dpmac_id, 0,
705 riser_phy_addr[dpmac_id - 10]);
706 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
707 env_hwconfig))
708 wriop_set_phy_address(dpmac_id, 0,
709 riser_phy_addr[dpmac_id - 11]);
710 } else {
711 wriop_set_phy_address(dpmac_id, 0,
712 riser_phy_addr[dpmac_id - 11]);
713 }
714 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
715 bus = mii_dev_for_muxval(EMI1_SLOT5);
716 wriop_set_mdio(dpmac_id, bus);
717 break;
718 case 6:
719 /* Slot housing a SGMII riser card? */
720 wriop_set_phy_address(dpmac_id, 0,
721 riser_phy_addr[dpmac_id - 13]);
722 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
723 bus = mii_dev_for_muxval(EMI1_SLOT6);
724 wriop_set_mdio(dpmac_id, bus);
725 break;
726 }
727 break;
728 default:
729 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
730 __func__, serdes2_prtcl);
731 break;
732 }
733 }
734
ls2080a_handle_phy_interface_qsgmii(int dpmac_id)735 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
736 {
737 int lane = 0, slot;
738 struct mii_dev *bus;
739 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
740 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
741 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
742 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
743
744 switch (serdes1_prtcl) {
745 case 0x33:
746 switch (dpmac_id) {
747 case 1:
748 case 2:
749 case 3:
750 case 4:
751 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
752 break;
753 case 5:
754 case 6:
755 case 7:
756 case 8:
757 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
758 break;
759 case 9:
760 case 10:
761 case 11:
762 case 12:
763 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
764 break;
765 case 13:
766 case 14:
767 case 15:
768 case 16:
769 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
770 break;
771 }
772
773 slot = lane_to_slot_fsm1[lane];
774
775 switch (++slot) {
776 case 1:
777 /* Slot housing a QSGMII riser card? */
778 wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
779 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
780 bus = mii_dev_for_muxval(EMI1_SLOT1);
781 wriop_set_mdio(dpmac_id, bus);
782 break;
783 case 3:
784 break;
785 case 4:
786 break;
787 case 5:
788 break;
789 case 6:
790 break;
791 }
792 break;
793 default:
794 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
795 serdes1_prtcl);
796 break;
797 }
798
799 qsgmii_configure_repeater(dpmac_id);
800 }
801
ls2080a_handle_phy_interface_xsgmii(int i)802 void ls2080a_handle_phy_interface_xsgmii(int i)
803 {
804 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
805 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
806 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
807 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
808
809 switch (serdes1_prtcl) {
810 case 0x2A:
811 case 0x4B:
812 case 0x4C:
813 /*
814 * XFI does not need a PHY to work, but to avoid U-Boot use
815 * default PHY address which is zero to a MAC when it found
816 * a MAC has no PHY address, we give a PHY address to XFI
817 * MAC, and should not use a real XAUI PHY address, since
818 * MDIO can access it successfully, and then MDIO thinks
819 * the XAUI card is used for the XFI MAC, which will cause
820 * error.
821 */
822 wriop_set_phy_address(i, 0, i + 4);
823 ls2080a_qds_enable_SFP_TX(SFP_TX);
824
825 break;
826 default:
827 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
828 serdes1_prtcl);
829 break;
830 }
831 }
832 #endif
833
board_eth_init(bd_t * bis)834 int board_eth_init(bd_t *bis)
835 {
836 int error;
837 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
838 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
839 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
840 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
841 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
842 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
843 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
844 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
845
846 struct memac_mdio_info *memac_mdio0_info;
847 struct memac_mdio_info *memac_mdio1_info;
848 unsigned int i;
849 char *env_hwconfig;
850
851 env_hwconfig = env_get("hwconfig");
852
853 initialize_dpmac_to_slot();
854
855 memac_mdio0_info = (struct memac_mdio_info *)malloc(
856 sizeof(struct memac_mdio_info));
857 memac_mdio0_info->regs =
858 (struct memac_mdio_controller *)
859 CONFIG_SYS_FSL_WRIOP1_MDIO1;
860 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
861
862 /* Register the real MDIO1 bus */
863 fm_memac_mdio_init(bis, memac_mdio0_info);
864
865 memac_mdio1_info = (struct memac_mdio_info *)malloc(
866 sizeof(struct memac_mdio_info));
867 memac_mdio1_info->regs =
868 (struct memac_mdio_controller *)
869 CONFIG_SYS_FSL_WRIOP1_MDIO2;
870 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
871
872 /* Register the real MDIO2 bus */
873 fm_memac_mdio_init(bis, memac_mdio1_info);
874
875 /* Register the muxing front-ends to the MDIO buses */
876 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
877 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
878 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
879 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
880 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
881 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
882
883 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
884
885 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
886 switch (wriop_get_enet_if(i)) {
887 case PHY_INTERFACE_MODE_QSGMII:
888 ls2080a_handle_phy_interface_qsgmii(i);
889 break;
890 case PHY_INTERFACE_MODE_SGMII:
891 ls2080a_handle_phy_interface_sgmii(i);
892 break;
893 case PHY_INTERFACE_MODE_XGMII:
894 ls2080a_handle_phy_interface_xsgmii(i);
895 break;
896 default:
897 break;
898
899 if (i == 16)
900 i = NUM_WRIOP_PORTS;
901 }
902 }
903
904 error = cpu_eth_init(bis);
905
906 if (hwconfig_f("xqsgmii", env_hwconfig)) {
907 if (serdes1_prtcl == 0x7)
908 sgmii_configure_repeater(1);
909 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
910 serdes2_prtcl == 0x49)
911 sgmii_configure_repeater(2);
912 }
913 #endif
914 error = pci_eth_init(bis);
915 return error;
916 }
917
918 #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)919 void reset_phy(void)
920 {
921 mc_env_boot();
922 }
923 #endif /* CONFIG_RESET_PHY_R */
924