1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <netdev.h>
9 #include <fdt_support.h>
10 #include <fm_eth.h>
11 #include <fsl_mdio.h>
12 #include <fsl_dtsec.h>
13 #include <linux/libfdt.h>
14 #include <malloc.h>
15 #include <asm/arch/fsl_serdes.h>
16
17 #include "../common/qixis.h"
18 #include "../common/fman.h"
19 #include "ls1043aqds_qixis.h"
20
21 #define EMI_NONE 0xFF
22 #define EMI1_RGMII1 0
23 #define EMI1_RGMII2 1
24 #define EMI1_SLOT1 2
25 #define EMI1_SLOT2 3
26 #define EMI1_SLOT3 4
27 #define EMI1_SLOT4 5
28 #define EMI2 6
29
30 static int mdio_mux[NUM_FM_PORTS];
31
32 static const char * const mdio_names[] = {
33 "LS1043AQDS_MDIO_RGMII1",
34 "LS1043AQDS_MDIO_RGMII2",
35 "LS1043AQDS_MDIO_SLOT1",
36 "LS1043AQDS_MDIO_SLOT2",
37 "LS1043AQDS_MDIO_SLOT3",
38 "LS1043AQDS_MDIO_SLOT4",
39 "NULL",
40 };
41
42 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
43 static u8 lane_to_slot[] = {1, 2, 3, 4};
44
ls1043aqds_mdio_name_for_muxval(u8 muxval)45 static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
46 {
47 return mdio_names[muxval];
48 }
49
mii_dev_for_muxval(u8 muxval)50 struct mii_dev *mii_dev_for_muxval(u8 muxval)
51 {
52 struct mii_dev *bus;
53 const char *name;
54
55 if (muxval > EMI2)
56 return NULL;
57
58 name = ls1043aqds_mdio_name_for_muxval(muxval);
59
60 if (!name) {
61 printf("No bus for muxval %x\n", muxval);
62 return NULL;
63 }
64
65 bus = miiphy_get_dev_by_name(name);
66
67 if (!bus) {
68 printf("No bus by name %s\n", name);
69 return NULL;
70 }
71
72 return bus;
73 }
74
75 struct ls1043aqds_mdio {
76 u8 muxval;
77 struct mii_dev *realbus;
78 };
79
ls1043aqds_mux_mdio(u8 muxval)80 static void ls1043aqds_mux_mdio(u8 muxval)
81 {
82 u8 brdcfg4;
83
84 if (muxval < 7) {
85 brdcfg4 = QIXIS_READ(brdcfg[4]);
86 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
87 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
88 QIXIS_WRITE(brdcfg[4], brdcfg4);
89 }
90 }
91
ls1043aqds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)92 static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
93 int regnum)
94 {
95 struct ls1043aqds_mdio *priv = bus->priv;
96
97 ls1043aqds_mux_mdio(priv->muxval);
98
99 return priv->realbus->read(priv->realbus, addr, devad, regnum);
100 }
101
ls1043aqds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)102 static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
103 int regnum, u16 value)
104 {
105 struct ls1043aqds_mdio *priv = bus->priv;
106
107 ls1043aqds_mux_mdio(priv->muxval);
108
109 return priv->realbus->write(priv->realbus, addr, devad,
110 regnum, value);
111 }
112
ls1043aqds_mdio_reset(struct mii_dev * bus)113 static int ls1043aqds_mdio_reset(struct mii_dev *bus)
114 {
115 struct ls1043aqds_mdio *priv = bus->priv;
116
117 return priv->realbus->reset(priv->realbus);
118 }
119
ls1043aqds_mdio_init(char * realbusname,u8 muxval)120 static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
121 {
122 struct ls1043aqds_mdio *pmdio;
123 struct mii_dev *bus = mdio_alloc();
124
125 if (!bus) {
126 printf("Failed to allocate ls1043aqds MDIO bus\n");
127 return -1;
128 }
129
130 pmdio = malloc(sizeof(*pmdio));
131 if (!pmdio) {
132 printf("Failed to allocate ls1043aqds private data\n");
133 free(bus);
134 return -1;
135 }
136
137 bus->read = ls1043aqds_mdio_read;
138 bus->write = ls1043aqds_mdio_write;
139 bus->reset = ls1043aqds_mdio_reset;
140 strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
141
142 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
143
144 if (!pmdio->realbus) {
145 printf("No bus with name %s\n", realbusname);
146 free(bus);
147 free(pmdio);
148 return -1;
149 }
150
151 pmdio->muxval = muxval;
152 bus->priv = pmdio;
153 return mdio_register(bus);
154 }
155
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)156 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
157 enum fm_port port, int offset)
158 {
159 struct fixed_link f_link;
160
161 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
162 if (port == FM1_DTSEC9) {
163 fdt_set_phy_handle(fdt, compat, addr,
164 "sgmii_riser_s1_p1");
165 } else if (port == FM1_DTSEC2) {
166 fdt_set_phy_handle(fdt, compat, addr,
167 "sgmii_riser_s2_p1");
168 } else if (port == FM1_DTSEC5) {
169 fdt_set_phy_handle(fdt, compat, addr,
170 "sgmii_riser_s3_p1");
171 } else if (port == FM1_DTSEC6) {
172 fdt_set_phy_handle(fdt, compat, addr,
173 "sgmii_riser_s4_p1");
174 }
175 } else if (fm_info_get_enet_if(port) ==
176 PHY_INTERFACE_MODE_SGMII_2500) {
177 /* 2.5G SGMII interface */
178 f_link.phy_id = cpu_to_fdt32(port);
179 f_link.duplex = cpu_to_fdt32(1);
180 f_link.link_speed = cpu_to_fdt32(1000);
181 f_link.pause = 0;
182 f_link.asym_pause = 0;
183 /* no PHY for 2.5G SGMII */
184 fdt_delprop(fdt, offset, "phy-handle");
185 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
186 fdt_setprop_string(fdt, offset, "phy-connection-type",
187 "sgmii-2500");
188 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
189 switch (mdio_mux[port]) {
190 case EMI1_SLOT1:
191 switch (port) {
192 case FM1_DTSEC1:
193 fdt_set_phy_handle(fdt, compat, addr,
194 "qsgmii_s1_p1");
195 break;
196 case FM1_DTSEC2:
197 fdt_set_phy_handle(fdt, compat, addr,
198 "qsgmii_s1_p2");
199 break;
200 case FM1_DTSEC5:
201 fdt_set_phy_handle(fdt, compat, addr,
202 "qsgmii_s1_p3");
203 break;
204 case FM1_DTSEC6:
205 fdt_set_phy_handle(fdt, compat, addr,
206 "qsgmii_s1_p4");
207 break;
208 default:
209 break;
210 }
211 break;
212 case EMI1_SLOT2:
213 switch (port) {
214 case FM1_DTSEC1:
215 fdt_set_phy_handle(fdt, compat, addr,
216 "qsgmii_s2_p1");
217 break;
218 case FM1_DTSEC2:
219 fdt_set_phy_handle(fdt, compat, addr,
220 "qsgmii_s2_p2");
221 break;
222 case FM1_DTSEC5:
223 fdt_set_phy_handle(fdt, compat, addr,
224 "qsgmii_s2_p3");
225 break;
226 case FM1_DTSEC6:
227 fdt_set_phy_handle(fdt, compat, addr,
228 "qsgmii_s2_p4");
229 break;
230 default:
231 break;
232 }
233 break;
234 default:
235 break;
236 }
237 fdt_delprop(fdt, offset, "phy-connection-type");
238 fdt_setprop_string(fdt, offset, "phy-connection-type",
239 "qsgmii");
240 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
241 port == FM1_10GEC1) {
242 /* XFI interface */
243 f_link.phy_id = cpu_to_fdt32(port);
244 f_link.duplex = cpu_to_fdt32(1);
245 f_link.link_speed = cpu_to_fdt32(10000);
246 f_link.pause = 0;
247 f_link.asym_pause = 0;
248 /* no PHY for XFI */
249 fdt_delprop(fdt, offset, "phy-handle");
250 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
251 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
252 }
253 }
254
fdt_fixup_board_enet(void * fdt)255 void fdt_fixup_board_enet(void *fdt)
256 {
257 int i;
258 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
259 u32 srds_s1;
260
261 srds_s1 = in_be32(&gur->rcwsr[4]) &
262 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
263 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
264
265 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
266 switch (fm_info_get_enet_if(i)) {
267 case PHY_INTERFACE_MODE_SGMII:
268 case PHY_INTERFACE_MODE_QSGMII:
269 switch (mdio_mux[i]) {
270 case EMI1_SLOT1:
271 fdt_status_okay_by_alias(fdt, "emi1_slot1");
272 break;
273 case EMI1_SLOT2:
274 fdt_status_okay_by_alias(fdt, "emi1_slot2");
275 break;
276 case EMI1_SLOT3:
277 fdt_status_okay_by_alias(fdt, "emi1_slot3");
278 break;
279 case EMI1_SLOT4:
280 fdt_status_okay_by_alias(fdt, "emi1_slot4");
281 break;
282 default:
283 break;
284 }
285 break;
286 case PHY_INTERFACE_MODE_XGMII:
287 break;
288 default:
289 break;
290 }
291 }
292 }
293
board_eth_init(bd_t * bis)294 int board_eth_init(bd_t *bis)
295 {
296 #ifdef CONFIG_FMAN_ENET
297 int i, idx, lane, slot, interface;
298 struct memac_mdio_info dtsec_mdio_info;
299 struct memac_mdio_info tgec_mdio_info;
300 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
301 u32 srds_s1;
302
303 srds_s1 = in_be32(&gur->rcwsr[4]) &
304 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
305 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
306
307 /* Initialize the mdio_mux array so we can recognize empty elements */
308 for (i = 0; i < NUM_FM_PORTS; i++)
309 mdio_mux[i] = EMI_NONE;
310
311 dtsec_mdio_info.regs =
312 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
313
314 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
315
316 /* Register the 1G MDIO bus */
317 fm_memac_mdio_init(bis, &dtsec_mdio_info);
318
319 tgec_mdio_info.regs =
320 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
321 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
322
323 /* Register the 10G MDIO bus */
324 fm_memac_mdio_init(bis, &tgec_mdio_info);
325
326 /* Register the muxing front-ends to the MDIO buses */
327 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
328 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
329 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
330 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
331 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
332 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
333 ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
334
335 /* Set the two on-board RGMII PHY address */
336 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
337 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
338
339 switch (srds_s1) {
340 case 0x2555:
341 /* 2.5G SGMII on lane A, MAC 9 */
342 fm_info_set_phy_address(FM1_DTSEC9, 9);
343 break;
344 case 0x4555:
345 case 0x4558:
346 /* QSGMII on lane A, MAC 1/2/5/6 */
347 fm_info_set_phy_address(FM1_DTSEC1,
348 QSGMII_CARD_PORT1_PHY_ADDR_S1);
349 fm_info_set_phy_address(FM1_DTSEC2,
350 QSGMII_CARD_PORT2_PHY_ADDR_S1);
351 fm_info_set_phy_address(FM1_DTSEC5,
352 QSGMII_CARD_PORT3_PHY_ADDR_S1);
353 fm_info_set_phy_address(FM1_DTSEC6,
354 QSGMII_CARD_PORT4_PHY_ADDR_S1);
355 break;
356 case 0x1355:
357 /* SGMII on lane B, MAC 2*/
358 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
359 break;
360 case 0x2355:
361 /* 2.5G SGMII on lane A, MAC 9 */
362 fm_info_set_phy_address(FM1_DTSEC9, 9);
363 /* SGMII on lane B, MAC 2*/
364 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
365 break;
366 case 0x3335:
367 /* SGMII on lane C, MAC 5 */
368 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
369 case 0x3355:
370 case 0x3358:
371 /* SGMII on lane B, MAC 2 */
372 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
373 case 0x3555:
374 case 0x3558:
375 /* SGMII on lane A, MAC 9 */
376 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
377 break;
378 case 0x1455:
379 /* QSGMII on lane B, MAC 1/2/5/6 */
380 fm_info_set_phy_address(FM1_DTSEC1,
381 QSGMII_CARD_PORT1_PHY_ADDR_S2);
382 fm_info_set_phy_address(FM1_DTSEC2,
383 QSGMII_CARD_PORT2_PHY_ADDR_S2);
384 fm_info_set_phy_address(FM1_DTSEC5,
385 QSGMII_CARD_PORT3_PHY_ADDR_S2);
386 fm_info_set_phy_address(FM1_DTSEC6,
387 QSGMII_CARD_PORT4_PHY_ADDR_S2);
388 break;
389 case 0x2455:
390 /* 2.5G SGMII on lane A, MAC 9 */
391 fm_info_set_phy_address(FM1_DTSEC9, 9);
392 /* QSGMII on lane B, MAC 1/2/5/6 */
393 fm_info_set_phy_address(FM1_DTSEC1,
394 QSGMII_CARD_PORT1_PHY_ADDR_S2);
395 fm_info_set_phy_address(FM1_DTSEC2,
396 QSGMII_CARD_PORT2_PHY_ADDR_S2);
397 fm_info_set_phy_address(FM1_DTSEC5,
398 QSGMII_CARD_PORT3_PHY_ADDR_S2);
399 fm_info_set_phy_address(FM1_DTSEC6,
400 QSGMII_CARD_PORT4_PHY_ADDR_S2);
401 break;
402 case 0x2255:
403 /* 2.5G SGMII on lane A, MAC 9 */
404 fm_info_set_phy_address(FM1_DTSEC9, 9);
405 /* 2.5G SGMII on lane B, MAC 2 */
406 fm_info_set_phy_address(FM1_DTSEC2, 2);
407 break;
408 case 0x3333:
409 /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
410 fm_info_set_phy_address(FM1_DTSEC9,
411 SGMII_CARD_PORT1_PHY_ADDR);
412 fm_info_set_phy_address(FM1_DTSEC2,
413 SGMII_CARD_PORT1_PHY_ADDR);
414 fm_info_set_phy_address(FM1_DTSEC5,
415 SGMII_CARD_PORT1_PHY_ADDR);
416 fm_info_set_phy_address(FM1_DTSEC6,
417 SGMII_CARD_PORT1_PHY_ADDR);
418 break;
419 default:
420 printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
421 srds_s1);
422 break;
423 }
424
425 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
426 idx = i - FM1_DTSEC1;
427 interface = fm_info_get_enet_if(i);
428 switch (interface) {
429 case PHY_INTERFACE_MODE_SGMII:
430 case PHY_INTERFACE_MODE_SGMII_2500:
431 case PHY_INTERFACE_MODE_QSGMII:
432 if (interface == PHY_INTERFACE_MODE_SGMII) {
433 lane = serdes_get_first_lane(FSL_SRDS_1,
434 SGMII_FM1_DTSEC1 + idx);
435 } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
436 lane = serdes_get_first_lane(FSL_SRDS_1,
437 SGMII_2500_FM1_DTSEC1 + idx);
438 } else {
439 lane = serdes_get_first_lane(FSL_SRDS_1,
440 QSGMII_FM1_A);
441 }
442
443 if (lane < 0)
444 break;
445
446 slot = lane_to_slot[lane];
447 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
448 idx + 1, slot);
449 if (QIXIS_READ(present2) & (1 << (slot - 1)))
450 fm_disable_port(i);
451
452 switch (slot) {
453 case 1:
454 mdio_mux[i] = EMI1_SLOT1;
455 fm_info_set_mdio(i, mii_dev_for_muxval(
456 mdio_mux[i]));
457 break;
458 case 2:
459 mdio_mux[i] = EMI1_SLOT2;
460 fm_info_set_mdio(i, mii_dev_for_muxval(
461 mdio_mux[i]));
462 break;
463 case 3:
464 mdio_mux[i] = EMI1_SLOT3;
465 fm_info_set_mdio(i, mii_dev_for_muxval(
466 mdio_mux[i]));
467 break;
468 case 4:
469 mdio_mux[i] = EMI1_SLOT4;
470 fm_info_set_mdio(i, mii_dev_for_muxval(
471 mdio_mux[i]));
472 break;
473 default:
474 break;
475 }
476 break;
477 case PHY_INTERFACE_MODE_RGMII:
478 case PHY_INTERFACE_MODE_RGMII_TXID:
479 if (i == FM1_DTSEC3)
480 mdio_mux[i] = EMI1_RGMII1;
481 else if (i == FM1_DTSEC4)
482 mdio_mux[i] = EMI1_RGMII2;
483 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
484 break;
485 default:
486 break;
487 }
488 }
489
490 cpu_eth_init(bis);
491 #endif /* CONFIG_FMAN_ENET */
492
493 return pci_eth_init(bis);
494 }
495