1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2015-2016 Freescale Semiconductor, Inc.
4  * Copyright 2017 NXP
5  */
6 
7 #include <common.h>
8 #include <dm.h>
9 #include <asm/io.h>
10 #include <netdev.h>
11 #include <fm_eth.h>
12 #include <fsl_mdio.h>
13 #include <malloc.h>
14 #include <asm/types.h>
15 #include <fsl_dtsec.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch-fsl-layerscape/config.h>
18 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
19 #include <asm/arch/fsl_serdes.h>
20 #include "../common/qixis.h"
21 #include <net/pfe_eth/pfe_eth.h>
22 #include <dm/platform_data/pfe_dm_eth.h>
23 #include "ls1012aqds_qixis.h"
24 
25 #define EMI_NONE	0xFF
26 #define EMI1_RGMII	1
27 #define EMI1_SLOT1	2
28 #define EMI1_SLOT2	3
29 
30 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
31 #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
32 
33 static const char * const mdio_names[] = {
34 	"NULL",
35 	"LS1012AQDS_MDIO_RGMII",
36 	"LS1012AQDS_MDIO_SLOT1",
37 	"LS1012AQDS_MDIO_SLOT2",
38 	"NULL",
39 };
40 
ls1012aqds_mdio_name_for_muxval(u8 muxval)41 static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
42 {
43 	return mdio_names[muxval];
44 }
45 
46 struct ls1012aqds_mdio {
47 	u8 muxval;
48 	struct mii_dev *realbus;
49 };
50 
ls1012aqds_mux_mdio(u8 muxval)51 static void ls1012aqds_mux_mdio(u8 muxval)
52 {
53 	u8 brdcfg4;
54 
55 	if (muxval < 7) {
56 		brdcfg4 = QIXIS_READ(brdcfg[4]);
57 		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
58 		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
59 		QIXIS_WRITE(brdcfg[4], brdcfg4);
60 	}
61 }
62 
ls1012aqds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)63 static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
64 				int regnum)
65 {
66 	struct ls1012aqds_mdio *priv = bus->priv;
67 
68 	ls1012aqds_mux_mdio(priv->muxval);
69 
70 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
71 }
72 
ls1012aqds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)73 static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
74 				 int regnum, u16 value)
75 {
76 	struct ls1012aqds_mdio *priv = bus->priv;
77 
78 	ls1012aqds_mux_mdio(priv->muxval);
79 
80 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
81 }
82 
ls1012aqds_mdio_reset(struct mii_dev * bus)83 static int ls1012aqds_mdio_reset(struct mii_dev *bus)
84 {
85 	struct ls1012aqds_mdio *priv = bus->priv;
86 
87 	if (priv->realbus->reset)
88 		return priv->realbus->reset(priv->realbus);
89 	else
90 		return -1;
91 }
92 
ls1012aqds_mdio_init(char * realbusname,u8 muxval)93 static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
94 {
95 	struct ls1012aqds_mdio *pmdio;
96 	struct mii_dev *bus = mdio_alloc();
97 
98 	if (!bus) {
99 		printf("Failed to allocate ls1012aqds MDIO bus\n");
100 		return -1;
101 	}
102 
103 	pmdio = malloc(sizeof(*pmdio));
104 	if (!pmdio) {
105 		printf("Failed to allocate ls1012aqds private data\n");
106 		free(bus);
107 		return -1;
108 	}
109 
110 	bus->read = ls1012aqds_mdio_read;
111 	bus->write = ls1012aqds_mdio_write;
112 	bus->reset = ls1012aqds_mdio_reset;
113 	sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
114 
115 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
116 
117 	if (!pmdio->realbus) {
118 		printf("No bus with name %s\n", realbusname);
119 		free(bus);
120 		free(pmdio);
121 		return -1;
122 	}
123 
124 	pmdio->muxval = muxval;
125 	bus->priv = pmdio;
126 	return mdio_register(bus);
127 }
128 
pfe_eth_board_init(struct udevice * dev)129 int pfe_eth_board_init(struct udevice *dev)
130 {
131 	static int init_done;
132 	struct mii_dev *bus;
133 	static const char *mdio_name;
134 	struct pfe_mdio_info mac_mdio_info;
135 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
136 	u8 data8;
137 	struct pfe_eth_dev *priv = dev_get_priv(dev);
138 
139 	int srds_s1 = in_be32(&gur->rcwsr[4]) &
140 			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
141 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
142 
143 	ls1012aqds_mux_mdio(EMI1_SLOT1);
144 
145 	if (!init_done) {
146 		mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
147 		mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
148 
149 		bus = pfe_mdio_init(&mac_mdio_info);
150 		if (!bus) {
151 			printf("Failed to register mdio\n");
152 			return -1;
153 		}
154 		init_done = 1;
155 	}
156 
157 	if (priv->gemac_port) {
158 		mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
159 		mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
160 
161 		bus = pfe_mdio_init(&mac_mdio_info);
162 		if (!bus) {
163 			printf("Failed to register mdio\n");
164 			return -1;
165 		}
166 	}
167 
168 	switch (srds_s1) {
169 	case 0x3508:
170 		printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
171 #ifdef CONFIG_PFE_RGMII_RESET_WA
172 		/*
173 		 * Work around for FPGA registers initialization
174 		 * This is needed for RGMII to work.
175 		 */
176 		printf("Reset RGMII WA....\n");
177 		data8 = QIXIS_READ(rst_frc[0]);
178 		data8 |= 0x2;
179 		QIXIS_WRITE(rst_frc[0], data8);
180 		data8 = QIXIS_READ(rst_frc[0]);
181 
182 		data8 = QIXIS_READ(res8[6]);
183 		data8 |= 0xff;
184 		QIXIS_WRITE(res8[6], data8);
185 		data8 = QIXIS_READ(res8[6]);
186 #endif
187 	if (priv->gemac_port) {
188 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
189 		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
190 		    < 0) {
191 			printf("Failed to register mdio for %s\n", mdio_name);
192 		}
193 
194 		/* MAC2 */
195 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
196 		bus = miiphy_get_dev_by_name(mdio_name);
197 		pfe_set_mdio(priv->gemac_port, bus);
198 		pfe_set_phy_address_mode(priv->gemac_port,
199 					 CONFIG_PFE_EMAC2_PHY_ADDR,
200 					 PHY_INTERFACE_MODE_RGMII);
201 
202 	} else {
203 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
204 		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
205 		< 0) {
206 			printf("Failed to register mdio for %s\n", mdio_name);
207 		}
208 
209 		/* MAC1 */
210 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
211 		bus = miiphy_get_dev_by_name(mdio_name);
212 		pfe_set_mdio(priv->gemac_port, bus);
213 		pfe_set_phy_address_mode(priv->gemac_port,
214 					 CONFIG_PFE_EMAC1_PHY_ADDR,
215 					 PHY_INTERFACE_MODE_SGMII);
216 	}
217 
218 		break;
219 
220 	case 0x2205:
221 		printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
222 		/*
223 		 * Work around for FPGA registers initialization
224 		 * This is needed for RGMII to work.
225 		 */
226 		printf("Reset SLOT1 SLOT2....\n");
227 		data8 = QIXIS_READ(rst_frc[2]);
228 		data8 |= 0xc0;
229 		QIXIS_WRITE(rst_frc[2], data8);
230 		mdelay(100);
231 		data8 = QIXIS_READ(rst_frc[2]);
232 		data8 &= 0x3f;
233 		QIXIS_WRITE(rst_frc[2], data8);
234 
235 	if (priv->gemac_port) {
236 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
237 		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
238 		< 0) {
239 			printf("Failed to register mdio for %s\n", mdio_name);
240 		}
241 		/* MAC2 */
242 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
243 		bus = miiphy_get_dev_by_name(mdio_name);
244 		pfe_set_mdio(1, bus);
245 		pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
246 					 PHY_INTERFACE_MODE_SGMII_2500);
247 
248 		data8 = QIXIS_READ(brdcfg[12]);
249 		data8 |= 0x20;
250 		QIXIS_WRITE(brdcfg[12], data8);
251 
252 	} else {
253 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
254 		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
255 		    < 0) {
256 			printf("Failed to register mdio for %s\n", mdio_name);
257 		}
258 
259 		/* MAC1 */
260 		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
261 		bus = miiphy_get_dev_by_name(mdio_name);
262 		pfe_set_mdio(0, bus);
263 		pfe_set_phy_address_mode(0,
264 					 CONFIG_PFE_SGMII_2500_PHY1_ADDR,
265 					 PHY_INTERFACE_MODE_SGMII_2500);
266 	}
267 		break;
268 
269 	default:
270 		printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
271 		break;
272 	}
273 	return 0;
274 }
275 
276 static struct pfe_eth_pdata pfe_pdata0 = {
277 	.pfe_eth_pdata_mac = {
278 		.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
279 		.phy_interface = 0,
280 	},
281 
282 	.pfe_ddr_addr = {
283 		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
284 		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
285 	},
286 };
287 
288 static struct pfe_eth_pdata pfe_pdata1 = {
289 	.pfe_eth_pdata_mac = {
290 		.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
291 		.phy_interface = 1,
292 	},
293 
294 	.pfe_ddr_addr = {
295 		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
296 		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
297 	},
298 };
299 
300 U_BOOT_DEVICE(ls1012a_pfe0) = {
301 	.name = "pfe_eth",
302 	.platdata = &pfe_pdata0,
303 };
304 
305 U_BOOT_DEVICE(ls1012a_pfe1) = {
306 	.name = "pfe_eth",
307 	.platdata = &pfe_pdata1,
308 };
309