1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Xilinx, Inc.
4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
5 *
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <malloc.h>
12 #include <spi.h>
13 #include <asm/io.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
18 #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
19 #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
20 #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
21 #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
22 #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
23 #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
24 #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
25 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
26 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
27 #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
28 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
29 #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
30 #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
31 #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
32 #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
33
34 /* zynq qspi Transmit Data Register */
35 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
36 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
37 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
38 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
39
40 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
41 #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
42
43 #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
44 #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
45 #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
46
47 #define ZYNQ_QSPI_FIFO_DEPTH 63
48 #ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
49 #define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
50 #endif
51
52 /* zynq qspi register set */
53 struct zynq_qspi_regs {
54 u32 cr; /* 0x00 */
55 u32 isr; /* 0x04 */
56 u32 ier; /* 0x08 */
57 u32 idr; /* 0x0C */
58 u32 imr; /* 0x10 */
59 u32 enr; /* 0x14 */
60 u32 dr; /* 0x18 */
61 u32 txd0r; /* 0x1C */
62 u32 drxr; /* 0x20 */
63 u32 sicr; /* 0x24 */
64 u32 txftr; /* 0x28 */
65 u32 rxftr; /* 0x2C */
66 u32 gpior; /* 0x30 */
67 u32 reserved0[19];
68 u32 txd1r; /* 0x80 */
69 u32 txd2r; /* 0x84 */
70 u32 txd3r; /* 0x88 */
71 u32 reserved1[5];
72 u32 lqspicfg; /* 0xA0 */
73 u32 lqspists; /* 0xA4 */
74 };
75
76 /* zynq qspi platform data */
77 struct zynq_qspi_platdata {
78 struct zynq_qspi_regs *regs;
79 u32 frequency; /* input frequency */
80 u32 speed_hz;
81 };
82
83 /* zynq qspi priv */
84 struct zynq_qspi_priv {
85 struct zynq_qspi_regs *regs;
86 u8 cs;
87 u8 mode;
88 u8 fifo_depth;
89 u32 freq; /* required frequency */
90 const void *tx_buf;
91 void *rx_buf;
92 unsigned len;
93 int bytes_to_transfer;
94 int bytes_to_receive;
95 unsigned int is_inst;
96 unsigned cs_change:1;
97 };
98
zynq_qspi_ofdata_to_platdata(struct udevice * bus)99 static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
100 {
101 struct zynq_qspi_platdata *plat = bus->platdata;
102 const void *blob = gd->fdt_blob;
103 int node = dev_of_offset(bus);
104
105 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
106 node, "reg");
107
108 /* FIXME: Use 166MHz as a suitable default */
109 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
110 166666666);
111 plat->speed_hz = plat->frequency / 2;
112
113 debug("%s: regs=%p max-frequency=%d\n", __func__,
114 plat->regs, plat->frequency);
115
116 return 0;
117 }
118
zynq_qspi_init_hw(struct zynq_qspi_priv * priv)119 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
120 {
121 struct zynq_qspi_regs *regs = priv->regs;
122 u32 confr;
123
124 /* Disable QSPI */
125 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
126
127 /* Disable Interrupts */
128 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
129
130 /* Clear the TX and RX threshold reg */
131 writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
132 writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
133
134 /* Clear the RX FIFO */
135 while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
136 readl(®s->drxr);
137
138 /* Clear Interrupts */
139 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
140
141 /* Manual slave select and Auto start */
142 confr = readl(®s->cr);
143 confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
144 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
145 ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
146 ZYNQ_QSPI_CR_MSTREN_MASK;
147 writel(confr, ®s->cr);
148
149 /* Disable the LQSPI feature */
150 confr = readl(®s->lqspicfg);
151 confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
152 writel(confr, ®s->lqspicfg);
153
154 /* Enable SPI */
155 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
156 }
157
zynq_qspi_probe(struct udevice * bus)158 static int zynq_qspi_probe(struct udevice *bus)
159 {
160 struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
161 struct zynq_qspi_priv *priv = dev_get_priv(bus);
162
163 priv->regs = plat->regs;
164 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
165
166 /* init the zynq spi hw */
167 zynq_qspi_init_hw(priv);
168
169 return 0;
170 }
171
172 /*
173 * zynq_qspi_read_data - Copy data to RX buffer
174 * @zqspi: Pointer to the zynq_qspi structure
175 * @data: The 32 bit variable where data is stored
176 * @size: Number of bytes to be copied from data to RX buffer
177 */
zynq_qspi_read_data(struct zynq_qspi_priv * priv,u32 data,u8 size)178 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
179 {
180 u8 byte3;
181
182 debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
183 data, (unsigned)(priv->rx_buf), size);
184
185 if (priv->rx_buf) {
186 switch (size) {
187 case 1:
188 *((u8 *)priv->rx_buf) = data;
189 priv->rx_buf += 1;
190 break;
191 case 2:
192 *((u16 *)priv->rx_buf) = data;
193 priv->rx_buf += 2;
194 break;
195 case 3:
196 *((u16 *)priv->rx_buf) = data;
197 priv->rx_buf += 2;
198 byte3 = (u8)(data >> 16);
199 *((u8 *)priv->rx_buf) = byte3;
200 priv->rx_buf += 1;
201 break;
202 case 4:
203 /* Can not assume word aligned buffer */
204 memcpy(priv->rx_buf, &data, size);
205 priv->rx_buf += 4;
206 break;
207 default:
208 /* This will never execute */
209 break;
210 }
211 }
212 priv->bytes_to_receive -= size;
213 if (priv->bytes_to_receive < 0)
214 priv->bytes_to_receive = 0;
215 }
216
217 /*
218 * zynq_qspi_write_data - Copy data from TX buffer
219 * @zqspi: Pointer to the zynq_qspi structure
220 * @data: Pointer to the 32 bit variable where data is to be copied
221 * @size: Number of bytes to be copied from TX buffer to data
222 */
zynq_qspi_write_data(struct zynq_qspi_priv * priv,u32 * data,u8 size)223 static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
224 u32 *data, u8 size)
225 {
226 if (priv->tx_buf) {
227 switch (size) {
228 case 1:
229 *data = *((u8 *)priv->tx_buf);
230 priv->tx_buf += 1;
231 *data |= 0xFFFFFF00;
232 break;
233 case 2:
234 *data = *((u16 *)priv->tx_buf);
235 priv->tx_buf += 2;
236 *data |= 0xFFFF0000;
237 break;
238 case 3:
239 *data = *((u16 *)priv->tx_buf);
240 priv->tx_buf += 2;
241 *data |= (*((u8 *)priv->tx_buf) << 16);
242 priv->tx_buf += 1;
243 *data |= 0xFF000000;
244 break;
245 case 4:
246 /* Can not assume word aligned buffer */
247 memcpy(data, priv->tx_buf, size);
248 priv->tx_buf += 4;
249 break;
250 default:
251 /* This will never execute */
252 break;
253 }
254 } else {
255 *data = 0;
256 }
257
258 debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
259 *data, (u32)priv->tx_buf, size);
260
261 priv->bytes_to_transfer -= size;
262 if (priv->bytes_to_transfer < 0)
263 priv->bytes_to_transfer = 0;
264 }
265
zynq_qspi_chipselect(struct zynq_qspi_priv * priv,int is_on)266 static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
267 {
268 u32 confr;
269 struct zynq_qspi_regs *regs = priv->regs;
270
271 confr = readl(®s->cr);
272
273 if (is_on) {
274 /* Select the slave */
275 confr &= ~ZYNQ_QSPI_CR_SS_MASK;
276 confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
277 ZYNQ_QSPI_CR_SS_MASK;
278 } else
279 /* Deselect the slave */
280 confr |= ZYNQ_QSPI_CR_SS_MASK;
281
282 writel(confr, ®s->cr);
283 }
284
285 /*
286 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
287 * @zqspi: Pointer to the zynq_qspi structure
288 */
zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv * priv,u32 size)289 static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
290 {
291 u32 data = 0;
292 u32 fifocount = 0;
293 unsigned len, offset;
294 struct zynq_qspi_regs *regs = priv->regs;
295 static const unsigned offsets[4] = {
296 ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
297 ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
298
299 while ((fifocount < size) &&
300 (priv->bytes_to_transfer > 0)) {
301 if (priv->bytes_to_transfer >= 4) {
302 if (priv->tx_buf) {
303 memcpy(&data, priv->tx_buf, 4);
304 priv->tx_buf += 4;
305 } else {
306 data = 0;
307 }
308 writel(data, ®s->txd0r);
309 priv->bytes_to_transfer -= 4;
310 fifocount++;
311 } else {
312 /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
313 if (!(readl(®s->isr)
314 & ZYNQ_QSPI_IXR_TXOW_MASK) &&
315 !priv->rx_buf)
316 return;
317 len = priv->bytes_to_transfer;
318 zynq_qspi_write_data(priv, &data, len);
319 offset = (priv->rx_buf) ? offsets[0] : offsets[len];
320 writel(data, ®s->cr + (offset / 4));
321 }
322 }
323 }
324
325 /*
326 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
327 * @zqspi: Pointer to the zynq_qspi structure
328 *
329 * This function handles TX empty and Mode Fault interrupts only.
330 * On TX empty interrupt this function reads the received data from RX FIFO and
331 * fills the TX FIFO if there is any data remaining to be transferred.
332 * On Mode Fault interrupt this function indicates that transfer is completed,
333 * the SPI subsystem will identify the error as the remaining bytes to be
334 * transferred is non-zero.
335 *
336 * returns: 0 for poll timeout
337 * 1 transfer operation complete
338 */
zynq_qspi_irq_poll(struct zynq_qspi_priv * priv)339 static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
340 {
341 struct zynq_qspi_regs *regs = priv->regs;
342 u32 rxindex = 0;
343 u32 rxcount;
344 u32 status, timeout;
345
346 /* Poll until any of the interrupt status bits are set */
347 timeout = get_timer(0);
348 do {
349 status = readl(®s->isr);
350 } while ((status == 0) &&
351 (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
352
353 if (status == 0) {
354 printf("zynq_qspi_irq_poll: Timeout!\n");
355 return -ETIMEDOUT;
356 }
357
358 writel(status, ®s->isr);
359
360 /* Disable all interrupts */
361 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
362 if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
363 (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
364 /*
365 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
366 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
367 * is empty
368 */
369 rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
370 rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
371 while ((rxindex < rxcount) &&
372 (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
373 /* Read out the data from the RX FIFO */
374 u32 data;
375 data = readl(®s->drxr);
376
377 if (priv->bytes_to_receive >= 4) {
378 if (priv->rx_buf) {
379 memcpy(priv->rx_buf, &data, 4);
380 priv->rx_buf += 4;
381 }
382 priv->bytes_to_receive -= 4;
383 } else {
384 zynq_qspi_read_data(priv, data,
385 priv->bytes_to_receive);
386 }
387 rxindex++;
388 }
389
390 if (priv->bytes_to_transfer) {
391 /* There is more data to send */
392 zynq_qspi_fill_tx_fifo(priv,
393 ZYNQ_QSPI_RXFIFO_THRESHOLD);
394
395 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
396 } else {
397 /*
398 * If transfer and receive is completed then only send
399 * complete signal
400 */
401 if (!priv->bytes_to_receive) {
402 /* return operation complete */
403 writel(ZYNQ_QSPI_IXR_ALL_MASK,
404 ®s->idr);
405 return 1;
406 }
407 }
408 }
409
410 return 0;
411 }
412
413 /*
414 * zynq_qspi_start_transfer - Initiates the QSPI transfer
415 * @qspi: Pointer to the spi_device structure
416 * @transfer: Pointer to the spi_transfer structure which provide information
417 * about next transfer parameters
418 *
419 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
420 * transfer to be completed.
421 *
422 * returns: Number of bytes transferred in the last transfer
423 */
zynq_qspi_start_transfer(struct zynq_qspi_priv * priv)424 static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
425 {
426 u32 data = 0;
427 struct zynq_qspi_regs *regs = priv->regs;
428
429 debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
430 (u32)priv, (u32)priv, priv->len);
431
432 priv->bytes_to_transfer = priv->len;
433 priv->bytes_to_receive = priv->len;
434
435 if (priv->len < 4)
436 zynq_qspi_fill_tx_fifo(priv, priv->len);
437 else
438 zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
439
440 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
441
442 /* wait for completion */
443 do {
444 data = zynq_qspi_irq_poll(priv);
445 } while (data == 0);
446
447 return (priv->len) - (priv->bytes_to_transfer);
448 }
449
zynq_qspi_transfer(struct zynq_qspi_priv * priv)450 static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
451 {
452 unsigned cs_change = 1;
453 int status = 0;
454
455 while (1) {
456 /* Select the chip if required */
457 if (cs_change)
458 zynq_qspi_chipselect(priv, 1);
459
460 cs_change = priv->cs_change;
461
462 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
463 status = -1;
464 break;
465 }
466
467 /* Request the transfer */
468 if (priv->len) {
469 status = zynq_qspi_start_transfer(priv);
470 priv->is_inst = 0;
471 }
472
473 if (status != priv->len) {
474 if (status > 0)
475 status = -EMSGSIZE;
476 debug("zynq_qspi_transfer:%d len:%d\n",
477 status, priv->len);
478 break;
479 }
480 status = 0;
481
482 if (cs_change)
483 /* Deselect the chip */
484 zynq_qspi_chipselect(priv, 0);
485
486 break;
487 }
488
489 return status;
490 }
491
zynq_qspi_claim_bus(struct udevice * dev)492 static int zynq_qspi_claim_bus(struct udevice *dev)
493 {
494 struct udevice *bus = dev->parent;
495 struct zynq_qspi_priv *priv = dev_get_priv(bus);
496 struct zynq_qspi_regs *regs = priv->regs;
497
498 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
499
500 return 0;
501 }
502
zynq_qspi_release_bus(struct udevice * dev)503 static int zynq_qspi_release_bus(struct udevice *dev)
504 {
505 struct udevice *bus = dev->parent;
506 struct zynq_qspi_priv *priv = dev_get_priv(bus);
507 struct zynq_qspi_regs *regs = priv->regs;
508
509 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
510
511 return 0;
512 }
513
zynq_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)514 static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
515 const void *dout, void *din, unsigned long flags)
516 {
517 struct udevice *bus = dev->parent;
518 struct zynq_qspi_priv *priv = dev_get_priv(bus);
519 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
520
521 priv->cs = slave_plat->cs;
522 priv->tx_buf = dout;
523 priv->rx_buf = din;
524 priv->len = bitlen / 8;
525
526 debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
527 bus->seq, slave_plat->cs, bitlen, priv->len, flags);
528
529 /*
530 * Festering sore.
531 * Assume that the beginning of a transfer with bits to
532 * transmit must contain a device command.
533 */
534 if (dout && flags & SPI_XFER_BEGIN)
535 priv->is_inst = 1;
536 else
537 priv->is_inst = 0;
538
539 if (flags & SPI_XFER_END)
540 priv->cs_change = 1;
541 else
542 priv->cs_change = 0;
543
544 zynq_qspi_transfer(priv);
545
546 return 0;
547 }
548
zynq_qspi_set_speed(struct udevice * bus,uint speed)549 static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
550 {
551 struct zynq_qspi_platdata *plat = bus->platdata;
552 struct zynq_qspi_priv *priv = dev_get_priv(bus);
553 struct zynq_qspi_regs *regs = priv->regs;
554 uint32_t confr;
555 u8 baud_rate_val = 0;
556
557 if (speed > plat->frequency)
558 speed = plat->frequency;
559
560 /* Set the clock frequency */
561 confr = readl(®s->cr);
562 if (speed == 0) {
563 /* Set baudrate x8, if the freq is 0 */
564 baud_rate_val = 0x2;
565 } else if (plat->speed_hz != speed) {
566 while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
567 ((plat->frequency /
568 (2 << baud_rate_val)) > speed))
569 baud_rate_val++;
570
571 plat->speed_hz = speed / (2 << baud_rate_val);
572 }
573 confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
574 confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
575
576 writel(confr, ®s->cr);
577 priv->freq = speed;
578
579 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
580
581 return 0;
582 }
583
zynq_qspi_set_mode(struct udevice * bus,uint mode)584 static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
585 {
586 struct zynq_qspi_priv *priv = dev_get_priv(bus);
587 struct zynq_qspi_regs *regs = priv->regs;
588 uint32_t confr;
589
590 /* Set the SPI Clock phase and polarities */
591 confr = readl(®s->cr);
592 confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
593
594 if (mode & SPI_CPHA)
595 confr |= ZYNQ_QSPI_CR_CPHA_MASK;
596 if (mode & SPI_CPOL)
597 confr |= ZYNQ_QSPI_CR_CPOL_MASK;
598
599 writel(confr, ®s->cr);
600 priv->mode = mode;
601
602 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
603
604 return 0;
605 }
606
607 static const struct dm_spi_ops zynq_qspi_ops = {
608 .claim_bus = zynq_qspi_claim_bus,
609 .release_bus = zynq_qspi_release_bus,
610 .xfer = zynq_qspi_xfer,
611 .set_speed = zynq_qspi_set_speed,
612 .set_mode = zynq_qspi_set_mode,
613 };
614
615 static const struct udevice_id zynq_qspi_ids[] = {
616 { .compatible = "xlnx,zynq-qspi-1.0" },
617 { }
618 };
619
620 U_BOOT_DRIVER(zynq_qspi) = {
621 .name = "zynq_qspi",
622 .id = UCLASS_SPI,
623 .of_match = zynq_qspi_ids,
624 .ops = &zynq_qspi_ops,
625 .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
626 .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
627 .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
628 .probe = zynq_qspi_probe,
629 };
630