xref: /openbmc/linux/drivers/tty/serial/fsl_lpuart.c (revision 8eb92cfc)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Freescale lpuart serial port driver
4  *
5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/console.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dmapool.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18 #include <linux/irq.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_dma.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/serial_core.h>
26 #include <linux/slab.h>
27 #include <linux/tty_flip.h>
28 
29 /* All registers are 8-bit width */
30 #define UARTBDH			0x00
31 #define UARTBDL			0x01
32 #define UARTCR1			0x02
33 #define UARTCR2			0x03
34 #define UARTSR1			0x04
35 #define UARTCR3			0x06
36 #define UARTDR			0x07
37 #define UARTCR4			0x0a
38 #define UARTCR5			0x0b
39 #define UARTMODEM		0x0d
40 #define UARTPFIFO		0x10
41 #define UARTCFIFO		0x11
42 #define UARTSFIFO		0x12
43 #define UARTTWFIFO		0x13
44 #define UARTTCFIFO		0x14
45 #define UARTRWFIFO		0x15
46 
47 #define UARTBDH_LBKDIE		0x80
48 #define UARTBDH_RXEDGIE		0x40
49 #define UARTBDH_SBR_MASK	0x1f
50 
51 #define UARTCR1_LOOPS		0x80
52 #define UARTCR1_RSRC		0x20
53 #define UARTCR1_M		0x10
54 #define UARTCR1_WAKE		0x08
55 #define UARTCR1_ILT		0x04
56 #define UARTCR1_PE		0x02
57 #define UARTCR1_PT		0x01
58 
59 #define UARTCR2_TIE		0x80
60 #define UARTCR2_TCIE		0x40
61 #define UARTCR2_RIE		0x20
62 #define UARTCR2_ILIE		0x10
63 #define UARTCR2_TE		0x08
64 #define UARTCR2_RE		0x04
65 #define UARTCR2_RWU		0x02
66 #define UARTCR2_SBK		0x01
67 
68 #define UARTSR1_TDRE		0x80
69 #define UARTSR1_TC		0x40
70 #define UARTSR1_RDRF		0x20
71 #define UARTSR1_IDLE		0x10
72 #define UARTSR1_OR		0x08
73 #define UARTSR1_NF		0x04
74 #define UARTSR1_FE		0x02
75 #define UARTSR1_PE		0x01
76 
77 #define UARTCR3_R8		0x80
78 #define UARTCR3_T8		0x40
79 #define UARTCR3_TXDIR		0x20
80 #define UARTCR3_TXINV		0x10
81 #define UARTCR3_ORIE		0x08
82 #define UARTCR3_NEIE		0x04
83 #define UARTCR3_FEIE		0x02
84 #define UARTCR3_PEIE		0x01
85 
86 #define UARTCR4_MAEN1		0x80
87 #define UARTCR4_MAEN2		0x40
88 #define UARTCR4_M10		0x20
89 #define UARTCR4_BRFA_MASK	0x1f
90 #define UARTCR4_BRFA_OFF	0
91 
92 #define UARTCR5_TDMAS		0x80
93 #define UARTCR5_RDMAS		0x20
94 
95 #define UARTMODEM_RXRTSE	0x08
96 #define UARTMODEM_TXRTSPOL	0x04
97 #define UARTMODEM_TXRTSE	0x02
98 #define UARTMODEM_TXCTSE	0x01
99 
100 #define UARTPFIFO_TXFE		0x80
101 #define UARTPFIFO_FIFOSIZE_MASK	0x7
102 #define UARTPFIFO_TXSIZE_OFF	4
103 #define UARTPFIFO_RXFE		0x08
104 #define UARTPFIFO_RXSIZE_OFF	0
105 
106 #define UARTCFIFO_TXFLUSH	0x80
107 #define UARTCFIFO_RXFLUSH	0x40
108 #define UARTCFIFO_RXOFE		0x04
109 #define UARTCFIFO_TXOFE		0x02
110 #define UARTCFIFO_RXUFE		0x01
111 
112 #define UARTSFIFO_TXEMPT	0x80
113 #define UARTSFIFO_RXEMPT	0x40
114 #define UARTSFIFO_RXOF		0x04
115 #define UARTSFIFO_TXOF		0x02
116 #define UARTSFIFO_RXUF		0x01
117 
118 /* 32-bit global registers only for i.MX7ULP/i.MX8x
119  * Used to reset all internal logic and registers, except the Global Register.
120  */
121 #define UART_GLOBAL		0x8
122 
123 /* 32-bit register definition */
124 #define UARTBAUD		0x00
125 #define UARTSTAT		0x04
126 #define UARTCTRL		0x08
127 #define UARTDATA		0x0C
128 #define UARTMATCH		0x10
129 #define UARTMODIR		0x14
130 #define UARTFIFO		0x18
131 #define UARTWATER		0x1c
132 
133 #define UARTBAUD_MAEN1		0x80000000
134 #define UARTBAUD_MAEN2		0x40000000
135 #define UARTBAUD_M10		0x20000000
136 #define UARTBAUD_TDMAE		0x00800000
137 #define UARTBAUD_RDMAE		0x00200000
138 #define UARTBAUD_MATCFG		0x00400000
139 #define UARTBAUD_BOTHEDGE	0x00020000
140 #define UARTBAUD_RESYNCDIS	0x00010000
141 #define UARTBAUD_LBKDIE		0x00008000
142 #define UARTBAUD_RXEDGIE	0x00004000
143 #define UARTBAUD_SBNS		0x00002000
144 #define UARTBAUD_SBR		0x00000000
145 #define UARTBAUD_SBR_MASK	0x1fff
146 #define UARTBAUD_OSR_MASK       0x1f
147 #define UARTBAUD_OSR_SHIFT      24
148 
149 #define UARTSTAT_LBKDIF		0x80000000
150 #define UARTSTAT_RXEDGIF	0x40000000
151 #define UARTSTAT_MSBF		0x20000000
152 #define UARTSTAT_RXINV		0x10000000
153 #define UARTSTAT_RWUID		0x08000000
154 #define UARTSTAT_BRK13		0x04000000
155 #define UARTSTAT_LBKDE		0x02000000
156 #define UARTSTAT_RAF		0x01000000
157 #define UARTSTAT_TDRE		0x00800000
158 #define UARTSTAT_TC		0x00400000
159 #define UARTSTAT_RDRF		0x00200000
160 #define UARTSTAT_IDLE		0x00100000
161 #define UARTSTAT_OR		0x00080000
162 #define UARTSTAT_NF		0x00040000
163 #define UARTSTAT_FE		0x00020000
164 #define UARTSTAT_PE		0x00010000
165 #define UARTSTAT_MA1F		0x00008000
166 #define UARTSTAT_M21F		0x00004000
167 
168 #define UARTCTRL_R8T9		0x80000000
169 #define UARTCTRL_R9T8		0x40000000
170 #define UARTCTRL_TXDIR		0x20000000
171 #define UARTCTRL_TXINV		0x10000000
172 #define UARTCTRL_ORIE		0x08000000
173 #define UARTCTRL_NEIE		0x04000000
174 #define UARTCTRL_FEIE		0x02000000
175 #define UARTCTRL_PEIE		0x01000000
176 #define UARTCTRL_TIE		0x00800000
177 #define UARTCTRL_TCIE		0x00400000
178 #define UARTCTRL_RIE		0x00200000
179 #define UARTCTRL_ILIE		0x00100000
180 #define UARTCTRL_TE		0x00080000
181 #define UARTCTRL_RE		0x00040000
182 #define UARTCTRL_RWU		0x00020000
183 #define UARTCTRL_SBK		0x00010000
184 #define UARTCTRL_MA1IE		0x00008000
185 #define UARTCTRL_MA2IE		0x00004000
186 #define UARTCTRL_IDLECFG	GENMASK(10, 8)
187 #define UARTCTRL_LOOPS		0x00000080
188 #define UARTCTRL_DOZEEN		0x00000040
189 #define UARTCTRL_RSRC		0x00000020
190 #define UARTCTRL_M		0x00000010
191 #define UARTCTRL_WAKE		0x00000008
192 #define UARTCTRL_ILT		0x00000004
193 #define UARTCTRL_PE		0x00000002
194 #define UARTCTRL_PT		0x00000001
195 
196 #define UARTDATA_NOISY		0x00008000
197 #define UARTDATA_PARITYE	0x00004000
198 #define UARTDATA_FRETSC		0x00002000
199 #define UARTDATA_RXEMPT		0x00001000
200 #define UARTDATA_IDLINE		0x00000800
201 #define UARTDATA_MASK		0x3ff
202 
203 #define UARTMODIR_IREN		0x00020000
204 #define UARTMODIR_RTSWATER	GENMASK(10, 8)
205 #define UARTMODIR_TXCTSSRC	0x00000020
206 #define UARTMODIR_TXCTSC	0x00000010
207 #define UARTMODIR_RXRTSE	0x00000008
208 #define UARTMODIR_TXRTSPOL	0x00000004
209 #define UARTMODIR_TXRTSE	0x00000002
210 #define UARTMODIR_TXCTSE	0x00000001
211 
212 #define UARTFIFO_TXEMPT		0x00800000
213 #define UARTFIFO_RXEMPT		0x00400000
214 #define UARTFIFO_TXOF		0x00020000
215 #define UARTFIFO_RXUF		0x00010000
216 #define UARTFIFO_TXFLUSH	0x00008000
217 #define UARTFIFO_RXFLUSH	0x00004000
218 #define UARTFIFO_RXIDEN	GENMASK(12, 10)
219 #define UARTFIFO_TXOFE		0x00000200
220 #define UARTFIFO_RXUFE		0x00000100
221 #define UARTFIFO_TXFE		0x00000080
222 #define UARTFIFO_FIFOSIZE_MASK	0x7
223 #define UARTFIFO_TXSIZE_OFF	4
224 #define UARTFIFO_RXFE		0x00000008
225 #define UARTFIFO_RXSIZE_OFF	0
226 #define UARTFIFO_DEPTH(x)	(0x1 << ((x) ? ((x) + 1) : 0))
227 
228 #define UARTWATER_COUNT_MASK	0xff
229 #define UARTWATER_TXCNT_OFF	8
230 #define UARTWATER_RXCNT_OFF	24
231 #define UARTWATER_WATER_MASK	0xff
232 #define UARTWATER_TXWATER_OFF	0
233 #define UARTWATER_RXWATER_OFF	16
234 
235 #define UART_GLOBAL_RST	0x2
236 #define GLOBAL_RST_MIN_US	20
237 #define GLOBAL_RST_MAX_US	40
238 
239 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
240 #define DMA_RX_TIMEOUT		(10)
241 #define DMA_RX_IDLE_CHARS	8
242 #define UART_AUTOSUSPEND_TIMEOUT	3000
243 
244 #define DRIVER_NAME	"fsl-lpuart"
245 #define DEV_NAME	"ttyLP"
246 #define UART_NR		8
247 
248 /* IMX lpuart has four extra unused regs located at the beginning */
249 #define IMX_REG_OFF	0x10
250 
251 enum lpuart_type {
252 	VF610_LPUART,
253 	LS1021A_LPUART,
254 	LS1028A_LPUART,
255 	IMX7ULP_LPUART,
256 	IMX8ULP_LPUART,
257 	IMX8QXP_LPUART,
258 	IMXRT1050_LPUART,
259 };
260 
261 struct lpuart_port {
262 	struct uart_port	port;
263 	enum lpuart_type	devtype;
264 	struct clk		*ipg_clk;
265 	struct clk		*baud_clk;
266 	unsigned int		txfifo_size;
267 	unsigned int		rxfifo_size;
268 
269 	u8			rx_watermark;
270 	bool			lpuart_dma_tx_use;
271 	bool			lpuart_dma_rx_use;
272 	struct dma_chan		*dma_tx_chan;
273 	struct dma_chan		*dma_rx_chan;
274 	struct dma_async_tx_descriptor  *dma_tx_desc;
275 	struct dma_async_tx_descriptor  *dma_rx_desc;
276 	dma_cookie_t		dma_tx_cookie;
277 	dma_cookie_t		dma_rx_cookie;
278 	unsigned int		dma_tx_bytes;
279 	unsigned int		dma_rx_bytes;
280 	bool			dma_tx_in_progress;
281 	unsigned int		dma_rx_timeout;
282 	struct timer_list	lpuart_timer;
283 	struct scatterlist	rx_sgl, tx_sgl[2];
284 	struct circ_buf		rx_ring;
285 	int			rx_dma_rng_buf_len;
286 	int                     last_residue;
287 	unsigned int		dma_tx_nents;
288 	wait_queue_head_t	dma_wait;
289 	bool			is_cs7; /* Set to true when character size is 7 */
290 					/* and the parity is enabled		*/
291 	bool			dma_idle_int;
292 };
293 
294 struct lpuart_soc_data {
295 	enum lpuart_type devtype;
296 	char iotype;
297 	u8 reg_off;
298 	u8 rx_watermark;
299 };
300 
301 static const struct lpuart_soc_data vf_data = {
302 	.devtype = VF610_LPUART,
303 	.iotype = UPIO_MEM,
304 	.rx_watermark = 1,
305 };
306 
307 static const struct lpuart_soc_data ls1021a_data = {
308 	.devtype = LS1021A_LPUART,
309 	.iotype = UPIO_MEM32BE,
310 	.rx_watermark = 1,
311 };
312 
313 static const struct lpuart_soc_data ls1028a_data = {
314 	.devtype = LS1028A_LPUART,
315 	.iotype = UPIO_MEM32,
316 	.rx_watermark = 0,
317 };
318 
319 static struct lpuart_soc_data imx7ulp_data = {
320 	.devtype = IMX7ULP_LPUART,
321 	.iotype = UPIO_MEM32,
322 	.reg_off = IMX_REG_OFF,
323 	.rx_watermark = 1,
324 };
325 
326 static struct lpuart_soc_data imx8ulp_data = {
327 	.devtype = IMX8ULP_LPUART,
328 	.iotype = UPIO_MEM32,
329 	.reg_off = IMX_REG_OFF,
330 	.rx_watermark = 3,
331 };
332 
333 static struct lpuart_soc_data imx8qxp_data = {
334 	.devtype = IMX8QXP_LPUART,
335 	.iotype = UPIO_MEM32,
336 	.reg_off = IMX_REG_OFF,
337 	.rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
338 };
339 static struct lpuart_soc_data imxrt1050_data = {
340 	.devtype = IMXRT1050_LPUART,
341 	.iotype = UPIO_MEM32,
342 	.reg_off = IMX_REG_OFF,
343 	.rx_watermark = 1,
344 };
345 
346 static const struct of_device_id lpuart_dt_ids[] = {
347 	{ .compatible = "fsl,vf610-lpuart",	.data = &vf_data, },
348 	{ .compatible = "fsl,ls1021a-lpuart",	.data = &ls1021a_data, },
349 	{ .compatible = "fsl,ls1028a-lpuart",	.data = &ls1028a_data, },
350 	{ .compatible = "fsl,imx7ulp-lpuart",	.data = &imx7ulp_data, },
351 	{ .compatible = "fsl,imx8ulp-lpuart",	.data = &imx8ulp_data, },
352 	{ .compatible = "fsl,imx8qxp-lpuart",	.data = &imx8qxp_data, },
353 	{ .compatible = "fsl,imxrt1050-lpuart",	.data = &imxrt1050_data},
354 	{ /* sentinel */ }
355 };
356 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
357 
358 /* Forward declare this for the dma callbacks*/
359 static void lpuart_dma_tx_complete(void *arg);
360 
is_layerscape_lpuart(struct lpuart_port * sport)361 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
362 {
363 	return (sport->devtype == LS1021A_LPUART ||
364 		sport->devtype == LS1028A_LPUART);
365 }
366 
is_imx7ulp_lpuart(struct lpuart_port * sport)367 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
368 {
369 	return sport->devtype == IMX7ULP_LPUART;
370 }
371 
is_imx8ulp_lpuart(struct lpuart_port * sport)372 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)
373 {
374 	return sport->devtype == IMX8ULP_LPUART;
375 }
376 
is_imx8qxp_lpuart(struct lpuart_port * sport)377 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
378 {
379 	return sport->devtype == IMX8QXP_LPUART;
380 }
381 
lpuart32_read(struct uart_port * port,u32 off)382 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
383 {
384 	switch (port->iotype) {
385 	case UPIO_MEM32:
386 		return readl(port->membase + off);
387 	case UPIO_MEM32BE:
388 		return ioread32be(port->membase + off);
389 	default:
390 		return 0;
391 	}
392 }
393 
lpuart32_write(struct uart_port * port,u32 val,u32 off)394 static inline void lpuart32_write(struct uart_port *port, u32 val,
395 				  u32 off)
396 {
397 	switch (port->iotype) {
398 	case UPIO_MEM32:
399 		writel(val, port->membase + off);
400 		break;
401 	case UPIO_MEM32BE:
402 		iowrite32be(val, port->membase + off);
403 		break;
404 	}
405 }
406 
__lpuart_enable_clks(struct lpuart_port * sport,bool is_en)407 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
408 {
409 	int ret = 0;
410 
411 	if (is_en) {
412 		ret = clk_prepare_enable(sport->ipg_clk);
413 		if (ret)
414 			return ret;
415 
416 		ret = clk_prepare_enable(sport->baud_clk);
417 		if (ret) {
418 			clk_disable_unprepare(sport->ipg_clk);
419 			return ret;
420 		}
421 	} else {
422 		clk_disable_unprepare(sport->baud_clk);
423 		clk_disable_unprepare(sport->ipg_clk);
424 	}
425 
426 	return 0;
427 }
428 
lpuart_get_baud_clk_rate(struct lpuart_port * sport)429 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
430 {
431 	if (is_imx8qxp_lpuart(sport))
432 		return clk_get_rate(sport->baud_clk);
433 
434 	return clk_get_rate(sport->ipg_clk);
435 }
436 
437 #define lpuart_enable_clks(x)	__lpuart_enable_clks(x, true)
438 #define lpuart_disable_clks(x)	__lpuart_enable_clks(x, false)
439 
lpuart_stop_tx(struct uart_port * port)440 static void lpuart_stop_tx(struct uart_port *port)
441 {
442 	unsigned char temp;
443 
444 	temp = readb(port->membase + UARTCR2);
445 	temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
446 	writeb(temp, port->membase + UARTCR2);
447 }
448 
lpuart32_stop_tx(struct uart_port * port)449 static void lpuart32_stop_tx(struct uart_port *port)
450 {
451 	unsigned long temp;
452 
453 	temp = lpuart32_read(port, UARTCTRL);
454 	temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
455 	lpuart32_write(port, temp, UARTCTRL);
456 }
457 
lpuart_stop_rx(struct uart_port * port)458 static void lpuart_stop_rx(struct uart_port *port)
459 {
460 	unsigned char temp;
461 
462 	temp = readb(port->membase + UARTCR2);
463 	writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
464 }
465 
lpuart32_stop_rx(struct uart_port * port)466 static void lpuart32_stop_rx(struct uart_port *port)
467 {
468 	unsigned long temp;
469 
470 	temp = lpuart32_read(port, UARTCTRL);
471 	lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
472 }
473 
lpuart_dma_tx(struct lpuart_port * sport)474 static void lpuart_dma_tx(struct lpuart_port *sport)
475 {
476 	struct circ_buf *xmit = &sport->port.state->xmit;
477 	struct scatterlist *sgl = sport->tx_sgl;
478 	struct device *dev = sport->port.dev;
479 	struct dma_chan *chan = sport->dma_tx_chan;
480 	int ret;
481 
482 	if (sport->dma_tx_in_progress)
483 		return;
484 
485 	sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
486 
487 	if (xmit->tail < xmit->head || xmit->head == 0) {
488 		sport->dma_tx_nents = 1;
489 		sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
490 	} else {
491 		sport->dma_tx_nents = 2;
492 		sg_init_table(sgl, 2);
493 		sg_set_buf(sgl, xmit->buf + xmit->tail,
494 				UART_XMIT_SIZE - xmit->tail);
495 		sg_set_buf(sgl + 1, xmit->buf, xmit->head);
496 	}
497 
498 	ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
499 			 DMA_TO_DEVICE);
500 	if (!ret) {
501 		dev_err(dev, "DMA mapping error for TX.\n");
502 		return;
503 	}
504 
505 	sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
506 					ret, DMA_MEM_TO_DEV,
507 					DMA_PREP_INTERRUPT);
508 	if (!sport->dma_tx_desc) {
509 		dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
510 			      DMA_TO_DEVICE);
511 		dev_err(dev, "Cannot prepare TX slave DMA!\n");
512 		return;
513 	}
514 
515 	sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
516 	sport->dma_tx_desc->callback_param = sport;
517 	sport->dma_tx_in_progress = true;
518 	sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
519 	dma_async_issue_pending(chan);
520 }
521 
lpuart_stopped_or_empty(struct uart_port * port)522 static bool lpuart_stopped_or_empty(struct uart_port *port)
523 {
524 	return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
525 }
526 
lpuart_dma_tx_complete(void * arg)527 static void lpuart_dma_tx_complete(void *arg)
528 {
529 	struct lpuart_port *sport = arg;
530 	struct scatterlist *sgl = &sport->tx_sgl[0];
531 	struct circ_buf *xmit = &sport->port.state->xmit;
532 	struct dma_chan *chan = sport->dma_tx_chan;
533 	unsigned long flags;
534 
535 	spin_lock_irqsave(&sport->port.lock, flags);
536 	if (!sport->dma_tx_in_progress) {
537 		spin_unlock_irqrestore(&sport->port.lock, flags);
538 		return;
539 	}
540 
541 	dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
542 		     DMA_TO_DEVICE);
543 
544 	uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
545 	sport->dma_tx_in_progress = false;
546 	spin_unlock_irqrestore(&sport->port.lock, flags);
547 
548 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
549 		uart_write_wakeup(&sport->port);
550 
551 	if (waitqueue_active(&sport->dma_wait)) {
552 		wake_up(&sport->dma_wait);
553 		return;
554 	}
555 
556 	spin_lock_irqsave(&sport->port.lock, flags);
557 
558 	if (!lpuart_stopped_or_empty(&sport->port))
559 		lpuart_dma_tx(sport);
560 
561 	spin_unlock_irqrestore(&sport->port.lock, flags);
562 }
563 
lpuart_dma_datareg_addr(struct lpuart_port * sport)564 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
565 {
566 	switch (sport->port.iotype) {
567 	case UPIO_MEM32:
568 		return sport->port.mapbase + UARTDATA;
569 	case UPIO_MEM32BE:
570 		return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
571 	}
572 	return sport->port.mapbase + UARTDR;
573 }
574 
lpuart_dma_tx_request(struct uart_port * port)575 static int lpuart_dma_tx_request(struct uart_port *port)
576 {
577 	struct lpuart_port *sport = container_of(port,
578 					struct lpuart_port, port);
579 	struct dma_slave_config dma_tx_sconfig = {};
580 	int ret;
581 
582 	dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
583 	dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
584 	dma_tx_sconfig.dst_maxburst = 1;
585 	dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
586 	ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
587 
588 	if (ret) {
589 		dev_err(sport->port.dev,
590 				"DMA slave config failed, err = %d\n", ret);
591 		return ret;
592 	}
593 
594 	return 0;
595 }
596 
lpuart_is_32(struct lpuart_port * sport)597 static bool lpuart_is_32(struct lpuart_port *sport)
598 {
599 	return sport->port.iotype == UPIO_MEM32 ||
600 	       sport->port.iotype ==  UPIO_MEM32BE;
601 }
602 
lpuart_flush_buffer(struct uart_port * port)603 static void lpuart_flush_buffer(struct uart_port *port)
604 {
605 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
606 	struct dma_chan *chan = sport->dma_tx_chan;
607 	u32 val;
608 
609 	if (sport->lpuart_dma_tx_use) {
610 		if (sport->dma_tx_in_progress) {
611 			dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
612 				sport->dma_tx_nents, DMA_TO_DEVICE);
613 			sport->dma_tx_in_progress = false;
614 		}
615 		dmaengine_terminate_async(chan);
616 	}
617 
618 	if (lpuart_is_32(sport)) {
619 		val = lpuart32_read(&sport->port, UARTFIFO);
620 		val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
621 		lpuart32_write(&sport->port, val, UARTFIFO);
622 	} else {
623 		val = readb(sport->port.membase + UARTCFIFO);
624 		val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
625 		writeb(val, sport->port.membase + UARTCFIFO);
626 	}
627 }
628 
lpuart_wait_bit_set(struct uart_port * port,unsigned int offset,u8 bit)629 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
630 				u8 bit)
631 {
632 	while (!(readb(port->membase + offset) & bit))
633 		cpu_relax();
634 }
635 
lpuart32_wait_bit_set(struct uart_port * port,unsigned int offset,u32 bit)636 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
637 				  u32 bit)
638 {
639 	while (!(lpuart32_read(port, offset) & bit))
640 		cpu_relax();
641 }
642 
643 #if defined(CONFIG_CONSOLE_POLL)
644 
lpuart_poll_init(struct uart_port * port)645 static int lpuart_poll_init(struct uart_port *port)
646 {
647 	struct lpuart_port *sport = container_of(port,
648 					struct lpuart_port, port);
649 	unsigned long flags;
650 	unsigned char temp;
651 
652 	sport->port.fifosize = 0;
653 
654 	spin_lock_irqsave(&sport->port.lock, flags);
655 	/* Disable Rx & Tx */
656 	writeb(0, sport->port.membase + UARTCR2);
657 
658 	temp = readb(sport->port.membase + UARTPFIFO);
659 	/* Enable Rx and Tx FIFO */
660 	writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
661 			sport->port.membase + UARTPFIFO);
662 
663 	/* flush Tx and Rx FIFO */
664 	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
665 			sport->port.membase + UARTCFIFO);
666 
667 	/* explicitly clear RDRF */
668 	if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
669 		readb(sport->port.membase + UARTDR);
670 		writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
671 	}
672 
673 	writeb(0, sport->port.membase + UARTTWFIFO);
674 	writeb(1, sport->port.membase + UARTRWFIFO);
675 
676 	/* Enable Rx and Tx */
677 	writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
678 	spin_unlock_irqrestore(&sport->port.lock, flags);
679 
680 	return 0;
681 }
682 
lpuart_poll_put_char(struct uart_port * port,unsigned char c)683 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
684 {
685 	/* drain */
686 	lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
687 	writeb(c, port->membase + UARTDR);
688 }
689 
lpuart_poll_get_char(struct uart_port * port)690 static int lpuart_poll_get_char(struct uart_port *port)
691 {
692 	if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
693 		return NO_POLL_CHAR;
694 
695 	return readb(port->membase + UARTDR);
696 }
697 
lpuart32_poll_init(struct uart_port * port)698 static int lpuart32_poll_init(struct uart_port *port)
699 {
700 	unsigned long flags;
701 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
702 	u32 temp;
703 
704 	sport->port.fifosize = 0;
705 
706 	spin_lock_irqsave(&sport->port.lock, flags);
707 
708 	/* Disable Rx & Tx */
709 	lpuart32_write(&sport->port, 0, UARTCTRL);
710 
711 	temp = lpuart32_read(&sport->port, UARTFIFO);
712 
713 	/* Enable Rx and Tx FIFO */
714 	lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
715 
716 	/* flush Tx and Rx FIFO */
717 	lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
718 
719 	/* explicitly clear RDRF */
720 	if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
721 		lpuart32_read(&sport->port, UARTDATA);
722 		lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
723 	}
724 
725 	/* Enable Rx and Tx */
726 	lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
727 	spin_unlock_irqrestore(&sport->port.lock, flags);
728 
729 	return 0;
730 }
731 
lpuart32_poll_put_char(struct uart_port * port,unsigned char c)732 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
733 {
734 	lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
735 	lpuart32_write(port, c, UARTDATA);
736 }
737 
lpuart32_poll_get_char(struct uart_port * port)738 static int lpuart32_poll_get_char(struct uart_port *port)
739 {
740 	if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
741 		return NO_POLL_CHAR;
742 
743 	return lpuart32_read(port, UARTDATA);
744 }
745 #endif
746 
lpuart_transmit_buffer(struct lpuart_port * sport)747 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
748 {
749 	struct uart_port *port = &sport->port;
750 	u8 ch;
751 
752 	uart_port_tx(port, ch,
753 		readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
754 		writeb(ch, port->membase + UARTDR));
755 }
756 
lpuart32_transmit_buffer(struct lpuart_port * sport)757 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
758 {
759 	struct circ_buf *xmit = &sport->port.state->xmit;
760 	unsigned long txcnt;
761 
762 	if (sport->port.x_char) {
763 		lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
764 		sport->port.icount.tx++;
765 		sport->port.x_char = 0;
766 		return;
767 	}
768 
769 	if (lpuart_stopped_or_empty(&sport->port)) {
770 		lpuart32_stop_tx(&sport->port);
771 		return;
772 	}
773 
774 	txcnt = lpuart32_read(&sport->port, UARTWATER);
775 	txcnt = txcnt >> UARTWATER_TXCNT_OFF;
776 	txcnt &= UARTWATER_COUNT_MASK;
777 	while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
778 		lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
779 		uart_xmit_advance(&sport->port, 1);
780 		txcnt = lpuart32_read(&sport->port, UARTWATER);
781 		txcnt = txcnt >> UARTWATER_TXCNT_OFF;
782 		txcnt &= UARTWATER_COUNT_MASK;
783 	}
784 
785 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
786 		uart_write_wakeup(&sport->port);
787 
788 	if (uart_circ_empty(xmit))
789 		lpuart32_stop_tx(&sport->port);
790 }
791 
lpuart_start_tx(struct uart_port * port)792 static void lpuart_start_tx(struct uart_port *port)
793 {
794 	struct lpuart_port *sport = container_of(port,
795 			struct lpuart_port, port);
796 	unsigned char temp;
797 
798 	temp = readb(port->membase + UARTCR2);
799 	writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
800 
801 	if (sport->lpuart_dma_tx_use) {
802 		if (!lpuart_stopped_or_empty(port))
803 			lpuart_dma_tx(sport);
804 	} else {
805 		if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
806 			lpuart_transmit_buffer(sport);
807 	}
808 }
809 
lpuart32_start_tx(struct uart_port * port)810 static void lpuart32_start_tx(struct uart_port *port)
811 {
812 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
813 	unsigned long temp;
814 
815 	if (sport->lpuart_dma_tx_use) {
816 		if (!lpuart_stopped_or_empty(port))
817 			lpuart_dma_tx(sport);
818 	} else {
819 		temp = lpuart32_read(port, UARTCTRL);
820 		lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
821 
822 		if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
823 			lpuart32_transmit_buffer(sport);
824 	}
825 }
826 
827 static void
lpuart_uart_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)828 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
829 {
830 	switch (state) {
831 	case UART_PM_STATE_OFF:
832 		pm_runtime_mark_last_busy(port->dev);
833 		pm_runtime_put_autosuspend(port->dev);
834 		break;
835 	default:
836 		pm_runtime_get_sync(port->dev);
837 		break;
838 	}
839 }
840 
841 /* return TIOCSER_TEMT when transmitter is not busy */
lpuart_tx_empty(struct uart_port * port)842 static unsigned int lpuart_tx_empty(struct uart_port *port)
843 {
844 	struct lpuart_port *sport = container_of(port,
845 			struct lpuart_port, port);
846 	unsigned char sr1 = readb(port->membase + UARTSR1);
847 	unsigned char sfifo = readb(port->membase + UARTSFIFO);
848 
849 	if (sport->dma_tx_in_progress)
850 		return 0;
851 
852 	if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
853 		return TIOCSER_TEMT;
854 
855 	return 0;
856 }
857 
lpuart32_tx_empty(struct uart_port * port)858 static unsigned int lpuart32_tx_empty(struct uart_port *port)
859 {
860 	struct lpuart_port *sport = container_of(port,
861 			struct lpuart_port, port);
862 	unsigned long stat = lpuart32_read(port, UARTSTAT);
863 	unsigned long sfifo = lpuart32_read(port, UARTFIFO);
864 	unsigned long ctrl = lpuart32_read(port, UARTCTRL);
865 
866 	if (sport->dma_tx_in_progress)
867 		return 0;
868 
869 	/*
870 	 * LPUART Transmission Complete Flag may never be set while queuing a break
871 	 * character, so avoid checking for transmission complete when UARTCTRL_SBK
872 	 * is asserted.
873 	 */
874 	if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
875 		return TIOCSER_TEMT;
876 
877 	return 0;
878 }
879 
lpuart_txint(struct lpuart_port * sport)880 static void lpuart_txint(struct lpuart_port *sport)
881 {
882 	spin_lock(&sport->port.lock);
883 	lpuart_transmit_buffer(sport);
884 	spin_unlock(&sport->port.lock);
885 }
886 
lpuart_rxint(struct lpuart_port * sport)887 static void lpuart_rxint(struct lpuart_port *sport)
888 {
889 	unsigned int flg, ignored = 0, overrun = 0;
890 	struct tty_port *port = &sport->port.state->port;
891 	unsigned char rx, sr;
892 
893 	spin_lock(&sport->port.lock);
894 
895 	while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
896 		flg = TTY_NORMAL;
897 		sport->port.icount.rx++;
898 		/*
899 		 * to clear the FE, OR, NF, FE, PE flags,
900 		 * read SR1 then read DR
901 		 */
902 		sr = readb(sport->port.membase + UARTSR1);
903 		rx = readb(sport->port.membase + UARTDR);
904 
905 		if (uart_prepare_sysrq_char(&sport->port, rx))
906 			continue;
907 
908 		if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
909 			if (sr & UARTSR1_PE)
910 				sport->port.icount.parity++;
911 			else if (sr & UARTSR1_FE)
912 				sport->port.icount.frame++;
913 
914 			if (sr & UARTSR1_OR)
915 				overrun++;
916 
917 			if (sr & sport->port.ignore_status_mask) {
918 				if (++ignored > 100)
919 					goto out;
920 				continue;
921 			}
922 
923 			sr &= sport->port.read_status_mask;
924 
925 			if (sr & UARTSR1_PE)
926 				flg = TTY_PARITY;
927 			else if (sr & UARTSR1_FE)
928 				flg = TTY_FRAME;
929 
930 			if (sr & UARTSR1_OR)
931 				flg = TTY_OVERRUN;
932 
933 			sport->port.sysrq = 0;
934 		}
935 
936 		if (tty_insert_flip_char(port, rx, flg) == 0)
937 			sport->port.icount.buf_overrun++;
938 	}
939 
940 out:
941 	if (overrun) {
942 		sport->port.icount.overrun += overrun;
943 
944 		/*
945 		 * Overruns cause FIFO pointers to become missaligned.
946 		 * Flushing the receive FIFO reinitializes the pointers.
947 		 */
948 		writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
949 		writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
950 	}
951 
952 	uart_unlock_and_check_sysrq(&sport->port);
953 
954 	tty_flip_buffer_push(port);
955 }
956 
lpuart32_txint(struct lpuart_port * sport)957 static void lpuart32_txint(struct lpuart_port *sport)
958 {
959 	spin_lock(&sport->port.lock);
960 	lpuart32_transmit_buffer(sport);
961 	spin_unlock(&sport->port.lock);
962 }
963 
lpuart32_rxint(struct lpuart_port * sport)964 static void lpuart32_rxint(struct lpuart_port *sport)
965 {
966 	unsigned int flg, ignored = 0;
967 	struct tty_port *port = &sport->port.state->port;
968 	unsigned long rx, sr;
969 	bool is_break;
970 
971 	spin_lock(&sport->port.lock);
972 
973 	while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
974 		flg = TTY_NORMAL;
975 		sport->port.icount.rx++;
976 		/*
977 		 * to clear the FE, OR, NF, FE, PE flags,
978 		 * read STAT then read DATA reg
979 		 */
980 		sr = lpuart32_read(&sport->port, UARTSTAT);
981 		rx = lpuart32_read(&sport->port, UARTDATA);
982 		rx &= UARTDATA_MASK;
983 
984 		/*
985 		 * The LPUART can't distinguish between a break and a framing error,
986 		 * thus we assume it is a break if the received data is zero.
987 		 */
988 		is_break = (sr & UARTSTAT_FE) && !rx;
989 
990 		if (is_break && uart_handle_break(&sport->port))
991 			continue;
992 
993 		if (uart_prepare_sysrq_char(&sport->port, rx))
994 			continue;
995 
996 		if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
997 			if (sr & UARTSTAT_PE) {
998 				sport->port.icount.parity++;
999 			} else if (sr & UARTSTAT_FE) {
1000 				if (is_break)
1001 					sport->port.icount.brk++;
1002 				else
1003 					sport->port.icount.frame++;
1004 			}
1005 
1006 			if (sr & UARTSTAT_OR)
1007 				sport->port.icount.overrun++;
1008 
1009 			if (sr & sport->port.ignore_status_mask) {
1010 				if (++ignored > 100)
1011 					goto out;
1012 				continue;
1013 			}
1014 
1015 			sr &= sport->port.read_status_mask;
1016 
1017 			if (sr & UARTSTAT_PE) {
1018 				flg = TTY_PARITY;
1019 			} else if (sr & UARTSTAT_FE) {
1020 				if (is_break)
1021 					flg = TTY_BREAK;
1022 				else
1023 					flg = TTY_FRAME;
1024 			}
1025 
1026 			if (sr & UARTSTAT_OR)
1027 				flg = TTY_OVERRUN;
1028 		}
1029 
1030 		if (sport->is_cs7)
1031 			rx &= 0x7F;
1032 
1033 		if (tty_insert_flip_char(port, rx, flg) == 0)
1034 			sport->port.icount.buf_overrun++;
1035 	}
1036 
1037 out:
1038 	uart_unlock_and_check_sysrq(&sport->port);
1039 
1040 	tty_flip_buffer_push(port);
1041 }
1042 
lpuart_int(int irq,void * dev_id)1043 static irqreturn_t lpuart_int(int irq, void *dev_id)
1044 {
1045 	struct lpuart_port *sport = dev_id;
1046 	unsigned char sts;
1047 
1048 	sts = readb(sport->port.membase + UARTSR1);
1049 
1050 	/* SysRq, using dma, check for linebreak by framing err. */
1051 	if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1052 		readb(sport->port.membase + UARTDR);
1053 		uart_handle_break(&sport->port);
1054 		/* linebreak produces some garbage, removing it */
1055 		writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1056 		return IRQ_HANDLED;
1057 	}
1058 
1059 	if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1060 		lpuart_rxint(sport);
1061 
1062 	if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1063 		lpuart_txint(sport);
1064 
1065 	return IRQ_HANDLED;
1066 }
1067 
lpuart_handle_sysrq_chars(struct uart_port * port,unsigned char * p,int count)1068 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1069 					     unsigned char *p, int count)
1070 {
1071 	while (count--) {
1072 		if (*p && uart_handle_sysrq_char(port, *p))
1073 			return;
1074 		p++;
1075 	}
1076 }
1077 
lpuart_handle_sysrq(struct lpuart_port * sport)1078 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1079 {
1080 	struct circ_buf *ring = &sport->rx_ring;
1081 	int count;
1082 
1083 	if (ring->head < ring->tail) {
1084 		count = sport->rx_sgl.length - ring->tail;
1085 		lpuart_handle_sysrq_chars(&sport->port,
1086 					  ring->buf + ring->tail, count);
1087 		ring->tail = 0;
1088 	}
1089 
1090 	if (ring->head > ring->tail) {
1091 		count = ring->head - ring->tail;
1092 		lpuart_handle_sysrq_chars(&sport->port,
1093 					  ring->buf + ring->tail, count);
1094 		ring->tail = ring->head;
1095 	}
1096 }
1097 
lpuart_tty_insert_flip_string(struct tty_port * port,unsigned char * chars,size_t size,bool is_cs7)1098 static int lpuart_tty_insert_flip_string(struct tty_port *port,
1099 	unsigned char *chars, size_t size, bool is_cs7)
1100 {
1101 	int i;
1102 
1103 	if (is_cs7)
1104 		for (i = 0; i < size; i++)
1105 			chars[i] &= 0x7F;
1106 	return tty_insert_flip_string(port, chars, size);
1107 }
1108 
lpuart_copy_rx_to_tty(struct lpuart_port * sport)1109 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1110 {
1111 	struct tty_port *port = &sport->port.state->port;
1112 	struct dma_tx_state state;
1113 	enum dma_status dmastat;
1114 	struct dma_chan *chan = sport->dma_rx_chan;
1115 	struct circ_buf *ring = &sport->rx_ring;
1116 	unsigned long flags;
1117 	int count, copied;
1118 
1119 	if (lpuart_is_32(sport)) {
1120 		unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1121 
1122 		if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1123 			/* Clear the error flags */
1124 			lpuart32_write(&sport->port, sr, UARTSTAT);
1125 
1126 			if (sr & UARTSTAT_PE)
1127 				sport->port.icount.parity++;
1128 			else if (sr & UARTSTAT_FE)
1129 				sport->port.icount.frame++;
1130 		}
1131 	} else {
1132 		unsigned char sr = readb(sport->port.membase + UARTSR1);
1133 
1134 		if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1135 			unsigned char cr2;
1136 
1137 			/* Disable receiver during this operation... */
1138 			cr2 = readb(sport->port.membase + UARTCR2);
1139 			cr2 &= ~UARTCR2_RE;
1140 			writeb(cr2, sport->port.membase + UARTCR2);
1141 
1142 			/* Read DR to clear the error flags */
1143 			readb(sport->port.membase + UARTDR);
1144 
1145 			if (sr & UARTSR1_PE)
1146 				sport->port.icount.parity++;
1147 			else if (sr & UARTSR1_FE)
1148 				sport->port.icount.frame++;
1149 			/*
1150 			 * At this point parity/framing error is
1151 			 * cleared However, since the DMA already read
1152 			 * the data register and we had to read it
1153 			 * again after reading the status register to
1154 			 * properly clear the flags, the FIFO actually
1155 			 * underflowed... This requires a clearing of
1156 			 * the FIFO...
1157 			 */
1158 			if (readb(sport->port.membase + UARTSFIFO) &
1159 			    UARTSFIFO_RXUF) {
1160 				writeb(UARTSFIFO_RXUF,
1161 				       sport->port.membase + UARTSFIFO);
1162 				writeb(UARTCFIFO_RXFLUSH,
1163 				       sport->port.membase + UARTCFIFO);
1164 			}
1165 
1166 			cr2 |= UARTCR2_RE;
1167 			writeb(cr2, sport->port.membase + UARTCR2);
1168 		}
1169 	}
1170 
1171 	async_tx_ack(sport->dma_rx_desc);
1172 
1173 	spin_lock_irqsave(&sport->port.lock, flags);
1174 
1175 	dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1176 	if (dmastat == DMA_ERROR) {
1177 		dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1178 		spin_unlock_irqrestore(&sport->port.lock, flags);
1179 		return;
1180 	}
1181 
1182 	/* CPU claims ownership of RX DMA buffer */
1183 	dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1184 			    DMA_FROM_DEVICE);
1185 
1186 	/*
1187 	 * ring->head points to the end of data already written by the DMA.
1188 	 * ring->tail points to the beginning of data to be read by the
1189 	 * framework.
1190 	 * The current transfer size should not be larger than the dma buffer
1191 	 * length.
1192 	 */
1193 	ring->head = sport->rx_sgl.length - state.residue;
1194 	BUG_ON(ring->head > sport->rx_sgl.length);
1195 
1196 	/*
1197 	 * Silent handling of keys pressed in the sysrq timeframe
1198 	 */
1199 	if (sport->port.sysrq) {
1200 		lpuart_handle_sysrq(sport);
1201 		goto exit;
1202 	}
1203 
1204 	/*
1205 	 * At this point ring->head may point to the first byte right after the
1206 	 * last byte of the dma buffer:
1207 	 * 0 <= ring->head <= sport->rx_sgl.length
1208 	 *
1209 	 * However ring->tail must always points inside the dma buffer:
1210 	 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1211 	 *
1212 	 * Since we use a ring buffer, we have to handle the case
1213 	 * where head is lower than tail. In such a case, we first read from
1214 	 * tail to the end of the buffer then reset tail.
1215 	 */
1216 	if (ring->head < ring->tail) {
1217 		count = sport->rx_sgl.length - ring->tail;
1218 
1219 		copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1220 					count, sport->is_cs7);
1221 		if (copied != count)
1222 			sport->port.icount.buf_overrun++;
1223 		ring->tail = 0;
1224 		sport->port.icount.rx += copied;
1225 	}
1226 
1227 	/* Finally we read data from tail to head */
1228 	if (ring->tail < ring->head) {
1229 		count = ring->head - ring->tail;
1230 		copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1231 					count, sport->is_cs7);
1232 		if (copied != count)
1233 			sport->port.icount.buf_overrun++;
1234 		/* Wrap ring->head if needed */
1235 		if (ring->head >= sport->rx_sgl.length)
1236 			ring->head = 0;
1237 		ring->tail = ring->head;
1238 		sport->port.icount.rx += copied;
1239 	}
1240 
1241 	sport->last_residue = state.residue;
1242 
1243 exit:
1244 	dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1245 			       DMA_FROM_DEVICE);
1246 
1247 	spin_unlock_irqrestore(&sport->port.lock, flags);
1248 
1249 	tty_flip_buffer_push(port);
1250 	if (!sport->dma_idle_int)
1251 		mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1252 }
1253 
lpuart_dma_rx_complete(void * arg)1254 static void lpuart_dma_rx_complete(void *arg)
1255 {
1256 	struct lpuart_port *sport = arg;
1257 
1258 	lpuart_copy_rx_to_tty(sport);
1259 }
1260 
lpuart32_dma_idleint(struct lpuart_port * sport)1261 static void lpuart32_dma_idleint(struct lpuart_port *sport)
1262 {
1263 	enum dma_status dmastat;
1264 	struct dma_chan *chan = sport->dma_rx_chan;
1265 	struct circ_buf *ring = &sport->rx_ring;
1266 	struct dma_tx_state state;
1267 	int count = 0;
1268 
1269 	dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1270 	if (dmastat == DMA_ERROR) {
1271 		dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1272 		return;
1273 	}
1274 
1275 	ring->head = sport->rx_sgl.length - state.residue;
1276 	count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
1277 
1278 	/* Check if new data received before copying */
1279 	if (count)
1280 		lpuart_copy_rx_to_tty(sport);
1281 }
1282 
lpuart32_int(int irq,void * dev_id)1283 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1284 {
1285 	struct lpuart_port *sport = dev_id;
1286 	unsigned long sts, rxcount;
1287 
1288 	sts = lpuart32_read(&sport->port, UARTSTAT);
1289 	rxcount = lpuart32_read(&sport->port, UARTWATER);
1290 	rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1291 
1292 	if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1293 		lpuart32_rxint(sport);
1294 
1295 	if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1296 		lpuart32_txint(sport);
1297 
1298 	if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int)
1299 		lpuart32_dma_idleint(sport);
1300 
1301 	lpuart32_write(&sport->port, sts, UARTSTAT);
1302 	return IRQ_HANDLED;
1303 }
1304 
1305 /*
1306  * Timer function to simulate the hardware EOP (End Of Package) event.
1307  * The timer callback is to check for new RX data and copy to TTY buffer.
1308  * If no new data are received since last interval, the EOP condition is
1309  * met, complete the DMA transfer by copying the data. Otherwise, just
1310  * restart timer.
1311  */
lpuart_timer_func(struct timer_list * t)1312 static void lpuart_timer_func(struct timer_list *t)
1313 {
1314 	struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1315 	enum dma_status dmastat;
1316 	struct dma_chan *chan = sport->dma_rx_chan;
1317 	struct circ_buf *ring = &sport->rx_ring;
1318 	struct dma_tx_state state;
1319 	unsigned long flags;
1320 	int count;
1321 
1322 	dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1323 	if (dmastat == DMA_ERROR) {
1324 		dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1325 		return;
1326 	}
1327 
1328 	ring->head = sport->rx_sgl.length - state.residue;
1329 	count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
1330 
1331 	/* Check if new data received before copying */
1332 	if ((count != 0) && (sport->last_residue == state.residue))
1333 		lpuart_copy_rx_to_tty(sport);
1334 	else
1335 		mod_timer(&sport->lpuart_timer,
1336 			  jiffies + sport->dma_rx_timeout);
1337 
1338 	if (spin_trylock_irqsave(&sport->port.lock, flags)) {
1339 		sport->last_residue = state.residue;
1340 		spin_unlock_irqrestore(&sport->port.lock, flags);
1341 	}
1342 }
1343 
lpuart_start_rx_dma(struct lpuart_port * sport)1344 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1345 {
1346 	struct dma_slave_config dma_rx_sconfig = {};
1347 	struct circ_buf *ring = &sport->rx_ring;
1348 	int ret, nent;
1349 	struct tty_port *port = &sport->port.state->port;
1350 	struct tty_struct *tty = port->tty;
1351 	struct ktermios *termios = &tty->termios;
1352 	struct dma_chan *chan = sport->dma_rx_chan;
1353 	unsigned int bits = tty_get_frame_size(termios->c_cflag);
1354 	unsigned int baud = tty_get_baud_rate(tty);
1355 
1356 	/*
1357 	 * Calculate length of one DMA buffer size to keep latency below
1358 	 * 10ms at any baud rate.
1359 	 */
1360 	sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1361 	sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1362 	sport->rx_dma_rng_buf_len = max_t(int,
1363 					  sport->rxfifo_size * 2,
1364 					  sport->rx_dma_rng_buf_len);
1365 	/*
1366 	 * Keep this condition check in case rxfifo_size is unavailable
1367 	 * for some SoCs.
1368 	 */
1369 	if (sport->rx_dma_rng_buf_len < 16)
1370 		sport->rx_dma_rng_buf_len = 16;
1371 
1372 	sport->last_residue = 0;
1373 	sport->dma_rx_timeout = max(nsecs_to_jiffies(
1374 		sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL);
1375 
1376 	ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1377 	if (!ring->buf)
1378 		return -ENOMEM;
1379 
1380 	sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1381 	nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1382 			  DMA_FROM_DEVICE);
1383 
1384 	if (!nent) {
1385 		dev_err(sport->port.dev, "DMA Rx mapping error\n");
1386 		return -EINVAL;
1387 	}
1388 
1389 	dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1390 	dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1391 	dma_rx_sconfig.src_maxburst = 1;
1392 	dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1393 	ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1394 
1395 	if (ret < 0) {
1396 		dev_err(sport->port.dev,
1397 				"DMA Rx slave config failed, err = %d\n", ret);
1398 		return ret;
1399 	}
1400 
1401 	sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1402 				 sg_dma_address(&sport->rx_sgl),
1403 				 sport->rx_sgl.length,
1404 				 sport->rx_sgl.length / 2,
1405 				 DMA_DEV_TO_MEM,
1406 				 DMA_PREP_INTERRUPT);
1407 	if (!sport->dma_rx_desc) {
1408 		dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1409 		return -EFAULT;
1410 	}
1411 
1412 	sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1413 	sport->dma_rx_desc->callback_param = sport;
1414 	sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1415 	dma_async_issue_pending(chan);
1416 
1417 	if (lpuart_is_32(sport)) {
1418 		unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1419 
1420 		lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1421 
1422 		if (sport->dma_idle_int) {
1423 			unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL);
1424 
1425 			lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL);
1426 		}
1427 	} else {
1428 		writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1429 		       sport->port.membase + UARTCR5);
1430 	}
1431 
1432 	return 0;
1433 }
1434 
lpuart_dma_rx_free(struct uart_port * port)1435 static void lpuart_dma_rx_free(struct uart_port *port)
1436 {
1437 	struct lpuart_port *sport = container_of(port,
1438 					struct lpuart_port, port);
1439 	struct dma_chan *chan = sport->dma_rx_chan;
1440 
1441 	dmaengine_terminate_sync(chan);
1442 	if (!sport->dma_idle_int)
1443 		del_timer_sync(&sport->lpuart_timer);
1444 
1445 	dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1446 	kfree(sport->rx_ring.buf);
1447 	sport->rx_ring.tail = 0;
1448 	sport->rx_ring.head = 0;
1449 	sport->dma_rx_desc = NULL;
1450 	sport->dma_rx_cookie = -EINVAL;
1451 }
1452 
lpuart_config_rs485(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1453 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1454 			struct serial_rs485 *rs485)
1455 {
1456 	struct lpuart_port *sport = container_of(port,
1457 			struct lpuart_port, port);
1458 
1459 	u8 modem = readb(sport->port.membase + UARTMODEM) &
1460 		~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1461 	writeb(modem, sport->port.membase + UARTMODEM);
1462 
1463 	if (rs485->flags & SER_RS485_ENABLED) {
1464 		/* Enable auto RS-485 RTS mode */
1465 		modem |= UARTMODEM_TXRTSE;
1466 
1467 		/*
1468 		 * The hardware defaults to RTS logic HIGH while transfer.
1469 		 * Switch polarity in case RTS shall be logic HIGH
1470 		 * after transfer.
1471 		 * Note: UART is assumed to be active high.
1472 		 */
1473 		if (rs485->flags & SER_RS485_RTS_ON_SEND)
1474 			modem |= UARTMODEM_TXRTSPOL;
1475 		else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1476 			modem &= ~UARTMODEM_TXRTSPOL;
1477 	}
1478 
1479 	writeb(modem, sport->port.membase + UARTMODEM);
1480 	return 0;
1481 }
1482 
lpuart32_config_rs485(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1483 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1484 			struct serial_rs485 *rs485)
1485 {
1486 	struct lpuart_port *sport = container_of(port,
1487 			struct lpuart_port, port);
1488 
1489 	unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1490 				& ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);
1491 	lpuart32_write(&sport->port, modem, UARTMODIR);
1492 
1493 	if (rs485->flags & SER_RS485_ENABLED) {
1494 		/* Enable auto RS-485 RTS mode */
1495 		modem |= UARTMODIR_TXRTSE;
1496 
1497 		/*
1498 		 * The hardware defaults to RTS logic HIGH while transfer.
1499 		 * Switch polarity in case RTS shall be logic HIGH
1500 		 * after transfer.
1501 		 * Note: UART is assumed to be active high.
1502 		 */
1503 		if (rs485->flags & SER_RS485_RTS_ON_SEND)
1504 			modem |= UARTMODIR_TXRTSPOL;
1505 		else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1506 			modem &= ~UARTMODIR_TXRTSPOL;
1507 	}
1508 
1509 	lpuart32_write(&sport->port, modem, UARTMODIR);
1510 	return 0;
1511 }
1512 
lpuart_get_mctrl(struct uart_port * port)1513 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1514 {
1515 	unsigned int mctrl = 0;
1516 	u8 reg;
1517 
1518 	reg = readb(port->membase + UARTCR1);
1519 	if (reg & UARTCR1_LOOPS)
1520 		mctrl |= TIOCM_LOOP;
1521 
1522 	return mctrl;
1523 }
1524 
lpuart32_get_mctrl(struct uart_port * port)1525 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1526 {
1527 	unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1528 	u32 reg;
1529 
1530 	reg = lpuart32_read(port, UARTCTRL);
1531 	if (reg & UARTCTRL_LOOPS)
1532 		mctrl |= TIOCM_LOOP;
1533 
1534 	return mctrl;
1535 }
1536 
lpuart_set_mctrl(struct uart_port * port,unsigned int mctrl)1537 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1538 {
1539 	u8 reg;
1540 
1541 	reg = readb(port->membase + UARTCR1);
1542 
1543 	/* for internal loopback we need LOOPS=1 and RSRC=0 */
1544 	reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1545 	if (mctrl & TIOCM_LOOP)
1546 		reg |= UARTCR1_LOOPS;
1547 
1548 	writeb(reg, port->membase + UARTCR1);
1549 }
1550 
lpuart32_set_mctrl(struct uart_port * port,unsigned int mctrl)1551 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1552 {
1553 	u32 reg;
1554 
1555 	reg = lpuart32_read(port, UARTCTRL);
1556 
1557 	/* for internal loopback we need LOOPS=1 and RSRC=0 */
1558 	reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1559 	if (mctrl & TIOCM_LOOP)
1560 		reg |= UARTCTRL_LOOPS;
1561 
1562 	lpuart32_write(port, reg, UARTCTRL);
1563 }
1564 
lpuart_break_ctl(struct uart_port * port,int break_state)1565 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1566 {
1567 	unsigned char temp;
1568 
1569 	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1570 
1571 	if (break_state != 0)
1572 		temp |= UARTCR2_SBK;
1573 
1574 	writeb(temp, port->membase + UARTCR2);
1575 }
1576 
lpuart32_break_ctl(struct uart_port * port,int break_state)1577 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1578 {
1579 	unsigned long temp;
1580 
1581 	temp = lpuart32_read(port, UARTCTRL);
1582 
1583 	/*
1584 	 * LPUART IP now has two known bugs, one is CTS has higher priority than the
1585 	 * break signal, which causes the break signal sending through UARTCTRL_SBK
1586 	 * may impacted by the CTS input if the HW flow control is enabled. It
1587 	 * exists on all platforms we support in this driver.
1588 	 * Another bug is i.MX8QM LPUART may have an additional break character
1589 	 * being sent after SBK was cleared.
1590 	 * To avoid above two bugs, we use Transmit Data Inversion function to send
1591 	 * the break signal instead of UARTCTRL_SBK.
1592 	 */
1593 	if (break_state != 0) {
1594 		/*
1595 		 * Disable the transmitter to prevent any data from being sent out
1596 		 * during break, then invert the TX line to send break.
1597 		 */
1598 		temp &= ~UARTCTRL_TE;
1599 		lpuart32_write(port, temp, UARTCTRL);
1600 		temp |= UARTCTRL_TXINV;
1601 		lpuart32_write(port, temp, UARTCTRL);
1602 	} else {
1603 		/* Disable the TXINV to turn off break and re-enable transmitter. */
1604 		temp &= ~UARTCTRL_TXINV;
1605 		lpuart32_write(port, temp, UARTCTRL);
1606 		temp |= UARTCTRL_TE;
1607 		lpuart32_write(port, temp, UARTCTRL);
1608 	}
1609 }
1610 
lpuart_setup_watermark(struct lpuart_port * sport)1611 static void lpuart_setup_watermark(struct lpuart_port *sport)
1612 {
1613 	unsigned char val, cr2;
1614 	unsigned char cr2_saved;
1615 
1616 	cr2 = readb(sport->port.membase + UARTCR2);
1617 	cr2_saved = cr2;
1618 	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1619 			UARTCR2_RIE | UARTCR2_RE);
1620 	writeb(cr2, sport->port.membase + UARTCR2);
1621 
1622 	val = readb(sport->port.membase + UARTPFIFO);
1623 	writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1624 			sport->port.membase + UARTPFIFO);
1625 
1626 	/* flush Tx and Rx FIFO */
1627 	writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1628 			sport->port.membase + UARTCFIFO);
1629 
1630 	/* explicitly clear RDRF */
1631 	if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1632 		readb(sport->port.membase + UARTDR);
1633 		writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1634 	}
1635 
1636 	if (uart_console(&sport->port))
1637 		sport->rx_watermark = 1;
1638 	writeb(0, sport->port.membase + UARTTWFIFO);
1639 	writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1640 
1641 	/* Restore cr2 */
1642 	writeb(cr2_saved, sport->port.membase + UARTCR2);
1643 }
1644 
lpuart_setup_watermark_enable(struct lpuart_port * sport)1645 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1646 {
1647 	unsigned char cr2;
1648 
1649 	lpuart_setup_watermark(sport);
1650 
1651 	cr2 = readb(sport->port.membase + UARTCR2);
1652 	cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1653 	writeb(cr2, sport->port.membase + UARTCR2);
1654 }
1655 
lpuart32_setup_watermark(struct lpuart_port * sport)1656 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1657 {
1658 	unsigned long val, ctrl;
1659 	unsigned long ctrl_saved;
1660 
1661 	ctrl = lpuart32_read(&sport->port, UARTCTRL);
1662 	ctrl_saved = ctrl;
1663 	ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1664 			UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE);
1665 	lpuart32_write(&sport->port, ctrl, UARTCTRL);
1666 
1667 	/* enable FIFO mode */
1668 	val = lpuart32_read(&sport->port, UARTFIFO);
1669 	val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1670 	val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1671 	val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3);
1672 	lpuart32_write(&sport->port, val, UARTFIFO);
1673 
1674 	/* set the watermark */
1675 	if (uart_console(&sport->port))
1676 		sport->rx_watermark = 1;
1677 	val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
1678 	      (0x0 << UARTWATER_TXWATER_OFF);
1679 	lpuart32_write(&sport->port, val, UARTWATER);
1680 
1681 	/* set RTS watermark */
1682 	if (!uart_console(&sport->port)) {
1683 		val = lpuart32_read(&sport->port, UARTMODIR);
1684 		val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);
1685 		lpuart32_write(&sport->port, val, UARTMODIR);
1686 	}
1687 
1688 	/* Restore cr2 */
1689 	lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1690 }
1691 
lpuart32_setup_watermark_enable(struct lpuart_port * sport)1692 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1693 {
1694 	u32 temp;
1695 
1696 	lpuart32_setup_watermark(sport);
1697 
1698 	temp = lpuart32_read(&sport->port, UARTCTRL);
1699 	temp |= UARTCTRL_RE | UARTCTRL_TE;
1700 	temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
1701 	lpuart32_write(&sport->port, temp, UARTCTRL);
1702 }
1703 
rx_dma_timer_init(struct lpuart_port * sport)1704 static void rx_dma_timer_init(struct lpuart_port *sport)
1705 {
1706 	if (sport->dma_idle_int)
1707 		return;
1708 
1709 	timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1710 	sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1711 	add_timer(&sport->lpuart_timer);
1712 }
1713 
lpuart_request_dma(struct lpuart_port * sport)1714 static void lpuart_request_dma(struct lpuart_port *sport)
1715 {
1716 	sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1717 	if (IS_ERR(sport->dma_tx_chan)) {
1718 		dev_dbg_once(sport->port.dev,
1719 			     "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1720 			     PTR_ERR(sport->dma_tx_chan));
1721 		sport->dma_tx_chan = NULL;
1722 	}
1723 
1724 	sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1725 	if (IS_ERR(sport->dma_rx_chan)) {
1726 		dev_dbg_once(sport->port.dev,
1727 			     "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1728 			     PTR_ERR(sport->dma_rx_chan));
1729 		sport->dma_rx_chan = NULL;
1730 	}
1731 }
1732 
lpuart_tx_dma_startup(struct lpuart_port * sport)1733 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1734 {
1735 	u32 uartbaud;
1736 	int ret;
1737 
1738 	if (uart_console(&sport->port))
1739 		goto err;
1740 
1741 	if (!sport->dma_tx_chan)
1742 		goto err;
1743 
1744 	ret = lpuart_dma_tx_request(&sport->port);
1745 	if (ret)
1746 		goto err;
1747 
1748 	init_waitqueue_head(&sport->dma_wait);
1749 	sport->lpuart_dma_tx_use = true;
1750 	if (lpuart_is_32(sport)) {
1751 		uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1752 		lpuart32_write(&sport->port,
1753 			       uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1754 	} else {
1755 		writeb(readb(sport->port.membase + UARTCR5) |
1756 		       UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1757 	}
1758 
1759 	return;
1760 
1761 err:
1762 	sport->lpuart_dma_tx_use = false;
1763 }
1764 
lpuart_rx_dma_startup(struct lpuart_port * sport)1765 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1766 {
1767 	int ret;
1768 	unsigned char cr3;
1769 
1770 	if (uart_console(&sport->port))
1771 		goto err;
1772 
1773 	if (!sport->dma_rx_chan)
1774 		goto err;
1775 
1776 	/* set default Rx DMA timeout */
1777 	sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1778 
1779 	ret = lpuart_start_rx_dma(sport);
1780 	if (ret)
1781 		goto err;
1782 
1783 	if (!sport->dma_rx_timeout)
1784 		sport->dma_rx_timeout = 1;
1785 
1786 	sport->lpuart_dma_rx_use = true;
1787 	rx_dma_timer_init(sport);
1788 
1789 	if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1790 		cr3 = readb(sport->port.membase + UARTCR3);
1791 		cr3 |= UARTCR3_FEIE;
1792 		writeb(cr3, sport->port.membase + UARTCR3);
1793 	}
1794 
1795 	return;
1796 
1797 err:
1798 	sport->lpuart_dma_rx_use = false;
1799 }
1800 
lpuart_hw_setup(struct lpuart_port * sport)1801 static void lpuart_hw_setup(struct lpuart_port *sport)
1802 {
1803 	unsigned long flags;
1804 
1805 	spin_lock_irqsave(&sport->port.lock, flags);
1806 
1807 	lpuart_setup_watermark_enable(sport);
1808 
1809 	lpuart_rx_dma_startup(sport);
1810 	lpuart_tx_dma_startup(sport);
1811 
1812 	spin_unlock_irqrestore(&sport->port.lock, flags);
1813 }
1814 
lpuart_startup(struct uart_port * port)1815 static int lpuart_startup(struct uart_port *port)
1816 {
1817 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1818 	unsigned char temp;
1819 
1820 	/* determine FIFO size and enable FIFO mode */
1821 	temp = readb(sport->port.membase + UARTPFIFO);
1822 
1823 	sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1824 					    UARTPFIFO_FIFOSIZE_MASK);
1825 	sport->port.fifosize = sport->txfifo_size;
1826 
1827 	sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1828 					    UARTPFIFO_FIFOSIZE_MASK);
1829 
1830 	lpuart_request_dma(sport);
1831 	lpuart_hw_setup(sport);
1832 
1833 	return 0;
1834 }
1835 
lpuart32_hw_disable(struct lpuart_port * sport)1836 static void lpuart32_hw_disable(struct lpuart_port *sport)
1837 {
1838 	unsigned long temp;
1839 
1840 	temp = lpuart32_read(&sport->port, UARTCTRL);
1841 	temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
1842 		  UARTCTRL_TIE | UARTCTRL_TE);
1843 	lpuart32_write(&sport->port, temp, UARTCTRL);
1844 }
1845 
lpuart32_configure(struct lpuart_port * sport)1846 static void lpuart32_configure(struct lpuart_port *sport)
1847 {
1848 	unsigned long temp;
1849 
1850 	temp = lpuart32_read(&sport->port, UARTCTRL);
1851 	if (!sport->lpuart_dma_rx_use)
1852 		temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
1853 	if (!sport->lpuart_dma_tx_use)
1854 		temp |= UARTCTRL_TIE;
1855 	lpuart32_write(&sport->port, temp, UARTCTRL);
1856 }
1857 
lpuart32_hw_setup(struct lpuart_port * sport)1858 static void lpuart32_hw_setup(struct lpuart_port *sport)
1859 {
1860 	unsigned long flags;
1861 
1862 	spin_lock_irqsave(&sport->port.lock, flags);
1863 
1864 	lpuart32_hw_disable(sport);
1865 
1866 	lpuart_rx_dma_startup(sport);
1867 	lpuart_tx_dma_startup(sport);
1868 
1869 	lpuart32_setup_watermark_enable(sport);
1870 	lpuart32_configure(sport);
1871 
1872 	spin_unlock_irqrestore(&sport->port.lock, flags);
1873 }
1874 
lpuart32_startup(struct uart_port * port)1875 static int lpuart32_startup(struct uart_port *port)
1876 {
1877 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1878 	unsigned long temp;
1879 
1880 	/* determine FIFO size */
1881 	temp = lpuart32_read(&sport->port, UARTFIFO);
1882 
1883 	sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1884 					    UARTFIFO_FIFOSIZE_MASK);
1885 	sport->port.fifosize = sport->txfifo_size;
1886 
1887 	sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1888 					    UARTFIFO_FIFOSIZE_MASK);
1889 
1890 	/*
1891 	 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1892 	 * Although they support the RX/TXSIZE fields, their encoding is
1893 	 * different. Eg the reference manual states 0b101 is 16 words.
1894 	 */
1895 	if (is_layerscape_lpuart(sport)) {
1896 		sport->rxfifo_size = 16;
1897 		sport->txfifo_size = 16;
1898 		sport->port.fifosize = sport->txfifo_size;
1899 	}
1900 
1901 	lpuart_request_dma(sport);
1902 	lpuart32_hw_setup(sport);
1903 
1904 	return 0;
1905 }
1906 
lpuart_dma_shutdown(struct lpuart_port * sport)1907 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1908 {
1909 	if (sport->lpuart_dma_rx_use) {
1910 		lpuart_dma_rx_free(&sport->port);
1911 		sport->lpuart_dma_rx_use = false;
1912 	}
1913 
1914 	if (sport->lpuart_dma_tx_use) {
1915 		if (wait_event_interruptible_timeout(sport->dma_wait,
1916 			!sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1917 			sport->dma_tx_in_progress = false;
1918 			dmaengine_terminate_sync(sport->dma_tx_chan);
1919 		}
1920 		sport->lpuart_dma_tx_use = false;
1921 	}
1922 
1923 	if (sport->dma_tx_chan)
1924 		dma_release_channel(sport->dma_tx_chan);
1925 	if (sport->dma_rx_chan)
1926 		dma_release_channel(sport->dma_rx_chan);
1927 }
1928 
lpuart_shutdown(struct uart_port * port)1929 static void lpuart_shutdown(struct uart_port *port)
1930 {
1931 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1932 	unsigned char temp;
1933 	unsigned long flags;
1934 
1935 	spin_lock_irqsave(&port->lock, flags);
1936 
1937 	/* disable Rx/Tx and interrupts */
1938 	temp = readb(port->membase + UARTCR2);
1939 	temp &= ~(UARTCR2_TE | UARTCR2_RE |
1940 			UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1941 	writeb(temp, port->membase + UARTCR2);
1942 
1943 	spin_unlock_irqrestore(&port->lock, flags);
1944 
1945 	lpuart_dma_shutdown(sport);
1946 }
1947 
lpuart32_shutdown(struct uart_port * port)1948 static void lpuart32_shutdown(struct uart_port *port)
1949 {
1950 	struct lpuart_port *sport =
1951 		container_of(port, struct lpuart_port, port);
1952 	unsigned long temp;
1953 	unsigned long flags;
1954 
1955 	spin_lock_irqsave(&port->lock, flags);
1956 
1957 	/* clear status */
1958 	temp = lpuart32_read(&sport->port, UARTSTAT);
1959 	lpuart32_write(&sport->port, temp, UARTSTAT);
1960 
1961 	/* disable Rx/Tx DMA */
1962 	temp = lpuart32_read(port, UARTBAUD);
1963 	temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1964 	lpuart32_write(port, temp, UARTBAUD);
1965 
1966 	/* disable Rx/Tx and interrupts and break condition */
1967 	temp = lpuart32_read(port, UARTCTRL);
1968 	temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE |
1969 			UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);
1970 	lpuart32_write(port, temp, UARTCTRL);
1971 
1972 	spin_unlock_irqrestore(&port->lock, flags);
1973 
1974 	lpuart_dma_shutdown(sport);
1975 }
1976 
1977 static void
lpuart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1978 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1979 		   const struct ktermios *old)
1980 {
1981 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1982 	unsigned long flags;
1983 	unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1984 	unsigned int  baud;
1985 	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1986 	unsigned int sbr, brfa;
1987 
1988 	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1989 	old_cr2 = readb(sport->port.membase + UARTCR2);
1990 	cr3 = readb(sport->port.membase + UARTCR3);
1991 	cr4 = readb(sport->port.membase + UARTCR4);
1992 	bdh = readb(sport->port.membase + UARTBDH);
1993 	modem = readb(sport->port.membase + UARTMODEM);
1994 	/*
1995 	 * only support CS8 and CS7, and for CS7 must enable PE.
1996 	 * supported mode:
1997 	 *  - (7,e/o,1)
1998 	 *  - (8,n,1)
1999 	 *  - (8,m/s,1)
2000 	 *  - (8,e/o,1)
2001 	 */
2002 	while ((termios->c_cflag & CSIZE) != CS8 &&
2003 		(termios->c_cflag & CSIZE) != CS7) {
2004 		termios->c_cflag &= ~CSIZE;
2005 		termios->c_cflag |= old_csize;
2006 		old_csize = CS8;
2007 	}
2008 
2009 	if ((termios->c_cflag & CSIZE) == CS8 ||
2010 		(termios->c_cflag & CSIZE) == CS7)
2011 		cr1 = old_cr1 & ~UARTCR1_M;
2012 
2013 	if (termios->c_cflag & CMSPAR) {
2014 		if ((termios->c_cflag & CSIZE) != CS8) {
2015 			termios->c_cflag &= ~CSIZE;
2016 			termios->c_cflag |= CS8;
2017 		}
2018 		cr1 |= UARTCR1_M;
2019 	}
2020 
2021 	/*
2022 	 * When auto RS-485 RTS mode is enabled,
2023 	 * hardware flow control need to be disabled.
2024 	 */
2025 	if (sport->port.rs485.flags & SER_RS485_ENABLED)
2026 		termios->c_cflag &= ~CRTSCTS;
2027 
2028 	if (termios->c_cflag & CRTSCTS)
2029 		modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
2030 	else
2031 		modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
2032 
2033 	termios->c_cflag &= ~CSTOPB;
2034 
2035 	/* parity must be enabled when CS7 to match 8-bits format */
2036 	if ((termios->c_cflag & CSIZE) == CS7)
2037 		termios->c_cflag |= PARENB;
2038 
2039 	if (termios->c_cflag & PARENB) {
2040 		if (termios->c_cflag & CMSPAR) {
2041 			cr1 &= ~UARTCR1_PE;
2042 			if (termios->c_cflag & PARODD)
2043 				cr3 |= UARTCR3_T8;
2044 			else
2045 				cr3 &= ~UARTCR3_T8;
2046 		} else {
2047 			cr1 |= UARTCR1_PE;
2048 			if ((termios->c_cflag & CSIZE) == CS8)
2049 				cr1 |= UARTCR1_M;
2050 			if (termios->c_cflag & PARODD)
2051 				cr1 |= UARTCR1_PT;
2052 			else
2053 				cr1 &= ~UARTCR1_PT;
2054 		}
2055 	} else {
2056 		cr1 &= ~UARTCR1_PE;
2057 	}
2058 
2059 	/* ask the core to calculate the divisor */
2060 	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
2061 
2062 	/*
2063 	 * Need to update the Ring buffer length according to the selected
2064 	 * baud rate and restart Rx DMA path.
2065 	 *
2066 	 * Since timer function acqures sport->port.lock, need to stop before
2067 	 * acquring same lock because otherwise del_timer_sync() can deadlock.
2068 	 */
2069 	if (old && sport->lpuart_dma_rx_use)
2070 		lpuart_dma_rx_free(&sport->port);
2071 
2072 	spin_lock_irqsave(&sport->port.lock, flags);
2073 
2074 	sport->port.read_status_mask = 0;
2075 	if (termios->c_iflag & INPCK)
2076 		sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
2077 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2078 		sport->port.read_status_mask |= UARTSR1_FE;
2079 
2080 	/* characters to ignore */
2081 	sport->port.ignore_status_mask = 0;
2082 	if (termios->c_iflag & IGNPAR)
2083 		sport->port.ignore_status_mask |= UARTSR1_PE;
2084 	if (termios->c_iflag & IGNBRK) {
2085 		sport->port.ignore_status_mask |= UARTSR1_FE;
2086 		/*
2087 		 * if we're ignoring parity and break indicators,
2088 		 * ignore overruns too (for real raw support).
2089 		 */
2090 		if (termios->c_iflag & IGNPAR)
2091 			sport->port.ignore_status_mask |= UARTSR1_OR;
2092 	}
2093 
2094 	/* update the per-port timeout */
2095 	uart_update_timeout(port, termios->c_cflag, baud);
2096 
2097 	/* wait transmit engin complete */
2098 	lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2099 
2100 	/* disable transmit and receive */
2101 	writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
2102 			sport->port.membase + UARTCR2);
2103 
2104 	sbr = sport->port.uartclk / (16 * baud);
2105 	brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
2106 	bdh &= ~UARTBDH_SBR_MASK;
2107 	bdh |= (sbr >> 8) & 0x1F;
2108 	cr4 &= ~UARTCR4_BRFA_MASK;
2109 	brfa &= UARTCR4_BRFA_MASK;
2110 	writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2111 	writeb(bdh, sport->port.membase + UARTBDH);
2112 	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2113 	writeb(cr3, sport->port.membase + UARTCR3);
2114 	writeb(cr1, sport->port.membase + UARTCR1);
2115 	writeb(modem, sport->port.membase + UARTMODEM);
2116 
2117 	/* restore control register */
2118 	writeb(old_cr2, sport->port.membase + UARTCR2);
2119 
2120 	if (old && sport->lpuart_dma_rx_use) {
2121 		if (!lpuart_start_rx_dma(sport))
2122 			rx_dma_timer_init(sport);
2123 		else
2124 			sport->lpuart_dma_rx_use = false;
2125 	}
2126 
2127 	spin_unlock_irqrestore(&sport->port.lock, flags);
2128 }
2129 
__lpuart32_serial_setbrg(struct uart_port * port,unsigned int baudrate,bool use_rx_dma,bool use_tx_dma)2130 static void __lpuart32_serial_setbrg(struct uart_port *port,
2131 				     unsigned int baudrate, bool use_rx_dma,
2132 				     bool use_tx_dma)
2133 {
2134 	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
2135 	u32 clk = port->uartclk;
2136 
2137 	/*
2138 	 * The idea is to use the best OSR (over-sampling rate) possible.
2139 	 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
2140 	 * Loop to find the best OSR value possible, one that generates minimum
2141 	 * baud_diff iterate through the rest of the supported values of OSR.
2142 	 *
2143 	 * Calculation Formula:
2144 	 *  Baud Rate = baud clock / ((OSR+1) × SBR)
2145 	 */
2146 	baud_diff = baudrate;
2147 	osr = 0;
2148 	sbr = 0;
2149 
2150 	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
2151 		/* calculate the temporary sbr value  */
2152 		tmp_sbr = (clk / (baudrate * tmp_osr));
2153 		if (tmp_sbr == 0)
2154 			tmp_sbr = 1;
2155 
2156 		/*
2157 		 * calculate the baud rate difference based on the temporary
2158 		 * osr and sbr values
2159 		 */
2160 		tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
2161 
2162 		/* select best values between sbr and sbr+1 */
2163 		tmp = clk / (tmp_osr * (tmp_sbr + 1));
2164 		if (tmp_diff > (baudrate - tmp)) {
2165 			tmp_diff = baudrate - tmp;
2166 			tmp_sbr++;
2167 		}
2168 
2169 		if (tmp_sbr > UARTBAUD_SBR_MASK)
2170 			continue;
2171 
2172 		if (tmp_diff <= baud_diff) {
2173 			baud_diff = tmp_diff;
2174 			osr = tmp_osr;
2175 			sbr = tmp_sbr;
2176 
2177 			if (!baud_diff)
2178 				break;
2179 		}
2180 	}
2181 
2182 	/* handle buadrate outside acceptable rate */
2183 	if (baud_diff > ((baudrate / 100) * 3))
2184 		dev_warn(port->dev,
2185 			 "unacceptable baud rate difference of more than 3%%\n");
2186 
2187 	tmp = lpuart32_read(port, UARTBAUD);
2188 
2189 	if ((osr > 3) && (osr < 8))
2190 		tmp |= UARTBAUD_BOTHEDGE;
2191 
2192 	tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2193 	tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2194 
2195 	tmp &= ~UARTBAUD_SBR_MASK;
2196 	tmp |= sbr & UARTBAUD_SBR_MASK;
2197 
2198 	if (!use_rx_dma)
2199 		tmp &= ~UARTBAUD_RDMAE;
2200 	if (!use_tx_dma)
2201 		tmp &= ~UARTBAUD_TDMAE;
2202 
2203 	lpuart32_write(port, tmp, UARTBAUD);
2204 }
2205 
lpuart32_serial_setbrg(struct lpuart_port * sport,unsigned int baudrate)2206 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2207 				   unsigned int baudrate)
2208 {
2209 	__lpuart32_serial_setbrg(&sport->port, baudrate,
2210 				 sport->lpuart_dma_rx_use,
2211 				 sport->lpuart_dma_tx_use);
2212 }
2213 
2214 
2215 static void
lpuart32_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2216 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2217 		     const struct ktermios *old)
2218 {
2219 	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2220 	unsigned long flags;
2221 	unsigned long ctrl, old_ctrl, bd, modem;
2222 	unsigned int  baud;
2223 	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2224 
2225 	ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2226 	bd = lpuart32_read(&sport->port, UARTBAUD);
2227 	modem = lpuart32_read(&sport->port, UARTMODIR);
2228 	sport->is_cs7 = false;
2229 	/*
2230 	 * only support CS8 and CS7, and for CS7 must enable PE.
2231 	 * supported mode:
2232 	 *  - (7,e/o,1)
2233 	 *  - (8,n,1)
2234 	 *  - (8,m/s,1)
2235 	 *  - (8,e/o,1)
2236 	 */
2237 	while ((termios->c_cflag & CSIZE) != CS8 &&
2238 		(termios->c_cflag & CSIZE) != CS7) {
2239 		termios->c_cflag &= ~CSIZE;
2240 		termios->c_cflag |= old_csize;
2241 		old_csize = CS8;
2242 	}
2243 
2244 	if ((termios->c_cflag & CSIZE) == CS8 ||
2245 		(termios->c_cflag & CSIZE) == CS7)
2246 		ctrl = old_ctrl & ~UARTCTRL_M;
2247 
2248 	if (termios->c_cflag & CMSPAR) {
2249 		if ((termios->c_cflag & CSIZE) != CS8) {
2250 			termios->c_cflag &= ~CSIZE;
2251 			termios->c_cflag |= CS8;
2252 		}
2253 		ctrl |= UARTCTRL_M;
2254 	}
2255 
2256 	/*
2257 	 * When auto RS-485 RTS mode is enabled,
2258 	 * hardware flow control need to be disabled.
2259 	 */
2260 	if (sport->port.rs485.flags & SER_RS485_ENABLED)
2261 		termios->c_cflag &= ~CRTSCTS;
2262 
2263 	if (termios->c_cflag & CRTSCTS)
2264 		modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2265 	else
2266 		modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2267 
2268 	if (termios->c_cflag & CSTOPB)
2269 		bd |= UARTBAUD_SBNS;
2270 	else
2271 		bd &= ~UARTBAUD_SBNS;
2272 
2273 	/* parity must be enabled when CS7 to match 8-bits format */
2274 	if ((termios->c_cflag & CSIZE) == CS7)
2275 		termios->c_cflag |= PARENB;
2276 
2277 	if ((termios->c_cflag & PARENB)) {
2278 		if (termios->c_cflag & CMSPAR) {
2279 			ctrl &= ~UARTCTRL_PE;
2280 			ctrl |= UARTCTRL_M;
2281 		} else {
2282 			ctrl |= UARTCTRL_PE;
2283 			if ((termios->c_cflag & CSIZE) == CS8)
2284 				ctrl |= UARTCTRL_M;
2285 			if (termios->c_cflag & PARODD)
2286 				ctrl |= UARTCTRL_PT;
2287 			else
2288 				ctrl &= ~UARTCTRL_PT;
2289 		}
2290 	} else {
2291 		ctrl &= ~UARTCTRL_PE;
2292 	}
2293 
2294 	/* ask the core to calculate the divisor */
2295 	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2296 
2297 	/*
2298 	 * Need to update the Ring buffer length according to the selected
2299 	 * baud rate and restart Rx DMA path.
2300 	 *
2301 	 * Since timer function acqures sport->port.lock, need to stop before
2302 	 * acquring same lock because otherwise del_timer_sync() can deadlock.
2303 	 */
2304 	if (old && sport->lpuart_dma_rx_use)
2305 		lpuart_dma_rx_free(&sport->port);
2306 
2307 	spin_lock_irqsave(&sport->port.lock, flags);
2308 
2309 	sport->port.read_status_mask = 0;
2310 	if (termios->c_iflag & INPCK)
2311 		sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2312 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2313 		sport->port.read_status_mask |= UARTSTAT_FE;
2314 
2315 	/* characters to ignore */
2316 	sport->port.ignore_status_mask = 0;
2317 	if (termios->c_iflag & IGNPAR)
2318 		sport->port.ignore_status_mask |= UARTSTAT_PE;
2319 	if (termios->c_iflag & IGNBRK) {
2320 		sport->port.ignore_status_mask |= UARTSTAT_FE;
2321 		/*
2322 		 * if we're ignoring parity and break indicators,
2323 		 * ignore overruns too (for real raw support).
2324 		 */
2325 		if (termios->c_iflag & IGNPAR)
2326 			sport->port.ignore_status_mask |= UARTSTAT_OR;
2327 	}
2328 
2329 	/* update the per-port timeout */
2330 	uart_update_timeout(port, termios->c_cflag, baud);
2331 
2332 	/*
2333 	 * LPUART Transmission Complete Flag may never be set while queuing a break
2334 	 * character, so skip waiting for transmission complete when UARTCTRL_SBK is
2335 	 * asserted.
2336 	 */
2337 	if (!(old_ctrl & UARTCTRL_SBK)) {
2338 		lpuart32_write(&sport->port, 0, UARTMODIR);
2339 		lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2340 	}
2341 
2342 	/* disable transmit and receive */
2343 	lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2344 		       UARTCTRL);
2345 
2346 	lpuart32_write(&sport->port, bd, UARTBAUD);
2347 	lpuart32_serial_setbrg(sport, baud);
2348 	/* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */
2349 	lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
2350 	/* restore control register */
2351 	lpuart32_write(&sport->port, ctrl, UARTCTRL);
2352 	/* re-enable the CTS if needed */
2353 	lpuart32_write(&sport->port, modem, UARTMODIR);
2354 
2355 	if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
2356 		sport->is_cs7 = true;
2357 
2358 	if (old && sport->lpuart_dma_rx_use) {
2359 		if (!lpuart_start_rx_dma(sport))
2360 			rx_dma_timer_init(sport);
2361 		else
2362 			sport->lpuart_dma_rx_use = false;
2363 	}
2364 
2365 	spin_unlock_irqrestore(&sport->port.lock, flags);
2366 }
2367 
lpuart_type(struct uart_port * port)2368 static const char *lpuart_type(struct uart_port *port)
2369 {
2370 	return "FSL_LPUART";
2371 }
2372 
lpuart_release_port(struct uart_port * port)2373 static void lpuart_release_port(struct uart_port *port)
2374 {
2375 	/* nothing to do */
2376 }
2377 
lpuart_request_port(struct uart_port * port)2378 static int lpuart_request_port(struct uart_port *port)
2379 {
2380 	return  0;
2381 }
2382 
2383 /* configure/autoconfigure the port */
lpuart_config_port(struct uart_port * port,int flags)2384 static void lpuart_config_port(struct uart_port *port, int flags)
2385 {
2386 	if (flags & UART_CONFIG_TYPE)
2387 		port->type = PORT_LPUART;
2388 }
2389 
lpuart_verify_port(struct uart_port * port,struct serial_struct * ser)2390 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2391 {
2392 	int ret = 0;
2393 
2394 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2395 		ret = -EINVAL;
2396 	if (port->irq != ser->irq)
2397 		ret = -EINVAL;
2398 	if (ser->io_type != UPIO_MEM)
2399 		ret = -EINVAL;
2400 	if (port->uartclk / 16 != ser->baud_base)
2401 		ret = -EINVAL;
2402 	if (port->iobase != ser->port)
2403 		ret = -EINVAL;
2404 	if (ser->hub6 != 0)
2405 		ret = -EINVAL;
2406 	return ret;
2407 }
2408 
2409 static const struct uart_ops lpuart_pops = {
2410 	.tx_empty	= lpuart_tx_empty,
2411 	.set_mctrl	= lpuart_set_mctrl,
2412 	.get_mctrl	= lpuart_get_mctrl,
2413 	.stop_tx	= lpuart_stop_tx,
2414 	.start_tx	= lpuart_start_tx,
2415 	.stop_rx	= lpuart_stop_rx,
2416 	.break_ctl	= lpuart_break_ctl,
2417 	.startup	= lpuart_startup,
2418 	.shutdown	= lpuart_shutdown,
2419 	.set_termios	= lpuart_set_termios,
2420 	.pm		= lpuart_uart_pm,
2421 	.type		= lpuart_type,
2422 	.request_port	= lpuart_request_port,
2423 	.release_port	= lpuart_release_port,
2424 	.config_port	= lpuart_config_port,
2425 	.verify_port	= lpuart_verify_port,
2426 	.flush_buffer	= lpuart_flush_buffer,
2427 #if defined(CONFIG_CONSOLE_POLL)
2428 	.poll_init	= lpuart_poll_init,
2429 	.poll_get_char	= lpuart_poll_get_char,
2430 	.poll_put_char	= lpuart_poll_put_char,
2431 #endif
2432 };
2433 
2434 static const struct uart_ops lpuart32_pops = {
2435 	.tx_empty	= lpuart32_tx_empty,
2436 	.set_mctrl	= lpuart32_set_mctrl,
2437 	.get_mctrl	= lpuart32_get_mctrl,
2438 	.stop_tx	= lpuart32_stop_tx,
2439 	.start_tx	= lpuart32_start_tx,
2440 	.stop_rx	= lpuart32_stop_rx,
2441 	.break_ctl	= lpuart32_break_ctl,
2442 	.startup	= lpuart32_startup,
2443 	.shutdown	= lpuart32_shutdown,
2444 	.set_termios	= lpuart32_set_termios,
2445 	.pm		= lpuart_uart_pm,
2446 	.type		= lpuart_type,
2447 	.request_port	= lpuart_request_port,
2448 	.release_port	= lpuart_release_port,
2449 	.config_port	= lpuart_config_port,
2450 	.verify_port	= lpuart_verify_port,
2451 	.flush_buffer	= lpuart_flush_buffer,
2452 #if defined(CONFIG_CONSOLE_POLL)
2453 	.poll_init	= lpuart32_poll_init,
2454 	.poll_get_char	= lpuart32_poll_get_char,
2455 	.poll_put_char	= lpuart32_poll_put_char,
2456 #endif
2457 };
2458 
2459 static struct lpuart_port *lpuart_ports[UART_NR];
2460 
2461 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
lpuart_console_putchar(struct uart_port * port,unsigned char ch)2462 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2463 {
2464 	lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2465 	writeb(ch, port->membase + UARTDR);
2466 }
2467 
lpuart32_console_putchar(struct uart_port * port,unsigned char ch)2468 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2469 {
2470 	lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2471 	lpuart32_write(port, ch, UARTDATA);
2472 }
2473 
2474 static void
lpuart_console_write(struct console * co,const char * s,unsigned int count)2475 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2476 {
2477 	struct lpuart_port *sport = lpuart_ports[co->index];
2478 	unsigned char  old_cr2, cr2;
2479 	unsigned long flags;
2480 	int locked = 1;
2481 
2482 	if (oops_in_progress)
2483 		locked = spin_trylock_irqsave(&sport->port.lock, flags);
2484 	else
2485 		spin_lock_irqsave(&sport->port.lock, flags);
2486 
2487 	/* first save CR2 and then disable interrupts */
2488 	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2489 	cr2 |= UARTCR2_TE | UARTCR2_RE;
2490 	cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2491 	writeb(cr2, sport->port.membase + UARTCR2);
2492 
2493 	uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2494 
2495 	/* wait for transmitter finish complete and restore CR2 */
2496 	lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2497 
2498 	writeb(old_cr2, sport->port.membase + UARTCR2);
2499 
2500 	if (locked)
2501 		spin_unlock_irqrestore(&sport->port.lock, flags);
2502 }
2503 
2504 static void
lpuart32_console_write(struct console * co,const char * s,unsigned int count)2505 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2506 {
2507 	struct lpuart_port *sport = lpuart_ports[co->index];
2508 	unsigned long  old_cr, cr;
2509 	unsigned long flags;
2510 	int locked = 1;
2511 
2512 	if (oops_in_progress)
2513 		locked = spin_trylock_irqsave(&sport->port.lock, flags);
2514 	else
2515 		spin_lock_irqsave(&sport->port.lock, flags);
2516 
2517 	/* first save CR2 and then disable interrupts */
2518 	cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2519 	cr |= UARTCTRL_TE | UARTCTRL_RE;
2520 	cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2521 	lpuart32_write(&sport->port, cr, UARTCTRL);
2522 
2523 	uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2524 
2525 	/* wait for transmitter finish complete and restore CR2 */
2526 	lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2527 
2528 	lpuart32_write(&sport->port, old_cr, UARTCTRL);
2529 
2530 	if (locked)
2531 		spin_unlock_irqrestore(&sport->port.lock, flags);
2532 }
2533 
2534 /*
2535  * if the port was already initialised (eg, by a boot loader),
2536  * try to determine the current setup.
2537  */
2538 static void __init
lpuart_console_get_options(struct lpuart_port * sport,int * baud,int * parity,int * bits)2539 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2540 			   int *parity, int *bits)
2541 {
2542 	unsigned char cr, bdh, bdl, brfa;
2543 	unsigned int sbr, uartclk, baud_raw;
2544 
2545 	cr = readb(sport->port.membase + UARTCR2);
2546 	cr &= UARTCR2_TE | UARTCR2_RE;
2547 	if (!cr)
2548 		return;
2549 
2550 	/* ok, the port was enabled */
2551 
2552 	cr = readb(sport->port.membase + UARTCR1);
2553 
2554 	*parity = 'n';
2555 	if (cr & UARTCR1_PE) {
2556 		if (cr & UARTCR1_PT)
2557 			*parity = 'o';
2558 		else
2559 			*parity = 'e';
2560 	}
2561 
2562 	if (cr & UARTCR1_M)
2563 		*bits = 9;
2564 	else
2565 		*bits = 8;
2566 
2567 	bdh = readb(sport->port.membase + UARTBDH);
2568 	bdh &= UARTBDH_SBR_MASK;
2569 	bdl = readb(sport->port.membase + UARTBDL);
2570 	sbr = bdh;
2571 	sbr <<= 8;
2572 	sbr |= bdl;
2573 	brfa = readb(sport->port.membase + UARTCR4);
2574 	brfa &= UARTCR4_BRFA_MASK;
2575 
2576 	uartclk = lpuart_get_baud_clk_rate(sport);
2577 	/*
2578 	 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2579 	 */
2580 	baud_raw = uartclk / (16 * (sbr + brfa / 32));
2581 
2582 	if (*baud != baud_raw)
2583 		dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2584 				"from %d to %d\n", baud_raw, *baud);
2585 }
2586 
2587 static void __init
lpuart32_console_get_options(struct lpuart_port * sport,int * baud,int * parity,int * bits)2588 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2589 			   int *parity, int *bits)
2590 {
2591 	unsigned long cr, bd;
2592 	unsigned int sbr, uartclk, baud_raw;
2593 
2594 	cr = lpuart32_read(&sport->port, UARTCTRL);
2595 	cr &= UARTCTRL_TE | UARTCTRL_RE;
2596 	if (!cr)
2597 		return;
2598 
2599 	/* ok, the port was enabled */
2600 
2601 	cr = lpuart32_read(&sport->port, UARTCTRL);
2602 
2603 	*parity = 'n';
2604 	if (cr & UARTCTRL_PE) {
2605 		if (cr & UARTCTRL_PT)
2606 			*parity = 'o';
2607 		else
2608 			*parity = 'e';
2609 	}
2610 
2611 	if (cr & UARTCTRL_M)
2612 		*bits = 9;
2613 	else
2614 		*bits = 8;
2615 
2616 	bd = lpuart32_read(&sport->port, UARTBAUD);
2617 	bd &= UARTBAUD_SBR_MASK;
2618 	if (!bd)
2619 		return;
2620 
2621 	sbr = bd;
2622 	uartclk = lpuart_get_baud_clk_rate(sport);
2623 	/*
2624 	 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2625 	 */
2626 	baud_raw = uartclk / (16 * sbr);
2627 
2628 	if (*baud != baud_raw)
2629 		dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2630 				"from %d to %d\n", baud_raw, *baud);
2631 }
2632 
lpuart_console_setup(struct console * co,char * options)2633 static int __init lpuart_console_setup(struct console *co, char *options)
2634 {
2635 	struct lpuart_port *sport;
2636 	int baud = 115200;
2637 	int bits = 8;
2638 	int parity = 'n';
2639 	int flow = 'n';
2640 
2641 	/*
2642 	 * check whether an invalid uart number has been specified, and
2643 	 * if so, search for the first available port that does have
2644 	 * console support.
2645 	 */
2646 	if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2647 		co->index = 0;
2648 
2649 	sport = lpuart_ports[co->index];
2650 	if (sport == NULL)
2651 		return -ENODEV;
2652 
2653 	if (options)
2654 		uart_parse_options(options, &baud, &parity, &bits, &flow);
2655 	else
2656 		if (lpuart_is_32(sport))
2657 			lpuart32_console_get_options(sport, &baud, &parity, &bits);
2658 		else
2659 			lpuart_console_get_options(sport, &baud, &parity, &bits);
2660 
2661 	if (lpuart_is_32(sport))
2662 		lpuart32_setup_watermark(sport);
2663 	else
2664 		lpuart_setup_watermark(sport);
2665 
2666 	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2667 }
2668 
2669 static struct uart_driver lpuart_reg;
2670 static struct console lpuart_console = {
2671 	.name		= DEV_NAME,
2672 	.write		= lpuart_console_write,
2673 	.device		= uart_console_device,
2674 	.setup		= lpuart_console_setup,
2675 	.flags		= CON_PRINTBUFFER,
2676 	.index		= -1,
2677 	.data		= &lpuart_reg,
2678 };
2679 
2680 static struct console lpuart32_console = {
2681 	.name		= DEV_NAME,
2682 	.write		= lpuart32_console_write,
2683 	.device		= uart_console_device,
2684 	.setup		= lpuart_console_setup,
2685 	.flags		= CON_PRINTBUFFER,
2686 	.index		= -1,
2687 	.data		= &lpuart_reg,
2688 };
2689 
lpuart_early_write(struct console * con,const char * s,unsigned n)2690 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2691 {
2692 	struct earlycon_device *dev = con->data;
2693 
2694 	uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2695 }
2696 
lpuart32_early_write(struct console * con,const char * s,unsigned n)2697 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2698 {
2699 	struct earlycon_device *dev = con->data;
2700 
2701 	uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2702 }
2703 
lpuart_early_console_setup(struct earlycon_device * device,const char * opt)2704 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2705 					  const char *opt)
2706 {
2707 	if (!device->port.membase)
2708 		return -ENODEV;
2709 
2710 	device->con->write = lpuart_early_write;
2711 	return 0;
2712 }
2713 
lpuart32_early_console_setup(struct earlycon_device * device,const char * opt)2714 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2715 					  const char *opt)
2716 {
2717 	if (!device->port.membase)
2718 		return -ENODEV;
2719 
2720 	if (device->port.iotype != UPIO_MEM32)
2721 		device->port.iotype = UPIO_MEM32BE;
2722 
2723 	device->con->write = lpuart32_early_write;
2724 	return 0;
2725 }
2726 
ls1028a_early_console_setup(struct earlycon_device * device,const char * opt)2727 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2728 					      const char *opt)
2729 {
2730 	u32 cr;
2731 
2732 	if (!device->port.membase)
2733 		return -ENODEV;
2734 
2735 	device->port.iotype = UPIO_MEM32;
2736 	device->con->write = lpuart32_early_write;
2737 
2738 	/* set the baudrate */
2739 	if (device->port.uartclk && device->baud)
2740 		__lpuart32_serial_setbrg(&device->port, device->baud,
2741 					 false, false);
2742 
2743 	/* enable transmitter */
2744 	cr = lpuart32_read(&device->port, UARTCTRL);
2745 	cr |= UARTCTRL_TE;
2746 	lpuart32_write(&device->port, cr, UARTCTRL);
2747 
2748 	return 0;
2749 }
2750 
lpuart32_imx_early_console_setup(struct earlycon_device * device,const char * opt)2751 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2752 						   const char *opt)
2753 {
2754 	if (!device->port.membase)
2755 		return -ENODEV;
2756 
2757 	device->port.iotype = UPIO_MEM32;
2758 	device->port.membase += IMX_REG_OFF;
2759 	device->con->write = lpuart32_early_write;
2760 
2761 	return 0;
2762 }
2763 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2764 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2765 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2766 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2767 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2768 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2769 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2770 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2771 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2772 
2773 #define LPUART_CONSOLE	(&lpuart_console)
2774 #define LPUART32_CONSOLE	(&lpuart32_console)
2775 #else
2776 #define LPUART_CONSOLE	NULL
2777 #define LPUART32_CONSOLE	NULL
2778 #endif
2779 
2780 static struct uart_driver lpuart_reg = {
2781 	.owner		= THIS_MODULE,
2782 	.driver_name	= DRIVER_NAME,
2783 	.dev_name	= DEV_NAME,
2784 	.nr		= ARRAY_SIZE(lpuart_ports),
2785 	.cons		= LPUART_CONSOLE,
2786 };
2787 
2788 static const struct serial_rs485 lpuart_rs485_supported = {
2789 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
2790 	/* delay_rts_* and RX_DURING_TX are not supported */
2791 };
2792 
lpuart_global_reset(struct lpuart_port * sport)2793 static int lpuart_global_reset(struct lpuart_port *sport)
2794 {
2795 	struct uart_port *port = &sport->port;
2796 	void __iomem *global_addr;
2797 	unsigned long ctrl, bd;
2798 	unsigned int val = 0;
2799 	int ret;
2800 
2801 	ret = clk_prepare_enable(sport->ipg_clk);
2802 	if (ret) {
2803 		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2804 		return ret;
2805 	}
2806 
2807 	if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
2808 		/*
2809 		 * If the transmitter is used by earlycon, wait for transmit engine to
2810 		 * complete and then reset.
2811 		 */
2812 		ctrl = lpuart32_read(port, UARTCTRL);
2813 		if (ctrl & UARTCTRL_TE) {
2814 			bd = lpuart32_read(&sport->port, UARTBAUD);
2815 			if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
2816 					      port)) {
2817 				dev_warn(sport->port.dev,
2818 					 "timeout waiting for transmit engine to complete\n");
2819 				clk_disable_unprepare(sport->ipg_clk);
2820 				return 0;
2821 			}
2822 		}
2823 
2824 		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2825 		writel(UART_GLOBAL_RST, global_addr);
2826 		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2827 		writel(0, global_addr);
2828 		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2829 
2830 		/* Recover the transmitter for earlycon. */
2831 		if (ctrl & UARTCTRL_TE) {
2832 			lpuart32_write(port, bd, UARTBAUD);
2833 			lpuart32_write(port, ctrl, UARTCTRL);
2834 		}
2835 	}
2836 
2837 	clk_disable_unprepare(sport->ipg_clk);
2838 	return 0;
2839 }
2840 
lpuart_probe(struct platform_device * pdev)2841 static int lpuart_probe(struct platform_device *pdev)
2842 {
2843 	const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2844 	struct device_node *np = pdev->dev.of_node;
2845 	struct lpuart_port *sport;
2846 	struct resource *res;
2847 	irq_handler_t handler;
2848 	int ret;
2849 
2850 	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2851 	if (!sport)
2852 		return -ENOMEM;
2853 
2854 	sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2855 	if (IS_ERR(sport->port.membase))
2856 		return PTR_ERR(sport->port.membase);
2857 
2858 	sport->port.membase += sdata->reg_off;
2859 	sport->port.mapbase = res->start + sdata->reg_off;
2860 	sport->port.dev = &pdev->dev;
2861 	sport->port.type = PORT_LPUART;
2862 	sport->devtype = sdata->devtype;
2863 	sport->rx_watermark = sdata->rx_watermark;
2864 	sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) ||
2865 			      is_imx8qxp_lpuart(sport);
2866 	ret = platform_get_irq(pdev, 0);
2867 	if (ret < 0)
2868 		return ret;
2869 	sport->port.irq = ret;
2870 	sport->port.iotype = sdata->iotype;
2871 	if (lpuart_is_32(sport))
2872 		sport->port.ops = &lpuart32_pops;
2873 	else
2874 		sport->port.ops = &lpuart_pops;
2875 	sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2876 	sport->port.flags = UPF_BOOT_AUTOCONF;
2877 
2878 	if (lpuart_is_32(sport))
2879 		sport->port.rs485_config = lpuart32_config_rs485;
2880 	else
2881 		sport->port.rs485_config = lpuart_config_rs485;
2882 	sport->port.rs485_supported = lpuart_rs485_supported;
2883 
2884 	sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2885 	if (IS_ERR(sport->ipg_clk)) {
2886 		ret = PTR_ERR(sport->ipg_clk);
2887 		dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2888 		return ret;
2889 	}
2890 
2891 	sport->baud_clk = NULL;
2892 	if (is_imx8qxp_lpuart(sport)) {
2893 		sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2894 		if (IS_ERR(sport->baud_clk)) {
2895 			ret = PTR_ERR(sport->baud_clk);
2896 			dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2897 			return ret;
2898 		}
2899 	}
2900 
2901 	ret = of_alias_get_id(np, "serial");
2902 	if (ret < 0) {
2903 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2904 		return ret;
2905 	}
2906 	if (ret >= ARRAY_SIZE(lpuart_ports)) {
2907 		dev_err(&pdev->dev, "serial%d out of range\n", ret);
2908 		return -EINVAL;
2909 	}
2910 	sport->port.line = ret;
2911 
2912 	ret = lpuart_enable_clks(sport);
2913 	if (ret)
2914 		return ret;
2915 	sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2916 
2917 	lpuart_ports[sport->port.line] = sport;
2918 
2919 	platform_set_drvdata(pdev, &sport->port);
2920 
2921 	if (lpuart_is_32(sport)) {
2922 		lpuart_reg.cons = LPUART32_CONSOLE;
2923 		handler = lpuart32_int;
2924 	} else {
2925 		lpuart_reg.cons = LPUART_CONSOLE;
2926 		handler = lpuart_int;
2927 	}
2928 
2929 	pm_runtime_use_autosuspend(&pdev->dev);
2930 	pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
2931 	pm_runtime_set_active(&pdev->dev);
2932 	pm_runtime_enable(&pdev->dev);
2933 	pm_runtime_mark_last_busy(&pdev->dev);
2934 
2935 	ret = lpuart_global_reset(sport);
2936 	if (ret)
2937 		goto failed_reset;
2938 
2939 	ret = uart_get_rs485_mode(&sport->port);
2940 	if (ret)
2941 		goto failed_get_rs485;
2942 
2943 	ret = uart_add_one_port(&lpuart_reg, &sport->port);
2944 	if (ret)
2945 		goto failed_attach_port;
2946 
2947 	ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2948 				DRIVER_NAME, sport);
2949 	if (ret)
2950 		goto failed_irq_request;
2951 
2952 	return 0;
2953 
2954 failed_irq_request:
2955 	uart_remove_one_port(&lpuart_reg, &sport->port);
2956 failed_attach_port:
2957 failed_get_rs485:
2958 failed_reset:
2959 	pm_runtime_disable(&pdev->dev);
2960 	pm_runtime_set_suspended(&pdev->dev);
2961 	pm_runtime_dont_use_autosuspend(&pdev->dev);
2962 	lpuart_disable_clks(sport);
2963 	return ret;
2964 }
2965 
lpuart_remove(struct platform_device * pdev)2966 static int lpuart_remove(struct platform_device *pdev)
2967 {
2968 	struct lpuart_port *sport = platform_get_drvdata(pdev);
2969 
2970 	uart_remove_one_port(&lpuart_reg, &sport->port);
2971 
2972 	lpuart_disable_clks(sport);
2973 
2974 	if (sport->dma_tx_chan)
2975 		dma_release_channel(sport->dma_tx_chan);
2976 
2977 	if (sport->dma_rx_chan)
2978 		dma_release_channel(sport->dma_rx_chan);
2979 
2980 	pm_runtime_disable(&pdev->dev);
2981 	pm_runtime_set_suspended(&pdev->dev);
2982 	pm_runtime_dont_use_autosuspend(&pdev->dev);
2983 	return 0;
2984 }
2985 
lpuart_runtime_suspend(struct device * dev)2986 static int lpuart_runtime_suspend(struct device *dev)
2987 {
2988 	struct platform_device *pdev = to_platform_device(dev);
2989 	struct lpuart_port *sport = platform_get_drvdata(pdev);
2990 
2991 	lpuart_disable_clks(sport);
2992 
2993 	return 0;
2994 };
2995 
lpuart_runtime_resume(struct device * dev)2996 static int lpuart_runtime_resume(struct device *dev)
2997 {
2998 	struct platform_device *pdev = to_platform_device(dev);
2999 	struct lpuart_port *sport = platform_get_drvdata(pdev);
3000 
3001 	return lpuart_enable_clks(sport);
3002 };
3003 
serial_lpuart_enable_wakeup(struct lpuart_port * sport,bool on)3004 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
3005 {
3006 	unsigned int val, baud;
3007 
3008 	if (lpuart_is_32(sport)) {
3009 		val = lpuart32_read(&sport->port, UARTCTRL);
3010 		baud = lpuart32_read(&sport->port, UARTBAUD);
3011 		if (on) {
3012 			/* set rx_watermark to 0 in wakeup source mode */
3013 			lpuart32_write(&sport->port, 0, UARTWATER);
3014 			val |= UARTCTRL_RIE;
3015 			/* clear RXEDGIF flag before enable RXEDGIE interrupt */
3016 			lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
3017 			baud |= UARTBAUD_RXEDGIE;
3018 		} else {
3019 			val &= ~UARTCTRL_RIE;
3020 			baud &= ~UARTBAUD_RXEDGIE;
3021 		}
3022 		lpuart32_write(&sport->port, val, UARTCTRL);
3023 		lpuart32_write(&sport->port, baud, UARTBAUD);
3024 	} else {
3025 		val = readb(sport->port.membase + UARTCR2);
3026 		if (on)
3027 			val |= UARTCR2_RIE;
3028 		else
3029 			val &= ~UARTCR2_RIE;
3030 		writeb(val, sport->port.membase + UARTCR2);
3031 	}
3032 }
3033 
lpuart_uport_is_active(struct lpuart_port * sport)3034 static bool lpuart_uport_is_active(struct lpuart_port *sport)
3035 {
3036 	struct tty_port *port = &sport->port.state->port;
3037 	struct tty_struct *tty;
3038 	struct device *tty_dev;
3039 	int may_wake = 0;
3040 
3041 	tty = tty_port_tty_get(port);
3042 	if (tty) {
3043 		tty_dev = tty->dev;
3044 		may_wake = tty_dev && device_may_wakeup(tty_dev);
3045 		tty_kref_put(tty);
3046 	}
3047 
3048 	if ((tty_port_initialized(port) && may_wake) ||
3049 	    (!console_suspend_enabled && uart_console(&sport->port)))
3050 		return true;
3051 
3052 	return false;
3053 }
3054 
lpuart_suspend_noirq(struct device * dev)3055 static int lpuart_suspend_noirq(struct device *dev)
3056 {
3057 	struct lpuart_port *sport = dev_get_drvdata(dev);
3058 	bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
3059 
3060 	if (lpuart_uport_is_active(sport))
3061 		serial_lpuart_enable_wakeup(sport, !!irq_wake);
3062 
3063 	pinctrl_pm_select_sleep_state(dev);
3064 
3065 	return 0;
3066 }
3067 
lpuart_resume_noirq(struct device * dev)3068 static int lpuart_resume_noirq(struct device *dev)
3069 {
3070 	struct lpuart_port *sport = dev_get_drvdata(dev);
3071 	unsigned int val;
3072 
3073 	pinctrl_pm_select_default_state(dev);
3074 
3075 	if (lpuart_uport_is_active(sport)) {
3076 		serial_lpuart_enable_wakeup(sport, false);
3077 
3078 		/* clear the wakeup flags */
3079 		if (lpuart_is_32(sport)) {
3080 			val = lpuart32_read(&sport->port, UARTSTAT);
3081 			lpuart32_write(&sport->port, val, UARTSTAT);
3082 		}
3083 	}
3084 
3085 	return 0;
3086 }
3087 
lpuart_suspend(struct device * dev)3088 static int lpuart_suspend(struct device *dev)
3089 {
3090 	struct lpuart_port *sport = dev_get_drvdata(dev);
3091 	unsigned long temp, flags;
3092 
3093 	uart_suspend_port(&lpuart_reg, &sport->port);
3094 
3095 	if (lpuart_uport_is_active(sport)) {
3096 		spin_lock_irqsave(&sport->port.lock, flags);
3097 		if (lpuart_is_32(sport)) {
3098 			/* disable Rx/Tx and interrupts */
3099 			temp = lpuart32_read(&sport->port, UARTCTRL);
3100 			temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
3101 			lpuart32_write(&sport->port, temp, UARTCTRL);
3102 		} else {
3103 			/* disable Rx/Tx and interrupts */
3104 			temp = readb(sport->port.membase + UARTCR2);
3105 			temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
3106 			writeb(temp, sport->port.membase + UARTCR2);
3107 		}
3108 		spin_unlock_irqrestore(&sport->port.lock, flags);
3109 
3110 		if (sport->lpuart_dma_rx_use) {
3111 			/*
3112 			 * EDMA driver during suspend will forcefully release any
3113 			 * non-idle DMA channels. If port wakeup is enabled or if port
3114 			 * is console port or 'no_console_suspend' is set the Rx DMA
3115 			 * cannot resume as expected, hence gracefully release the
3116 			 * Rx DMA path before suspend and start Rx DMA path on resume.
3117 			 */
3118 			lpuart_dma_rx_free(&sport->port);
3119 
3120 			/* Disable Rx DMA to use UART port as wakeup source */
3121 			spin_lock_irqsave(&sport->port.lock, flags);
3122 			if (lpuart_is_32(sport)) {
3123 				temp = lpuart32_read(&sport->port, UARTBAUD);
3124 				lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
3125 					       UARTBAUD);
3126 			} else {
3127 				writeb(readb(sport->port.membase + UARTCR5) &
3128 				       ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3129 			}
3130 			spin_unlock_irqrestore(&sport->port.lock, flags);
3131 		}
3132 
3133 		if (sport->lpuart_dma_tx_use) {
3134 			spin_lock_irqsave(&sport->port.lock, flags);
3135 			if (lpuart_is_32(sport)) {
3136 				temp = lpuart32_read(&sport->port, UARTBAUD);
3137 				temp &= ~UARTBAUD_TDMAE;
3138 				lpuart32_write(&sport->port, temp, UARTBAUD);
3139 			} else {
3140 				temp = readb(sport->port.membase + UARTCR5);
3141 				temp &= ~UARTCR5_TDMAS;
3142 				writeb(temp, sport->port.membase + UARTCR5);
3143 			}
3144 			spin_unlock_irqrestore(&sport->port.lock, flags);
3145 			sport->dma_tx_in_progress = false;
3146 			dmaengine_terminate_sync(sport->dma_tx_chan);
3147 		}
3148 	} else if (pm_runtime_active(sport->port.dev)) {
3149 		lpuart_disable_clks(sport);
3150 		pm_runtime_disable(sport->port.dev);
3151 		pm_runtime_set_suspended(sport->port.dev);
3152 	}
3153 
3154 	return 0;
3155 }
3156 
lpuart_console_fixup(struct lpuart_port * sport)3157 static void lpuart_console_fixup(struct lpuart_port *sport)
3158 {
3159 	struct tty_port *port = &sport->port.state->port;
3160 	struct uart_port *uport = &sport->port;
3161 	struct ktermios termios;
3162 
3163 	/* i.MX7ULP enter VLLS mode that lpuart module power off and registers
3164 	 * all lost no matter the port is wakeup source.
3165 	 * For console port, console baud rate setting lost and print messy
3166 	 * log when enable the console port as wakeup source. To avoid the
3167 	 * issue happen, user should not enable uart port as wakeup source
3168 	 * in VLLS mode, or restore console setting here.
3169 	 */
3170 	if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
3171 	    console_suspend_enabled && uart_console(&sport->port)) {
3172 
3173 		mutex_lock(&port->mutex);
3174 		memset(&termios, 0, sizeof(struct ktermios));
3175 		termios.c_cflag = uport->cons->cflag;
3176 		if (port->tty && termios.c_cflag == 0)
3177 			termios = port->tty->termios;
3178 		uport->ops->set_termios(uport, &termios, NULL);
3179 		mutex_unlock(&port->mutex);
3180 	}
3181 }
3182 
lpuart_resume(struct device * dev)3183 static int lpuart_resume(struct device *dev)
3184 {
3185 	struct lpuart_port *sport = dev_get_drvdata(dev);
3186 	int ret;
3187 
3188 	if (lpuart_uport_is_active(sport)) {
3189 		if (lpuart_is_32(sport))
3190 			lpuart32_hw_setup(sport);
3191 		else
3192 			lpuart_hw_setup(sport);
3193 	} else if (pm_runtime_active(sport->port.dev)) {
3194 		ret = lpuart_enable_clks(sport);
3195 		if (ret)
3196 			return ret;
3197 		pm_runtime_set_active(sport->port.dev);
3198 		pm_runtime_enable(sport->port.dev);
3199 	}
3200 
3201 	lpuart_console_fixup(sport);
3202 	uart_resume_port(&lpuart_reg, &sport->port);
3203 
3204 	return 0;
3205 }
3206 
3207 static const struct dev_pm_ops lpuart_pm_ops = {
3208 	RUNTIME_PM_OPS(lpuart_runtime_suspend,
3209 			   lpuart_runtime_resume, NULL)
3210 	NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
3211 				      lpuart_resume_noirq)
3212 	SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
3213 };
3214 
3215 static struct platform_driver lpuart_driver = {
3216 	.probe		= lpuart_probe,
3217 	.remove		= lpuart_remove,
3218 	.driver		= {
3219 		.name	= "fsl-lpuart",
3220 		.of_match_table = lpuart_dt_ids,
3221 		.pm	= pm_ptr(&lpuart_pm_ops),
3222 	},
3223 };
3224 
lpuart_serial_init(void)3225 static int __init lpuart_serial_init(void)
3226 {
3227 	int ret = uart_register_driver(&lpuart_reg);
3228 
3229 	if (ret)
3230 		return ret;
3231 
3232 	ret = platform_driver_register(&lpuart_driver);
3233 	if (ret)
3234 		uart_unregister_driver(&lpuart_reg);
3235 
3236 	return ret;
3237 }
3238 
lpuart_serial_exit(void)3239 static void __exit lpuart_serial_exit(void)
3240 {
3241 	platform_driver_unregister(&lpuart_driver);
3242 	uart_unregister_driver(&lpuart_reg);
3243 }
3244 
3245 module_init(lpuart_serial_init);
3246 module_exit(lpuart_serial_exit);
3247 
3248 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
3249 MODULE_LICENSE("GPL v2");
3250