1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/acpi/acpi.h" 34 #include "hw/char/parallel-isa.h" 35 #include "hw/loader.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "system/tcg.h" 39 #include "system/kvm.h" 40 #include "hw/i386/kvm/clock.h" 41 #include "hw/pci-host/q35.h" 42 #include "hw/pci/pcie_port.h" 43 #include "hw/qdev-properties.h" 44 #include "hw/i386/x86.h" 45 #include "hw/i386/pc.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/vfio/types.h" 49 #include "hw/virtio/virtio-iommu.h" 50 #include "hw/display/ramfb.h" 51 #include "hw/ide/pci.h" 52 #include "hw/ide/ahci-pci.h" 53 #include "hw/intc/ioapic.h" 54 #include "hw/southbridge/ich9.h" 55 #include "hw/usb.h" 56 #include "hw/usb/hcd-uhci.h" 57 #include "qapi/error.h" 58 #include "qemu/error-report.h" 59 #include "system/numa.h" 60 #include "hw/hyperv/vmbus-bridge.h" 61 #include "hw/mem/nvdimm.h" 62 #include "hw/uefi/var-service-api.h" 63 #include "hw/i386/acpi-build.h" 64 #include "target/i386/cpu.h" 65 66 /* ICH9 AHCI has 6 ports */ 67 #define MAX_SATA_PORTS 6 68 69 static GlobalProperty pc_q35_compat_defaults[] = { 70 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "39" }, 71 { TYPE_RAMFB_DEVICE, "use-legacy-x86-rom", "true" }, 72 { TYPE_VFIO_PCI_NOHOTPLUG, "use-legacy-x86-rom", "true" }, 73 }; 74 static const size_t pc_q35_compat_defaults_len = 75 G_N_ELEMENTS(pc_q35_compat_defaults); 76 77 struct ehci_companions { 78 const char *name; 79 int func; 80 int port; 81 }; 82 83 static const struct ehci_companions ich9_1d[] = { 84 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 85 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 86 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 87 }; 88 89 static const struct ehci_companions ich9_1a[] = { 90 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 91 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 92 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 93 }; 94 95 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 96 { 97 const struct ehci_companions *comp; 98 PCIDevice *ehci, *uhci; 99 BusState *usbbus; 100 const char *name; 101 int i; 102 103 switch (slot) { 104 case 0x1d: 105 name = "ich9-usb-ehci1"; 106 comp = ich9_1d; 107 break; 108 case 0x1a: 109 name = "ich9-usb-ehci2"; 110 comp = ich9_1a; 111 break; 112 default: 113 return -1; 114 } 115 116 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 117 pci_realize_and_unref(ehci, bus, &error_fatal); 118 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 119 120 for (i = 0; i < 3; i++) { 121 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 122 comp[i].name); 123 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 124 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 125 pci_realize_and_unref(uhci, bus, &error_fatal); 126 } 127 return 0; 128 } 129 130 /* PC hardware initialisation */ 131 static void pc_q35_init(MachineState *machine) 132 { 133 PCMachineState *pcms = PC_MACHINE(machine); 134 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 135 X86MachineState *x86ms = X86_MACHINE(machine); 136 Object *phb; 137 PCIDevice *lpc; 138 DeviceState *lpc_dev; 139 MemoryRegion *system_memory = get_system_memory(); 140 MemoryRegion *system_io = get_system_io(); 141 MemoryRegion *pci_memory = g_new(MemoryRegion, 1); 142 GSIState *gsi_state; 143 ISABus *isa_bus; 144 int i; 145 ram_addr_t lowmem; 146 DriveInfo *hd[MAX_SATA_PORTS]; 147 MachineClass *mc = MACHINE_GET_CLASS(machine); 148 bool acpi_pcihp; 149 bool keep_pci_slot_hpc; 150 uint64_t pci_hole64_size = 0; 151 152 assert(pcmc->pci_enabled); 153 154 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 155 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 156 * also known as MMCFG). 157 * If it doesn't, we need to split it in chunks below and above 4G. 158 * In any case, try to make sure that guest addresses aligned at 159 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 160 */ 161 if (machine->ram_size >= 0xb0000000) { 162 lowmem = 0x80000000; 163 } else { 164 lowmem = 0xb0000000; 165 } 166 167 /* Handle the machine opt max-ram-below-4g. It is basically doing 168 * min(qemu limit, user limit). 169 */ 170 if (!pcms->max_ram_below_4g) { 171 pcms->max_ram_below_4g = 4 * GiB; 172 } 173 if (lowmem > pcms->max_ram_below_4g) { 174 lowmem = pcms->max_ram_below_4g; 175 if (machine->ram_size - lowmem > lowmem && 176 lowmem & (1 * GiB - 1)) { 177 warn_report("There is possibly poor performance as the ram size " 178 " (0x%" PRIx64 ") is more then twice the size of" 179 " max-ram-below-4g (%"PRIu64") and" 180 " max-ram-below-4g is not a multiple of 1G.", 181 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 182 } 183 } 184 185 if (machine->ram_size >= lowmem) { 186 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 187 x86ms->below_4g_mem_size = lowmem; 188 } else { 189 x86ms->above_4g_mem_size = 0; 190 x86ms->below_4g_mem_size = machine->ram_size; 191 } 192 193 pc_machine_init_sgx_epc(pcms); 194 x86_cpus_init(x86ms, pcmc->default_cpu_version); 195 196 if (kvm_enabled()) { 197 kvmclock_create(pcmc->kvmclock_create_always); 198 } 199 200 /* create pci host bus */ 201 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 202 203 pci_hole64_size = object_property_get_uint(phb, 204 PCI_HOST_PROP_PCI_HOLE64_SIZE, 205 &error_abort); 206 207 /* allocate ram and load rom/bios */ 208 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 209 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); 210 211 object_property_add_child(OBJECT(machine), "q35", phb); 212 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 213 OBJECT(machine->ram), NULL); 214 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 215 OBJECT(pci_memory), NULL); 216 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 217 OBJECT(system_memory), NULL); 218 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 219 OBJECT(system_io), NULL); 220 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 221 x86ms->below_4g_mem_size, NULL); 222 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 223 x86ms->above_4g_mem_size, NULL); 224 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 225 pcms->default_bus_bypass_iommu, NULL); 226 object_property_set_bool(phb, PCI_HOST_PROP_SMM_RANGES, 227 x86_machine_is_smm_enabled(x86ms), NULL); 228 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 229 230 /* pci */ 231 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 232 233 /* irq lines */ 234 gsi_state = pc_gsi_create(&x86ms->gsi, true); 235 236 /* create ISA bus */ 237 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 238 TYPE_ICH9_LPC_DEVICE); 239 lpc_dev = DEVICE(lpc); 240 qdev_prop_set_bit(lpc_dev, "smm-enabled", 241 x86_machine_is_smm_enabled(x86ms)); 242 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 243 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 244 } 245 pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal); 246 247 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 248 249 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 250 TYPE_HOTPLUG_HANDLER, 251 (Object **)&x86ms->acpi_dev, 252 object_property_allow_set_link, 253 OBJ_PROP_LINK_STRONG); 254 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 255 OBJECT(lpc), &error_abort); 256 257 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 258 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 259 NULL); 260 261 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 262 "x-keep-pci-slot-hpc", 263 NULL); 264 265 if (!keep_pci_slot_hpc && acpi_pcihp) { 266 object_register_sugar_prop(TYPE_PCIE_SLOT, 267 "x-do-not-expose-native-hotplug-cap", 268 "true", true); 269 } 270 271 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 272 273 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 274 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 275 } 276 277 ioapic_init_gsi(gsi_state, OBJECT(phb)); 278 279 if (tcg_enabled()) { 280 x86_register_ferr_irq(x86ms->gsi[13]); 281 } 282 283 /* init basic PC hardware */ 284 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !mc->no_floppy, 285 0xff0104); 286 287 if (pcms->sata_enabled) { 288 PCIDevice *pdev; 289 AHCIPCIState *ich9; 290 291 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 292 pdev = pci_create_simple_multifunction(pcms->pcibus, 293 PCI_DEVFN(ICH9_SATA1_DEV, 294 ICH9_SATA1_FUNC), 295 "ich9-ahci"); 296 ich9 = ICH9_AHCI(pdev); 297 pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); 298 pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); 299 g_assert(MAX_SATA_PORTS == ich9->ahci.ports); 300 ide_drive_get(hd, ich9->ahci.ports); 301 ahci_ide_create_devs(&ich9->ahci, hd); 302 } 303 304 if (machine_usb(machine)) { 305 /* Should we create 6 UHCI according to ich9 spec? */ 306 ehci_create_ich9_with_companions(pcms->pcibus, 0x1d); 307 } 308 309 if (pcms->smbus_enabled) { 310 PCIDevice *smb; 311 312 /* TODO: Populate SPD eeprom data. */ 313 smb = pci_create_simple_multifunction(pcms->pcibus, 314 PCI_DEVFN(ICH9_SMB_DEV, 315 ICH9_SMB_FUNC), 316 TYPE_ICH9_SMB_DEVICE); 317 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 318 319 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 320 } 321 322 /* the rest devices to which pci devfn is automatically assigned */ 323 pc_vga_init(isa_bus, pcms->pcibus); 324 pc_nic_init(pcmc, isa_bus, pcms->pcibus); 325 326 if (machine->nvdimms_state->is_enabled) { 327 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 328 x86_nvdimm_acpi_dsmio, 329 x86ms->fw_cfg, OBJECT(pcms)); 330 } 331 332 #if defined(CONFIG_IGVM) 333 /* Apply guest state from IGVM if supplied */ 334 if (x86ms->igvm) { 335 if (IGVM_CFG_GET_CLASS(x86ms->igvm) 336 ->process(x86ms->igvm, machine->cgs, false, &error_fatal) < 0) { 337 g_assert_not_reached(); 338 } 339 } 340 #endif 341 } 342 343 #define DEFINE_Q35_MACHINE(major, minor) \ 344 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, NULL, major, minor); 345 346 #define DEFINE_Q35_MACHINE_AS_LATEST(major, minor) \ 347 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, "q35", major, minor); 348 349 #define DEFINE_Q35_MACHINE_BUGFIX(major, minor, micro) \ 350 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, NULL, major, minor, micro); 351 352 static void pc_q35_machine_options(MachineClass *m) 353 { 354 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 355 pcmc->pci_root_uid = 0; 356 pcmc->default_cpu_version = 1; 357 358 m->family = "pc_q35"; 359 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 360 m->units_per_default_bus = 1; 361 m->default_machine_opts = "firmware=bios-256k.bin"; 362 m->default_display = "std"; 363 m->default_nic = "e1000e"; 364 m->default_kernel_irqchip_split = false; 365 m->no_floppy = 1; 366 m->max_cpus = 4096; 367 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 368 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 369 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 370 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 371 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 372 machine_class_allow_dynamic_sysbus_dev(m, TYPE_UEFI_VARS_X64); 373 compat_props_add(m->compat_props, 374 pc_q35_compat_defaults, pc_q35_compat_defaults_len); 375 } 376 377 static void pc_q35_machine_10_2_options(MachineClass *m) 378 { 379 pc_q35_machine_options(m); 380 } 381 382 DEFINE_Q35_MACHINE_AS_LATEST(10, 2); 383 384 static void pc_q35_machine_10_1_options(MachineClass *m) 385 { 386 pc_q35_machine_10_2_options(m); 387 m->smbios_memory_device_size = 2047 * TiB; 388 compat_props_add(m->compat_props, hw_compat_10_1, hw_compat_10_1_len); 389 compat_props_add(m->compat_props, pc_compat_10_1, pc_compat_10_1_len); 390 } 391 392 DEFINE_Q35_MACHINE(10, 1); 393 394 static void pc_q35_machine_10_0_options(MachineClass *m) 395 { 396 pc_q35_machine_10_1_options(m); 397 compat_props_add(m->compat_props, hw_compat_10_0, hw_compat_10_0_len); 398 compat_props_add(m->compat_props, pc_compat_10_0, pc_compat_10_0_len); 399 } 400 401 DEFINE_Q35_MACHINE(10, 0); 402 403 static void pc_q35_machine_9_2_options(MachineClass *m) 404 { 405 pc_q35_machine_10_0_options(m); 406 compat_props_add(m->compat_props, hw_compat_9_2, hw_compat_9_2_len); 407 compat_props_add(m->compat_props, pc_compat_9_2, pc_compat_9_2_len); 408 } 409 410 DEFINE_Q35_MACHINE(9, 2); 411 412 static void pc_q35_machine_9_1_options(MachineClass *m) 413 { 414 pc_q35_machine_9_2_options(m); 415 compat_props_add(m->compat_props, hw_compat_9_1, hw_compat_9_1_len); 416 compat_props_add(m->compat_props, pc_compat_9_1, pc_compat_9_1_len); 417 } 418 419 DEFINE_Q35_MACHINE(9, 1); 420 421 static void pc_q35_machine_9_0_options(MachineClass *m) 422 { 423 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 424 pc_q35_machine_9_1_options(m); 425 m->smbios_memory_device_size = 16 * GiB; 426 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); 427 compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); 428 pcmc->isa_bios_alias = false; 429 } 430 431 DEFINE_Q35_MACHINE(9, 0); 432 433 static void pc_q35_machine_8_2_options(MachineClass *m) 434 { 435 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 436 pc_q35_machine_9_0_options(m); 437 m->max_cpus = 1024; 438 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 439 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 440 /* For pc-q35-8.2 and 8.1, use SMBIOS 3.X by default */ 441 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 442 } 443 444 DEFINE_Q35_MACHINE(8, 2); 445 446 static void pc_q35_machine_8_1_options(MachineClass *m) 447 { 448 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 449 pc_q35_machine_8_2_options(m); 450 pcmc->broken_32bit_mem_addr_check = true; 451 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 452 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 453 } 454 455 DEFINE_Q35_MACHINE(8, 1); 456 457 static void pc_q35_machine_8_0_options(MachineClass *m) 458 { 459 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 460 461 pc_q35_machine_8_1_options(m); 462 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 463 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 464 465 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 466 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 467 m->max_cpus = 288; 468 } 469 470 DEFINE_Q35_MACHINE(8, 0); 471 472 static void pc_q35_machine_7_2_options(MachineClass *m) 473 { 474 pc_q35_machine_8_0_options(m); 475 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 476 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 477 } 478 479 DEFINE_Q35_MACHINE(7, 2); 480 481 static void pc_q35_machine_7_1_options(MachineClass *m) 482 { 483 pc_q35_machine_7_2_options(m); 484 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 485 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 486 } 487 488 DEFINE_Q35_MACHINE(7, 1); 489 490 static void pc_q35_machine_7_0_options(MachineClass *m) 491 { 492 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 493 pc_q35_machine_7_1_options(m); 494 pcmc->enforce_amd_1tb_hole = false; 495 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 496 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 497 } 498 499 DEFINE_Q35_MACHINE(7, 0); 500 501 static void pc_q35_machine_6_2_options(MachineClass *m) 502 { 503 pc_q35_machine_7_0_options(m); 504 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 505 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 506 } 507 508 DEFINE_Q35_MACHINE(6, 2); 509 510 static void pc_q35_machine_6_1_options(MachineClass *m) 511 { 512 pc_q35_machine_6_2_options(m); 513 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 514 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 515 m->smp_props.prefer_sockets = true; 516 } 517 518 DEFINE_Q35_MACHINE(6, 1); 519 520 static void pc_q35_machine_6_0_options(MachineClass *m) 521 { 522 pc_q35_machine_6_1_options(m); 523 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 524 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 525 } 526 527 DEFINE_Q35_MACHINE(6, 0); 528 529 static void pc_q35_machine_5_2_options(MachineClass *m) 530 { 531 pc_q35_machine_6_0_options(m); 532 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 533 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 534 } 535 536 DEFINE_Q35_MACHINE(5, 2); 537 538 static void pc_q35_machine_5_1_options(MachineClass *m) 539 { 540 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 541 542 pc_q35_machine_5_2_options(m); 543 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 544 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 545 pcmc->kvmclock_create_always = false; 546 pcmc->pci_root_uid = 1; 547 } 548 549 DEFINE_Q35_MACHINE(5, 1); 550 551 static void pc_q35_machine_5_0_options(MachineClass *m) 552 { 553 pc_q35_machine_5_1_options(m); 554 m->numa_mem_supported = true; 555 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 556 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 557 m->auto_enable_numa_with_memdev = false; 558 } 559 560 DEFINE_Q35_MACHINE(5, 0); 561 562 static void pc_q35_machine_4_2_options(MachineClass *m) 563 { 564 pc_q35_machine_5_0_options(m); 565 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 566 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 567 } 568 569 DEFINE_Q35_MACHINE(4, 2); 570 571 static void pc_q35_machine_4_1_options(MachineClass *m) 572 { 573 pc_q35_machine_4_2_options(m); 574 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 575 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 576 } 577 578 DEFINE_Q35_MACHINE(4, 1); 579 580 static void pc_q35_machine_4_0_1_options(MachineClass *m) 581 { 582 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 583 pc_q35_machine_4_1_options(m); 584 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 585 /* 586 * This is the default machine for the 4.0-stable branch. It is basically 587 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 588 * 4.0 compat props. 589 */ 590 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 591 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 592 } 593 594 DEFINE_Q35_MACHINE_BUGFIX(4, 0, 1); 595 596 static void pc_q35_machine_4_0_options(MachineClass *m) 597 { 598 pc_q35_machine_4_0_1_options(m); 599 m->default_kernel_irqchip_split = true; 600 /* Compat props are applied by the 4.0.1 machine */ 601 } 602 603 DEFINE_Q35_MACHINE(4, 0); 604 605 static void pc_q35_machine_3_1_options(MachineClass *m) 606 { 607 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 608 609 pc_q35_machine_4_0_options(m); 610 m->default_kernel_irqchip_split = false; 611 m->smbus_no_migration_support = true; 612 pcmc->pvh_enabled = false; 613 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 614 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 615 } 616 617 DEFINE_Q35_MACHINE(3, 1); 618 619 static void pc_q35_machine_3_0_options(MachineClass *m) 620 { 621 pc_q35_machine_3_1_options(m); 622 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 623 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 624 } 625 626 DEFINE_Q35_MACHINE(3, 0); 627 628 static void pc_q35_machine_2_12_options(MachineClass *m) 629 { 630 pc_q35_machine_3_0_options(m); 631 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 632 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 633 } 634 635 DEFINE_Q35_MACHINE(2, 12); 636 637 static void pc_q35_machine_2_11_options(MachineClass *m) 638 { 639 pc_q35_machine_2_12_options(m); 640 m->default_nic = "e1000"; 641 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 642 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 643 } 644 645 DEFINE_Q35_MACHINE(2, 11); 646 647 static void pc_q35_machine_2_10_options(MachineClass *m) 648 { 649 pc_q35_machine_2_11_options(m); 650 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 651 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 652 m->auto_enable_numa_with_memhp = false; 653 } 654 655 DEFINE_Q35_MACHINE(2, 10); 656 657 static void pc_q35_machine_2_9_options(MachineClass *m) 658 { 659 pc_q35_machine_2_10_options(m); 660 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 661 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 662 } 663 664 DEFINE_Q35_MACHINE(2, 9); 665 666 static void pc_q35_machine_2_8_options(MachineClass *m) 667 { 668 pc_q35_machine_2_9_options(m); 669 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 670 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 671 } 672 673 DEFINE_Q35_MACHINE(2, 8); 674 675 static void pc_q35_machine_2_7_options(MachineClass *m) 676 { 677 pc_q35_machine_2_8_options(m); 678 m->max_cpus = 255; 679 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 680 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 681 } 682 683 DEFINE_Q35_MACHINE(2, 7); 684 685 static void pc_q35_machine_2_6_options(MachineClass *m) 686 { 687 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 688 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 689 690 pc_q35_machine_2_7_options(m); 691 pcmc->legacy_cpu_hotplug = true; 692 x86mc->fwcfg_dma_enabled = false; 693 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 694 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 695 } 696 697 DEFINE_Q35_MACHINE(2, 6); 698