1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4  * Copyright (c) 2006, 2007 Cisco Systems.  All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 
35 #ifndef MLX4_FW_H
36 #define MLX4_FW_H
37 
38 #include "mlx4.h"
39 #include "icm.h"
40 
41 struct mlx4_mod_stat_cfg {
42 	u8 log_pg_sz;
43 	u8 log_pg_sz_m;
44 };
45 
46 struct mlx4_port_cap {
47 	u8  link_state;
48 	u8  supported_port_types;
49 	u8  suggested_type;
50 	u8  default_sense;
51 	u8  log_max_macs;
52 	u8  log_max_vlans;
53 	int ib_mtu;
54 	int max_port_width;
55 	int max_vl;
56 	int max_tc_eth;
57 	int max_gids;
58 	int max_pkeys;
59 	u64 def_mac;
60 	u16 eth_mtu;
61 	int trans_type;
62 	int vendor_oui;
63 	u16 wavelength;
64 	u64 trans_code;
65 	u8 dmfs_optimized_state;
66 };
67 
68 struct mlx4_dev_cap {
69 	int max_srq_sz;
70 	int max_qp_sz;
71 	int reserved_qps;
72 	int max_qps;
73 	int reserved_srqs;
74 	int max_srqs;
75 	int max_cq_sz;
76 	int reserved_cqs;
77 	int max_cqs;
78 	int max_mpts;
79 	int reserved_eqs;
80 	int max_eqs;
81 	int num_sys_eqs;
82 	int reserved_mtts;
83 	int reserved_mrws;
84 	int max_requester_per_qp;
85 	int max_responder_per_qp;
86 	int max_rdma_global;
87 	int local_ca_ack_delay;
88 	int num_ports;
89 	u32 max_msg_sz;
90 	u16 stat_rate_support;
91 	int fs_log_max_ucast_qp_range_size;
92 	int fs_max_num_qp_per_entry;
93 	u64 flags;
94 	u64 flags2;
95 	int reserved_uars;
96 	int uar_size;
97 	int min_page_sz;
98 	int bf_reg_size;
99 	int bf_regs_per_page;
100 	int max_sq_sg;
101 	int max_sq_desc_sz;
102 	int max_rq_sg;
103 	int max_rq_desc_sz;
104 	int max_qp_per_mcg;
105 	int reserved_mgms;
106 	int max_mcgs;
107 	int reserved_pds;
108 	int max_pds;
109 	int reserved_xrcds;
110 	int max_xrcds;
111 	int qpc_entry_sz;
112 	int rdmarc_entry_sz;
113 	int altc_entry_sz;
114 	int aux_entry_sz;
115 	int srq_entry_sz;
116 	int cqc_entry_sz;
117 	int eqc_entry_sz;
118 	int dmpt_entry_sz;
119 	int cmpt_entry_sz;
120 	int mtt_entry_sz;
121 	int resize_srq;
122 	u32 bmme_flags;
123 	u32 reserved_lkey;
124 	u64 max_icm_sz;
125 	int max_gso_sz;
126 	int max_rss_tbl_sz;
127 	u32 max_counters;
128 	u32 dmfs_high_rate_qpn_base;
129 	u32 dmfs_high_rate_qpn_range;
130 	struct mlx4_rate_limit_caps rl_caps;
131 	u32 health_buffer_addrs;
132 	struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1];
133 	bool wol_port[MLX4_MAX_PORTS + 1];
134 	bool map_clock_to_user;
135 };
136 
137 struct mlx4_func_cap {
138 	u8	num_ports;
139 	u8	flags;
140 	u32	pf_context_behaviour;
141 	int	qp_quota;
142 	int	cq_quota;
143 	int	srq_quota;
144 	int	mpt_quota;
145 	int	mtt_quota;
146 	int	max_eq;
147 	int	reserved_eq;
148 	int	mcg_quota;
149 	struct mlx4_spec_qps spec_qps;
150 	u32	reserved_lkey;
151 	u8	physical_port;
152 	u8	flags0;
153 	u8	flags1;
154 	u64	phys_port_id;
155 	u32	extra_flags;
156 };
157 
158 struct mlx4_func {
159 	int	bus;
160 	int	device;
161 	int	function;
162 	int	physical_function;
163 	int	rsvd_eqs;
164 	int	max_eq;
165 	int	rsvd_uars;
166 };
167 
168 struct mlx4_adapter {
169 	char board_id[MLX4_BOARD_ID_LEN];
170 	u8   inta_pin;
171 };
172 
173 struct mlx4_init_hca_param {
174 	u64 qpc_base;
175 	u64 rdmarc_base;
176 	u64 auxc_base;
177 	u64 altc_base;
178 	u64 srqc_base;
179 	u64 cqc_base;
180 	u64 eqc_base;
181 	u64 mc_base;
182 	u64 dmpt_base;
183 	u64 cmpt_base;
184 	u64 mtt_base;
185 	u64 global_caps;
186 	u8 log_mc_entry_sz;
187 	u8 log_mc_hash_sz;
188 	u16 hca_core_clock; /* Internal Clock Frequency (in MHz) */
189 	u8  log_num_qps;
190 	u8  log_num_srqs;
191 	u8  log_num_cqs;
192 	u8  log_num_eqs;
193 	u16 num_sys_eqs;
194 	u8  log_rd_per_qp;
195 	u8  log_mc_table_sz;
196 	u8  log_mpt_sz;
197 	u8  log_uar_sz;
198 	u8  mw_enabled;  /* Enable memory windows */
199 	u8  uar_page_sz; /* log pg sz in 4k chunks */
200 	u8  steering_mode; /* for QUERY_HCA */
201 	u8  dmfs_high_steer_mode; /* for QUERY_HCA */
202 	u64 dev_cap_enabled;
203 	u16 cqe_size; /* For use only when CQE stride feature enabled */
204 	u16 eqe_size; /* For use only when EQE stride feature enabled */
205 	u8 rss_ip_frags;
206 	u8 phv_check_en; /* for QUERY_HCA */
207 };
208 
209 struct mlx4_init_ib_param {
210 	int port_width;
211 	int vl_cap;
212 	int mtu_cap;
213 	u16 gid_cap;
214 	u16 pkey_cap;
215 	int set_guid0;
216 	u64 guid0;
217 	int set_node_guid;
218 	u64 node_guid;
219 	int set_si_guid;
220 	u64 si_guid;
221 };
222 
223 struct mlx4_set_ib_param {
224 	int set_si_guid;
225 	int reset_qkey_viol;
226 	u64 si_guid;
227 	u32 cap_mask;
228 };
229 
230 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
231 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
232 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap);
233 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
234 			struct mlx4_func_cap *func_cap);
235 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
236 				struct mlx4_vhcr *vhcr,
237 				struct mlx4_cmd_mailbox *inbox,
238 				struct mlx4_cmd_mailbox *outbox,
239 				struct mlx4_cmd_info *cmd);
240 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave);
241 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
242 int mlx4_UNMAP_FA(struct mlx4_dev *dev);
243 int mlx4_RUN_FW(struct mlx4_dev *dev);
244 int mlx4_QUERY_FW(struct mlx4_dev *dev);
245 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
246 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
247 int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
248 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
249 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
250 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
251 int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
252 int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
253 int mlx4_NOP(struct mlx4_dev *dev);
254 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
255 void mlx4_opreq_action(struct work_struct *work);
256 
257 #endif /* MLX4_FW_H */
258