xref: /openbmc/linux/sound/soc/sof/ipc4-pcm.c (revision 3cac6eeb)
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license.  When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2022 Intel Corporation. All rights reserved.
7 //
8 
9 #include <sound/pcm_params.h>
10 #include <sound/sof/ipc4/header.h>
11 #include "sof-audio.h"
12 #include "sof-priv.h"
13 #include "ops.h"
14 #include "ipc4-priv.h"
15 #include "ipc4-topology.h"
16 #include "ipc4-fw-reg.h"
17 
sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev * sdev,u32 state,struct ipc4_pipeline_set_state_data * trigger_list)18 static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state,
19 					     struct ipc4_pipeline_set_state_data *trigger_list)
20 {
21 	struct sof_ipc4_msg msg = {{ 0 }};
22 	u32 primary, ipc_size;
23 
24 	/* trigger a single pipeline */
25 	if (trigger_list->count == 1)
26 		return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_instance_ids[0],
27 						   state);
28 
29 	primary = state;
30 	primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
31 	primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
32 	primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
33 	msg.primary = primary;
34 
35 	/* trigger multiple pipelines with a single IPC */
36 	msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI;
37 
38 	/* ipc_size includes the count and the pipeline IDs for the number of pipelines */
39 	ipc_size = sizeof(u32) * (trigger_list->count + 1);
40 	msg.data_size = ipc_size;
41 	msg.data_ptr = trigger_list;
42 
43 	return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size);
44 }
45 
sof_ipc4_set_pipeline_state(struct snd_sof_dev * sdev,u32 instance_id,u32 state)46 int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 instance_id, u32 state)
47 {
48 	struct sof_ipc4_msg msg = {{ 0 }};
49 	u32 primary;
50 
51 	dev_dbg(sdev->dev, "ipc4 set pipeline instance %d state %d", instance_id, state);
52 
53 	primary = state;
54 	primary |= SOF_IPC4_GLB_PIPE_STATE_ID(instance_id);
55 	primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
56 	primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
57 	primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
58 
59 	msg.primary = primary;
60 
61 	return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
62 }
63 EXPORT_SYMBOL(sof_ipc4_set_pipeline_state);
64 
65 static void
sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev * sdev,int state,struct snd_sof_pipeline * spipe,struct ipc4_pipeline_set_state_data * trigger_list)66 sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state,
67 				      struct snd_sof_pipeline *spipe,
68 				      struct ipc4_pipeline_set_state_data *trigger_list)
69 {
70 	struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
71 	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
72 
73 	if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
74 		return;
75 
76 	switch (state) {
77 	case SOF_IPC4_PIPE_RUNNING:
78 		/*
79 		 * Trigger pipeline if all PCMs containing it are paused or if it is RUNNING
80 		 * for the first time
81 		 */
82 		if (spipe->started_count == spipe->paused_count)
83 			trigger_list->pipeline_instance_ids[trigger_list->count++] =
84 				pipe_widget->instance_id;
85 		break;
86 	case SOF_IPC4_PIPE_RESET:
87 		/* RESET if the pipeline is neither running nor paused */
88 		if (!spipe->started_count && !spipe->paused_count)
89 			trigger_list->pipeline_instance_ids[trigger_list->count++] =
90 				pipe_widget->instance_id;
91 		break;
92 	case SOF_IPC4_PIPE_PAUSED:
93 		/* Pause the pipeline only when its started_count is 1 more than paused_count */
94 		if (spipe->paused_count == (spipe->started_count - 1))
95 			trigger_list->pipeline_instance_ids[trigger_list->count++] =
96 				pipe_widget->instance_id;
97 		break;
98 	default:
99 		break;
100 	}
101 }
102 
103 static void
sof_ipc4_update_pipeline_state(struct snd_sof_dev * sdev,int state,int cmd,struct snd_sof_pipeline * spipe,struct ipc4_pipeline_set_state_data * trigger_list)104 sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd,
105 			       struct snd_sof_pipeline *spipe,
106 			       struct ipc4_pipeline_set_state_data *trigger_list)
107 {
108 	struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
109 	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
110 	int i;
111 
112 	if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
113 		return;
114 
115 	/* set state for pipeline if it was just triggered */
116 	for (i = 0; i < trigger_list->count; i++) {
117 		if (trigger_list->pipeline_instance_ids[i] == pipe_widget->instance_id) {
118 			pipeline->state = state;
119 			break;
120 		}
121 	}
122 
123 	switch (state) {
124 	case SOF_IPC4_PIPE_PAUSED:
125 		switch (cmd) {
126 		case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
127 			/*
128 			 * increment paused_count if the PAUSED is the final state during
129 			 * the PAUSE trigger
130 			 */
131 			spipe->paused_count++;
132 			break;
133 		case SNDRV_PCM_TRIGGER_STOP:
134 		case SNDRV_PCM_TRIGGER_SUSPEND:
135 			/*
136 			 * decrement started_count if PAUSED is the final state during the
137 			 * STOP trigger
138 			 */
139 			spipe->started_count--;
140 			break;
141 		default:
142 			break;
143 		}
144 		break;
145 	case SOF_IPC4_PIPE_RUNNING:
146 		switch (cmd) {
147 		case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
148 			/* decrement paused_count for RELEASE */
149 			spipe->paused_count--;
150 			break;
151 		case SNDRV_PCM_TRIGGER_START:
152 		case SNDRV_PCM_TRIGGER_RESUME:
153 			/* increment started_count for START/RESUME */
154 			spipe->started_count++;
155 			break;
156 		default:
157 			break;
158 		}
159 		break;
160 	default:
161 		break;
162 	}
163 }
164 
165 /*
166  * The picture below represents the pipeline state machine wrt PCM actions corresponding to the
167  * triggers and ioctls
168  *				+---------------+
169  *				|               |
170  *				|    INIT       |
171  *				|               |
172  *				+-------+-------+
173  *					|
174  *					|
175  *					| START
176  *					|
177  *					|
178  * +----------------+		   +------v-------+		  +-------------+
179  * |                |   START     |              |   HW_FREE	  |             |
180  * |   RUNNING      <-------------+  PAUSED      +--------------> +   RESET     |
181  * |                |   PAUSE     |              |		  |             |
182  * +------+---------+   RELEASE   +---------+----+		  +-------------+
183  *	  |				     ^
184  *	  |				     |
185  *	  |				     |
186  *	  |				     |
187  *	  |		PAUSE		     |
188  *	  +---------------------------------+
189  *			STOP/SUSPEND
190  *
191  * Note that during system suspend, the suspend trigger is followed by a hw_free in
192  * sof_pcm_trigger(). So, the final state during suspend would be RESET.
193  * Also, since the SOF driver doesn't support full resume, streams would be restarted with the
194  * prepare ioctl before the START trigger.
195  */
196 
197 /*
198  * Chained DMA is a special case where there is no processing on
199  * DSP. The samples are just moved over by host side DMA to a single
200  * buffer on DSP and directly from there to link DMA. However, the
201  * model on SOF driver has two notional pipelines, one at host DAI,
202  * and another at link DAI. They both shall have the use_chain_dma
203  * attribute.
204  */
205 
sof_ipc4_chain_dma_trigger(struct snd_sof_dev * sdev,struct snd_sof_pcm_stream_pipeline_list * pipeline_list,int state,int cmd)206 static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev,
207 				      struct snd_sof_pcm_stream_pipeline_list *pipeline_list,
208 				      int state, int cmd)
209 {
210 	bool allocate, enable, set_fifo_size;
211 	struct sof_ipc4_msg msg = {{ 0 }};
212 	int i;
213 
214 	switch (state) {
215 	case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */
216 		allocate = true;
217 		enable = true;
218 		/*
219 		 * SOF assumes creation of a new stream from the presence of fifo_size
220 		 * in the message, so we must leave it out in pause release case.
221 		 */
222 		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
223 			set_fifo_size = false;
224 		else
225 			set_fifo_size = true;
226 		break;
227 	case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */
228 		allocate = true;
229 		enable = false;
230 		set_fifo_size = false;
231 		break;
232 	case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */
233 		allocate = false;
234 		enable = false;
235 		set_fifo_size = false;
236 		break;
237 	default:
238 		dev_err(sdev->dev, "Unexpected state %d", state);
239 		return -EINVAL;
240 	}
241 
242 	msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA);
243 	msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
244 	msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
245 
246 	/*
247 	 * To set-up the DMA chain, the host DMA ID and SCS setting
248 	 * are retrieved from the host pipeline configuration. Likewise
249 	 * the link DMA ID and fifo_size are retrieved from the link
250 	 * pipeline configuration.
251 	 */
252 	for (i = 0; i < pipeline_list->count; i++) {
253 		struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i];
254 		struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
255 		struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
256 
257 		if (!pipeline->use_chain_dma) {
258 			dev_err(sdev->dev,
259 				"All pipelines in chained DMA stream should have use_chain_dma attribute set.");
260 			return -EINVAL;
261 		}
262 
263 		msg.primary |= pipeline->msg.primary;
264 
265 		/* Add fifo_size (actually DMA buffer size) field to the message */
266 		if (set_fifo_size)
267 			msg.extension |= pipeline->msg.extension;
268 	}
269 
270 	if (allocate)
271 		msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK;
272 
273 	if (enable)
274 		msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK;
275 
276 	return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
277 }
278 
sof_ipc4_trigger_pipelines(struct snd_soc_component * component,struct snd_pcm_substream * substream,int state,int cmd)279 static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component,
280 				      struct snd_pcm_substream *substream, int state, int cmd)
281 {
282 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
283 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
284 	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
285 	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
286 	struct ipc4_pipeline_set_state_data *trigger_list;
287 	struct snd_sof_widget *pipe_widget;
288 	struct sof_ipc4_pipeline *pipeline;
289 	struct snd_sof_pipeline *spipe;
290 	struct snd_sof_pcm *spcm;
291 	int ret;
292 	int i;
293 
294 	dev_dbg(sdev->dev, "trigger cmd: %d state: %d\n", cmd, state);
295 
296 	spcm = snd_sof_find_spcm_dai(component, rtd);
297 	if (!spcm)
298 		return -EINVAL;
299 
300 	pipeline_list = &spcm->stream[substream->stream].pipeline_list;
301 
302 	/* nothing to trigger if the list is empty */
303 	if (!pipeline_list->pipelines || !pipeline_list->count)
304 		return 0;
305 
306 	spipe = pipeline_list->pipelines[0];
307 	pipe_widget = spipe->pipe_widget;
308 	pipeline = pipe_widget->private;
309 
310 	/*
311 	 * If use_chain_dma attribute is set we proceed to chained DMA
312 	 * trigger function that handles the rest for the substream.
313 	 */
314 	if (pipeline->use_chain_dma)
315 		return sof_ipc4_chain_dma_trigger(sdev, pipeline_list, state, cmd);
316 
317 	/* allocate memory for the pipeline data */
318 	trigger_list = kzalloc(struct_size(trigger_list, pipeline_instance_ids,
319 					   pipeline_list->count), GFP_KERNEL);
320 	if (!trigger_list)
321 		return -ENOMEM;
322 
323 	mutex_lock(&ipc4_data->pipeline_state_mutex);
324 
325 	/*
326 	 * IPC4 requires pipelines to be triggered in order starting at the sink and
327 	 * walking all the way to the source. So traverse the pipeline_list in the order
328 	 * sink->source when starting PCM's and in the reverse order to pause/stop PCM's.
329 	 * Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork
330 	 * in the pipeline, the order of triggering between the left/right paths will be
331 	 * indeterministic. But the sink->source trigger order sink->source would still be
332 	 * guaranteed for each fork independently.
333 	 */
334 	if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET)
335 		for (i = pipeline_list->count - 1; i >= 0; i--) {
336 			spipe = pipeline_list->pipelines[i];
337 			sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list);
338 		}
339 	else
340 		for (i = 0; i < pipeline_list->count; i++) {
341 			spipe = pipeline_list->pipelines[i];
342 			sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list);
343 		}
344 
345 	/* return if all pipelines are in the requested state already */
346 	if (!trigger_list->count) {
347 		ret = 0;
348 		goto free;
349 	}
350 
351 	/* no need to pause before reset or before pause release */
352 	if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
353 		goto skip_pause_transition;
354 
355 	/*
356 	 * set paused state for pipelines if the final state is PAUSED or when the pipeline
357 	 * is set to RUNNING for the first time after the PCM is started.
358 	 */
359 	ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list);
360 	if (ret < 0) {
361 		dev_err(sdev->dev, "failed to pause all pipelines\n");
362 		goto free;
363 	}
364 
365 	/* update PAUSED state for all pipelines just triggered */
366 	for (i = 0; i < pipeline_list->count ; i++) {
367 		spipe = pipeline_list->pipelines[i];
368 		sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe,
369 					       trigger_list);
370 	}
371 
372 	/* return if this is the final state */
373 	if (state == SOF_IPC4_PIPE_PAUSED)
374 		goto free;
375 skip_pause_transition:
376 	/* else set the RUNNING/RESET state in the DSP */
377 	ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list);
378 	if (ret < 0) {
379 		dev_err(sdev->dev, "failed to set final state %d for all pipelines\n", state);
380 		/*
381 		 * workaround: if the firmware is crashed while setting the
382 		 * pipelines to reset state we must ignore the error code and
383 		 * reset it to 0.
384 		 * Since the firmware is crashed we will not send IPC messages
385 		 * and we are going to see errors printed, but the state of the
386 		 * widgets will be correct for the next boot.
387 		 */
388 		if (sdev->fw_state != SOF_FW_CRASHED || state != SOF_IPC4_PIPE_RESET)
389 			goto free;
390 
391 		ret = 0;
392 	}
393 
394 	/* update RUNNING/RESET state for all pipelines that were just triggered */
395 	for (i = 0; i < pipeline_list->count; i++) {
396 		spipe = pipeline_list->pipelines[i];
397 		sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list);
398 	}
399 
400 free:
401 	mutex_unlock(&ipc4_data->pipeline_state_mutex);
402 	kfree(trigger_list);
403 	return ret;
404 }
405 
sof_ipc4_pcm_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)406 static int sof_ipc4_pcm_trigger(struct snd_soc_component *component,
407 				struct snd_pcm_substream *substream, int cmd)
408 {
409 	int state;
410 
411 	/* determine the pipeline state */
412 	switch (cmd) {
413 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
414 		state = SOF_IPC4_PIPE_PAUSED;
415 		break;
416 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
417 	case SNDRV_PCM_TRIGGER_RESUME:
418 	case SNDRV_PCM_TRIGGER_START:
419 		state = SOF_IPC4_PIPE_RUNNING;
420 		break;
421 	case SNDRV_PCM_TRIGGER_SUSPEND:
422 	case SNDRV_PCM_TRIGGER_STOP:
423 		state = SOF_IPC4_PIPE_PAUSED;
424 		break;
425 	default:
426 		dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd);
427 		return -EINVAL;
428 	}
429 
430 	/* set the pipeline state */
431 	return sof_ipc4_trigger_pipelines(component, substream, state, cmd);
432 }
433 
sof_ipc4_pcm_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)434 static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component,
435 				struct snd_pcm_substream *substream)
436 {
437 	/* command is not relevant with RESET, so just pass 0 */
438 	return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0);
439 }
440 
ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev * sdev,const char * link_name,struct snd_pcm_hw_params * params)441 static void ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, const char *link_name,
442 						 struct snd_pcm_hw_params *params)
443 {
444 	struct snd_sof_dai_link *slink;
445 	struct snd_sof_dai *dai;
446 	bool dai_link_found = false;
447 	int i;
448 
449 	list_for_each_entry(slink, &sdev->dai_link_list, list) {
450 		if (!strcmp(slink->link->name, link_name)) {
451 			dai_link_found = true;
452 			break;
453 		}
454 	}
455 
456 	if (!dai_link_found)
457 		return;
458 
459 	for (i = 0; i < slink->num_hw_configs; i++) {
460 		struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i];
461 
462 		if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate)) {
463 			/* set current config for all DAI's with matching name */
464 			list_for_each_entry(dai, &sdev->dai_list, list)
465 				if (!strcmp(slink->link->name, dai->name))
466 					dai->current_config = le32_to_cpu(hw_config->id);
467 			break;
468 		}
469 	}
470 }
471 
472 /*
473  * Fixup DAI link parameters for sampling rate based on
474  * DAI copier configuration.
475  */
sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev * sdev,struct snd_pcm_hw_params * params,struct sof_ipc4_copier * ipc4_copier)476 static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev,
477 					    struct snd_pcm_hw_params *params,
478 					    struct sof_ipc4_copier *ipc4_copier)
479 {
480 	struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
481 	struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
482 	int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
483 	unsigned int fe_rate = params_rate(params);
484 	bool fe_be_rate_match = false;
485 	bool single_be_rate = true;
486 	unsigned int be_rate;
487 	int i;
488 
489 	/*
490 	 * Copier does not change sampling rate, so we
491 	 * need to only consider the input pin information.
492 	 */
493 	for (i = 0; i < num_input_formats; i++) {
494 		unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency;
495 
496 		if (i == 0)
497 			be_rate = val;
498 		else if (val != be_rate)
499 			single_be_rate = false;
500 
501 		if (val == fe_rate) {
502 			fe_be_rate_match = true;
503 			break;
504 		}
505 	}
506 
507 	/*
508 	 * If rate is different than FE rate, topology must
509 	 * contain an SRC. But we do require topology to
510 	 * define a single rate in the DAI copier config in
511 	 * this case (FE rate may be variable).
512 	 */
513 	if (!fe_be_rate_match) {
514 		if (!single_be_rate) {
515 			dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n");
516 			return -EINVAL;
517 		}
518 
519 		rate->min = be_rate;
520 		rate->max = rate->min;
521 	}
522 
523 	return 0;
524 }
525 
sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)526 static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
527 				       struct snd_pcm_hw_params *params)
528 {
529 	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
530 	struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
531 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
532 	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
533 	struct sof_ipc4_copier *ipc4_copier;
534 	bool use_chain_dma = false;
535 	int dir;
536 
537 	if (!dai) {
538 		dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
539 			rtd->dai_link->name);
540 		return -EINVAL;
541 	}
542 
543 	ipc4_copier = dai->private;
544 	if (!ipc4_copier) {
545 		dev_err(component->dev, "%s: No private data found for DAI %s\n",
546 			__func__, rtd->dai_link->name);
547 		return -EINVAL;
548 	}
549 
550 	for_each_pcm_streams(dir) {
551 		struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir);
552 
553 		if (w) {
554 			struct snd_sof_widget *swidget = w->dobj.private;
555 			struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
556 			struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
557 
558 			if (pipeline->use_chain_dma)
559 				use_chain_dma = true;
560 		}
561 	}
562 
563 	/* Chain DMA does not use copiers, so no fixup needed */
564 	if (!use_chain_dma) {
565 		int ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier);
566 
567 		if (ret)
568 			return ret;
569 	}
570 
571 	switch (ipc4_copier->dai_type) {
572 	case SOF_DAI_INTEL_SSP:
573 		ipc4_ssp_dai_config_pcm_params_match(sdev, (char *)rtd->dai_link->name, params);
574 		break;
575 	default:
576 		break;
577 	}
578 
579 	return 0;
580 }
581 
sof_ipc4_pcm_free(struct snd_sof_dev * sdev,struct snd_sof_pcm * spcm)582 static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
583 {
584 	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
585 	int stream;
586 
587 	for_each_pcm_streams(stream) {
588 		pipeline_list = &spcm->stream[stream].pipeline_list;
589 		kfree(pipeline_list->pipelines);
590 		pipeline_list->pipelines = NULL;
591 		kfree(spcm->stream[stream].private);
592 		spcm->stream[stream].private = NULL;
593 	}
594 }
595 
sof_ipc4_pcm_setup(struct snd_sof_dev * sdev,struct snd_sof_pcm * spcm)596 static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
597 {
598 	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
599 	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
600 	struct sof_ipc4_timestamp_info *stream_info;
601 	bool support_info = true;
602 	u32 abi_version;
603 	u32 abi_offset;
604 	int stream;
605 
606 	abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver);
607 	sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version,
608 			 sizeof(abi_version));
609 
610 	if (abi_version < SOF_IPC4_FW_REGS_ABI_VER)
611 		support_info = false;
612 
613 	for_each_pcm_streams(stream) {
614 		pipeline_list = &spcm->stream[stream].pipeline_list;
615 
616 		/* allocate memory for max number of pipeline IDs */
617 		pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines,
618 						   sizeof(struct snd_sof_widget *), GFP_KERNEL);
619 		if (!pipeline_list->pipelines) {
620 			sof_ipc4_pcm_free(sdev, spcm);
621 			return -ENOMEM;
622 		}
623 
624 		if (!support_info)
625 			continue;
626 
627 		stream_info = kzalloc(sizeof(*stream_info), GFP_KERNEL);
628 		if (!stream_info) {
629 			sof_ipc4_pcm_free(sdev, spcm);
630 			return -ENOMEM;
631 		}
632 
633 		spcm->stream[stream].private = stream_info;
634 	}
635 
636 	return 0;
637 }
638 
sof_ipc4_build_time_info(struct snd_sof_dev * sdev,struct snd_sof_pcm_stream * spcm)639 static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *spcm)
640 {
641 	struct sof_ipc4_copier *host_copier = NULL;
642 	struct sof_ipc4_copier *dai_copier = NULL;
643 	struct sof_ipc4_llp_reading_slot llp_slot;
644 	struct sof_ipc4_timestamp_info *info;
645 	struct snd_soc_dapm_widget *widget;
646 	struct snd_sof_dai *dai;
647 	int i;
648 
649 	/* find host & dai to locate info in memory window */
650 	for_each_dapm_widgets(spcm->list, i, widget) {
651 		struct snd_sof_widget *swidget = widget->dobj.private;
652 
653 		if (!swidget)
654 			continue;
655 
656 		if (WIDGET_IS_AIF(swidget->widget->id)) {
657 			host_copier = swidget->private;
658 		} else if (WIDGET_IS_DAI(swidget->widget->id)) {
659 			dai = swidget->private;
660 			dai_copier = dai->private;
661 		}
662 	}
663 
664 	/* both host and dai copier must be valid for time_info */
665 	if (!host_copier || !dai_copier) {
666 		dev_err(sdev->dev, "host or dai copier are not found\n");
667 		return;
668 	}
669 
670 	info = spcm->private;
671 	info->host_copier = host_copier;
672 	info->dai_copier = dai_copier;
673 	info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_gpdma_reading_slots) +
674 				    sdev->fw_info_box.offset;
675 
676 	/* find llp slot used by current dai */
677 	for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) {
678 		sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
679 		if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
680 			break;
681 
682 		info->llp_offset += sizeof(llp_slot);
683 	}
684 
685 	if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS)
686 		return;
687 
688 	/* if no llp gpdma slot is used, check aggregated sdw slot */
689 	info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_sndw_reading_slots) +
690 					sdev->fw_info_box.offset;
691 	for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) {
692 		sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
693 		if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
694 			break;
695 
696 		info->llp_offset += sizeof(llp_slot);
697 	}
698 
699 	if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS)
700 		return;
701 
702 	/* check EVAD slot */
703 	info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_evad_reading_slot) +
704 					sdev->fw_info_box.offset;
705 	sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
706 	if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id) {
707 		dev_info(sdev->dev, "no llp found, fall back to default HDA path");
708 		info->llp_offset = 0;
709 	}
710 }
711 
sof_ipc4_pcm_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_sof_platform_stream_params * platform_params)712 static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component,
713 				  struct snd_pcm_substream *substream,
714 				  struct snd_pcm_hw_params *params,
715 				  struct snd_sof_platform_stream_params *platform_params)
716 {
717 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
718 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
719 	struct sof_ipc4_timestamp_info *time_info;
720 	struct snd_sof_pcm *spcm;
721 
722 	spcm = snd_sof_find_spcm_dai(component, rtd);
723 	if (!spcm)
724 		return -EINVAL;
725 
726 	time_info = spcm->stream[substream->stream].private;
727 	/* delay calculation is not supported by current fw_reg ABI */
728 	if (!time_info)
729 		return 0;
730 
731 	time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
732 	time_info->llp_offset = 0;
733 
734 	sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]);
735 
736 	return 0;
737 }
738 
sof_ipc4_get_stream_start_offset(struct snd_sof_dev * sdev,struct snd_pcm_substream * substream,struct snd_sof_pcm_stream * stream,struct sof_ipc4_timestamp_info * time_info)739 static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev,
740 					    struct snd_pcm_substream *substream,
741 					    struct snd_sof_pcm_stream *stream,
742 					    struct sof_ipc4_timestamp_info *time_info)
743 {
744 	struct sof_ipc4_copier *host_copier = time_info->host_copier;
745 	struct sof_ipc4_copier *dai_copier = time_info->dai_copier;
746 	struct sof_ipc4_pipeline_registers ppl_reg;
747 	u64 stream_start_position;
748 	u32 dai_sample_size;
749 	u32 ch, node_index;
750 	u32 offset;
751 
752 	if (!host_copier || !dai_copier)
753 		return -EINVAL;
754 
755 	if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID)
756 		return -EINVAL;
757 
758 	node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id);
759 	offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg);
760 	sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg));
761 	if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION)
762 		return -EINVAL;
763 
764 	stream_start_position = ppl_reg.stream_start_offset;
765 	ch = dai_copier->data.out_format.fmt_cfg;
766 	ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch);
767 	dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch;
768 	/* convert offset to sample count */
769 	do_div(stream_start_position, dai_sample_size);
770 	time_info->stream_start_offset = stream_start_position;
771 
772 	return 0;
773 }
774 
sof_ipc4_pcm_delay(struct snd_soc_component * component,struct snd_pcm_substream * substream)775 static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component,
776 					    struct snd_pcm_substream *substream)
777 {
778 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
779 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
780 	struct sof_ipc4_timestamp_info *time_info;
781 	struct sof_ipc4_llp_reading_slot llp;
782 	snd_pcm_uframes_t head_ptr, tail_ptr;
783 	struct snd_sof_pcm_stream *stream;
784 	struct snd_sof_pcm *spcm;
785 	u64 tmp_ptr;
786 	int ret;
787 
788 	spcm = snd_sof_find_spcm_dai(component, rtd);
789 	if (!spcm)
790 		return 0;
791 
792 	stream = &spcm->stream[substream->stream];
793 	time_info = stream->private;
794 	if (!time_info)
795 		return 0;
796 
797 	/*
798 	 * stream_start_offset is updated to memory window by FW based on
799 	 * pipeline statistics and it may be invalid if host query happens before
800 	 * the statistics is complete. And it will not change after the first initiailization.
801 	 */
802 	if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) {
803 		ret = sof_ipc4_get_stream_start_offset(sdev, substream, stream, time_info);
804 		if (ret < 0)
805 			return 0;
806 	}
807 
808 	/*
809 	 * HDaudio links don't support the LLP counter reported by firmware
810 	 * the link position is read directly from hardware registers.
811 	 */
812 	if (!time_info->llp_offset) {
813 		tmp_ptr = snd_sof_pcm_get_stream_position(sdev, component, substream);
814 		if (!tmp_ptr)
815 			return 0;
816 	} else {
817 		sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp));
818 		tmp_ptr = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l;
819 	}
820 
821 	/* In two cases dai dma position is not accurate
822 	 * (1) dai pipeline is started before host pipeline
823 	 * (2) multiple streams mixed into one. Each stream has the same dai dma position
824 	 *
825 	 * Firmware calculates correct stream_start_offset for all cases including above two.
826 	 * Driver subtracts stream_start_offset from dai dma position to get accurate one
827 	 */
828 	tmp_ptr -= time_info->stream_start_offset;
829 
830 	/* Calculate the delay taking into account that both pointer can wrap */
831 	div64_u64_rem(tmp_ptr, substream->runtime->boundary, &tmp_ptr);
832 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
833 		head_ptr = substream->runtime->status->hw_ptr;
834 		tail_ptr = tmp_ptr;
835 	} else {
836 		head_ptr = tmp_ptr;
837 		tail_ptr = substream->runtime->status->hw_ptr;
838 	}
839 
840 	if (head_ptr < tail_ptr)
841 		return substream->runtime->boundary - tail_ptr + head_ptr;
842 
843 	return head_ptr - tail_ptr;
844 }
845 
846 const struct sof_ipc_pcm_ops ipc4_pcm_ops = {
847 	.hw_params = sof_ipc4_pcm_hw_params,
848 	.trigger = sof_ipc4_pcm_trigger,
849 	.hw_free = sof_ipc4_pcm_hw_free,
850 	.dai_link_fixup = sof_ipc4_pcm_dai_link_fixup,
851 	.pcm_setup = sof_ipc4_pcm_setup,
852 	.pcm_free = sof_ipc4_pcm_free,
853 	.delay = sof_ipc4_pcm_delay,
854 	.ipc_first_on_start = true,
855 	.platform_stop_during_hw_free = true,
856 };
857