1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file manages link detection states and receiver states by using various
28 * link protocols. It also provides helper functions to interpret certain
29 * capabilities or status based on the states it manages or retrieve them
30 * directly from connected receivers.
31 */
32
33 #include "link_dpms.h"
34 #include "link_detection.h"
35 #include "link_hwss.h"
36 #include "protocols/link_edp_panel_control.h"
37 #include "protocols/link_ddc.h"
38 #include "protocols/link_hpd.h"
39 #include "protocols/link_dpcd.h"
40 #include "protocols/link_dp_capability.h"
41 #include "protocols/link_dp_dpia.h"
42 #include "protocols/link_dp_phy.h"
43 #include "protocols/link_dp_training.h"
44 #include "accessories/link_dp_trace.h"
45
46 #include "link_enc_cfg.h"
47 #include "dm_helpers.h"
48 #include "clk_mgr.h"
49
50 #define DC_LOGGER_INIT(logger)
51
52 #define LINK_INFO(...) \
53 DC_LOG_HW_HOTPLUG( \
54 __VA_ARGS__)
55 /*
56 * Some receivers fail to train on first try and are good
57 * on subsequent tries. 2 retries should be plenty. If we
58 * don't have a successful training then we don't expect to
59 * ever get one.
60 */
61 #define LINK_TRAINING_MAX_VERIFY_RETRY 2
62
63 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";
64
65 static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
66
get_ddc_transaction_type(enum signal_type sink_signal)67 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
68 {
69 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
70
71 switch (sink_signal) {
72 case SIGNAL_TYPE_DVI_SINGLE_LINK:
73 case SIGNAL_TYPE_DVI_DUAL_LINK:
74 case SIGNAL_TYPE_HDMI_TYPE_A:
75 case SIGNAL_TYPE_LVDS:
76 case SIGNAL_TYPE_RGB:
77 transaction_type = DDC_TRANSACTION_TYPE_I2C;
78 break;
79
80 case SIGNAL_TYPE_DISPLAY_PORT:
81 case SIGNAL_TYPE_EDP:
82 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
83 break;
84
85 case SIGNAL_TYPE_DISPLAY_PORT_MST:
86 /* MST does not use I2COverAux, but there is the
87 * SPECIAL use case for "immediate dwnstrm device
88 * access" (EPR#370830).
89 */
90 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
91 break;
92
93 default:
94 break;
95 }
96
97 return transaction_type;
98 }
99
get_basic_signal_type(struct graphics_object_id encoder,struct graphics_object_id downstream)100 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
101 struct graphics_object_id downstream)
102 {
103 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
104 switch (downstream.id) {
105 case CONNECTOR_ID_SINGLE_LINK_DVII:
106 switch (encoder.id) {
107 case ENCODER_ID_INTERNAL_DAC1:
108 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
109 case ENCODER_ID_INTERNAL_DAC2:
110 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
111 return SIGNAL_TYPE_RGB;
112 default:
113 return SIGNAL_TYPE_DVI_SINGLE_LINK;
114 }
115 break;
116 case CONNECTOR_ID_DUAL_LINK_DVII:
117 {
118 switch (encoder.id) {
119 case ENCODER_ID_INTERNAL_DAC1:
120 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
121 case ENCODER_ID_INTERNAL_DAC2:
122 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
123 return SIGNAL_TYPE_RGB;
124 default:
125 return SIGNAL_TYPE_DVI_DUAL_LINK;
126 }
127 }
128 break;
129 case CONNECTOR_ID_SINGLE_LINK_DVID:
130 return SIGNAL_TYPE_DVI_SINGLE_LINK;
131 case CONNECTOR_ID_DUAL_LINK_DVID:
132 return SIGNAL_TYPE_DVI_DUAL_LINK;
133 case CONNECTOR_ID_VGA:
134 return SIGNAL_TYPE_RGB;
135 case CONNECTOR_ID_HDMI_TYPE_A:
136 return SIGNAL_TYPE_HDMI_TYPE_A;
137 case CONNECTOR_ID_LVDS:
138 return SIGNAL_TYPE_LVDS;
139 case CONNECTOR_ID_DISPLAY_PORT:
140 case CONNECTOR_ID_USBC:
141 return SIGNAL_TYPE_DISPLAY_PORT;
142 case CONNECTOR_ID_EDP:
143 return SIGNAL_TYPE_EDP;
144 default:
145 return SIGNAL_TYPE_NONE;
146 }
147 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
148 switch (downstream.id) {
149 case ENCODER_ID_EXTERNAL_NUTMEG:
150 case ENCODER_ID_EXTERNAL_TRAVIS:
151 return SIGNAL_TYPE_DISPLAY_PORT;
152 default:
153 return SIGNAL_TYPE_NONE;
154 }
155 }
156
157 return SIGNAL_TYPE_NONE;
158 }
159
160 /*
161 * @brief
162 * Detect output sink type
163 */
link_detect_sink_signal_type(struct dc_link * link,enum dc_detect_reason reason)164 static enum signal_type link_detect_sink_signal_type(struct dc_link *link,
165 enum dc_detect_reason reason)
166 {
167 enum signal_type result;
168 struct graphics_object_id enc_id;
169
170 if (link->is_dig_mapping_flexible)
171 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
172 else
173 enc_id = link->link_enc->id;
174 result = get_basic_signal_type(enc_id, link->link_id);
175
176 /* Use basic signal type for link without physical connector. */
177 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
178 return result;
179
180 /* Internal digital encoder will detect only dongles
181 * that require digital signal
182 */
183
184 /* Detection mechanism is different
185 * for different native connectors.
186 * LVDS connector supports only LVDS signal;
187 * PCIE is a bus slot, the actual connector needs to be detected first;
188 * eDP connector supports only eDP signal;
189 * HDMI should check straps for audio
190 */
191
192 /* PCIE detects the actual connector on add-on board */
193 if (link->link_id.id == CONNECTOR_ID_PCIE) {
194 /* ZAZTODO implement PCIE add-on card detection */
195 }
196
197 switch (link->link_id.id) {
198 case CONNECTOR_ID_HDMI_TYPE_A: {
199 /* check audio support:
200 * if native HDMI is not supported, switch to DVI
201 */
202 struct audio_support *aud_support =
203 &link->dc->res_pool->audio_support;
204
205 if (!aud_support->hdmi_audio_native)
206 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
207 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
208 }
209 break;
210 case CONNECTOR_ID_DISPLAY_PORT:
211 case CONNECTOR_ID_USBC: {
212 /* DP HPD short pulse. Passive DP dongle will not
213 * have short pulse
214 */
215 if (reason != DETECT_REASON_HPDRX) {
216 /* Check whether DP signal detected: if not -
217 * we assume signal is DVI; it could be corrected
218 * to HDMI after dongle detection
219 */
220 if (!dm_helpers_is_dp_sink_present(link))
221 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
222 }
223 }
224 break;
225 default:
226 break;
227 }
228
229 return result;
230 }
231
decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,struct audio_support * audio_support)232 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
233 struct audio_support *audio_support)
234 {
235 enum signal_type signal = SIGNAL_TYPE_NONE;
236
237 switch (dongle_type) {
238 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
239 if (audio_support->hdmi_audio_on_dongle)
240 signal = SIGNAL_TYPE_HDMI_TYPE_A;
241 else
242 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
243 break;
244 case DISPLAY_DONGLE_DP_DVI_DONGLE:
245 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
246 break;
247 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
248 if (audio_support->hdmi_audio_native)
249 signal = SIGNAL_TYPE_HDMI_TYPE_A;
250 else
251 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
252 break;
253 default:
254 signal = SIGNAL_TYPE_NONE;
255 break;
256 }
257
258 return signal;
259 }
260
read_scdc_caps(struct ddc_service * ddc_service,struct dc_sink * sink)261 static void read_scdc_caps(struct ddc_service *ddc_service,
262 struct dc_sink *sink)
263 {
264 uint8_t slave_address = HDMI_SCDC_ADDRESS;
265 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;
266
267 link_query_ddc_data(ddc_service, slave_address, &offset,
268 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte,
269 sizeof(sink->scdc_caps.manufacturer_OUI.byte));
270
271 offset = HDMI_SCDC_DEVICE_ID;
272
273 link_query_ddc_data(ddc_service, slave_address, &offset,
274 sizeof(offset), &(sink->scdc_caps.device_id.byte),
275 sizeof(sink->scdc_caps.device_id.byte));
276 }
277
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)278 static bool i2c_read(
279 struct ddc_service *ddc,
280 uint32_t address,
281 uint8_t *buffer,
282 uint32_t len)
283 {
284 uint8_t offs_data = 0;
285 struct i2c_payload payloads[2] = {
286 {
287 .write = true,
288 .address = address,
289 .length = 1,
290 .data = &offs_data },
291 {
292 .write = false,
293 .address = address,
294 .length = len,
295 .data = buffer } };
296
297 struct i2c_command command = {
298 .payloads = payloads,
299 .number_of_payloads = 2,
300 .engine = DDC_I2C_COMMAND_ENGINE,
301 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
302
303 return dm_helpers_submit_i2c(
304 ddc->ctx,
305 ddc->link,
306 &command);
307 }
308
309 enum {
310 DP_SINK_CAP_SIZE =
311 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
312 };
313
query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)314 static void query_dp_dual_mode_adaptor(
315 struct ddc_service *ddc,
316 struct display_sink_capability *sink_cap)
317 {
318 uint8_t i;
319 bool is_valid_hdmi_signature;
320 enum display_dongle_type *dongle = &sink_cap->dongle_type;
321 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
322 bool is_type2_dongle = false;
323 int retry_count = 2;
324 struct dp_hdmi_dongle_signature_data *dongle_signature;
325
326 /* Assume we have no valid DP passive dongle connected */
327 *dongle = DISPLAY_DONGLE_NONE;
328 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
329
330 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
331 if (!i2c_read(
332 ddc,
333 DP_HDMI_DONGLE_ADDRESS,
334 type2_dongle_buf,
335 sizeof(type2_dongle_buf))) {
336 /* Passive HDMI dongles can sometimes fail here without retrying*/
337 while (retry_count > 0) {
338 if (i2c_read(ddc,
339 DP_HDMI_DONGLE_ADDRESS,
340 type2_dongle_buf,
341 sizeof(type2_dongle_buf)))
342 break;
343 retry_count--;
344 }
345 if (retry_count == 0) {
346 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
347 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
348
349 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
350 "DP-DVI passive dongle %dMhz: ",
351 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
352 return;
353 }
354 }
355
356 /* Check if Type 2 dongle.*/
357 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
358 is_type2_dongle = true;
359
360 dongle_signature =
361 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
362
363 is_valid_hdmi_signature = true;
364
365 /* Check EOT */
366 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
367 is_valid_hdmi_signature = false;
368 }
369
370 /* Check signature */
371 for (i = 0; i < sizeof(dongle_signature->id); ++i) {
372 /* If its not the right signature,
373 * skip mismatch in subversion byte.*/
374 if (dongle_signature->id[i] !=
375 dp_hdmi_dongle_signature_str[i] && i != 3) {
376
377 if (is_type2_dongle) {
378 is_valid_hdmi_signature = false;
379 break;
380 }
381
382 }
383 }
384
385 if (is_type2_dongle) {
386 uint32_t max_tmds_clk =
387 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
388
389 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
390
391 if (0 == max_tmds_clk ||
392 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
393 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
394 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
395
396 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
397 sizeof(type2_dongle_buf),
398 "DP-DVI passive dongle %dMhz: ",
399 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
400 } else {
401 if (is_valid_hdmi_signature == true) {
402 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
403
404 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
405 sizeof(type2_dongle_buf),
406 "Type 2 DP-HDMI passive dongle %dMhz: ",
407 max_tmds_clk);
408 } else {
409 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
410
411 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
412 sizeof(type2_dongle_buf),
413 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
414 max_tmds_clk);
415
416 }
417
418 /* Multiply by 1000 to convert to kHz. */
419 sink_cap->max_hdmi_pixel_clock =
420 max_tmds_clk * 1000;
421 }
422 sink_cap->is_dongle_type_one = false;
423
424 } else {
425 if (is_valid_hdmi_signature == true) {
426 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
427
428 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
429 sizeof(type2_dongle_buf),
430 "Type 1 DP-HDMI passive dongle %dMhz: ",
431 sink_cap->max_hdmi_pixel_clock / 1000);
432 } else {
433 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
434
435 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
436 sizeof(type2_dongle_buf),
437 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
438 sink_cap->max_hdmi_pixel_clock / 1000);
439 }
440 sink_cap->is_dongle_type_one = true;
441 }
442
443 return;
444 }
445
dp_passive_dongle_detection(struct ddc_service * ddc,struct display_sink_capability * sink_cap,struct audio_support * audio_support)446 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
447 struct display_sink_capability *sink_cap,
448 struct audio_support *audio_support)
449 {
450 query_dp_dual_mode_adaptor(ddc, sink_cap);
451
452 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
453 audio_support);
454 }
455
link_disconnect_sink(struct dc_link * link)456 static void link_disconnect_sink(struct dc_link *link)
457 {
458 if (link->local_sink) {
459 dc_sink_release(link->local_sink);
460 link->local_sink = NULL;
461 }
462
463 link->dpcd_sink_count = 0;
464 //link->dpcd_caps.dpcd_rev.raw = 0;
465 }
466
link_disconnect_remap(struct dc_sink * prev_sink,struct dc_link * link)467 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
468 {
469 dc_sink_release(link->local_sink);
470 link->local_sink = prev_sink;
471 }
472
query_hdcp_capability(enum signal_type signal,struct dc_link * link)473 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
474 {
475 struct hdcp_protection_message msg22;
476 struct hdcp_protection_message msg14;
477
478 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
479 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
480 memset(link->hdcp_caps.rx_caps.raw, 0,
481 sizeof(link->hdcp_caps.rx_caps.raw));
482
483 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
484 link->ddc->transaction_type ==
485 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
486 link->connector_signal == SIGNAL_TYPE_EDP) {
487 msg22.data = link->hdcp_caps.rx_caps.raw;
488 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
489 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
490 } else {
491 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
492 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
493 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
494 }
495 msg22.version = HDCP_VERSION_22;
496 msg22.link = HDCP_LINK_PRIMARY;
497 msg22.max_retries = 5;
498 dc_process_hdcp_msg(signal, link, &msg22);
499
500 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
501 msg14.data = &link->hdcp_caps.bcaps.raw;
502 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
503 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
504 msg14.version = HDCP_VERSION_14;
505 msg14.link = HDCP_LINK_PRIMARY;
506 msg14.max_retries = 5;
507
508 dc_process_hdcp_msg(signal, link, &msg14);
509 }
510
511 }
read_current_link_settings_on_detect(struct dc_link * link)512 static void read_current_link_settings_on_detect(struct dc_link *link)
513 {
514 union lane_count_set lane_count_set = {0};
515 uint8_t link_bw_set;
516 uint8_t link_rate_set;
517 uint32_t read_dpcd_retry_cnt = 10;
518 enum dc_status status = DC_ERROR_UNEXPECTED;
519 int i;
520 union max_down_spread max_down_spread = {0};
521
522 // Read DPCD 00101h to find out the number of lanes currently set
523 for (i = 0; i < read_dpcd_retry_cnt; i++) {
524 status = core_link_read_dpcd(link,
525 DP_LANE_COUNT_SET,
526 &lane_count_set.raw,
527 sizeof(lane_count_set));
528 /* First DPCD read after VDD ON can fail if the particular board
529 * does not have HPD pin wired correctly. So if DPCD read fails,
530 * which it should never happen, retry a few times. Target worst
531 * case scenario of 80 ms.
532 */
533 if (status == DC_OK) {
534 link->cur_link_settings.lane_count =
535 lane_count_set.bits.LANE_COUNT_SET;
536 break;
537 }
538
539 msleep(8);
540 }
541
542 // Read DPCD 00100h to find if standard link rates are set
543 core_link_read_dpcd(link, DP_LINK_BW_SET,
544 &link_bw_set, sizeof(link_bw_set));
545
546 if (link_bw_set == 0) {
547 if (link->connector_signal == SIGNAL_TYPE_EDP) {
548 /* If standard link rates are not being used,
549 * Read DPCD 00115h to find the edp link rate set used
550 */
551 core_link_read_dpcd(link, DP_LINK_RATE_SET,
552 &link_rate_set, sizeof(link_rate_set));
553
554 // edp_supported_link_rates_count = 0 for DP
555 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
556 link->cur_link_settings.link_rate =
557 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
558 link->cur_link_settings.link_rate_set = link_rate_set;
559 link->cur_link_settings.use_link_rate_set = true;
560 }
561 } else {
562 // Link Rate not found. Seamless boot may not work.
563 ASSERT(false);
564 }
565 } else {
566 link->cur_link_settings.link_rate = link_bw_set;
567 link->cur_link_settings.use_link_rate_set = false;
568 }
569 // Read DPCD 00003h to find the max down spread.
570 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
571 &max_down_spread.raw, sizeof(max_down_spread));
572 link->cur_link_settings.link_spread =
573 max_down_spread.bits.MAX_DOWN_SPREAD ?
574 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
575 }
576
detect_dp(struct dc_link * link,struct display_sink_capability * sink_caps,enum dc_detect_reason reason)577 static bool detect_dp(struct dc_link *link,
578 struct display_sink_capability *sink_caps,
579 enum dc_detect_reason reason)
580 {
581 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
582
583 sink_caps->signal = link_detect_sink_signal_type(link, reason);
584 sink_caps->transaction_type =
585 get_ddc_transaction_type(sink_caps->signal);
586
587 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
588 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
589 if (!detect_dp_sink_caps(link))
590 return false;
591
592 if (is_dp_branch_device(link))
593 /* DP SST branch */
594 link->type = dc_connection_sst_branch;
595 } else {
596 if (link->dc->debug.disable_dp_plus_plus_wa &&
597 link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE)
598 return false;
599
600 /* DP passive dongles */
601 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
602 sink_caps,
603 audio_support);
604 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
605 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
606 link->dpcd_caps.dpcd_rev.raw = 0;
607 }
608
609 return true;
610 }
611
is_same_edid(struct dc_edid * old_edid,struct dc_edid * new_edid)612 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
613 {
614 if (old_edid->length != new_edid->length)
615 return false;
616
617 if (new_edid->length == 0)
618 return false;
619
620 return (memcmp(old_edid->raw_edid,
621 new_edid->raw_edid, new_edid->length) == 0);
622 }
623
wait_for_entering_dp_alt_mode(struct dc_link * link)624 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
625 {
626
627 /**
628 * something is terribly wrong if time out is > 200ms. (5Hz)
629 * 500 microseconds * 400 tries us 200 ms
630 **/
631 unsigned int sleep_time_in_microseconds = 500;
632 unsigned int tries_allowed = 400;
633 bool is_in_alt_mode;
634 unsigned long long enter_timestamp;
635 unsigned long long finish_timestamp;
636 unsigned long long time_taken_in_ns;
637 int tries_taken;
638
639 DC_LOGGER_INIT(link->ctx->logger);
640
641 /**
642 * this function will only exist if we are on dcn21 (is_in_alt_mode is a
643 * function pointer, so checking to see if it is equal to 0 is the same
644 * as checking to see if it is null
645 **/
646 if (!link->link_enc->funcs->is_in_alt_mode)
647 return true;
648
649 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
650 DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
651
652 if (is_in_alt_mode)
653 return true;
654
655 enter_timestamp = dm_get_timestamp(link->ctx);
656
657 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
658 udelay(sleep_time_in_microseconds);
659 /* ask the link if alt mode is enabled, if so return ok */
660 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
661 finish_timestamp = dm_get_timestamp(link->ctx);
662 time_taken_in_ns =
663 dm_get_elapse_time_in_ns(link->ctx,
664 finish_timestamp,
665 enter_timestamp);
666 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
667 div_u64(time_taken_in_ns, 1000000));
668 return true;
669 }
670 }
671 finish_timestamp = dm_get_timestamp(link->ctx);
672 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
673 enter_timestamp);
674 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
675 div_u64(time_taken_in_ns, 1000000));
676 return false;
677 }
678
apply_dpia_mst_dsc_always_on_wa(struct dc_link * link)679 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
680 {
681 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
682 * reports DSC support.
683 */
684 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
685 link->type == dc_connection_mst_branch &&
686 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
687 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
688 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
689 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
690 link->wa_flags.dpia_mst_dsc_always_on = true;
691 }
692
revert_dpia_mst_dsc_always_on_wa(struct dc_link * link)693 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
694 {
695 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
696 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
697 link->wa_flags.dpia_mst_dsc_always_on = false;
698 }
699
discover_dp_mst_topology(struct dc_link * link,enum dc_detect_reason reason)700 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
701 {
702 DC_LOGGER_INIT(link->ctx->logger);
703
704 LINK_INFO("link=%d, mst branch is now Connected\n",
705 link->link_index);
706
707 link->type = dc_connection_mst_branch;
708 apply_dpia_mst_dsc_always_on_wa(link);
709
710 dm_helpers_dp_update_branch_info(link->ctx, link);
711 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
712 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
713 link_disconnect_sink(link);
714 } else {
715 link->type = dc_connection_sst_branch;
716 }
717
718 return link->type == dc_connection_mst_branch;
719 }
720
link_reset_cur_dp_mst_topology(struct dc_link * link)721 bool link_reset_cur_dp_mst_topology(struct dc_link *link)
722 {
723 DC_LOGGER_INIT(link->ctx->logger);
724
725 LINK_INFO("link=%d, mst branch is now Disconnected\n",
726 link->link_index);
727
728 revert_dpia_mst_dsc_always_on_wa(link);
729 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
730 }
731
should_prepare_phy_clocks_for_link_verification(const struct dc * dc,enum dc_detect_reason reason)732 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
733 enum dc_detect_reason reason)
734 {
735 int i;
736 bool can_apply_seamless_boot = false;
737
738 for (i = 0; i < dc->current_state->stream_count; i++) {
739 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
740 can_apply_seamless_boot = true;
741 break;
742 }
743 }
744
745 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
746 }
747
prepare_phy_clocks_for_destructive_link_verification(const struct dc * dc)748 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
749 {
750 dc_z10_restore(dc);
751 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
752 }
753
restore_phy_clocks_for_destructive_link_verification(const struct dc * dc)754 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
755 {
756 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
757 }
758
verify_link_capability_destructive(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)759 static void verify_link_capability_destructive(struct dc_link *link,
760 struct dc_sink *sink,
761 enum dc_detect_reason reason)
762 {
763 bool should_prepare_phy_clocks =
764 should_prepare_phy_clocks_for_link_verification(link->dc, reason);
765
766 if (should_prepare_phy_clocks)
767 prepare_phy_clocks_for_destructive_link_verification(link->dc);
768
769 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
770 struct dc_link_settings known_limit_link_setting =
771 dp_get_max_link_cap(link);
772 link_set_all_streams_dpms_off_for_link(link);
773 dp_verify_link_cap_with_retries(
774 link, &known_limit_link_setting,
775 LINK_TRAINING_MAX_VERIFY_RETRY);
776 } else {
777 ASSERT(0);
778 }
779
780 if (should_prepare_phy_clocks)
781 restore_phy_clocks_for_destructive_link_verification(link->dc);
782 }
783
verify_link_capability_non_destructive(struct dc_link * link)784 static void verify_link_capability_non_destructive(struct dc_link *link)
785 {
786 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
787 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
788 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
789 /* TODO - should we check link encoder's max link caps here?
790 * How do we know which link encoder to check from?
791 */
792 link->verified_link_cap = link->reported_link_cap;
793 else
794 link->verified_link_cap = dp_get_max_link_cap(link);
795 }
796 }
797
should_verify_link_capability_destructively(struct dc_link * link,enum dc_detect_reason reason)798 static bool should_verify_link_capability_destructively(struct dc_link *link,
799 enum dc_detect_reason reason)
800 {
801 bool destrictive = false;
802 struct dc_link_settings max_link_cap;
803 bool is_link_enc_unavailable = link->link_enc &&
804 link->dc->res_pool->funcs->link_encs_assign &&
805 !link_enc_cfg_is_link_enc_avail(
806 link->ctx->dc,
807 link->link_enc->preferred_engine,
808 link);
809
810 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
811 max_link_cap = dp_get_max_link_cap(link);
812 destrictive = true;
813
814 if (link->dc->debug.skip_detection_link_training ||
815 dc_is_embedded_signal(link->local_sink->sink_signal) ||
816 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
817 destrictive = false;
818 } else if (link_dp_get_encoding_format(&max_link_cap) ==
819 DP_8b_10b_ENCODING) {
820 if (link->dpcd_caps.is_mst_capable ||
821 is_link_enc_unavailable) {
822 destrictive = false;
823 }
824 }
825 }
826
827 return destrictive;
828 }
829
verify_link_capability(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)830 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
831 enum dc_detect_reason reason)
832 {
833 if (should_verify_link_capability_destructively(link, reason))
834 verify_link_capability_destructive(link, sink, reason);
835 else
836 verify_link_capability_non_destructive(link);
837 }
838
839 /*
840 * detect_link_and_local_sink() - Detect if a sink is attached to a given link
841 *
842 * link->local_sink is created or destroyed as needed.
843 *
844 * This does not create remote sinks.
845 */
detect_link_and_local_sink(struct dc_link * link,enum dc_detect_reason reason)846 static bool detect_link_and_local_sink(struct dc_link *link,
847 enum dc_detect_reason reason)
848 {
849 struct dc_sink_init_data sink_init_data = { 0 };
850 struct display_sink_capability sink_caps = { 0 };
851 uint32_t i;
852 bool converter_disable_audio = false;
853 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
854 bool same_edid = false;
855 enum dc_edid_status edid_status;
856 struct dc_context *dc_ctx = link->ctx;
857 struct dc *dc = dc_ctx->dc;
858 struct dc_sink *sink = NULL;
859 struct dc_sink *prev_sink = NULL;
860 struct dpcd_caps prev_dpcd_caps;
861 enum dc_connection_type new_connection_type = dc_connection_none;
862 enum dc_connection_type pre_connection_type = link->type;
863 const uint32_t post_oui_delay = 30; // 30ms
864
865 DC_LOGGER_INIT(link->ctx->logger);
866
867 if (dc_is_virtual_signal(link->connector_signal))
868 return false;
869
870 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
871 link->connector_signal == SIGNAL_TYPE_EDP) &&
872 (!link->dc->config.allow_edp_hotplug_detection)) &&
873 link->local_sink) {
874 // need to re-write OUI and brightness in resume case
875 if (link->connector_signal == SIGNAL_TYPE_EDP &&
876 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
877 dpcd_set_source_specific_data(link);
878 msleep(post_oui_delay);
879 set_default_brightness_aux(link);
880 }
881
882 return true;
883 }
884
885 if (!link_detect_connection_type(link, &new_connection_type)) {
886 BREAK_TO_DEBUGGER();
887 return false;
888 }
889
890 prev_sink = link->local_sink;
891 if (prev_sink) {
892 dc_sink_retain(prev_sink);
893 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
894 }
895
896 link_disconnect_sink(link);
897 if (new_connection_type != dc_connection_none) {
898 link->type = new_connection_type;
899 link->link_state_valid = false;
900
901 /* From Disconnected-to-Connected. */
902 switch (link->connector_signal) {
903 case SIGNAL_TYPE_HDMI_TYPE_A: {
904 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
905 if (aud_support->hdmi_audio_native)
906 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
907 else
908 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
909 break;
910 }
911
912 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
913 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
914 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
915 break;
916 }
917
918 case SIGNAL_TYPE_DVI_DUAL_LINK: {
919 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
920 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
921 break;
922 }
923
924 case SIGNAL_TYPE_LVDS: {
925 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
926 sink_caps.signal = SIGNAL_TYPE_LVDS;
927 break;
928 }
929
930 case SIGNAL_TYPE_EDP: {
931 detect_edp_sink_caps(link);
932 read_current_link_settings_on_detect(link);
933
934 /* Disable power sequence on MIPI panel + converter
935 */
936 if (dc->config.enable_mipi_converter_optimization &&
937 dc_ctx->dce_version == DCN_VERSION_3_01 &&
938 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
939 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
940 sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
941 dc->config.edp_no_power_sequencing = true;
942
943 if (!link->dpcd_caps.set_power_state_capable_edp)
944 link->wa_flags.dp_keep_receiver_powered = true;
945 }
946
947 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
948 sink_caps.signal = SIGNAL_TYPE_EDP;
949 break;
950 }
951
952 case SIGNAL_TYPE_DISPLAY_PORT: {
953
954 /* wa HPD high coming too early*/
955 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
956 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
957
958 /* if alt mode times out, return false */
959 if (!wait_for_entering_dp_alt_mode(link))
960 return false;
961 }
962
963 if (!detect_dp(link, &sink_caps, reason)) {
964 link->type = pre_connection_type;
965
966 if (prev_sink)
967 dc_sink_release(prev_sink);
968 return false;
969 }
970
971 /* Active SST downstream branch device unplug*/
972 if (link->type == dc_connection_sst_branch &&
973 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
974 if (prev_sink)
975 /* Downstream unplug */
976 dc_sink_release(prev_sink);
977 return true;
978 }
979
980 /* disable audio for non DP to HDMI active sst converter */
981 if (link->type == dc_connection_sst_branch &&
982 is_dp_active_dongle(link) &&
983 (link->dpcd_caps.dongle_type !=
984 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
985 converter_disable_audio = true;
986
987 /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
988 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
989 link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
990 link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
991 break;
992 }
993
994 default:
995 DC_ERROR("Invalid connector type! signal:%d\n",
996 link->connector_signal);
997 if (prev_sink)
998 dc_sink_release(prev_sink);
999 return false;
1000 } /* switch() */
1001
1002 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1003 link->dpcd_sink_count =
1004 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1005 else
1006 link->dpcd_sink_count = 1;
1007
1008 set_ddc_transaction_type(link->ddc,
1009 sink_caps.transaction_type);
1010
1011 link->aux_mode =
1012 link_is_in_aux_transaction_mode(link->ddc);
1013
1014 sink_init_data.link = link;
1015 sink_init_data.sink_signal = sink_caps.signal;
1016
1017 sink = dc_sink_create(&sink_init_data);
1018 if (!sink) {
1019 DC_ERROR("Failed to create sink!\n");
1020 if (prev_sink)
1021 dc_sink_release(prev_sink);
1022 return false;
1023 }
1024
1025 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1026 sink->converter_disable_audio = converter_disable_audio;
1027
1028 /* dc_sink_create returns a new reference */
1029 link->local_sink = sink;
1030
1031 edid_status = dm_helpers_read_local_edid(link->ctx,
1032 link, sink);
1033
1034 switch (edid_status) {
1035 case EDID_BAD_CHECKSUM:
1036 DC_LOG_ERROR("EDID checksum invalid.\n");
1037 break;
1038 case EDID_PARTIAL_VALID:
1039 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1040 break;
1041 case EDID_NO_RESPONSE:
1042 DC_LOG_ERROR("No EDID read.\n");
1043 /*
1044 * Abort detection for non-DP connectors if we have
1045 * no EDID
1046 *
1047 * DP needs to report as connected if HDP is high
1048 * even if we have no EDID in order to go to
1049 * fail-safe mode
1050 */
1051 if (dc_is_hdmi_signal(link->connector_signal) ||
1052 dc_is_dvi_signal(link->connector_signal)) {
1053 if (prev_sink)
1054 dc_sink_release(prev_sink);
1055
1056 return false;
1057 }
1058
1059 if (link->type == dc_connection_sst_branch &&
1060 link->dpcd_caps.dongle_type ==
1061 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1062 reason == DETECT_REASON_HPDRX) {
1063 /* Abort detection for DP-VGA adapters when EDID
1064 * can't be read and detection reason is VGA-side
1065 * hotplug
1066 */
1067 if (prev_sink)
1068 dc_sink_release(prev_sink);
1069 link_disconnect_sink(link);
1070
1071 return true;
1072 }
1073
1074 break;
1075 default:
1076 break;
1077 }
1078
1079 // Check if edid is the same
1080 if ((prev_sink) &&
1081 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1082 same_edid = is_same_edid(&prev_sink->dc_edid,
1083 &sink->dc_edid);
1084
1085 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1086 link->ctx->dc->debug.hdmi20_disable = true;
1087
1088 if (sink->edid_caps.panel_patch.remove_sink_ext_caps)
1089 link->dpcd_sink_ext_caps.raw = 0;
1090
1091 if (dc_is_hdmi_signal(link->connector_signal))
1092 read_scdc_caps(link->ddc, link->local_sink);
1093
1094 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1095 sink_caps.transaction_type ==
1096 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1097 /*
1098 * TODO debug why certain monitors don't like
1099 * two link trainings
1100 */
1101 query_hdcp_capability(sink->sink_signal, link);
1102 } else {
1103 // If edid is the same, then discard new sink and revert back to original sink
1104 if (same_edid) {
1105 link_disconnect_remap(prev_sink, link);
1106 sink = prev_sink;
1107 prev_sink = NULL;
1108 }
1109 query_hdcp_capability(sink->sink_signal, link);
1110 }
1111
1112 /* HDMI-DVI Dongle */
1113 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1114 !sink->edid_caps.edid_hdmi)
1115 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1116
1117 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1118 dp_trace_init(link);
1119
1120 /* Connectivity log: detection */
1121 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1122 CONN_DATA_DETECT(link,
1123 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1124 DC_EDID_BLOCK_SIZE,
1125 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1126 }
1127
1128 DC_LOG_DETECTION_EDID_PARSER("%s: "
1129 "manufacturer_id = %X, "
1130 "product_id = %X, "
1131 "serial_number = %X, "
1132 "manufacture_week = %d, "
1133 "manufacture_year = %d, "
1134 "display_name = %s, "
1135 "speaker_flag = %d, "
1136 "audio_mode_count = %d\n",
1137 __func__,
1138 sink->edid_caps.manufacturer_id,
1139 sink->edid_caps.product_id,
1140 sink->edid_caps.serial_number,
1141 sink->edid_caps.manufacture_week,
1142 sink->edid_caps.manufacture_year,
1143 sink->edid_caps.display_name,
1144 sink->edid_caps.speaker_flags,
1145 sink->edid_caps.audio_mode_count);
1146
1147 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1148 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1149 "format_code = %d, "
1150 "channel_count = %d, "
1151 "sample_rate = %d, "
1152 "sample_size = %d\n",
1153 __func__,
1154 i,
1155 sink->edid_caps.audio_modes[i].format_code,
1156 sink->edid_caps.audio_modes[i].channel_count,
1157 sink->edid_caps.audio_modes[i].sample_rate,
1158 sink->edid_caps.audio_modes[i].sample_size);
1159 }
1160
1161 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1162 // Init dc_panel_config by HW config
1163 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
1164 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
1165 // Pickup base DM settings
1166 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1167 // Override dc_panel_config if system has specific settings
1168 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
1169
1170 //sink only can use supported link rate table, we are foreced to enable it
1171 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
1172 link->panel_config.ilr.optimize_edp_link_rate = true;
1173 if (edp_is_ilr_optimization_enabled(link))
1174 link->reported_link_cap.link_rate = get_max_link_rate_from_ilr_table(link);
1175 }
1176
1177 } else {
1178 /* From Connected-to-Disconnected. */
1179 link->type = dc_connection_none;
1180 sink_caps.signal = SIGNAL_TYPE_NONE;
1181 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps));
1182 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1183 * is not cleared. If we emulate a DP signal on this connection, it thinks
1184 * the dongle is still there and limits the number of modes we can emulate.
1185 * Clear dongle_max_pix_clk on disconnect to fix this
1186 */
1187 link->dongle_max_pix_clk = 0;
1188
1189 dc_link_clear_dprx_states(link);
1190 dp_trace_reset(link);
1191 }
1192
1193 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1194 link->link_index, sink,
1195 (sink_caps.signal ==
1196 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1197 prev_sink, same_edid);
1198
1199 if (prev_sink)
1200 dc_sink_release(prev_sink);
1201
1202 return true;
1203 }
1204
1205 /*
1206 * link_detect_connection_type() - Determine if there is a sink connected
1207 *
1208 * @type: Returned connection type
1209 * Does not detect downstream devices, such as MST sinks
1210 * or display connected through active dongles
1211 */
link_detect_connection_type(struct dc_link * link,enum dc_connection_type * type)1212 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
1213 {
1214 uint32_t is_hpd_high = 0;
1215
1216 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
1217 *type = dc_connection_single;
1218 return true;
1219 }
1220
1221 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1222 /*in case it is not on*/
1223 if (!link->dc->config.edp_no_power_sequencing)
1224 link->dc->hwss.edp_power_control(link, true);
1225 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1226 }
1227
1228 /* Link may not have physical HPD pin. */
1229 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
1230 if (link->is_hpd_pending || !dpia_query_hpd_status(link))
1231 *type = dc_connection_none;
1232 else
1233 *type = dc_connection_single;
1234
1235 return true;
1236 }
1237
1238
1239 if (!query_hpd_status(link, &is_hpd_high))
1240 goto hpd_gpio_failure;
1241
1242 if (is_hpd_high) {
1243 *type = dc_connection_single;
1244 /* TODO: need to do the actual detection */
1245 } else {
1246 *type = dc_connection_none;
1247 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1248 /* eDP is not connected, power down it */
1249 if (!link->dc->config.edp_no_power_sequencing)
1250 link->dc->hwss.edp_power_control(link, false);
1251 }
1252 }
1253
1254 return true;
1255
1256 hpd_gpio_failure:
1257 return false;
1258 }
1259
link_detect(struct dc_link * link,enum dc_detect_reason reason)1260 bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
1261 {
1262 bool is_local_sink_detect_success;
1263 bool is_delegated_to_mst_top_mgr = false;
1264 enum dc_connection_type pre_link_type = link->type;
1265
1266 DC_LOGGER_INIT(link->ctx->logger);
1267
1268 is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1269
1270 if (is_local_sink_detect_success && link->local_sink)
1271 verify_link_capability(link, link->local_sink, reason);
1272
1273 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__,
1274 link->link_index, is_local_sink_detect_success, pre_link_type, link->type);
1275
1276 if (is_local_sink_detect_success && link->local_sink &&
1277 dc_is_dp_signal(link->local_sink->sink_signal) &&
1278 link->dpcd_caps.is_mst_capable)
1279 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1280
1281 if (is_local_sink_detect_success &&
1282 pre_link_type == dc_connection_mst_branch &&
1283 link->type != dc_connection_mst_branch)
1284 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);
1285
1286 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1287 }
1288
link_clear_dprx_states(struct dc_link * link)1289 void link_clear_dprx_states(struct dc_link *link)
1290 {
1291 memset(&link->dprx_states, 0, sizeof(link->dprx_states));
1292 }
1293
link_is_hdcp14(struct dc_link * link,enum signal_type signal)1294 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal)
1295 {
1296 bool ret = false;
1297
1298 switch (signal) {
1299 case SIGNAL_TYPE_DISPLAY_PORT:
1300 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1301 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
1302 break;
1303 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1304 case SIGNAL_TYPE_DVI_DUAL_LINK:
1305 case SIGNAL_TYPE_HDMI_TYPE_A:
1306 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
1307 * we can poll for bksv but some displays have an issue with this. Since its so rare
1308 * for a display to not be 1.4 capable, this assumtion is ok
1309 */
1310 ret = true;
1311 break;
1312 default:
1313 break;
1314 }
1315 return ret;
1316 }
1317
link_is_hdcp22(struct dc_link * link,enum signal_type signal)1318 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal)
1319 {
1320 bool ret = false;
1321
1322 switch (signal) {
1323 case SIGNAL_TYPE_DISPLAY_PORT:
1324 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1325 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
1326 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
1327 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
1328 break;
1329 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1330 case SIGNAL_TYPE_DVI_DUAL_LINK:
1331 case SIGNAL_TYPE_HDMI_TYPE_A:
1332 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
1333 break;
1334 default:
1335 break;
1336 }
1337
1338 return ret;
1339 }
1340
link_get_status(const struct dc_link * link)1341 const struct dc_link_status *link_get_status(const struct dc_link *link)
1342 {
1343 return &link->link_status;
1344 }
1345
1346
link_add_remote_sink_helper(struct dc_link * dc_link,struct dc_sink * sink)1347 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1348 {
1349 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1350 BREAK_TO_DEBUGGER();
1351 return false;
1352 }
1353
1354 dc_sink_retain(sink);
1355
1356 dc_link->remote_sinks[dc_link->sink_count] = sink;
1357 dc_link->sink_count++;
1358
1359 return true;
1360 }
1361
link_add_remote_sink(struct dc_link * link,const uint8_t * edid,int len,struct dc_sink_init_data * init_data)1362 struct dc_sink *link_add_remote_sink(
1363 struct dc_link *link,
1364 const uint8_t *edid,
1365 int len,
1366 struct dc_sink_init_data *init_data)
1367 {
1368 struct dc_sink *dc_sink;
1369 enum dc_edid_status edid_status;
1370
1371 if (len > DC_MAX_EDID_BUFFER_SIZE) {
1372 dm_error("Max EDID buffer size breached!\n");
1373 return NULL;
1374 }
1375
1376 if (!init_data) {
1377 BREAK_TO_DEBUGGER();
1378 return NULL;
1379 }
1380
1381 if (!init_data->link) {
1382 BREAK_TO_DEBUGGER();
1383 return NULL;
1384 }
1385
1386 dc_sink = dc_sink_create(init_data);
1387
1388 if (!dc_sink)
1389 return NULL;
1390
1391 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1392 dc_sink->dc_edid.length = len;
1393
1394 if (!link_add_remote_sink_helper(
1395 link,
1396 dc_sink))
1397 goto fail_add_sink;
1398
1399 edid_status = dm_helpers_parse_edid_caps(
1400 link,
1401 &dc_sink->dc_edid,
1402 &dc_sink->edid_caps);
1403
1404 /*
1405 * Treat device as no EDID device if EDID
1406 * parsing fails
1407 */
1408 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) {
1409 dc_sink->dc_edid.length = 0;
1410 dm_error("Bad EDID, status%d!\n", edid_status);
1411 }
1412
1413 return dc_sink;
1414
1415 fail_add_sink:
1416 dc_sink_release(dc_sink);
1417 return NULL;
1418 }
1419
link_remove_remote_sink(struct dc_link * link,struct dc_sink * sink)1420 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
1421 {
1422 int i;
1423
1424 if (!link->sink_count) {
1425 BREAK_TO_DEBUGGER();
1426 return;
1427 }
1428
1429 for (i = 0; i < link->sink_count; i++) {
1430 if (link->remote_sinks[i] == sink) {
1431 dc_sink_release(sink);
1432 link->remote_sinks[i] = NULL;
1433
1434 /* shrink array to remove empty place */
1435 while (i < link->sink_count - 1) {
1436 link->remote_sinks[i] = link->remote_sinks[i+1];
1437 i++;
1438 }
1439 link->remote_sinks[i] = NULL;
1440 link->sink_count--;
1441 return;
1442 }
1443 }
1444 }
1445