1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010, 2011 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef _WARM_BOOT_H_ 8 #define _WARM_BOOT_H_ 9 10 #define STRAP_OPT_A_RAM_CODE_SHIFT 4 11 #define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) 12 13 /* Defines the supported operating modes */ 14 enum fuse_operating_mode { 15 MODE_PRODUCTION = 3, 16 MODE_UNDEFINED, 17 }; 18 19 /* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ 20 enum { 21 HASH_LENGTH = 4 22 }; 23 24 /* Defines the storage for a hash value (128 bits) */ 25 struct hash { 26 u32 hash[HASH_LENGTH]; 27 }; 28 29 /* 30 * Defines the code header information for the boot rom. 31 * 32 * The code immediately follows the code header. 33 * 34 * Note that the code header needs to be 16 bytes aligned to preserve 35 * the alignment of relevant data for hash and decryption computations without 36 * requiring extra copies to temporary memory areas. 37 */ 38 struct wb_header { 39 u32 length_insecure; /* length of the code header */ 40 u32 reserved[3]; 41 struct hash hash; /* hash of header+code, starts next field*/ 42 struct hash random_aes_block; /* a data block to aid security. */ 43 u32 length_secure; /* length of the code header */ 44 u32 destination; /* destination address to put the wb code */ 45 u32 entry_point; /* execution address of the wb code */ 46 u32 code_length; /* length of the code */ 47 }; 48 49 /* 50 * The warm boot code needs direct access to these registers since it runs in 51 * SRAM and cannot call other U-Boot code. 52 */ 53 union osc_ctrl_reg { 54 struct { 55 u32 xoe:1; 56 u32 xobp:1; 57 u32 reserved0:2; 58 u32 xofs:6; 59 u32 reserved1:2; 60 u32 xods:5; 61 u32 reserved2:3; 62 u32 oscfi_spare:8; 63 u32 pll_ref_div:2; 64 u32 osc_freq:2; 65 }; 66 u32 word; 67 }; 68 69 union pllx_base_reg { 70 struct { 71 u32 divm:5; 72 u32 reserved0:3; 73 u32 divn:10; 74 u32 reserved1:2; 75 u32 divp:3; 76 u32 reserved2:4; 77 u32 lock:1; 78 u32 reserved3:1; 79 u32 ref_dis:1; 80 u32 enable:1; 81 u32 bypass:1; 82 }; 83 u32 word; 84 }; 85 86 union pllx_misc_reg { 87 struct { 88 u32 vcocon:4; 89 u32 lfcon:4; 90 u32 cpcon:4; 91 u32 lock_sel:6; 92 u32 reserved0:1; 93 u32 lock_enable:1; 94 u32 reserved1:1; 95 u32 dccon:1; 96 u32 pts:2; 97 u32 reserved2:6; 98 u32 out1_div_byp:1; 99 u32 out1_inv_clk:1; 100 }; 101 u32 word; 102 }; 103 104 /* 105 * TODO: This register is not documented in the TRM yet. We could move this 106 * into the EMC and give it a proper interface, but not while it is 107 * undocumented. 108 */ 109 union scratch3_reg { 110 struct { 111 u32 pllx_base_divm:5; 112 u32 pllx_base_divn:10; 113 u32 pllx_base_divp:3; 114 u32 pllx_misc_lfcon:4; 115 u32 pllx_misc_cpcon:4; 116 }; 117 u32 word; 118 }; 119 120 121 /** 122 * Save warmboot memory settings for a later resume 123 * 124 * @return 0 if ok, -1 on error 125 */ 126 int warmboot_save_sdram_params(void); 127 128 int warmboot_prepare_code(u32 seg_address, u32 seg_length); 129 int sign_data_block(u8 *source, u32 length, u8 *signature); 130 void wb_start(void); /* Start of WB assembly code */ 131 void wb_end(void); /* End of WB assembly code */ 132 133 #endif 134