1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale i.MX23/i.MX28 common code
4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 *
8 * Based on code from LTIB:
9 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 */
11
12 #include <common.h>
13 #include <linux/errno.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/mach-imx/dma.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/sys_proto.h>
21 #include <linux/compiler.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
lowlevel_init(void)26 __weak void lowlevel_init(void) {}
27
28 void reset_cpu(ulong ignored) __attribute__((noreturn));
29
reset_cpu(ulong ignored)30 void reset_cpu(ulong ignored)
31 {
32 struct mxs_rtc_regs *rtc_regs =
33 (struct mxs_rtc_regs *)MXS_RTC_BASE;
34 struct mxs_lcdif_regs *lcdif_regs =
35 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
36
37 /*
38 * Shut down the LCD controller as it interferes with BootROM boot mode
39 * pads sampling.
40 */
41 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
42
43 /* Wait 1 uS before doing the actual watchdog reset */
44 writel(1, &rtc_regs->hw_rtc_watchdog);
45 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
46
47 /* Endless loop, reset will exit from here */
48 for (;;)
49 ;
50 }
51
52 /*
53 * This function will craft a jumptable at 0x0 which will redirect interrupt
54 * vectoring to proper location of U-Boot in RAM.
55 *
56 * The structure of the jumptable will be as follows:
57 * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
58 * <destination address> ... for each previous ldr, thus also repeated 8 times
59 *
60 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
61 * offset 0x18 from current value of PC register. Note that PC is already
62 * incremented by 4 when computing the offset, so the effective offset is
63 * actually 0x20, this the associated <destination address>. Loading the PC
64 * register with an address performs a jump to that address.
65 */
mx28_fixup_vt(uint32_t start_addr)66 void mx28_fixup_vt(uint32_t start_addr)
67 {
68 /* ldr pc, [pc, #0x18] */
69 const uint32_t ldr_pc = 0xe59ff018;
70 /* Jumptable location is 0x0 */
71 uint32_t *vt = (uint32_t *)0x0;
72 int i;
73
74 for (i = 0; i < 8; i++) {
75 /* cppcheck-suppress nullPointer */
76 vt[i] = ldr_pc;
77 /* cppcheck-suppress nullPointer */
78 vt[i + 8] = start_addr + (4 * i);
79 }
80 }
81
82 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)83 int arch_misc_init(void)
84 {
85 mx28_fixup_vt(gd->relocaddr);
86 return 0;
87 }
88 #endif
89
arch_cpu_init(void)90 int arch_cpu_init(void)
91 {
92 struct mxs_clkctrl_regs *clkctrl_regs =
93 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
94 extern uint32_t _start;
95
96 mx28_fixup_vt((uint32_t)&_start);
97
98 /*
99 * Enable NAND clock
100 */
101 /* Clear bypass bit */
102 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
103 &clkctrl_regs->hw_clkctrl_clkseq_set);
104
105 /* Set GPMI clock to ref_gpmi / 12 */
106 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
107 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
108
109 udelay(1000);
110
111 /*
112 * Configure GPIO unit
113 */
114 mxs_gpio_init();
115
116 #ifdef CONFIG_APBH_DMA
117 /* Start APBH DMA */
118 mxs_dma_init();
119 #endif
120
121 return 0;
122 }
123
get_cpu_rev(void)124 u32 get_cpu_rev(void)
125 {
126 struct mxs_digctl_regs *digctl_regs =
127 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
128 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
129
130 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
131 case HW_DIGCTL_CHIPID_MX23:
132 switch (rev) {
133 case 0x0:
134 case 0x1:
135 case 0x2:
136 case 0x3:
137 case 0x4:
138 return (MXC_CPU_MX23 << 12) | (rev + 0x10);
139 default:
140 return 0;
141 }
142 case HW_DIGCTL_CHIPID_MX28:
143 switch (rev) {
144 case 0x1:
145 return (MXC_CPU_MX28 << 12) | 0x12;
146 default:
147 return 0;
148 }
149 default:
150 return 0;
151 }
152 }
153
154 #if defined(CONFIG_DISPLAY_CPUINFO)
get_imx_type(u32 imxtype)155 const char *get_imx_type(u32 imxtype)
156 {
157 switch (imxtype) {
158 case MXC_CPU_MX23:
159 return "23";
160 case MXC_CPU_MX28:
161 return "28";
162 default:
163 return "??";
164 }
165 }
166
print_cpuinfo(void)167 int print_cpuinfo(void)
168 {
169 u32 cpurev;
170 struct mxs_spl_data *data = MXS_SPL_DATA;
171
172 cpurev = get_cpu_rev();
173 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
174 get_imx_type((cpurev & 0xFF000) >> 12),
175 (cpurev & 0x000F0) >> 4,
176 (cpurev & 0x0000F) >> 0,
177 mxc_get_clock(MXC_ARM_CLK) / 1000000);
178 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
179 return 0;
180 }
181 #endif
182
do_mx28_showclocks(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])183 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
184 {
185 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
186 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
187 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
188 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
189 return 0;
190 }
191
192 /*
193 * Initializes on-chip ethernet controllers.
194 */
195 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
cpu_eth_init(bd_t * bis)196 int cpu_eth_init(bd_t *bis)
197 {
198 struct mxs_clkctrl_regs *clkctrl_regs =
199 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
200
201 /* Turn on ENET clocks */
202 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
203 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
204
205 /* Set up ENET PLL for 50 MHz */
206 /* Power on ENET PLL */
207 writel(CLKCTRL_PLL2CTRL0_POWER,
208 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
209
210 udelay(10);
211
212 /* Gate on ENET PLL */
213 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
214 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
215
216 /* Enable pad output */
217 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
218
219 return 0;
220 }
221 #endif
222
mx28_adjust_mac(int dev_id,unsigned char * mac)223 __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
224 {
225 mac[0] = 0x00;
226 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
227
228 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
229 mac[5] += 1;
230 }
231
232 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
233
234 #define MXS_OCOTP_MAX_TIMEOUT 1000000
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)235 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
236 {
237 struct mxs_ocotp_regs *ocotp_regs =
238 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
239 uint32_t data;
240
241 memset(mac, 0, 6);
242
243 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
244
245 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
246 MXS_OCOTP_MAX_TIMEOUT)) {
247 printf("MXS FEC: Can't get MAC from OCOTP\n");
248 return;
249 }
250
251 data = readl(&ocotp_regs->hw_ocotp_cust0);
252
253 mac[2] = (data >> 24) & 0xff;
254 mac[3] = (data >> 16) & 0xff;
255 mac[4] = (data >> 8) & 0xff;
256 mac[5] = data & 0xff;
257 mx28_adjust_mac(dev_id, mac);
258 }
259 #else
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)260 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
261 {
262 memset(mac, 0, 6);
263 }
264 #endif
265
mxs_dram_init(void)266 int mxs_dram_init(void)
267 {
268 struct mxs_spl_data *data = MXS_SPL_DATA;
269
270 if (data->mem_dram_size == 0) {
271 printf("MXS:\n"
272 "Error, the RAM size passed up from SPL is 0!\n");
273 hang();
274 }
275
276 gd->ram_size = data->mem_dram_size;
277 return 0;
278 }
279
280 U_BOOT_CMD(
281 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
282 "display clocks",
283 ""
284 );
285