1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34 #define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36 #include <linux/delay.h>
37 #include <linux/iopoll.h>
38 #include <linux/ktime.h>
39 #include <linux/rwsem.h>
40 #include <linux/wait.h>
41 #include <linux/topology.h>
42 #include <linux/dmi.h>
43 #include <linux/units.h>
44 #include <asm/unaligned.h>
45
46 #include <acpi/cppc_acpi.h>
47
48 struct cppc_pcc_data {
49 struct pcc_mbox_chan *pcc_channel;
50 void __iomem *pcc_comm_addr;
51 bool pcc_channel_acquired;
52 unsigned int deadline_us;
53 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
54
55 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
56 bool platform_owns_pcc; /* Ownership of PCC subspace */
57 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
58
59 /*
60 * Lock to provide controlled access to the PCC channel.
61 *
62 * For performance critical usecases(currently cppc_set_perf)
63 * We need to take read_lock and check if channel belongs to OSPM
64 * before reading or writing to PCC subspace
65 * We need to take write_lock before transferring the channel
66 * ownership to the platform via a Doorbell
67 * This allows us to batch a number of CPPC requests if they happen
68 * to originate in about the same time
69 *
70 * For non-performance critical usecases(init)
71 * Take write_lock for all purposes which gives exclusive access
72 */
73 struct rw_semaphore pcc_lock;
74
75 /* Wait queue for CPUs whose requests were batched */
76 wait_queue_head_t pcc_write_wait_q;
77 ktime_t last_cmd_cmpl_time;
78 ktime_t last_mpar_reset;
79 int mpar_count;
80 int refcount;
81 };
82
83 /* Array to represent the PCC channel per subspace ID */
84 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
85 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
86 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
87
88 /*
89 * The cpc_desc structure contains the ACPI register details
90 * as described in the per CPU _CPC tables. The details
91 * include the type of register (e.g. PCC, System IO, FFH etc.)
92 * and destination addresses which lets us READ/WRITE CPU performance
93 * information using the appropriate I/O methods.
94 */
95 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
96
97 /* pcc mapped address + header size + offset within PCC subspace */
98 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
99 0x8 + (offs))
100
101 /* Check if a CPC register is in PCC */
102 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
103 (cpc)->cpc_entry.reg.space_id == \
104 ACPI_ADR_SPACE_PLATFORM_COMM)
105
106 /* Check if a CPC register is in FFH */
107 #define CPC_IN_FFH(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
108 (cpc)->cpc_entry.reg.space_id == \
109 ACPI_ADR_SPACE_FIXED_HARDWARE)
110
111 /* Check if a CPC register is in SystemMemory */
112 #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
113 (cpc)->cpc_entry.reg.space_id == \
114 ACPI_ADR_SPACE_SYSTEM_MEMORY)
115
116 /* Check if a CPC register is in SystemIo */
117 #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
118 (cpc)->cpc_entry.reg.space_id == \
119 ACPI_ADR_SPACE_SYSTEM_IO)
120
121 /* Evaluates to True if reg is a NULL register descriptor */
122 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
123 (reg)->address == 0 && \
124 (reg)->bit_width == 0 && \
125 (reg)->bit_offset == 0 && \
126 (reg)->access_width == 0)
127
128 /* Evaluates to True if an optional cpc field is supported */
129 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
130 !!(cpc)->cpc_entry.int_value : \
131 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
132 /*
133 * Arbitrary Retries in case the remote processor is slow to respond
134 * to PCC commands. Keeping it high enough to cover emulators where
135 * the processors run painfully slow.
136 */
137 #define NUM_RETRIES 500ULL
138
139 #define OVER_16BTS_MASK ~0xFFFFULL
140
141 #define define_one_cppc_ro(_name) \
142 static struct kobj_attribute _name = \
143 __ATTR(_name, 0444, show_##_name, NULL)
144
145 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
146
147 #define show_cppc_data(access_fn, struct_name, member_name) \
148 static ssize_t show_##member_name(struct kobject *kobj, \
149 struct kobj_attribute *attr, char *buf) \
150 { \
151 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
152 struct struct_name st_name = {0}; \
153 int ret; \
154 \
155 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
156 if (ret) \
157 return ret; \
158 \
159 return sysfs_emit(buf, "%llu\n", \
160 (u64)st_name.member_name); \
161 } \
162 define_one_cppc_ro(member_name)
163
164 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
165 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
166 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
167 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
168 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
169 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
170
171 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
172 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
173
174 /* Check for valid access_width, otherwise, fallback to using bit_width */
175 #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
176
177 /* Shift and apply the mask for CPC reads/writes */
178 #define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) & \
179 GENMASK(((reg)->bit_width) - 1, 0))
180 #define MASK_VAL_WRITE(reg, prev_val, val) \
181 ((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \
182 ((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \
183
show_feedback_ctrs(struct kobject * kobj,struct kobj_attribute * attr,char * buf)184 static ssize_t show_feedback_ctrs(struct kobject *kobj,
185 struct kobj_attribute *attr, char *buf)
186 {
187 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
188 struct cppc_perf_fb_ctrs fb_ctrs = {0};
189 int ret;
190
191 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
192 if (ret)
193 return ret;
194
195 return sysfs_emit(buf, "ref:%llu del:%llu\n",
196 fb_ctrs.reference, fb_ctrs.delivered);
197 }
198 define_one_cppc_ro(feedback_ctrs);
199
200 static struct attribute *cppc_attrs[] = {
201 &feedback_ctrs.attr,
202 &reference_perf.attr,
203 &wraparound_time.attr,
204 &highest_perf.attr,
205 &lowest_perf.attr,
206 &lowest_nonlinear_perf.attr,
207 &nominal_perf.attr,
208 &nominal_freq.attr,
209 &lowest_freq.attr,
210 NULL
211 };
212 ATTRIBUTE_GROUPS(cppc);
213
214 static const struct kobj_type cppc_ktype = {
215 .sysfs_ops = &kobj_sysfs_ops,
216 .default_groups = cppc_groups,
217 };
218
check_pcc_chan(int pcc_ss_id,bool chk_err_bit)219 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
220 {
221 int ret, status;
222 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
223 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
224 pcc_ss_data->pcc_comm_addr;
225
226 if (!pcc_ss_data->platform_owns_pcc)
227 return 0;
228
229 /*
230 * Poll PCC status register every 3us(delay_us) for maximum of
231 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
232 */
233 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
234 status & PCC_CMD_COMPLETE_MASK, 3,
235 pcc_ss_data->deadline_us);
236
237 if (likely(!ret)) {
238 pcc_ss_data->platform_owns_pcc = false;
239 if (chk_err_bit && (status & PCC_ERROR_MASK))
240 ret = -EIO;
241 }
242
243 if (unlikely(ret))
244 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
245 pcc_ss_id, ret);
246
247 return ret;
248 }
249
250 /*
251 * This function transfers the ownership of the PCC to the platform
252 * So it must be called while holding write_lock(pcc_lock)
253 */
send_pcc_cmd(int pcc_ss_id,u16 cmd)254 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
255 {
256 int ret = -EIO, i;
257 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
258 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
259 pcc_ss_data->pcc_comm_addr;
260 unsigned int time_delta;
261
262 /*
263 * For CMD_WRITE we know for a fact the caller should have checked
264 * the channel before writing to PCC space
265 */
266 if (cmd == CMD_READ) {
267 /*
268 * If there are pending cpc_writes, then we stole the channel
269 * before write completion, so first send a WRITE command to
270 * platform
271 */
272 if (pcc_ss_data->pending_pcc_write_cmd)
273 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
274
275 ret = check_pcc_chan(pcc_ss_id, false);
276 if (ret)
277 goto end;
278 } else /* CMD_WRITE */
279 pcc_ss_data->pending_pcc_write_cmd = FALSE;
280
281 /*
282 * Handle the Minimum Request Turnaround Time(MRTT)
283 * "The minimum amount of time that OSPM must wait after the completion
284 * of a command before issuing the next command, in microseconds"
285 */
286 if (pcc_ss_data->pcc_mrtt) {
287 time_delta = ktime_us_delta(ktime_get(),
288 pcc_ss_data->last_cmd_cmpl_time);
289 if (pcc_ss_data->pcc_mrtt > time_delta)
290 udelay(pcc_ss_data->pcc_mrtt - time_delta);
291 }
292
293 /*
294 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
295 * "The maximum number of periodic requests that the subspace channel can
296 * support, reported in commands per minute. 0 indicates no limitation."
297 *
298 * This parameter should be ideally zero or large enough so that it can
299 * handle maximum number of requests that all the cores in the system can
300 * collectively generate. If it is not, we will follow the spec and just
301 * not send the request to the platform after hitting the MPAR limit in
302 * any 60s window
303 */
304 if (pcc_ss_data->pcc_mpar) {
305 if (pcc_ss_data->mpar_count == 0) {
306 time_delta = ktime_ms_delta(ktime_get(),
307 pcc_ss_data->last_mpar_reset);
308 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
309 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
310 pcc_ss_id);
311 ret = -EIO;
312 goto end;
313 }
314 pcc_ss_data->last_mpar_reset = ktime_get();
315 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
316 }
317 pcc_ss_data->mpar_count--;
318 }
319
320 /* Write to the shared comm region. */
321 writew_relaxed(cmd, &generic_comm_base->command);
322
323 /* Flip CMD COMPLETE bit */
324 writew_relaxed(0, &generic_comm_base->status);
325
326 pcc_ss_data->platform_owns_pcc = true;
327
328 /* Ring doorbell */
329 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
330 if (ret < 0) {
331 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
332 pcc_ss_id, cmd, ret);
333 goto end;
334 }
335
336 /* wait for completion and check for PCC error bit */
337 ret = check_pcc_chan(pcc_ss_id, true);
338
339 if (pcc_ss_data->pcc_mrtt)
340 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
341
342 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
343 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
344 else
345 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
346
347 end:
348 if (cmd == CMD_WRITE) {
349 if (unlikely(ret)) {
350 for_each_possible_cpu(i) {
351 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
352
353 if (!desc)
354 continue;
355
356 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
357 desc->write_cmd_status = ret;
358 }
359 }
360 pcc_ss_data->pcc_write_cnt++;
361 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
362 }
363
364 return ret;
365 }
366
cppc_chan_tx_done(struct mbox_client * cl,void * msg,int ret)367 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
368 {
369 if (ret < 0)
370 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
371 *(u16 *)msg, ret);
372 else
373 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
374 *(u16 *)msg, ret);
375 }
376
377 static struct mbox_client cppc_mbox_cl = {
378 .tx_done = cppc_chan_tx_done,
379 .knows_txdone = true,
380 };
381
acpi_get_psd(struct cpc_desc * cpc_ptr,acpi_handle handle)382 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
383 {
384 int result = -EFAULT;
385 acpi_status status = AE_OK;
386 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
387 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
388 struct acpi_buffer state = {0, NULL};
389 union acpi_object *psd = NULL;
390 struct acpi_psd_package *pdomain;
391
392 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
393 &buffer, ACPI_TYPE_PACKAGE);
394 if (status == AE_NOT_FOUND) /* _PSD is optional */
395 return 0;
396 if (ACPI_FAILURE(status))
397 return -ENODEV;
398
399 psd = buffer.pointer;
400 if (!psd || psd->package.count != 1) {
401 pr_debug("Invalid _PSD data\n");
402 goto end;
403 }
404
405 pdomain = &(cpc_ptr->domain_info);
406
407 state.length = sizeof(struct acpi_psd_package);
408 state.pointer = pdomain;
409
410 status = acpi_extract_package(&(psd->package.elements[0]),
411 &format, &state);
412 if (ACPI_FAILURE(status)) {
413 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
414 goto end;
415 }
416
417 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
418 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
419 goto end;
420 }
421
422 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
423 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
424 goto end;
425 }
426
427 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
428 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
429 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
430 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
431 goto end;
432 }
433
434 result = 0;
435 end:
436 kfree(buffer.pointer);
437 return result;
438 }
439
acpi_cpc_valid(void)440 bool acpi_cpc_valid(void)
441 {
442 struct cpc_desc *cpc_ptr;
443 int cpu;
444
445 if (acpi_disabled)
446 return false;
447
448 for_each_present_cpu(cpu) {
449 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
450 if (!cpc_ptr)
451 return false;
452 }
453
454 return true;
455 }
456 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
457
cppc_allow_fast_switch(void)458 bool cppc_allow_fast_switch(void)
459 {
460 struct cpc_register_resource *desired_reg;
461 struct cpc_desc *cpc_ptr;
462 int cpu;
463
464 for_each_possible_cpu(cpu) {
465 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
466 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
467 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
468 !CPC_IN_SYSTEM_IO(desired_reg))
469 return false;
470 }
471
472 return true;
473 }
474 EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
475
476 /**
477 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
478 * @cpu: Find all CPUs that share a domain with cpu.
479 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
480 *
481 * Return: 0 for success or negative value for err.
482 */
acpi_get_psd_map(unsigned int cpu,struct cppc_cpudata * cpu_data)483 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
484 {
485 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
486 struct acpi_psd_package *match_pdomain;
487 struct acpi_psd_package *pdomain;
488 int count_target, i;
489
490 /*
491 * Now that we have _PSD data from all CPUs, let's setup P-state
492 * domain info.
493 */
494 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
495 if (!cpc_ptr)
496 return -EFAULT;
497
498 pdomain = &(cpc_ptr->domain_info);
499 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
500 if (pdomain->num_processors <= 1)
501 return 0;
502
503 /* Validate the Domain info */
504 count_target = pdomain->num_processors;
505 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
506 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
507 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
508 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
509 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
510 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
511
512 for_each_possible_cpu(i) {
513 if (i == cpu)
514 continue;
515
516 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
517 if (!match_cpc_ptr)
518 goto err_fault;
519
520 match_pdomain = &(match_cpc_ptr->domain_info);
521 if (match_pdomain->domain != pdomain->domain)
522 continue;
523
524 /* Here i and cpu are in the same domain */
525 if (match_pdomain->num_processors != count_target)
526 goto err_fault;
527
528 if (pdomain->coord_type != match_pdomain->coord_type)
529 goto err_fault;
530
531 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
532 }
533
534 return 0;
535
536 err_fault:
537 /* Assume no coordination on any error parsing domain info */
538 cpumask_clear(cpu_data->shared_cpu_map);
539 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
540 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
541
542 return -EFAULT;
543 }
544 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
545
register_pcc_channel(int pcc_ss_idx)546 static int register_pcc_channel(int pcc_ss_idx)
547 {
548 struct pcc_mbox_chan *pcc_chan;
549 u64 usecs_lat;
550
551 if (pcc_ss_idx >= 0) {
552 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
553
554 if (IS_ERR(pcc_chan)) {
555 pr_err("Failed to find PCC channel for subspace %d\n",
556 pcc_ss_idx);
557 return -ENODEV;
558 }
559
560 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
561 /*
562 * cppc_ss->latency is just a Nominal value. In reality
563 * the remote processor could be much slower to reply.
564 * So add an arbitrary amount of wait on top of Nominal.
565 */
566 usecs_lat = NUM_RETRIES * pcc_chan->latency;
567 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
568 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
569 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
570 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
571
572 pcc_data[pcc_ss_idx]->pcc_comm_addr =
573 acpi_os_ioremap(pcc_chan->shmem_base_addr,
574 pcc_chan->shmem_size);
575 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
576 pr_err("Failed to ioremap PCC comm region mem for %d\n",
577 pcc_ss_idx);
578 return -ENOMEM;
579 }
580
581 /* Set flag so that we don't come here for each CPU. */
582 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
583 }
584
585 return 0;
586 }
587
588 /**
589 * cpc_ffh_supported() - check if FFH reading supported
590 *
591 * Check if the architecture has support for functional fixed hardware
592 * read/write capability.
593 *
594 * Return: true for supported, false for not supported
595 */
cpc_ffh_supported(void)596 bool __weak cpc_ffh_supported(void)
597 {
598 return false;
599 }
600
601 /**
602 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
603 *
604 * Check if the architectural support for CPPC is present even
605 * if the _OSC hasn't prescribed it
606 *
607 * Return: true for supported, false for not supported
608 */
cpc_supported_by_cpu(void)609 bool __weak cpc_supported_by_cpu(void)
610 {
611 return false;
612 }
613
614 /**
615 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
616 * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
617 *
618 * Check and allocate the cppc_pcc_data memory.
619 * In some processor configurations it is possible that same subspace
620 * is shared between multiple CPUs. This is seen especially in CPUs
621 * with hardware multi-threading support.
622 *
623 * Return: 0 for success, errno for failure
624 */
pcc_data_alloc(int pcc_ss_id)625 static int pcc_data_alloc(int pcc_ss_id)
626 {
627 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
628 return -EINVAL;
629
630 if (pcc_data[pcc_ss_id]) {
631 pcc_data[pcc_ss_id]->refcount++;
632 } else {
633 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
634 GFP_KERNEL);
635 if (!pcc_data[pcc_ss_id])
636 return -ENOMEM;
637 pcc_data[pcc_ss_id]->refcount++;
638 }
639
640 return 0;
641 }
642
643 /*
644 * An example CPC table looks like the following.
645 *
646 * Name (_CPC, Package() {
647 * 17, // NumEntries
648 * 1, // Revision
649 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
650 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
651 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
652 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
653 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
654 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
655 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
656 * ...
657 * ...
658 * ...
659 * }
660 * Each Register() encodes how to access that specific register.
661 * e.g. a sample PCC entry has the following encoding:
662 *
663 * Register (
664 * PCC, // AddressSpaceKeyword
665 * 8, // RegisterBitWidth
666 * 8, // RegisterBitOffset
667 * 0x30, // RegisterAddress
668 * 9, // AccessSize (subspace ID)
669 * )
670 */
671
672 #ifndef arch_init_invariance_cppc
arch_init_invariance_cppc(void)673 static inline void arch_init_invariance_cppc(void) { }
674 #endif
675
676 /**
677 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
678 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
679 *
680 * Return: 0 for success or negative value for err.
681 */
acpi_cppc_processor_probe(struct acpi_processor * pr)682 int acpi_cppc_processor_probe(struct acpi_processor *pr)
683 {
684 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
685 union acpi_object *out_obj, *cpc_obj;
686 struct cpc_desc *cpc_ptr;
687 struct cpc_reg *gas_t;
688 struct device *cpu_dev;
689 acpi_handle handle = pr->handle;
690 unsigned int num_ent, i, cpc_rev;
691 int pcc_subspace_id = -1;
692 acpi_status status;
693 int ret = -ENODATA;
694
695 if (!osc_sb_cppc2_support_acked) {
696 pr_debug("CPPC v2 _OSC not acked\n");
697 if (!cpc_supported_by_cpu())
698 return -ENODEV;
699 }
700
701 /* Parse the ACPI _CPC table for this CPU. */
702 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
703 ACPI_TYPE_PACKAGE);
704 if (ACPI_FAILURE(status)) {
705 ret = -ENODEV;
706 goto out_buf_free;
707 }
708
709 out_obj = (union acpi_object *) output.pointer;
710
711 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
712 if (!cpc_ptr) {
713 ret = -ENOMEM;
714 goto out_buf_free;
715 }
716
717 /* First entry is NumEntries. */
718 cpc_obj = &out_obj->package.elements[0];
719 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
720 num_ent = cpc_obj->integer.value;
721 if (num_ent <= 1) {
722 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
723 num_ent, pr->id);
724 goto out_free;
725 }
726 } else {
727 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
728 cpc_obj->type, pr->id);
729 goto out_free;
730 }
731
732 /* Second entry should be revision. */
733 cpc_obj = &out_obj->package.elements[1];
734 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
735 cpc_rev = cpc_obj->integer.value;
736 } else {
737 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
738 cpc_obj->type, pr->id);
739 goto out_free;
740 }
741
742 if (cpc_rev < CPPC_V2_REV) {
743 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
744 pr->id);
745 goto out_free;
746 }
747
748 /*
749 * Disregard _CPC if the number of entries in the return pachage is not
750 * as expected, but support future revisions being proper supersets of
751 * the v3 and only causing more entries to be returned by _CPC.
752 */
753 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
754 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
755 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
756 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
757 num_ent, pr->id);
758 goto out_free;
759 }
760 if (cpc_rev > CPPC_V3_REV) {
761 num_ent = CPPC_V3_NUM_ENT;
762 cpc_rev = CPPC_V3_REV;
763 }
764
765 cpc_ptr->num_entries = num_ent;
766 cpc_ptr->version = cpc_rev;
767
768 /* Iterate through remaining entries in _CPC */
769 for (i = 2; i < num_ent; i++) {
770 cpc_obj = &out_obj->package.elements[i];
771
772 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
773 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
774 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
775 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
776 gas_t = (struct cpc_reg *)
777 cpc_obj->buffer.pointer;
778
779 /*
780 * The PCC Subspace index is encoded inside
781 * the CPC table entries. The same PCC index
782 * will be used for all the PCC entries,
783 * so extract it only once.
784 */
785 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
786 if (pcc_subspace_id < 0) {
787 pcc_subspace_id = gas_t->access_width;
788 if (pcc_data_alloc(pcc_subspace_id))
789 goto out_free;
790 } else if (pcc_subspace_id != gas_t->access_width) {
791 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
792 pr->id);
793 goto out_free;
794 }
795 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
796 if (gas_t->address) {
797 void __iomem *addr;
798 size_t access_width;
799
800 if (!osc_cpc_flexible_adr_space_confirmed) {
801 pr_debug("Flexible address space capability not supported\n");
802 if (!cpc_supported_by_cpu())
803 goto out_free;
804 }
805
806 access_width = GET_BIT_WIDTH(gas_t) / 8;
807 addr = ioremap(gas_t->address, access_width);
808 if (!addr)
809 goto out_free;
810 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
811 }
812 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
813 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
814 /*
815 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
816 * SystemIO doesn't implement 64-bit
817 * registers.
818 */
819 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
820 gas_t->access_width);
821 goto out_free;
822 }
823 if (gas_t->address & OVER_16BTS_MASK) {
824 /* SystemIO registers use 16-bit integer addresses */
825 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
826 gas_t->address);
827 goto out_free;
828 }
829 if (!osc_cpc_flexible_adr_space_confirmed) {
830 pr_debug("Flexible address space capability not supported\n");
831 if (!cpc_supported_by_cpu())
832 goto out_free;
833 }
834 } else {
835 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
836 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
837 pr_debug("Unsupported register type (%d) in _CPC\n",
838 gas_t->space_id);
839 goto out_free;
840 }
841 }
842
843 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
844 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
845 } else {
846 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
847 i, pr->id);
848 goto out_free;
849 }
850 }
851 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
852
853 /*
854 * Initialize the remaining cpc_regs as unsupported.
855 * Example: In case FW exposes CPPC v2, the below loop will initialize
856 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
857 */
858 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
859 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
860 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
861 }
862
863
864 /* Store CPU Logical ID */
865 cpc_ptr->cpu_id = pr->id;
866 raw_spin_lock_init(&cpc_ptr->rmw_lock);
867
868 /* Parse PSD data for this CPU */
869 ret = acpi_get_psd(cpc_ptr, handle);
870 if (ret)
871 goto out_free;
872
873 /* Register PCC channel once for all PCC subspace ID. */
874 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
875 ret = register_pcc_channel(pcc_subspace_id);
876 if (ret)
877 goto out_free;
878
879 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
880 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
881 }
882
883 /* Everything looks okay */
884 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
885
886 /* Add per logical CPU nodes for reading its feedback counters. */
887 cpu_dev = get_cpu_device(pr->id);
888 if (!cpu_dev) {
889 ret = -EINVAL;
890 goto out_free;
891 }
892
893 /* Plug PSD data into this CPU's CPC descriptor. */
894 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
895
896 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
897 "acpi_cppc");
898 if (ret) {
899 per_cpu(cpc_desc_ptr, pr->id) = NULL;
900 kobject_put(&cpc_ptr->kobj);
901 goto out_free;
902 }
903
904 arch_init_invariance_cppc();
905
906 kfree(output.pointer);
907 return 0;
908
909 out_free:
910 /* Free all the mapped sys mem areas for this CPU */
911 for (i = 2; i < cpc_ptr->num_entries; i++) {
912 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
913
914 if (addr)
915 iounmap(addr);
916 }
917 kfree(cpc_ptr);
918
919 out_buf_free:
920 kfree(output.pointer);
921 return ret;
922 }
923 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
924
925 /**
926 * acpi_cppc_processor_exit - Cleanup CPC structs.
927 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
928 *
929 * Return: Void
930 */
acpi_cppc_processor_exit(struct acpi_processor * pr)931 void acpi_cppc_processor_exit(struct acpi_processor *pr)
932 {
933 struct cpc_desc *cpc_ptr;
934 unsigned int i;
935 void __iomem *addr;
936 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
937
938 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
939 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
940 pcc_data[pcc_ss_id]->refcount--;
941 if (!pcc_data[pcc_ss_id]->refcount) {
942 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
943 kfree(pcc_data[pcc_ss_id]);
944 pcc_data[pcc_ss_id] = NULL;
945 }
946 }
947 }
948
949 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
950 if (!cpc_ptr)
951 return;
952
953 /* Free all the mapped sys mem areas for this CPU */
954 for (i = 2; i < cpc_ptr->num_entries; i++) {
955 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
956 if (addr)
957 iounmap(addr);
958 }
959
960 kobject_put(&cpc_ptr->kobj);
961 kfree(cpc_ptr);
962 }
963 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
964
965 /**
966 * cpc_read_ffh() - Read FFH register
967 * @cpunum: CPU number to read
968 * @reg: cppc register information
969 * @val: place holder for return value
970 *
971 * Read bit_width bits from a specified address and bit_offset
972 *
973 * Return: 0 for success and error code
974 */
cpc_read_ffh(int cpunum,struct cpc_reg * reg,u64 * val)975 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
976 {
977 return -ENOTSUPP;
978 }
979
980 /**
981 * cpc_write_ffh() - Write FFH register
982 * @cpunum: CPU number to write
983 * @reg: cppc register information
984 * @val: value to write
985 *
986 * Write value of bit_width bits to a specified address and bit_offset
987 *
988 * Return: 0 for success and error code
989 */
cpc_write_ffh(int cpunum,struct cpc_reg * reg,u64 val)990 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
991 {
992 return -ENOTSUPP;
993 }
994
995 /*
996 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
997 * as fast as possible. We have already mapped the PCC subspace during init, so
998 * we can directly write to it.
999 */
1000
cpc_read(int cpu,struct cpc_register_resource * reg_res,u64 * val)1001 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
1002 {
1003 void __iomem *vaddr = NULL;
1004 int size;
1005 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1006 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1007
1008 if (reg_res->type == ACPI_TYPE_INTEGER) {
1009 *val = reg_res->cpc_entry.int_value;
1010 return 0;
1011 }
1012
1013 *val = 0;
1014 size = GET_BIT_WIDTH(reg);
1015
1016 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1017 u32 val_u32;
1018 acpi_status status;
1019
1020 status = acpi_os_read_port((acpi_io_address)reg->address,
1021 &val_u32, size);
1022 if (ACPI_FAILURE(status)) {
1023 pr_debug("Error: Failed to read SystemIO port %llx\n",
1024 reg->address);
1025 return -EFAULT;
1026 }
1027
1028 *val = val_u32;
1029 return 0;
1030 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1031 /*
1032 * For registers in PCC space, the register size is determined
1033 * by the bit width field; the access size is used to indicate
1034 * the PCC subspace id.
1035 */
1036 size = reg->bit_width;
1037 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1038 }
1039 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1040 vaddr = reg_res->sys_mem_vaddr;
1041 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1042 return cpc_read_ffh(cpu, reg, val);
1043 else
1044 return acpi_os_read_memory((acpi_physical_address)reg->address,
1045 val, size);
1046
1047 switch (size) {
1048 case 8:
1049 *val = readb_relaxed(vaddr);
1050 break;
1051 case 16:
1052 *val = readw_relaxed(vaddr);
1053 break;
1054 case 32:
1055 *val = readl_relaxed(vaddr);
1056 break;
1057 case 64:
1058 *val = readq_relaxed(vaddr);
1059 break;
1060 default:
1061 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1062 pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
1063 size, reg->address);
1064 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1065 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1066 size, pcc_ss_id);
1067 }
1068 return -EFAULT;
1069 }
1070
1071 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1072 *val = MASK_VAL_READ(reg, *val);
1073
1074 return 0;
1075 }
1076
cpc_write(int cpu,struct cpc_register_resource * reg_res,u64 val)1077 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1078 {
1079 int ret_val = 0;
1080 int size;
1081 u64 prev_val;
1082 void __iomem *vaddr = NULL;
1083 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1084 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1085 struct cpc_desc *cpc_desc;
1086 unsigned long flags;
1087
1088 size = GET_BIT_WIDTH(reg);
1089
1090 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1091 acpi_status status;
1092
1093 status = acpi_os_write_port((acpi_io_address)reg->address,
1094 (u32)val, size);
1095 if (ACPI_FAILURE(status)) {
1096 pr_debug("Error: Failed to write SystemIO port %llx\n",
1097 reg->address);
1098 return -EFAULT;
1099 }
1100
1101 return 0;
1102 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1103 /*
1104 * For registers in PCC space, the register size is determined
1105 * by the bit width field; the access size is used to indicate
1106 * the PCC subspace id.
1107 */
1108 size = reg->bit_width;
1109 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1110 }
1111 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1112 vaddr = reg_res->sys_mem_vaddr;
1113 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1114 return cpc_write_ffh(cpu, reg, val);
1115 else
1116 return acpi_os_write_memory((acpi_physical_address)reg->address,
1117 val, size);
1118
1119 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1120 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1121 if (!cpc_desc) {
1122 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1123 return -ENODEV;
1124 }
1125
1126 raw_spin_lock_irqsave(&cpc_desc->rmw_lock, flags);
1127 switch (size) {
1128 case 8:
1129 prev_val = readb_relaxed(vaddr);
1130 break;
1131 case 16:
1132 prev_val = readw_relaxed(vaddr);
1133 break;
1134 case 32:
1135 prev_val = readl_relaxed(vaddr);
1136 break;
1137 case 64:
1138 prev_val = readq_relaxed(vaddr);
1139 break;
1140 default:
1141 raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags);
1142 return -EFAULT;
1143 }
1144 val = MASK_VAL_WRITE(reg, prev_val, val);
1145 val |= prev_val;
1146 }
1147
1148 switch (size) {
1149 case 8:
1150 writeb_relaxed(val, vaddr);
1151 break;
1152 case 16:
1153 writew_relaxed(val, vaddr);
1154 break;
1155 case 32:
1156 writel_relaxed(val, vaddr);
1157 break;
1158 case 64:
1159 writeq_relaxed(val, vaddr);
1160 break;
1161 default:
1162 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1163 pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
1164 size, reg->address);
1165 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1166 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1167 size, pcc_ss_id);
1168 }
1169 ret_val = -EFAULT;
1170 break;
1171 }
1172
1173 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1174 raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags);
1175
1176 return ret_val;
1177 }
1178
cppc_get_perf(int cpunum,enum cppc_regs reg_idx,u64 * perf)1179 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1180 {
1181 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1182 struct cpc_register_resource *reg;
1183
1184 if (!cpc_desc) {
1185 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1186 return -ENODEV;
1187 }
1188
1189 reg = &cpc_desc->cpc_regs[reg_idx];
1190
1191 if (CPC_IN_PCC(reg)) {
1192 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1193 struct cppc_pcc_data *pcc_ss_data = NULL;
1194 int ret = 0;
1195
1196 if (pcc_ss_id < 0)
1197 return -EIO;
1198
1199 pcc_ss_data = pcc_data[pcc_ss_id];
1200
1201 down_write(&pcc_ss_data->pcc_lock);
1202
1203 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1204 cpc_read(cpunum, reg, perf);
1205 else
1206 ret = -EIO;
1207
1208 up_write(&pcc_ss_data->pcc_lock);
1209
1210 return ret;
1211 }
1212
1213 cpc_read(cpunum, reg, perf);
1214
1215 return 0;
1216 }
1217
1218 /**
1219 * cppc_get_desired_perf - Get the desired performance register value.
1220 * @cpunum: CPU from which to get desired performance.
1221 * @desired_perf: Return address.
1222 *
1223 * Return: 0 for success, -EIO otherwise.
1224 */
cppc_get_desired_perf(int cpunum,u64 * desired_perf)1225 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1226 {
1227 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1228 }
1229 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1230
1231 /**
1232 * cppc_get_nominal_perf - Get the nominal performance register value.
1233 * @cpunum: CPU from which to get nominal performance.
1234 * @nominal_perf: Return address.
1235 *
1236 * Return: 0 for success, -EIO otherwise.
1237 */
cppc_get_nominal_perf(int cpunum,u64 * nominal_perf)1238 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1239 {
1240 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1241 }
1242
1243 /**
1244 * cppc_get_highest_perf - Get the highest performance register value.
1245 * @cpunum: CPU from which to get highest performance.
1246 * @highest_perf: Return address.
1247 *
1248 * Return: 0 for success, -EIO otherwise.
1249 */
cppc_get_highest_perf(int cpunum,u64 * highest_perf)1250 int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
1251 {
1252 return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
1253 }
1254 EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
1255
1256 /**
1257 * cppc_get_epp_perf - Get the epp register value.
1258 * @cpunum: CPU from which to get epp preference value.
1259 * @epp_perf: Return address.
1260 *
1261 * Return: 0 for success, -EIO otherwise.
1262 */
cppc_get_epp_perf(int cpunum,u64 * epp_perf)1263 int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
1264 {
1265 return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf);
1266 }
1267 EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
1268
1269 /**
1270 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1271 * @cpunum: CPU from which to get capabilities info.
1272 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1273 *
1274 * Return: 0 for success with perf_caps populated else -ERRNO.
1275 */
cppc_get_perf_caps(int cpunum,struct cppc_perf_caps * perf_caps)1276 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1277 {
1278 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1279 struct cpc_register_resource *highest_reg, *lowest_reg,
1280 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1281 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1282 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1283 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1284 struct cppc_pcc_data *pcc_ss_data = NULL;
1285 int ret = 0, regs_in_pcc = 0;
1286
1287 if (!cpc_desc) {
1288 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1289 return -ENODEV;
1290 }
1291
1292 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1293 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1294 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1295 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1296 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1297 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1298 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1299
1300 /* Are any of the regs PCC ?*/
1301 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1302 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1303 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1304 if (pcc_ss_id < 0) {
1305 pr_debug("Invalid pcc_ss_id\n");
1306 return -ENODEV;
1307 }
1308 pcc_ss_data = pcc_data[pcc_ss_id];
1309 regs_in_pcc = 1;
1310 down_write(&pcc_ss_data->pcc_lock);
1311 /* Ring doorbell once to update PCC subspace */
1312 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1313 ret = -EIO;
1314 goto out_err;
1315 }
1316 }
1317
1318 cpc_read(cpunum, highest_reg, &high);
1319 perf_caps->highest_perf = high;
1320
1321 cpc_read(cpunum, lowest_reg, &low);
1322 perf_caps->lowest_perf = low;
1323
1324 cpc_read(cpunum, nominal_reg, &nom);
1325 perf_caps->nominal_perf = nom;
1326
1327 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1328 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1329 perf_caps->guaranteed_perf = 0;
1330 } else {
1331 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1332 perf_caps->guaranteed_perf = guaranteed;
1333 }
1334
1335 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1336 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1337
1338 if (!high || !low || !nom || !min_nonlinear)
1339 ret = -EFAULT;
1340
1341 /* Read optional lowest and nominal frequencies if present */
1342 if (CPC_SUPPORTED(low_freq_reg))
1343 cpc_read(cpunum, low_freq_reg, &low_f);
1344
1345 if (CPC_SUPPORTED(nom_freq_reg))
1346 cpc_read(cpunum, nom_freq_reg, &nom_f);
1347
1348 perf_caps->lowest_freq = low_f;
1349 perf_caps->nominal_freq = nom_f;
1350
1351
1352 out_err:
1353 if (regs_in_pcc)
1354 up_write(&pcc_ss_data->pcc_lock);
1355 return ret;
1356 }
1357 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1358
1359 /**
1360 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1361 *
1362 * CPPC has flexibility about how CPU performance counters are accessed.
1363 * One of the choices is PCC regions, which can have a high access latency. This
1364 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1365 *
1366 * Return: true if any of the counters are in PCC regions, false otherwise
1367 */
cppc_perf_ctrs_in_pcc(void)1368 bool cppc_perf_ctrs_in_pcc(void)
1369 {
1370 int cpu;
1371
1372 for_each_present_cpu(cpu) {
1373 struct cpc_register_resource *ref_perf_reg;
1374 struct cpc_desc *cpc_desc;
1375
1376 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1377
1378 if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1379 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1380 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
1381 return true;
1382
1383
1384 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1385
1386 /*
1387 * If reference perf register is not supported then we should
1388 * use the nominal perf value
1389 */
1390 if (!CPC_SUPPORTED(ref_perf_reg))
1391 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1392
1393 if (CPC_IN_PCC(ref_perf_reg))
1394 return true;
1395 }
1396
1397 return false;
1398 }
1399 EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1400
1401 /**
1402 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1403 * @cpunum: CPU from which to read counters.
1404 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1405 *
1406 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1407 */
cppc_get_perf_ctrs(int cpunum,struct cppc_perf_fb_ctrs * perf_fb_ctrs)1408 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1409 {
1410 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1411 struct cpc_register_resource *delivered_reg, *reference_reg,
1412 *ref_perf_reg, *ctr_wrap_reg;
1413 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1414 struct cppc_pcc_data *pcc_ss_data = NULL;
1415 u64 delivered, reference, ref_perf, ctr_wrap_time;
1416 int ret = 0, regs_in_pcc = 0;
1417
1418 if (!cpc_desc) {
1419 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1420 return -ENODEV;
1421 }
1422
1423 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1424 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1425 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1426 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1427
1428 /*
1429 * If reference perf register is not supported then we should
1430 * use the nominal perf value
1431 */
1432 if (!CPC_SUPPORTED(ref_perf_reg))
1433 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1434
1435 /* Are any of the regs PCC ?*/
1436 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1437 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1438 if (pcc_ss_id < 0) {
1439 pr_debug("Invalid pcc_ss_id\n");
1440 return -ENODEV;
1441 }
1442 pcc_ss_data = pcc_data[pcc_ss_id];
1443 down_write(&pcc_ss_data->pcc_lock);
1444 regs_in_pcc = 1;
1445 /* Ring doorbell once to update PCC subspace */
1446 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1447 ret = -EIO;
1448 goto out_err;
1449 }
1450 }
1451
1452 cpc_read(cpunum, delivered_reg, &delivered);
1453 cpc_read(cpunum, reference_reg, &reference);
1454 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1455
1456 /*
1457 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1458 * performance counters are assumed to never wrap during the lifetime of
1459 * platform
1460 */
1461 ctr_wrap_time = (u64)(~((u64)0));
1462 if (CPC_SUPPORTED(ctr_wrap_reg))
1463 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1464
1465 if (!delivered || !reference || !ref_perf) {
1466 ret = -EFAULT;
1467 goto out_err;
1468 }
1469
1470 perf_fb_ctrs->delivered = delivered;
1471 perf_fb_ctrs->reference = reference;
1472 perf_fb_ctrs->reference_perf = ref_perf;
1473 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1474 out_err:
1475 if (regs_in_pcc)
1476 up_write(&pcc_ss_data->pcc_lock);
1477 return ret;
1478 }
1479 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1480
1481 /*
1482 * Set Energy Performance Preference Register value through
1483 * Performance Controls Interface
1484 */
cppc_set_epp_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls,bool enable)1485 int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
1486 {
1487 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1488 struct cpc_register_resource *epp_set_reg;
1489 struct cpc_register_resource *auto_sel_reg;
1490 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1491 struct cppc_pcc_data *pcc_ss_data = NULL;
1492 int ret;
1493
1494 if (!cpc_desc) {
1495 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1496 return -ENODEV;
1497 }
1498
1499 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1500 epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
1501
1502 if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
1503 if (pcc_ss_id < 0) {
1504 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
1505 return -ENODEV;
1506 }
1507
1508 if (CPC_SUPPORTED(auto_sel_reg)) {
1509 ret = cpc_write(cpu, auto_sel_reg, enable);
1510 if (ret)
1511 return ret;
1512 }
1513
1514 if (CPC_SUPPORTED(epp_set_reg)) {
1515 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1516 if (ret)
1517 return ret;
1518 }
1519
1520 pcc_ss_data = pcc_data[pcc_ss_id];
1521
1522 down_write(&pcc_ss_data->pcc_lock);
1523 /* after writing CPC, transfer the ownership of PCC to platform */
1524 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1525 up_write(&pcc_ss_data->pcc_lock);
1526 } else if (osc_cpc_flexible_adr_space_confirmed &&
1527 CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) {
1528 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1529 } else {
1530 ret = -ENOTSUPP;
1531 pr_debug("_CPC in PCC and _CPC in FFH are not supported\n");
1532 }
1533
1534 return ret;
1535 }
1536 EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
1537
1538 /**
1539 * cppc_get_auto_sel_caps - Read autonomous selection register.
1540 * @cpunum : CPU from which to read register.
1541 * @perf_caps : struct where autonomous selection register value is updated.
1542 */
cppc_get_auto_sel_caps(int cpunum,struct cppc_perf_caps * perf_caps)1543 int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1544 {
1545 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1546 struct cpc_register_resource *auto_sel_reg;
1547 u64 auto_sel;
1548
1549 if (!cpc_desc) {
1550 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1551 return -ENODEV;
1552 }
1553
1554 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1555
1556 if (!CPC_SUPPORTED(auto_sel_reg))
1557 pr_warn_once("Autonomous mode is not unsupported!\n");
1558
1559 if (CPC_IN_PCC(auto_sel_reg)) {
1560 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1561 struct cppc_pcc_data *pcc_ss_data = NULL;
1562 int ret = 0;
1563
1564 if (pcc_ss_id < 0)
1565 return -ENODEV;
1566
1567 pcc_ss_data = pcc_data[pcc_ss_id];
1568
1569 down_write(&pcc_ss_data->pcc_lock);
1570
1571 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
1572 cpc_read(cpunum, auto_sel_reg, &auto_sel);
1573 perf_caps->auto_sel = (bool)auto_sel;
1574 } else {
1575 ret = -EIO;
1576 }
1577
1578 up_write(&pcc_ss_data->pcc_lock);
1579
1580 return ret;
1581 }
1582
1583 return 0;
1584 }
1585 EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
1586
1587 /**
1588 * cppc_set_auto_sel - Write autonomous selection register.
1589 * @cpu : CPU to which to write register.
1590 * @enable : the desired value of autonomous selection resiter to be updated.
1591 */
cppc_set_auto_sel(int cpu,bool enable)1592 int cppc_set_auto_sel(int cpu, bool enable)
1593 {
1594 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1595 struct cpc_register_resource *auto_sel_reg;
1596 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1597 struct cppc_pcc_data *pcc_ss_data = NULL;
1598 int ret = -EINVAL;
1599
1600 if (!cpc_desc) {
1601 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1602 return -ENODEV;
1603 }
1604
1605 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1606
1607 if (CPC_IN_PCC(auto_sel_reg)) {
1608 if (pcc_ss_id < 0) {
1609 pr_debug("Invalid pcc_ss_id\n");
1610 return -ENODEV;
1611 }
1612
1613 if (CPC_SUPPORTED(auto_sel_reg)) {
1614 ret = cpc_write(cpu, auto_sel_reg, enable);
1615 if (ret)
1616 return ret;
1617 }
1618
1619 pcc_ss_data = pcc_data[pcc_ss_id];
1620
1621 down_write(&pcc_ss_data->pcc_lock);
1622 /* after writing CPC, transfer the ownership of PCC to platform */
1623 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1624 up_write(&pcc_ss_data->pcc_lock);
1625 } else {
1626 ret = -ENOTSUPP;
1627 pr_debug("_CPC in PCC is not supported\n");
1628 }
1629
1630 return ret;
1631 }
1632 EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
1633
1634 /**
1635 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1636 * Continuous Performance Control package EnableRegister field.
1637 * @cpu: CPU for which to enable CPPC register.
1638 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1639 *
1640 * Return: 0 for success, -ERRNO or -EIO otherwise.
1641 */
cppc_set_enable(int cpu,bool enable)1642 int cppc_set_enable(int cpu, bool enable)
1643 {
1644 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1645 struct cpc_register_resource *enable_reg;
1646 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1647 struct cppc_pcc_data *pcc_ss_data = NULL;
1648 int ret = -EINVAL;
1649
1650 if (!cpc_desc) {
1651 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1652 return -EINVAL;
1653 }
1654
1655 enable_reg = &cpc_desc->cpc_regs[ENABLE];
1656
1657 if (CPC_IN_PCC(enable_reg)) {
1658
1659 if (pcc_ss_id < 0)
1660 return -EIO;
1661
1662 ret = cpc_write(cpu, enable_reg, enable);
1663 if (ret)
1664 return ret;
1665
1666 pcc_ss_data = pcc_data[pcc_ss_id];
1667
1668 down_write(&pcc_ss_data->pcc_lock);
1669 /* after writing CPC, transfer the ownership of PCC to platfrom */
1670 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1671 up_write(&pcc_ss_data->pcc_lock);
1672 return ret;
1673 }
1674
1675 return cpc_write(cpu, enable_reg, enable);
1676 }
1677 EXPORT_SYMBOL_GPL(cppc_set_enable);
1678
1679 /**
1680 * cppc_set_perf - Set a CPU's performance controls.
1681 * @cpu: CPU for which to set performance controls.
1682 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1683 *
1684 * Return: 0 for success, -ERRNO otherwise.
1685 */
cppc_set_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls)1686 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1687 {
1688 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1689 struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
1690 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1691 struct cppc_pcc_data *pcc_ss_data = NULL;
1692 int ret = 0;
1693
1694 if (!cpc_desc) {
1695 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1696 return -ENODEV;
1697 }
1698
1699 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1700 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
1701 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
1702
1703 /*
1704 * This is Phase-I where we want to write to CPC registers
1705 * -> We want all CPUs to be able to execute this phase in parallel
1706 *
1707 * Since read_lock can be acquired by multiple CPUs simultaneously we
1708 * achieve that goal here
1709 */
1710 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1711 if (pcc_ss_id < 0) {
1712 pr_debug("Invalid pcc_ss_id\n");
1713 return -ENODEV;
1714 }
1715 pcc_ss_data = pcc_data[pcc_ss_id];
1716 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1717 if (pcc_ss_data->platform_owns_pcc) {
1718 ret = check_pcc_chan(pcc_ss_id, false);
1719 if (ret) {
1720 up_read(&pcc_ss_data->pcc_lock);
1721 return ret;
1722 }
1723 }
1724 /*
1725 * Update the pending_write to make sure a PCC CMD_READ will not
1726 * arrive and steal the channel during the switch to write lock
1727 */
1728 pcc_ss_data->pending_pcc_write_cmd = true;
1729 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1730 cpc_desc->write_cmd_status = 0;
1731 }
1732
1733 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1734
1735 /*
1736 * Only write if min_perf and max_perf not zero. Some drivers pass zero
1737 * value to min and max perf, but they don't mean to set the zero value,
1738 * they just don't want to write to those registers.
1739 */
1740 if (perf_ctrls->min_perf)
1741 cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
1742 if (perf_ctrls->max_perf)
1743 cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
1744
1745 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
1746 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1747 /*
1748 * This is Phase-II where we transfer the ownership of PCC to Platform
1749 *
1750 * Short Summary: Basically if we think of a group of cppc_set_perf
1751 * requests that happened in short overlapping interval. The last CPU to
1752 * come out of Phase-I will enter Phase-II and ring the doorbell.
1753 *
1754 * We have the following requirements for Phase-II:
1755 * 1. We want to execute Phase-II only when there are no CPUs
1756 * currently executing in Phase-I
1757 * 2. Once we start Phase-II we want to avoid all other CPUs from
1758 * entering Phase-I.
1759 * 3. We want only one CPU among all those who went through Phase-I
1760 * to run phase-II
1761 *
1762 * If write_trylock fails to get the lock and doesn't transfer the
1763 * PCC ownership to the platform, then one of the following will be TRUE
1764 * 1. There is at-least one CPU in Phase-I which will later execute
1765 * write_trylock, so the CPUs in Phase-I will be responsible for
1766 * executing the Phase-II.
1767 * 2. Some other CPU has beaten this CPU to successfully execute the
1768 * write_trylock and has already acquired the write_lock. We know for a
1769 * fact it (other CPU acquiring the write_lock) couldn't have happened
1770 * before this CPU's Phase-I as we held the read_lock.
1771 * 3. Some other CPU executing pcc CMD_READ has stolen the
1772 * down_write, in which case, send_pcc_cmd will check for pending
1773 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1774 * So this CPU can be certain that its request will be delivered
1775 * So in all cases, this CPU knows that its request will be delivered
1776 * by another CPU and can return
1777 *
1778 * After getting the down_write we still need to check for
1779 * pending_pcc_write_cmd to take care of the following scenario
1780 * The thread running this code could be scheduled out between
1781 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1782 * could have delivered the request to Platform by triggering the
1783 * doorbell and transferred the ownership of PCC to platform. So this
1784 * avoids triggering an unnecessary doorbell and more importantly before
1785 * triggering the doorbell it makes sure that the PCC channel ownership
1786 * is still with OSPM.
1787 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1788 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1789 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1790 * case during a CMD_READ and if there are pending writes it delivers
1791 * the write command before servicing the read command
1792 */
1793 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1794 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1795 /* Update only if there are pending write commands */
1796 if (pcc_ss_data->pending_pcc_write_cmd)
1797 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1798 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1799 } else
1800 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1801 wait_event(pcc_ss_data->pcc_write_wait_q,
1802 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1803
1804 /* send_pcc_cmd updates the status in case of failure */
1805 ret = cpc_desc->write_cmd_status;
1806 }
1807 return ret;
1808 }
1809 EXPORT_SYMBOL_GPL(cppc_set_perf);
1810
1811 /**
1812 * cppc_get_transition_latency - returns frequency transition latency in ns
1813 * @cpu_num: CPU number for per_cpu().
1814 *
1815 * ACPI CPPC does not explicitly specify how a platform can specify the
1816 * transition latency for performance change requests. The closest we have
1817 * is the timing information from the PCCT tables which provides the info
1818 * on the number and frequency of PCC commands the platform can handle.
1819 *
1820 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
1821 * then assume there is no latency.
1822 */
cppc_get_transition_latency(int cpu_num)1823 unsigned int cppc_get_transition_latency(int cpu_num)
1824 {
1825 /*
1826 * Expected transition latency is based on the PCCT timing values
1827 * Below are definition from ACPI spec:
1828 * pcc_nominal- Expected latency to process a command, in microseconds
1829 * pcc_mpar - The maximum number of periodic requests that the subspace
1830 * channel can support, reported in commands per minute. 0
1831 * indicates no limitation.
1832 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1833 * completion of a command before issuing the next command,
1834 * in microseconds.
1835 */
1836 unsigned int latency_ns = 0;
1837 struct cpc_desc *cpc_desc;
1838 struct cpc_register_resource *desired_reg;
1839 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1840 struct cppc_pcc_data *pcc_ss_data;
1841
1842 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1843 if (!cpc_desc)
1844 return CPUFREQ_ETERNAL;
1845
1846 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1847 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
1848 return 0;
1849 else if (!CPC_IN_PCC(desired_reg))
1850 return CPUFREQ_ETERNAL;
1851
1852 if (pcc_ss_id < 0)
1853 return CPUFREQ_ETERNAL;
1854
1855 pcc_ss_data = pcc_data[pcc_ss_id];
1856 if (pcc_ss_data->pcc_mpar)
1857 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1858
1859 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1860 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1861
1862 return latency_ns;
1863 }
1864 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1865
1866 /* Minimum struct length needed for the DMI processor entry we want */
1867 #define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
1868
1869 /* Offset in the DMI processor structure for the max frequency */
1870 #define DMI_PROCESSOR_MAX_SPEED 0x14
1871
1872 /* Callback function used to retrieve the max frequency from DMI */
cppc_find_dmi_mhz(const struct dmi_header * dm,void * private)1873 static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
1874 {
1875 const u8 *dmi_data = (const u8 *)dm;
1876 u16 *mhz = (u16 *)private;
1877
1878 if (dm->type == DMI_ENTRY_PROCESSOR &&
1879 dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
1880 u16 val = (u16)get_unaligned((const u16 *)
1881 (dmi_data + DMI_PROCESSOR_MAX_SPEED));
1882 *mhz = val > *mhz ? val : *mhz;
1883 }
1884 }
1885
1886 /* Look up the max frequency in DMI */
cppc_get_dmi_max_khz(void)1887 static u64 cppc_get_dmi_max_khz(void)
1888 {
1889 u16 mhz = 0;
1890
1891 dmi_walk(cppc_find_dmi_mhz, &mhz);
1892
1893 /*
1894 * Real stupid fallback value, just in case there is no
1895 * actual value set.
1896 */
1897 mhz = mhz ? mhz : 1;
1898
1899 return KHZ_PER_MHZ * mhz;
1900 }
1901
1902 /*
1903 * If CPPC lowest_freq and nominal_freq registers are exposed then we can
1904 * use them to convert perf to freq and vice versa. The conversion is
1905 * extrapolated as an affine function passing by the 2 points:
1906 * - (Low perf, Low freq)
1907 * - (Nominal perf, Nominal freq)
1908 */
cppc_perf_to_khz(struct cppc_perf_caps * caps,unsigned int perf)1909 unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf)
1910 {
1911 s64 retval, offset = 0;
1912 static u64 max_khz;
1913 u64 mul, div;
1914
1915 if (caps->lowest_freq && caps->nominal_freq) {
1916 /* Avoid special case when nominal_freq is equal to lowest_freq */
1917 if (caps->lowest_freq == caps->nominal_freq) {
1918 mul = caps->nominal_freq;
1919 div = caps->nominal_perf;
1920 } else {
1921 mul = caps->nominal_freq - caps->lowest_freq;
1922 div = caps->nominal_perf - caps->lowest_perf;
1923 }
1924 mul *= KHZ_PER_MHZ;
1925 offset = caps->nominal_freq * KHZ_PER_MHZ -
1926 div64_u64(caps->nominal_perf * mul, div);
1927 } else {
1928 if (!max_khz)
1929 max_khz = cppc_get_dmi_max_khz();
1930 mul = max_khz;
1931 div = caps->highest_perf;
1932 }
1933
1934 retval = offset + div64_u64(perf * mul, div);
1935 if (retval >= 0)
1936 return retval;
1937 return 0;
1938 }
1939 EXPORT_SYMBOL_GPL(cppc_perf_to_khz);
1940
cppc_khz_to_perf(struct cppc_perf_caps * caps,unsigned int freq)1941 unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq)
1942 {
1943 s64 retval, offset = 0;
1944 static u64 max_khz;
1945 u64 mul, div;
1946
1947 if (caps->lowest_freq && caps->nominal_freq) {
1948 /* Avoid special case when nominal_freq is equal to lowest_freq */
1949 if (caps->lowest_freq == caps->nominal_freq) {
1950 mul = caps->nominal_perf;
1951 div = caps->nominal_freq;
1952 } else {
1953 mul = caps->nominal_perf - caps->lowest_perf;
1954 div = caps->nominal_freq - caps->lowest_freq;
1955 }
1956 /*
1957 * We don't need to convert to kHz for computing offset and can
1958 * directly use nominal_freq and lowest_freq as the div64_u64
1959 * will remove the frequency unit.
1960 */
1961 offset = caps->nominal_perf -
1962 div64_u64(caps->nominal_freq * mul, div);
1963 /* But we need it for computing the perf level. */
1964 div *= KHZ_PER_MHZ;
1965 } else {
1966 if (!max_khz)
1967 max_khz = cppc_get_dmi_max_khz();
1968 mul = caps->highest_perf;
1969 div = max_khz;
1970 }
1971
1972 retval = offset + div64_u64(freq * mul, div);
1973 if (retval >= 0)
1974 return retval;
1975 return 0;
1976 }
1977 EXPORT_SYMBOL_GPL(cppc_khz_to_perf);
1978