1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DC_DP_TYPES_H
27 #define DC_DP_TYPES_H
28 
29 #include "os_types.h"
30 #include "dc_ddc_types.h"
31 
32 enum dc_lane_count {
33 	LANE_COUNT_UNKNOWN = 0,
34 	LANE_COUNT_ONE = 1,
35 	LANE_COUNT_TWO = 2,
36 	LANE_COUNT_FOUR = 4,
37 	LANE_COUNT_EIGHT = 8,
38 	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
39 };
40 
41 /* This is actually a reference clock (27MHz) multiplier
42  * 162MBps bandwidth for 1.62GHz like rate,
43  * 270MBps for 2.70GHz,
44  * 324MBps for 3.24Ghz,
45  * 540MBps for 5.40GHz
46  * 810MBps for 8.10GHz
47  */
48 enum dc_link_rate {
49 	LINK_RATE_UNKNOWN = 0,
50 	LINK_RATE_LOW = 0x06,		// Rate_1 (RBR)  - 1.62 Gbps/Lane
51 	LINK_RATE_RATE_2 = 0x08,	// Rate_2        - 2.16 Gbps/Lane
52 	LINK_RATE_RATE_3 = 0x09,	// Rate_3        - 2.43 Gbps/Lane
53 	LINK_RATE_HIGH = 0x0A,		// Rate_4 (HBR)  - 2.70 Gbps/Lane
54 	LINK_RATE_RBR2 = 0x0C,		// Rate_5 (RBR2) - 3.24 Gbps/Lane
55 	LINK_RATE_RATE_6 = 0x10,	// Rate_6        - 4.32 Gbps/Lane
56 	LINK_RATE_HIGH2 = 0x14,		// Rate_7 (HBR2) - 5.40 Gbps/Lane
57 	LINK_RATE_RATE_8 = 0x19,	// Rate_8        - 6.75 Gbps/Lane
58 	LINK_RATE_HIGH3 = 0x1E,		// Rate_9 (HBR3) - 8.10 Gbps/Lane
59 	/* Starting from DP2.0 link rate enum directly represents actual
60 	 * link rate value in unit of 10 mbps
61 	 */
62 	LINK_RATE_UHBR10 = 1000,	// UHBR10 - 10.0 Gbps/Lane
63 	LINK_RATE_UHBR13_5 = 1350,	// UHBR13.5 - 13.5 Gbps/Lane
64 	LINK_RATE_UHBR20 = 2000,	// UHBR20 - 20.0 Gbps/Lane
65 };
66 
67 enum dc_link_spread {
68 	LINK_SPREAD_DISABLED = 0x00,
69 	/* 0.5 % downspread 30 kHz */
70 	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
71 	/* 0.5 % downspread 33 kHz */
72 	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
73 };
74 
75 enum dc_voltage_swing {
76 	VOLTAGE_SWING_LEVEL0 = 0,	/* direct HW translation! */
77 	VOLTAGE_SWING_LEVEL1,
78 	VOLTAGE_SWING_LEVEL2,
79 	VOLTAGE_SWING_LEVEL3,
80 	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
81 };
82 
83 enum dc_pre_emphasis {
84 	PRE_EMPHASIS_DISABLED = 0,	/* direct HW translation! */
85 	PRE_EMPHASIS_LEVEL1,
86 	PRE_EMPHASIS_LEVEL2,
87 	PRE_EMPHASIS_LEVEL3,
88 	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
89 };
90 /* Post Cursor 2 is optional for transmitter
91  * and it applies only to the main link operating at HBR2
92  */
93 enum dc_post_cursor2 {
94 	POST_CURSOR2_DISABLED = 0,	/* direct HW translation! */
95 	POST_CURSOR2_LEVEL1,
96 	POST_CURSOR2_LEVEL2,
97 	POST_CURSOR2_LEVEL3,
98 	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
99 };
100 
101 enum dc_dp_ffe_preset_level {
102 	DP_FFE_PRESET_LEVEL0 = 0,
103 	DP_FFE_PRESET_LEVEL1,
104 	DP_FFE_PRESET_LEVEL2,
105 	DP_FFE_PRESET_LEVEL3,
106 	DP_FFE_PRESET_LEVEL4,
107 	DP_FFE_PRESET_LEVEL5,
108 	DP_FFE_PRESET_LEVEL6,
109 	DP_FFE_PRESET_LEVEL7,
110 	DP_FFE_PRESET_LEVEL8,
111 	DP_FFE_PRESET_LEVEL9,
112 	DP_FFE_PRESET_LEVEL10,
113 	DP_FFE_PRESET_LEVEL11,
114 	DP_FFE_PRESET_LEVEL12,
115 	DP_FFE_PRESET_LEVEL13,
116 	DP_FFE_PRESET_LEVEL14,
117 	DP_FFE_PRESET_LEVEL15,
118 	DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15,
119 };
120 
121 enum dc_dp_training_pattern {
122 	DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
123 	DP_TRAINING_PATTERN_SEQUENCE_2,
124 	DP_TRAINING_PATTERN_SEQUENCE_3,
125 	DP_TRAINING_PATTERN_SEQUENCE_4,
126 	DP_TRAINING_PATTERN_VIDEOIDLE,
127 	DP_128b_132b_TPS1,
128 	DP_128b_132b_TPS2,
129 	DP_128b_132b_TPS2_CDS,
130 };
131 
132 enum dp_link_encoding {
133 	DP_UNKNOWN_ENCODING = 0,
134 	DP_8b_10b_ENCODING = 1,
135 	DP_128b_132b_ENCODING = 2,
136 };
137 
138 enum dp_test_link_rate {
139 	DP_TEST_LINK_RATE_RBR		= 0x06,
140 	DP_TEST_LINK_RATE_HBR		= 0x0A,
141 	DP_TEST_LINK_RATE_HBR2		= 0x14,
142 	DP_TEST_LINK_RATE_HBR3		= 0x1E,
143 	DP_TEST_LINK_RATE_UHBR10	= 0x01,
144 	DP_TEST_LINK_RATE_UHBR20	= 0x02,
145 	DP_TEST_LINK_RATE_UHBR13_5	= 0x03,
146 };
147 
148 struct dc_link_settings {
149 	enum dc_lane_count lane_count;
150 	enum dc_link_rate link_rate;
151 	enum dc_link_spread link_spread;
152 	bool use_link_rate_set;
153 	uint8_t link_rate_set;
154 };
155 
156 union dc_dp_ffe_preset {
157 	struct {
158 		uint8_t level		: 4;
159 		uint8_t reserved	: 1;
160 		uint8_t no_preshoot	: 1;
161 		uint8_t no_deemphasis	: 1;
162 		uint8_t method2		: 1;
163 	} settings;
164 	uint8_t raw;
165 };
166 
167 struct dc_lane_settings {
168 	enum dc_voltage_swing VOLTAGE_SWING;
169 	enum dc_pre_emphasis PRE_EMPHASIS;
170 	enum dc_post_cursor2 POST_CURSOR2;
171 	union dc_dp_ffe_preset FFE_PRESET;
172 };
173 
174 struct dc_link_training_overrides {
175 	enum dc_voltage_swing *voltage_swing;
176 	enum dc_pre_emphasis *pre_emphasis;
177 	enum dc_post_cursor2 *post_cursor2;
178 	union dc_dp_ffe_preset *ffe_preset;
179 
180 	uint16_t *cr_pattern_time;
181 	uint16_t *eq_pattern_time;
182 	enum dc_dp_training_pattern *pattern_for_cr;
183 	enum dc_dp_training_pattern *pattern_for_eq;
184 
185 	enum dc_link_spread *downspread;
186 	bool *alternate_scrambler_reset;
187 	bool *enhanced_framing;
188 	bool *mst_enable;
189 	bool *fec_enable;
190 };
191 
192 union payload_table_update_status {
193 	struct {
194 		uint8_t  VC_PAYLOAD_TABLE_UPDATED:1;
195 		uint8_t  ACT_HANDLED:1;
196 	} bits;
197 	uint8_t  raw;
198 };
199 
200 union dpcd_rev {
201 	struct {
202 		uint8_t MINOR:4;
203 		uint8_t MAJOR:4;
204 	} bits;
205 	uint8_t raw;
206 };
207 
208 union max_lane_count {
209 	struct {
210 		uint8_t MAX_LANE_COUNT:5;
211 		uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
212 		uint8_t TPS3_SUPPORTED:1;
213 		uint8_t ENHANCED_FRAME_CAP:1;
214 	} bits;
215 	uint8_t raw;
216 };
217 
218 union max_down_spread {
219 	struct {
220 		uint8_t MAX_DOWN_SPREAD:1;
221 		uint8_t RESERVED:5;
222 		uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
223 		uint8_t TPS4_SUPPORTED:1;
224 	} bits;
225 	uint8_t raw;
226 };
227 
228 union mstm_cap {
229 	struct {
230 		uint8_t MST_CAP:1;
231 		uint8_t RESERVED:7;
232 	} bits;
233 	uint8_t raw;
234 };
235 
236 union lane_count_set {
237 	struct {
238 		uint8_t LANE_COUNT_SET:5;
239 		uint8_t POST_LT_ADJ_REQ_GRANTED:1;
240 		uint8_t RESERVED:1;
241 		uint8_t ENHANCED_FRAMING:1;
242 	} bits;
243 	uint8_t raw;
244 };
245 
246 union lane_status {
247 	struct {
248 		uint8_t CR_DONE_0:1;
249 		uint8_t CHANNEL_EQ_DONE_0:1;
250 		uint8_t SYMBOL_LOCKED_0:1;
251 		uint8_t RESERVED0:1;
252 		uint8_t CR_DONE_1:1;
253 		uint8_t CHANNEL_EQ_DONE_1:1;
254 		uint8_t SYMBOL_LOCKED_1:1;
255 		uint8_t RESERVED_1:1;
256 	} bits;
257 	uint8_t raw;
258 };
259 
260 union device_service_irq {
261 	struct {
262 		uint8_t REMOTE_CONTROL_CMD_PENDING:1;
263 		uint8_t AUTOMATED_TEST:1;
264 		uint8_t CP_IRQ:1;
265 		uint8_t MCCS_IRQ:1;
266 		uint8_t DOWN_REP_MSG_RDY:1;
267 		uint8_t UP_REQ_MSG_RDY:1;
268 		uint8_t SINK_SPECIFIC:1;
269 		uint8_t reserved:1;
270 	} bits;
271 	uint8_t raw;
272 };
273 
274 union sink_count {
275 	struct {
276 		uint8_t SINK_COUNT:6;
277 		uint8_t CPREADY:1;
278 		uint8_t RESERVED:1;
279 	} bits;
280 	uint8_t raw;
281 };
282 
283 union lane_align_status_updated {
284 	struct {
285 		uint8_t INTERLANE_ALIGN_DONE:1;
286 		uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
287 		uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1;
288 		uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1;
289 		uint8_t LT_FAILED_128b_132b:1;
290 		uint8_t RESERVED:1;
291 		uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
292 		uint8_t LINK_STATUS_UPDATED:1;
293 	} bits;
294 	uint8_t raw;
295 };
296 
297 union lane_adjust {
298 	struct {
299 		uint8_t VOLTAGE_SWING_LANE:2;
300 		uint8_t PRE_EMPHASIS_LANE:2;
301 		uint8_t RESERVED:4;
302 	} bits;
303 	struct {
304 		uint8_t PRESET_VALUE	:4;
305 		uint8_t RESERVED	:4;
306 	} tx_ffe;
307 	uint8_t raw;
308 };
309 
310 union dpcd_training_pattern {
311 	struct {
312 		uint8_t TRAINING_PATTERN_SET:4;
313 		uint8_t RECOVERED_CLOCK_OUT_EN:1;
314 		uint8_t SCRAMBLING_DISABLE:1;
315 		uint8_t SYMBOL_ERROR_COUNT_SEL:2;
316 	} v1_4;
317 	struct {
318 		uint8_t TRAINING_PATTERN_SET:2;
319 		uint8_t LINK_QUAL_PATTERN_SET:2;
320 		uint8_t RESERVED:4;
321 	} v1_3;
322 	uint8_t raw;
323 };
324 
325 /* Training Lane is used to configure downstream DP device's voltage swing
326 and pre-emphasis levels*/
327 /* The DPCD addresses are from 0x103 to 0x106*/
328 union dpcd_training_lane {
329 	struct {
330 		uint8_t VOLTAGE_SWING_SET:2;
331 		uint8_t MAX_SWING_REACHED:1;
332 		uint8_t PRE_EMPHASIS_SET:2;
333 		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
334 		uint8_t RESERVED:2;
335 	} bits;
336 	struct {
337 		uint8_t PRESET_VALUE	:4;
338 		uint8_t RESERVED	:4;
339 	} tx_ffe;
340 	uint8_t raw;
341 };
342 
343 /* TMDS-converter related */
344 union dwnstream_port_caps_byte0 {
345 	struct {
346 		uint8_t DWN_STRM_PORTX_TYPE:3;
347 		uint8_t DWN_STRM_PORTX_HPD:1;
348 		uint8_t RESERVERD:4;
349 	} bits;
350 	uint8_t raw;
351 };
352 
353 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
354 enum dpcd_downstream_port_detailed_type {
355 	DOWN_STREAM_DETAILED_DP = 0,
356 	DOWN_STREAM_DETAILED_VGA,
357 	DOWN_STREAM_DETAILED_DVI,
358 	DOWN_STREAM_DETAILED_HDMI,
359 	DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
360 	DOWN_STREAM_DETAILED_DP_PLUS_PLUS
361 };
362 
363 union dwnstream_port_caps_byte2 {
364 	struct {
365 		uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
366 		uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3;
367 		uint8_t SOURCE_CONTROL_MODE_SUPPORT:1;
368 		uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1;
369 		uint8_t RESERVED:1;
370 	} bits;
371 	uint8_t raw;
372 };
373 
374 union dp_downstream_port_present {
375 	uint8_t byte;
376 	struct {
377 		uint8_t PORT_PRESENT:1;
378 		uint8_t PORT_TYPE:2;
379 		uint8_t FMT_CONVERSION:1;
380 		uint8_t DETAILED_CAPS:1;
381 		uint8_t RESERVED:3;
382 	} fields;
383 };
384 
385 union dwnstream_port_caps_byte3_dvi {
386 	struct {
387 		uint8_t RESERVED1:1;
388 		uint8_t DUAL_LINK:1;
389 		uint8_t HIGH_COLOR_DEPTH:1;
390 		uint8_t RESERVED2:5;
391 	} bits;
392 	uint8_t raw;
393 };
394 
395 union dwnstream_port_caps_byte3_hdmi {
396 	struct {
397 		uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
398 		uint8_t YCrCr422_PASS_THROUGH:1;
399 		uint8_t YCrCr420_PASS_THROUGH:1;
400 		uint8_t YCrCr422_CONVERSION:1;
401 		uint8_t YCrCr420_CONVERSION:1;
402 		uint8_t RESERVED:3;
403 	} bits;
404 	uint8_t raw;
405 };
406 
407 union hdmi_sink_encoded_link_bw_support {
408 	struct {
409 		uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3;
410 		uint8_t RESERVED:5;
411 	} bits;
412 	uint8_t raw;
413 };
414 
415 union hdmi_encoded_link_bw {
416 	struct {
417 		uint8_t FRL_MODE:1; // Bit 0
418 		uint8_t BW_9Gbps:1;
419 		uint8_t BW_18Gbps:1;
420 		uint8_t BW_24Gbps:1;
421 		uint8_t BW_32Gbps:1;
422 		uint8_t BW_40Gbps:1;
423 		uint8_t BW_48Gbps:1;
424 		uint8_t RESERVED:1; // Bit 7
425 	} bits;
426 	uint8_t raw;
427 };
428 
429 /*4-byte structure for detailed capabilities of a down-stream port
430 (DP-to-TMDS converter).*/
431 union dwnstream_portxcaps {
432 	struct {
433 		union dwnstream_port_caps_byte0 byte0;
434 		unsigned char max_TMDS_clock;   //byte1
435 		union dwnstream_port_caps_byte2 byte2;
436 
437 		union {
438 			union dwnstream_port_caps_byte3_dvi byteDVI;
439 			union dwnstream_port_caps_byte3_hdmi byteHDMI;
440 		} byte3;
441 	} bytes;
442 
443 	unsigned char raw[4];
444 };
445 
446 union downstream_port {
447 	struct {
448 		unsigned char   present:1;
449 		unsigned char   type:2;
450 		unsigned char   format_conv:1;
451 		unsigned char   detailed_caps:1;
452 		unsigned char   reserved:3;
453 	} bits;
454 	unsigned char raw;
455 };
456 
457 
458 union sink_status {
459 	struct {
460 		uint8_t RX_PORT0_STATUS:1;
461 		uint8_t RX_PORT1_STATUS:1;
462 		uint8_t RESERVED:6;
463 	} bits;
464 	uint8_t raw;
465 };
466 
467 /*6-byte structure corresponding to 6 registers (200h-205h)
468 read during handling of HPD-IRQ*/
469 union hpd_irq_data {
470 	struct {
471 		union sink_count sink_cnt;/* 200h */
472 		union device_service_irq device_service_irq;/* 201h */
473 		union lane_status lane01_status;/* 202h */
474 		union lane_status lane23_status;/* 203h */
475 		union lane_align_status_updated lane_status_updated;/* 204h */
476 		union sink_status sink_status;
477 	} bytes;
478 	uint8_t raw[6];
479 };
480 
481 union down_stream_port_count {
482 	struct {
483 		uint8_t DOWN_STR_PORT_COUNT:4;
484 		uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
485 		/*Bit 6 = MSA_TIMING_PAR_IGNORED
486 		0 = Sink device requires the MSA timing parameters
487 		1 = Sink device is capable of rendering incoming video
488 		 stream without MSA timing parameters*/
489 		uint8_t IGNORE_MSA_TIMING_PARAM:1;
490 		/*Bit 7 = OUI Support
491 		0 = OUI not supported
492 		1 = OUI supported
493 		(OUI and Device Identification mandatory for DP 1.2)*/
494 		uint8_t OUI_SUPPORT:1;
495 	} bits;
496 	uint8_t raw;
497 };
498 
499 union down_spread_ctrl {
500 	struct {
501 		uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
502 	/* Bits 4 = SPREAD_AMP. Spreading amplitude
503 	0 = Main link signal is not downspread
504 	1 = Main link signal is downspread <= 0.5%
505 	with frequency in the range of 30kHz ~ 33kHz*/
506 		uint8_t SPREAD_AMP:1;
507 		uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/
508 	/* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE.
509 	0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default)
510 	1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */
511 		uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1;
512 	/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
513 	0 = Source device will send valid data for the MSA Timing Params
514 	1 = Source device may send invalid data for these MSA Timing Params*/
515 		uint8_t IGNORE_MSA_TIMING_PARAM:1;
516 	} bits;
517 	uint8_t raw;
518 };
519 
520 union dpcd_edp_config {
521 	struct {
522 		uint8_t PANEL_MODE_EDP:1;
523 		uint8_t FRAMING_CHANGE_ENABLE:1;
524 		uint8_t RESERVED:5;
525 		uint8_t PANEL_SELF_TEST_ENABLE:1;
526 	} bits;
527 	uint8_t raw;
528 };
529 
530 struct dp_device_vendor_id {
531 	uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
532 	uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
533 };
534 
535 struct dp_sink_hw_fw_revision {
536 	uint8_t ieee_hw_rev;
537 	uint8_t ieee_fw_rev[2];
538 };
539 
540 struct dpcd_vendor_signature {
541 	bool is_valid;
542 
543 	union dpcd_ieee_vendor_signature {
544 		struct {
545 			uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
546 			uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
547 			uint8_t ieee_hw_rev;
548 			uint8_t ieee_fw_rev[2];
549 		};
550 		uint8_t raw[12];
551 	} data;
552 };
553 
554 struct dpcd_amd_signature {
555 	uint8_t AMD_IEEE_TxSignature_byte1;
556 	uint8_t AMD_IEEE_TxSignature_byte2;
557 	uint8_t AMD_IEEE_TxSignature_byte3;
558 };
559 
560 struct dpcd_amd_device_id {
561 	uint8_t device_id_byte1;
562 	uint8_t device_id_byte2;
563 	uint8_t zero[4];
564 	uint8_t dce_version;
565 	uint8_t dal_version_byte1;
566 	uint8_t dal_version_byte2;
567 };
568 
569 struct target_luminance_value {
570 	uint8_t byte0;
571 	uint8_t byte1;
572 	uint8_t byte2;
573 };
574 
575 struct dpcd_source_backlight_set {
576 	struct  {
577 		uint8_t byte0;
578 		uint8_t byte1;
579 		uint8_t byte2;
580 		uint8_t byte3;
581 	} backlight_level_millinits;
582 
583 	struct  {
584 		uint8_t byte0;
585 		uint8_t byte1;
586 	} backlight_transition_time_ms;
587 };
588 
589 union dpcd_source_backlight_get {
590 	struct {
591 		uint32_t backlight_millinits_peak; /* 326h */
592 		uint32_t backlight_millinits_avg; /* 32Ah */
593 	} bytes;
594 	uint8_t raw[8];
595 };
596 
597 /*DPCD register of DP receiver capability field bits-*/
598 union edp_configuration_cap {
599 	struct {
600 		uint8_t ALT_SCRAMBLER_RESET:1;
601 		uint8_t FRAMING_CHANGE:1;
602 		uint8_t RESERVED:1;
603 		uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
604 		uint8_t RESERVED2:4;
605 	} bits;
606 	uint8_t raw;
607 };
608 
609 union dprx_feature {
610 	struct {
611 		uint8_t GTC_CAP:1;                             // bit 0: DP 1.3+
612 		uint8_t SST_SPLIT_SDP_CAP:1;                   // bit 1: DP 1.4
613 		uint8_t AV_SYNC_CAP:1;                         // bit 2: DP 1.3+
614 		uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1;       // bit 3: DP 1.3+
615 		uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1;          // bit 4: DP 1.4
616 		uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
617 		uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1;           // bit 6: DP 1.4
618 		uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1;  // bit 7: DP 1.4
619 	} bits;
620 	uint8_t raw;
621 };
622 
623 union training_aux_rd_interval {
624 	struct {
625 		uint8_t TRAINIG_AUX_RD_INTERVAL:7;
626 		uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
627 	} bits;
628 	uint8_t raw;
629 };
630 
631 /* Automated test structures */
632 union test_request {
633 	struct {
634 	uint8_t LINK_TRAINING                :1;
635 	uint8_t LINK_TEST_PATTRN             :1;
636 	uint8_t EDID_READ                    :1;
637 	uint8_t PHY_TEST_PATTERN             :1;
638 	uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2;
639 	uint8_t AUDIO_TEST_PATTERN           :1;
640 	uint8_t TEST_AUDIO_DISABLED_VIDEO    :1;
641 	} bits;
642 	uint8_t raw;
643 };
644 
645 union test_response {
646 	struct {
647 		uint8_t ACK         :1;
648 		uint8_t NO_ACK      :1;
649 		uint8_t EDID_CHECKSUM_WRITE:1;
650 		uint8_t RESERVED    :5;
651 	} bits;
652 	uint8_t raw;
653 };
654 
655 union phy_test_pattern {
656 	struct {
657 		/* This field is 7 bits for DP2.0 */
658 		uint8_t PATTERN     :7;
659 		uint8_t RESERVED    :1;
660 	} bits;
661 	uint8_t raw;
662 };
663 
664 /* States of Compliance Test Specification (CTS DP1.2). */
665 union compliance_test_state {
666 	struct {
667 		unsigned char STEREO_3D_RUNNING        : 1;
668 		unsigned char RESERVED                 : 7;
669 	} bits;
670 	unsigned char raw;
671 };
672 
673 union link_test_pattern {
674 	struct {
675 		/* dpcd_link_test_patterns */
676 		unsigned char PATTERN :2;
677 		unsigned char RESERVED:6;
678 	} bits;
679 	unsigned char raw;
680 };
681 
682 union test_misc {
683 	struct dpcd_test_misc_bits {
684 		unsigned char SYNC_CLOCK  :1;
685 		/* dpcd_test_color_format */
686 		unsigned char CLR_FORMAT  :2;
687 		/* dpcd_test_dyn_range */
688 		unsigned char DYN_RANGE   :1;
689 		unsigned char YCBCR_COEFS :1;
690 		/* dpcd_test_bit_depth */
691 		unsigned char BPC         :3;
692 	} bits;
693 	unsigned char raw;
694 };
695 
696 union audio_test_mode {
697 	struct {
698 		unsigned char sampling_rate   :4;
699 		unsigned char channel_count   :4;
700 	} bits;
701 	unsigned char raw;
702 };
703 
704 union audio_test_pattern_period {
705 	struct {
706 		unsigned char pattern_period   :4;
707 		unsigned char reserved         :4;
708 	} bits;
709 	unsigned char raw;
710 };
711 
712 struct audio_test_pattern_type {
713 	unsigned char value;
714 };
715 
716 struct dp_audio_test_data_flags {
717 	uint8_t test_requested  :1;
718 	uint8_t disable_video   :1;
719 };
720 
721 struct dp_audio_test_data {
722 
723 	struct dp_audio_test_data_flags flags;
724 	uint8_t sampling_rate;
725 	uint8_t channel_count;
726 	uint8_t pattern_type;
727 	uint8_t pattern_period[8];
728 };
729 
730 /* FEC capability DPCD register field bits-*/
731 union dpcd_fec_capability {
732 	struct {
733 		uint8_t FEC_CAPABLE:1;
734 		uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
735 		uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
736 		uint8_t BIT_ERROR_COUNT_CAPABLE:1;
737 		uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1;
738 		uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1;
739 		uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1;
740 		uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1;
741 	} bits;
742 	uint8_t raw;
743 };
744 
745 /* DSC capability DPCD register field bits-*/
746 struct dpcd_dsc_support {
747 	uint8_t DSC_SUPPORT		:1;
748 	uint8_t DSC_PASSTHROUGH_SUPPORT	:1;
749 	uint8_t RESERVED		:6;
750 };
751 
752 struct dpcd_dsc_algorithm_revision {
753 	uint8_t DSC_VERSION_MAJOR	:4;
754 	uint8_t DSC_VERSION_MINOR	:4;
755 };
756 
757 struct dpcd_dsc_rc_buffer_block_size {
758 	uint8_t RC_BLOCK_BUFFER_SIZE	:2;
759 	uint8_t RESERVED		:6;
760 };
761 
762 struct dpcd_dsc_slice_capability1 {
763 	uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE	:1;
764 	uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
765 	uint8_t RESERVED				:1;
766 	uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
767 	uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
768 	uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
769 	uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
770 	uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
771 };
772 
773 struct dpcd_dsc_line_buffer_bit_depth {
774 	uint8_t LINE_BUFFER_BIT_DEPTH	:4;
775 	uint8_t RESERVED		:4;
776 };
777 
778 struct dpcd_dsc_block_prediction_support {
779 	uint8_t BLOCK_PREDICTION_SUPPORT:1;
780 	uint8_t RESERVED		:7;
781 };
782 
783 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
784 	uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW	:7;
785 	uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH	:7;
786 	uint8_t RESERVED							:2;
787 };
788 
789 struct dpcd_dsc_decoder_color_format_capabilities {
790 	uint8_t RGB_SUPPORT			:1;
791 	uint8_t Y_CB_CR_444_SUPPORT		:1;
792 	uint8_t Y_CB_CR_SIMPLE_422_SUPPORT	:1;
793 	uint8_t Y_CB_CR_NATIVE_422_SUPPORT	:1;
794 	uint8_t Y_CB_CR_NATIVE_420_SUPPORT	:1;
795 	uint8_t RESERVED			:3;
796 };
797 
798 struct dpcd_dsc_decoder_color_depth_capabilities {
799 	uint8_t RESERVED0			:1;
800 	uint8_t EIGHT_BITS_PER_COLOR_SUPPORT	:1;
801 	uint8_t TEN_BITS_PER_COLOR_SUPPORT	:1;
802 	uint8_t TWELVE_BITS_PER_COLOR_SUPPORT	:1;
803 	uint8_t RESERVED1			:4;
804 };
805 
806 struct dpcd_peak_dsc_throughput_dsc_sink {
807 	uint8_t THROUGHPUT_MODE_0:4;
808 	uint8_t THROUGHPUT_MODE_1:4;
809 };
810 
811 struct dpcd_dsc_slice_capabilities_2 {
812 	uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE	:1;
813 	uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE	:1;
814 	uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE	:1;
815 	uint8_t RESERVED				:5;
816 };
817 
818 struct dpcd_bits_per_pixel_increment{
819 	uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED	:3;
820 	uint8_t RESERVED				:5;
821 };
822 union dpcd_dsc_basic_capabilities {
823 	struct {
824 		struct dpcd_dsc_support dsc_support;
825 		struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
826 		struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
827 		uint8_t dsc_rc_buffer_size;
828 		struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
829 		struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
830 		struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
831 		struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
832 		struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
833 		struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
834 		struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
835 		uint8_t dsc_maximum_slice_width;
836 		struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
837 		uint8_t reserved;
838 		struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
839 	} fields;
840 	uint8_t raw[16];
841 };
842 
843 union dpcd_dsc_branch_decoder_capabilities {
844 	struct {
845 		uint8_t BRANCH_OVERALL_THROUGHPUT_0;
846 		uint8_t BRANCH_OVERALL_THROUGHPUT_1;
847 		uint8_t BRANCH_MAX_LINE_WIDTH;
848 	} fields;
849 	uint8_t raw[3];
850 };
851 
852 struct dpcd_dsc_capabilities {
853 	union dpcd_dsc_basic_capabilities dsc_basic_caps;
854 	union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps;
855 };
856 
857 /* These parameters are from PSR capabilities reported by Sink DPCD */
858 struct psr_caps {
859 	unsigned char psr_version;
860 	unsigned int psr_rfb_setup_time;
861 	bool psr_exit_link_training_required;
862 	unsigned char edp_revision;
863 	unsigned char support_ver;
864 	bool su_granularity_required;
865 	bool y_coordinate_required;
866 	uint8_t su_y_granularity;
867 	bool alpm_cap;
868 	bool standby_support;
869 	uint8_t rate_control_caps;
870 	unsigned int psr_power_opt_flag;
871 };
872 
873 union dpcd_dprx_feature_enumeration_list_cont_1 {
874 	struct {
875 		uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1;
876 		uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1;
877 		uint8_t RESERVED0: 2;
878 		uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1;
879 		uint8_t RESERVED1: 3;
880 	} bits;
881 	uint8_t raw;
882 };
883 
884 struct adaptive_sync_caps {
885 	union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps;
886 };
887 
888 /* Length of router topology ID read from DPCD in bytes. */
889 #define DPCD_USB4_TOPOLOGY_ID_LEN 5
890 
891 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */
892 union dp_tun_cap_support {
893 	struct {
894 		uint8_t dp_tunneling :1;
895 		uint8_t rsvd :5;
896 		uint8_t panel_replay_tun_opt :1;
897 		uint8_t dpia_bw_alloc :1;
898 	} bits;
899 	uint8_t raw;
900 };
901 
902 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */
903 union dpia_info {
904 	struct {
905 		uint8_t dpia_num :5;
906 		uint8_t rsvd :3;
907 	} bits;
908 	uint8_t raw;
909 };
910 
911 /* DP Tunneling over USB4 */
912 struct dpcd_usb4_dp_tunneling_info {
913 	union dp_tun_cap_support dp_tun_cap;
914 	union dpia_info dpia_info;
915 	uint8_t usb4_driver_id;
916 	uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
917 };
918 
919 #ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
920 #define DP_MAIN_LINK_CHANNEL_CODING_CAP			0x006
921 #endif
922 #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
923 #define DP_SINK_VIDEO_FALLBACK_FORMATS			0x020
924 #endif
925 #ifndef DP_FEC_CAPABILITY_1
926 #define DP_FEC_CAPABILITY_1				0x091
927 #endif
928 #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
929 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT		0x0A3
930 #endif
931 #ifndef DP_DSC_CONFIGURATION
932 #define DP_DSC_CONFIGURATION				0x161
933 #endif
934 #ifndef DP_PHY_SQUARE_PATTERN
935 #define DP_PHY_SQUARE_PATTERN				0x249
936 #endif
937 #ifndef DP_128b_132b_SUPPORTED_LINK_RATES
938 #define DP_128b_132b_SUPPORTED_LINK_RATES		0x2215
939 #endif
940 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
941 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL		0x2216
942 #endif
943 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
944 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0		0X2230
945 #endif
946 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
947 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256		0X2250
948 #endif
949 #ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
950 #define DP_DSC_SUPPORT_AND_DECODER_COUNT		0x2260
951 #endif
952 #ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
953 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0	0x2270
954 #endif
955 #ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
956 #define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK	(1 << 0)
957 #endif
958 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
959 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK	(0b111 << 1)
960 #endif
961 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
962 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT	1
963 #endif
964 #ifndef DP_DSC_DECODER_COUNT_MASK
965 #define DP_DSC_DECODER_COUNT_MASK			(0b111 << 5)
966 #endif
967 #ifndef DP_DSC_DECODER_COUNT_SHIFT
968 #define DP_DSC_DECODER_COUNT_SHIFT			5
969 #endif
970 #ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
971 #define DP_MAIN_LINK_CHANNEL_CODING_SET			0x108
972 #endif
973 #ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
974 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER	0xF0006
975 #endif
976 #ifndef DP_PHY_REPEATER_128b_132b_RATES
977 #define DP_PHY_REPEATER_128b_132b_RATES			0xF0007
978 #endif
979 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
980 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1	0xF0022
981 #endif
982 #ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
983 #define DP_INTRA_HOP_AUX_REPLY_INDICATION		(1 << 3)
984 /* TODO - Use DRM header to replace above once available */
985 #endif // DP_INTRA_HOP_AUX_REPLY_INDICATION
986 union dp_main_line_channel_coding_cap {
987 	struct {
988 		uint8_t DP_8b_10b_SUPPORTED	:1;
989 		uint8_t DP_128b_132b_SUPPORTED	:1;
990 		uint8_t RESERVED		:6;
991 	} bits;
992 	uint8_t raw;
993 };
994 
995 union dp_main_link_channel_coding_lttpr_cap {
996 	struct {
997 		uint8_t DP_128b_132b_SUPPORTED	:1;
998 		uint8_t RESERVED		:7;
999 	} bits;
1000 	uint8_t raw;
1001 };
1002 
1003 union dp_128b_132b_supported_link_rates {
1004 	struct {
1005 		uint8_t UHBR10	:1;
1006 		uint8_t UHBR20	:1;
1007 		uint8_t UHBR13_5:1;
1008 		uint8_t RESERVED:5;
1009 	} bits;
1010 	uint8_t raw;
1011 };
1012 
1013 union dp_128b_132b_supported_lttpr_link_rates {
1014 	struct {
1015 		uint8_t UHBR10	:1;
1016 		uint8_t UHBR20	:1;
1017 		uint8_t UHBR13_5:1;
1018 		uint8_t RESERVED:5;
1019 	} bits;
1020 	uint8_t raw;
1021 };
1022 
1023 union dp_sink_video_fallback_formats {
1024 	struct {
1025 		uint8_t dp_1024x768_60Hz_24bpp_support	:1;
1026 		uint8_t dp_1280x720_60Hz_24bpp_support	:1;
1027 		uint8_t dp_1920x1080_60Hz_24bpp_support	:1;
1028 		uint8_t RESERVED			:5;
1029 	} bits;
1030 	uint8_t raw;
1031 };
1032 
1033 union dp_fec_capability1 {
1034 	struct {
1035 		uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE	:1;
1036 		uint8_t RESERVED				:7;
1037 	} bits;
1038 	uint8_t raw;
1039 };
1040 
1041 union dp_cable_id {
1042 	struct {
1043 		uint8_t UHBR10_20_CAPABILITY	:2;
1044 		uint8_t UHBR13_5_CAPABILITY	:1;
1045 		uint8_t CABLE_TYPE		:3;
1046 		uint8_t RESERVED		:2;
1047 	} bits;
1048 	uint8_t raw;
1049 };
1050 
1051 struct dp_color_depth_caps {
1052 	uint8_t support_6bpc	:1;
1053 	uint8_t support_8bpc	:1;
1054 	uint8_t support_10bpc	:1;
1055 	uint8_t support_12bpc	:1;
1056 	uint8_t support_16bpc	:1;
1057 	uint8_t RESERVED	:3;
1058 };
1059 
1060 struct dp_encoding_format_caps {
1061 	uint8_t support_rgb	:1;
1062 	uint8_t support_ycbcr444:1;
1063 	uint8_t support_ycbcr422:1;
1064 	uint8_t support_ycbcr420:1;
1065 	uint8_t RESERVED	:4;
1066 };
1067 
1068 union dp_dfp_cap_ext {
1069 	struct {
1070 		uint8_t supported;
1071 		uint8_t max_pixel_rate_in_mps[2];
1072 		uint8_t max_video_h_active_width[2];
1073 		uint8_t max_video_v_active_height[2];
1074 		struct dp_encoding_format_caps encoding_format_caps;
1075 		struct dp_color_depth_caps rgb_color_depth_caps;
1076 		struct dp_color_depth_caps ycbcr444_color_depth_caps;
1077 		struct dp_color_depth_caps ycbcr422_color_depth_caps;
1078 		struct dp_color_depth_caps ycbcr420_color_depth_caps;
1079 	} fields;
1080 	uint8_t raw[12];
1081 };
1082 
1083 union dp_128b_132b_training_aux_rd_interval {
1084 	struct {
1085 		uint8_t VALUE	:7;
1086 		uint8_t UNIT	:1;
1087 	} bits;
1088 	uint8_t raw;
1089 };
1090 
1091 union edp_alpm_caps {
1092 	struct {
1093 		uint8_t AUX_WAKE_ALPM_CAP       :1;
1094 		uint8_t PM_STATE_2A_SUPPORT     :1;
1095 		uint8_t AUX_LESS_ALPM_CAP       :1;
1096 		uint8_t RESERVED                :5;
1097 	} bits;
1098 	uint8_t raw;
1099 };
1100 
1101 union edp_psr_dpcd_caps {
1102 	struct {
1103 		uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED      :1;
1104 		uint8_t PSR_SETUP_TIME  :3;
1105 		uint8_t Y_COORDINATE_REQUIRED   :1;
1106 		uint8_t SU_GRANULARITY_REQUIRED :1;
1107 		uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1;
1108 		uint8_t RESERVED                :1;
1109 	} bits;
1110 	uint8_t raw;
1111 };
1112 
1113 struct edp_psr_info {
1114 	uint8_t psr_version;
1115 	union edp_psr_dpcd_caps psr_dpcd_caps;
1116 	uint8_t psr2_su_y_granularity_cap;
1117 	uint8_t force_psrsu_cap;
1118 };
1119 
1120 struct replay_info {
1121 	uint8_t pixel_deviation_per_line;
1122 	uint8_t max_deviation_line;
1123 };
1124 
1125 struct dprx_states {
1126 	bool cable_id_written;
1127 };
1128 
1129 enum dpcd_downstream_port_max_bpc {
1130 	DOWN_STREAM_MAX_8BPC = 0,
1131 	DOWN_STREAM_MAX_10BPC,
1132 	DOWN_STREAM_MAX_12BPC,
1133 	DOWN_STREAM_MAX_16BPC
1134 };
1135 
1136 enum link_training_offset {
1137 	DPRX                = 0,
1138 	LTTPR_PHY_REPEATER1 = 1,
1139 	LTTPR_PHY_REPEATER2 = 2,
1140 	LTTPR_PHY_REPEATER3 = 3,
1141 	LTTPR_PHY_REPEATER4 = 4,
1142 	LTTPR_PHY_REPEATER5 = 5,
1143 	LTTPR_PHY_REPEATER6 = 6,
1144 	LTTPR_PHY_REPEATER7 = 7,
1145 	LTTPR_PHY_REPEATER8 = 8
1146 };
1147 
1148 #define MAX_REPEATER_CNT 8
1149 
1150 struct dc_lttpr_caps {
1151 	union dpcd_rev revision;
1152 	uint8_t mode;
1153 	uint8_t max_lane_count;
1154 	uint8_t max_link_rate;
1155 	uint8_t phy_repeater_cnt;
1156 	uint8_t max_ext_timeout;
1157 	union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding;
1158 	union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;
1159 	uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
1160 };
1161 
1162 struct dc_dongle_dfp_cap_ext {
1163 	bool supported;
1164 	uint16_t max_pixel_rate_in_mps;
1165 	uint16_t max_video_h_active_width;
1166 	uint16_t max_video_v_active_height;
1167 	struct dp_encoding_format_caps encoding_format_caps;
1168 	struct dp_color_depth_caps rgb_color_depth_caps;
1169 	struct dp_color_depth_caps ycbcr444_color_depth_caps;
1170 	struct dp_color_depth_caps ycbcr422_color_depth_caps;
1171 	struct dp_color_depth_caps ycbcr420_color_depth_caps;
1172 };
1173 
1174 struct dc_dongle_caps {
1175 	/* dongle type (DP converter, CV smart dongle) */
1176 	enum display_dongle_type dongle_type;
1177 	bool extendedCapValid;
1178 	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1179 	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1180 	bool is_dp_hdmi_s3d_converter;
1181 	bool is_dp_hdmi_ycbcr422_pass_through;
1182 	bool is_dp_hdmi_ycbcr420_pass_through;
1183 	bool is_dp_hdmi_ycbcr422_converter;
1184 	bool is_dp_hdmi_ycbcr420_converter;
1185 	uint32_t dp_hdmi_max_bpc;
1186 	uint32_t dp_hdmi_max_pixel_clk_in_khz;
1187 	uint32_t dp_hdmi_frl_max_link_bw_in_kbps;
1188 	struct dc_dongle_dfp_cap_ext dfp_cap_ext;
1189 };
1190 
1191 struct dpcd_caps {
1192 	union dpcd_rev dpcd_rev;
1193 	union max_lane_count max_ln_count;
1194 	union max_down_spread max_down_spread;
1195 	union dprx_feature dprx_feature;
1196 
1197 	/* valid only for eDP v1.4 or higher*/
1198 	uint8_t edp_supported_link_rates_count;
1199 	enum dc_link_rate edp_supported_link_rates[8];
1200 
1201 	/* dongle type (DP converter, CV smart dongle) */
1202 	enum display_dongle_type dongle_type;
1203 	bool is_dongle_type_one;
1204 	/* branch device or sink device */
1205 	bool is_branch_dev;
1206 	/* Dongle's downstream count. */
1207 	union sink_count sink_count;
1208 	bool is_mst_capable;
1209 	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1210 	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1211 	struct dc_dongle_caps dongle_caps;
1212 
1213 	uint32_t sink_dev_id;
1214 	int8_t sink_dev_id_str[6];
1215 	int8_t sink_hw_revision;
1216 	int8_t sink_fw_revision[2];
1217 
1218 	uint32_t branch_dev_id;
1219 	int8_t branch_dev_name[6];
1220 	int8_t branch_hw_revision;
1221 	int8_t branch_fw_revision[2];
1222 
1223 	bool allow_invalid_MSA_timing_param;
1224 	bool panel_mode_edp;
1225 	bool dpcd_display_control_capable;
1226 	bool ext_receiver_cap_field_present;
1227 	bool set_power_state_capable_edp;
1228 	bool dynamic_backlight_capable_edp;
1229 	union dpcd_fec_capability fec_cap;
1230 	struct dpcd_dsc_capabilities dsc_caps;
1231 	struct dc_lttpr_caps lttpr_caps;
1232 	struct adaptive_sync_caps adaptive_sync_caps;
1233 	struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1234 
1235 	union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
1236 	union dp_main_line_channel_coding_cap channel_coding_cap;
1237 	union dp_sink_video_fallback_formats fallback_formats;
1238 	union dp_fec_capability1 fec_cap1;
1239 	bool panel_luminance_control;
1240 	union dp_cable_id cable_id;
1241 	uint8_t edp_rev;
1242 	union edp_alpm_caps alpm_caps;
1243 	struct edp_psr_info psr_info;
1244 
1245 	struct replay_info pr_info;
1246 };
1247 
1248 union dpcd_sink_ext_caps {
1249 	struct {
1250 		/* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1251 		 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1252 		 */
1253 		uint8_t sdr_aux_backlight_control : 1;
1254 		uint8_t hdr_aux_backlight_control : 1;
1255 		uint8_t reserved_1 : 2;
1256 		uint8_t oled : 1;
1257 		uint8_t reserved_2 : 1;
1258 		uint8_t miniled : 1;
1259 		uint8_t reserved : 1;
1260 	} bits;
1261 	uint8_t raw;
1262 };
1263 
1264 enum dc_link_fec_state {
1265 	dc_link_fec_not_ready,
1266 	dc_link_fec_ready,
1267 	dc_link_fec_enabled
1268 };
1269 
1270 union dpcd_psr_configuration {
1271 	struct {
1272 		unsigned char ENABLE                    : 1;
1273 		unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
1274 		unsigned char CRC_VERIFICATION          : 1;
1275 		unsigned char FRAME_CAPTURE_INDICATION  : 1;
1276 		/* For eDP 1.4, PSR v2*/
1277 		unsigned char LINE_CAPTURE_INDICATION   : 1;
1278 		/* For eDP 1.4, PSR v2*/
1279 		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
1280 		unsigned char ENABLE_PSR2               : 1;
1281 		unsigned char EARLY_TRANSPORT_ENABLE    : 1;
1282 	} bits;
1283 	unsigned char raw;
1284 };
1285 
1286 union replay_enable_and_configuration {
1287 	struct {
1288 		unsigned char FREESYNC_PANEL_REPLAY_MODE              :1;
1289 		unsigned char TIMING_DESYNC_ERROR_VERIFICATION        :1;
1290 		unsigned char STATE_TRANSITION_ERROR_DETECTION        :1;
1291 		unsigned char RESERVED0                               :1;
1292 		unsigned char RESERVED1                               :4;
1293 	} bits;
1294 	unsigned char raw;
1295 };
1296 
1297 union dpcd_replay_configuration {
1298 	struct {
1299 		unsigned char STATE_TRANSITION_ERROR_STATUS    : 1;
1300 		unsigned char DESYNC_ERROR_STATUS              : 1;
1301 		unsigned char SINK_DEVICE_REPLAY_STATUS        : 3;
1302 		unsigned char SINK_FRAME_LOCKED                : 2;
1303 		unsigned char RESERVED                         : 1;
1304 	} bits;
1305 	unsigned char raw;
1306 };
1307 
1308 union dpcd_alpm_configuration {
1309 	struct {
1310 		unsigned char ENABLE                    : 1;
1311 		unsigned char IRQ_HPD_ENABLE            : 1;
1312 		unsigned char RESERVED                  : 6;
1313 	} bits;
1314 	unsigned char raw;
1315 };
1316 
1317 union dpcd_sink_active_vtotal_control_mode {
1318 	struct {
1319 		unsigned char ENABLE                    : 1;
1320 		unsigned char RESERVED                  : 7;
1321 	} bits;
1322 	unsigned char raw;
1323 };
1324 
1325 union psr_error_status {
1326 	struct {
1327 		unsigned char LINK_CRC_ERROR        :1;
1328 		unsigned char RFB_STORAGE_ERROR     :1;
1329 		unsigned char VSC_SDP_ERROR         :1;
1330 		unsigned char RESERVED              :5;
1331 	} bits;
1332 	unsigned char raw;
1333 };
1334 
1335 union psr_sink_psr_status {
1336 	struct {
1337 	unsigned char SINK_SELF_REFRESH_STATUS  :3;
1338 	unsigned char RESERVED                  :5;
1339 	} bits;
1340 	unsigned char raw;
1341 };
1342 
1343 struct edp_trace_power_timestamps {
1344 	uint64_t poweroff;
1345 	uint64_t poweron;
1346 };
1347 
1348 struct dp_trace_lt_counts {
1349 	unsigned int total;
1350 	unsigned int fail;
1351 };
1352 
1353 enum link_training_result {
1354 	LINK_TRAINING_SUCCESS,
1355 	LINK_TRAINING_CR_FAIL_LANE0,
1356 	LINK_TRAINING_CR_FAIL_LANE1,
1357 	LINK_TRAINING_CR_FAIL_LANE23,
1358 	/* CR DONE bit is cleared during EQ step */
1359 	LINK_TRAINING_EQ_FAIL_CR,
1360 	/* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */
1361 	LINK_TRAINING_EQ_FAIL_CR_PARTIAL,
1362 	/* other failure during EQ step */
1363 	LINK_TRAINING_EQ_FAIL_EQ,
1364 	LINK_TRAINING_LQA_FAIL,
1365 	/* one of the CR,EQ or symbol lock is dropped */
1366 	LINK_TRAINING_LINK_LOSS,
1367 	/* Abort link training (because sink unplugged) */
1368 	LINK_TRAINING_ABORT,
1369 	DP_128b_132b_LT_FAILED,
1370 	DP_128b_132b_MAX_LOOP_COUNT_REACHED,
1371 	DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT,
1372 	DP_128b_132b_CDS_DONE_TIMEOUT,
1373 };
1374 
1375 struct dp_trace_lt {
1376 	struct dp_trace_lt_counts counts;
1377 	struct dp_trace_timestamps {
1378 		unsigned long long start;
1379 		unsigned long long end;
1380 	} timestamps;
1381 	enum link_training_result result;
1382 	bool is_logged;
1383 };
1384 
1385 struct dp_trace {
1386 	struct dp_trace_lt detect_lt_trace;
1387 	struct dp_trace_lt commit_lt_trace;
1388 	unsigned int link_loss_count;
1389 	bool is_initialized;
1390 	struct edp_trace_power_timestamps edp_trace_power_timestamps;
1391 };
1392 
1393 /* TODO - This is a temporary location for any new DPCD definitions.
1394  * We should move these to drm_dp header.
1395  */
1396 #ifndef DP_LINK_SQUARE_PATTERN
1397 #define DP_LINK_SQUARE_PATTERN				0x10F
1398 #endif
1399 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX
1400 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX		0x2217
1401 #endif
1402 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX
1403 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX		0x110
1404 #endif
1405 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
1406 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE	0x50
1407 #endif
1408 #ifndef DP_TUNNELING_IRQ
1409 #define DP_TUNNELING_IRQ				(1 << 5)
1410 #endif
1411 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/
1412 #ifndef DP_TUNNELING_CAPABILITIES
1413 #define DP_TUNNELING_CAPABILITIES			0xE000D /* 1.4a */
1414 #endif
1415 #ifndef USB4_DRIVER_ID
1416 #define USB4_DRIVER_ID					0xE000F /* 1.4a */
1417 #endif
1418 #ifndef USB4_DRIVER_BW_CAPABILITY
1419 #define USB4_DRIVER_BW_CAPABILITY			0xE0020 /* 1.4a */
1420 #endif
1421 #ifndef DP_IN_ADAPTER_TUNNEL_INFO
1422 #define DP_IN_ADAPTER_TUNNEL_INFO			0xE0021 /* 1.4a */
1423 #endif
1424 #ifndef DP_BW_GRANULALITY
1425 #define DP_BW_GRANULALITY				0xE0022 /* 1.4a */
1426 #endif
1427 #ifndef ESTIMATED_BW
1428 #define ESTIMATED_BW					0xE0023 /* 1.4a */
1429 #endif
1430 #ifndef ALLOCATED_BW
1431 #define ALLOCATED_BW					0xE0024 /* 1.4a */
1432 #endif
1433 #ifndef DP_TUNNELING_STATUS
1434 #define DP_TUNNELING_STATUS				0xE0025 /* 1.4a */
1435 #endif
1436 #ifndef DP_TUNNELING_MAX_LINK_RATE
1437 #define DP_TUNNELING_MAX_LINK_RATE			0xE0028 /* 1.4a */
1438 #endif
1439 #ifndef DP_TUNNELING_MAX_LANE_COUNT
1440 #define DP_TUNNELING_MAX_LANE_COUNT			0xE0029 /* 1.4a */
1441 #endif
1442 #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL
1443 #define DPTX_BW_ALLOCATION_MODE_CONTROL			0xE0030 /* 1.4a */
1444 #endif
1445 #ifndef REQUESTED_BW
1446 #define REQUESTED_BW					0xE0031 /* 1.4a */
1447 #endif
1448 #endif /* DC_DP_TYPES_H */
1449