1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9
10 #include <hyp/adjust_pc.h>
11 #include <hyp/fault.h>
12
13 #include <linux/arm-smccc.h>
14 #include <linux/kvm_host.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <uapi/linux/psci.h>
18
19 #include <kvm/arm_psci.h>
20
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/extable.h>
24 #include <asm/kprobes.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_hyp.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/kvm_nested.h>
30 #include <asm/fpsimd.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/processor.h>
33
34 struct kvm_exception_table_entry {
35 int insn, fixup;
36 };
37
38 extern struct kvm_exception_table_entry __start___kvm_ex_table;
39 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
40
41 /* Check whether the FP regs are owned by the guest */
guest_owns_fp_regs(struct kvm_vcpu * vcpu)42 static inline bool guest_owns_fp_regs(struct kvm_vcpu *vcpu)
43 {
44 return vcpu->arch.fp_state == FP_STATE_GUEST_OWNED;
45 }
46
47 /* Save the 32-bit only FPSIMD system register state */
__fpsimd_save_fpexc32(struct kvm_vcpu * vcpu)48 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
49 {
50 if (!vcpu_el1_is_32bit(vcpu))
51 return;
52
53 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
54 }
55
__activate_traps_fpsimd32(struct kvm_vcpu * vcpu)56 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
57 {
58 /*
59 * We are about to set CPTR_EL2.TFP to trap all floating point
60 * register accesses to EL2, however, the ARM ARM clearly states that
61 * traps are only taken to EL2 if the operation would not otherwise
62 * trap to EL1. Therefore, always make sure that for 32-bit guests,
63 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
64 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
65 * it will cause an exception.
66 */
67 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
68 write_sysreg(1 << 30, fpexc32_el2);
69 isb();
70 }
71 }
72
73 #define compute_clr_set(vcpu, reg, clr, set) \
74 do { \
75 u64 hfg; \
76 hfg = __vcpu_sys_reg(vcpu, reg) & ~__ ## reg ## _RES0; \
77 set |= hfg & __ ## reg ## _MASK; \
78 clr |= ~hfg & __ ## reg ## _nMASK; \
79 } while(0)
80
81
__activate_traps_hfgxtr(struct kvm_vcpu * vcpu)82 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
83 {
84 struct kvm_cpu_context *hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
85 u64 r_clr = 0, w_clr = 0, r_set = 0, w_set = 0, tmp;
86 u64 r_val, w_val;
87
88 if (!cpus_have_final_cap(ARM64_HAS_FGT))
89 return;
90
91 ctxt_sys_reg(hctxt, HFGRTR_EL2) = read_sysreg_s(SYS_HFGRTR_EL2);
92 ctxt_sys_reg(hctxt, HFGWTR_EL2) = read_sysreg_s(SYS_HFGWTR_EL2);
93
94 if (cpus_have_final_cap(ARM64_SME)) {
95 tmp = HFGxTR_EL2_nSMPRI_EL1_MASK | HFGxTR_EL2_nTPIDR2_EL0_MASK;
96
97 r_clr |= tmp;
98 w_clr |= tmp;
99 }
100
101 /*
102 * Trap guest writes to TCR_EL1 to prevent it from enabling HA or HD.
103 */
104 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
105 w_set |= HFGxTR_EL2_TCR_EL1_MASK;
106
107 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
108 compute_clr_set(vcpu, HFGRTR_EL2, r_clr, r_set);
109 compute_clr_set(vcpu, HFGWTR_EL2, w_clr, w_set);
110 }
111
112 /* The default is not to trap anything but ACCDATA_EL1 */
113 r_val = __HFGRTR_EL2_nMASK & ~HFGxTR_EL2_nACCDATA_EL1;
114 r_val |= r_set;
115 r_val &= ~r_clr;
116
117 w_val = __HFGWTR_EL2_nMASK & ~HFGxTR_EL2_nACCDATA_EL1;
118 w_val |= w_set;
119 w_val &= ~w_clr;
120
121 write_sysreg_s(r_val, SYS_HFGRTR_EL2);
122 write_sysreg_s(w_val, SYS_HFGWTR_EL2);
123
124 if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
125 return;
126
127 ctxt_sys_reg(hctxt, HFGITR_EL2) = read_sysreg_s(SYS_HFGITR_EL2);
128
129 r_set = r_clr = 0;
130 compute_clr_set(vcpu, HFGITR_EL2, r_clr, r_set);
131 r_val = __HFGITR_EL2_nMASK;
132 r_val |= r_set;
133 r_val &= ~r_clr;
134
135 write_sysreg_s(r_val, SYS_HFGITR_EL2);
136
137 ctxt_sys_reg(hctxt, HDFGRTR_EL2) = read_sysreg_s(SYS_HDFGRTR_EL2);
138 ctxt_sys_reg(hctxt, HDFGWTR_EL2) = read_sysreg_s(SYS_HDFGWTR_EL2);
139
140 r_clr = r_set = w_clr = w_set = 0;
141
142 compute_clr_set(vcpu, HDFGRTR_EL2, r_clr, r_set);
143 compute_clr_set(vcpu, HDFGWTR_EL2, w_clr, w_set);
144
145 r_val = __HDFGRTR_EL2_nMASK;
146 r_val |= r_set;
147 r_val &= ~r_clr;
148
149 w_val = __HDFGWTR_EL2_nMASK;
150 w_val |= w_set;
151 w_val &= ~w_clr;
152
153 write_sysreg_s(r_val, SYS_HDFGRTR_EL2);
154 write_sysreg_s(w_val, SYS_HDFGWTR_EL2);
155 }
156
__deactivate_traps_hfgxtr(struct kvm_vcpu * vcpu)157 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
158 {
159 struct kvm_cpu_context *hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
160
161 if (!cpus_have_final_cap(ARM64_HAS_FGT))
162 return;
163
164 write_sysreg_s(ctxt_sys_reg(hctxt, HFGRTR_EL2), SYS_HFGRTR_EL2);
165 write_sysreg_s(ctxt_sys_reg(hctxt, HFGWTR_EL2), SYS_HFGWTR_EL2);
166
167 if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
168 return;
169
170 write_sysreg_s(ctxt_sys_reg(hctxt, HFGITR_EL2), SYS_HFGITR_EL2);
171 write_sysreg_s(ctxt_sys_reg(hctxt, HDFGRTR_EL2), SYS_HDFGRTR_EL2);
172 write_sysreg_s(ctxt_sys_reg(hctxt, HDFGWTR_EL2), SYS_HDFGWTR_EL2);
173 }
174
__activate_traps_common(struct kvm_vcpu * vcpu)175 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
176 {
177 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
178 write_sysreg(1 << 15, hstr_el2);
179
180 /*
181 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
182 * PMSELR_EL0 to make sure it never contains the cycle
183 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
184 * EL1 instead of being trapped to EL2.
185 */
186 if (kvm_arm_support_pmu_v3()) {
187 struct kvm_cpu_context *hctxt;
188
189 write_sysreg(0, pmselr_el0);
190
191 hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
192 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
193 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
194 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
195 }
196
197 vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2);
198 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
199
200 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
201 u64 hcrx = HCRX_GUEST_FLAGS;
202 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
203 u64 clr = 0, set = 0;
204
205 compute_clr_set(vcpu, HCRX_EL2, clr, set);
206
207 hcrx |= set;
208 hcrx &= ~clr;
209 }
210
211 write_sysreg_s(hcrx, SYS_HCRX_EL2);
212 }
213
214 __activate_traps_hfgxtr(vcpu);
215 }
216
__deactivate_traps_common(struct kvm_vcpu * vcpu)217 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
218 {
219 write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2);
220
221 write_sysreg(0, hstr_el2);
222 if (kvm_arm_support_pmu_v3()) {
223 struct kvm_cpu_context *hctxt;
224
225 hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
226 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
227 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
228 }
229
230 if (cpus_have_final_cap(ARM64_HAS_HCX))
231 write_sysreg_s(HCRX_HOST_FLAGS, SYS_HCRX_EL2);
232
233 __deactivate_traps_hfgxtr(vcpu);
234 }
235
___activate_traps(struct kvm_vcpu * vcpu)236 static inline void ___activate_traps(struct kvm_vcpu *vcpu)
237 {
238 u64 hcr = vcpu->arch.hcr_el2;
239
240 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
241 hcr |= HCR_TVM;
242
243 write_sysreg(hcr, hcr_el2);
244
245 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
246 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
247 }
248
___deactivate_traps(struct kvm_vcpu * vcpu)249 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
250 {
251 /*
252 * If we pended a virtual abort, preserve it until it gets
253 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
254 * the crucial bit is "On taking a vSError interrupt,
255 * HCR_EL2.VSE is cleared to 0."
256 */
257 if (vcpu->arch.hcr_el2 & HCR_VSE) {
258 vcpu->arch.hcr_el2 &= ~HCR_VSE;
259 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
260 }
261 }
262
__populate_fault_info(struct kvm_vcpu * vcpu)263 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
264 {
265 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
266 }
267
__hyp_sve_restore_guest(struct kvm_vcpu * vcpu)268 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
269 {
270 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
271 __sve_restore_state(vcpu_sve_pffr(vcpu),
272 &vcpu->arch.ctxt.fp_regs.fpsr);
273 write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR);
274 }
275
276 /*
277 * We trap the first access to the FP/SIMD to save the host context and
278 * restore the guest context lazily.
279 * If FP/SIMD is not implemented, handle the trap and inject an undefined
280 * instruction exception to the guest. Similarly for trapped SVE accesses.
281 */
kvm_hyp_handle_fpsimd(struct kvm_vcpu * vcpu,u64 * exit_code)282 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
283 {
284 bool sve_guest;
285 u8 esr_ec;
286 u64 reg;
287
288 if (!system_supports_fpsimd())
289 return false;
290
291 sve_guest = vcpu_has_sve(vcpu);
292 esr_ec = kvm_vcpu_trap_get_class(vcpu);
293
294 /* Only handle traps the vCPU can support here: */
295 switch (esr_ec) {
296 case ESR_ELx_EC_FP_ASIMD:
297 break;
298 case ESR_ELx_EC_SVE:
299 if (!sve_guest)
300 return false;
301 break;
302 default:
303 return false;
304 }
305
306 /* Valid trap. Switch the context: */
307
308 /* First disable enough traps to allow us to update the registers */
309 if (has_vhe() || has_hvhe()) {
310 reg = CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN;
311 if (sve_guest)
312 reg |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
313
314 sysreg_clear_set(cpacr_el1, 0, reg);
315 } else {
316 reg = CPTR_EL2_TFP;
317 if (sve_guest)
318 reg |= CPTR_EL2_TZ;
319
320 sysreg_clear_set(cptr_el2, reg, 0);
321 }
322 isb();
323
324 /* Write out the host state if it's in the registers */
325 if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED)
326 __fpsimd_save_state(vcpu->arch.host_fpsimd_state);
327
328 /* Restore the guest state */
329 if (sve_guest)
330 __hyp_sve_restore_guest(vcpu);
331 else
332 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
333
334 /* Skip restoring fpexc32 for AArch64 guests */
335 if (!(read_sysreg(hcr_el2) & HCR_RW))
336 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
337
338 vcpu->arch.fp_state = FP_STATE_GUEST_OWNED;
339
340 return true;
341 }
342
handle_tx2_tvm(struct kvm_vcpu * vcpu)343 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
344 {
345 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
346 int rt = kvm_vcpu_sys_get_rt(vcpu);
347 u64 val = vcpu_get_reg(vcpu, rt);
348
349 /*
350 * The normal sysreg handling code expects to see the traps,
351 * let's not do anything here.
352 */
353 if (vcpu->arch.hcr_el2 & HCR_TVM)
354 return false;
355
356 switch (sysreg) {
357 case SYS_SCTLR_EL1:
358 write_sysreg_el1(val, SYS_SCTLR);
359 break;
360 case SYS_TTBR0_EL1:
361 write_sysreg_el1(val, SYS_TTBR0);
362 break;
363 case SYS_TTBR1_EL1:
364 write_sysreg_el1(val, SYS_TTBR1);
365 break;
366 case SYS_TCR_EL1:
367 write_sysreg_el1(val, SYS_TCR);
368 break;
369 case SYS_ESR_EL1:
370 write_sysreg_el1(val, SYS_ESR);
371 break;
372 case SYS_FAR_EL1:
373 write_sysreg_el1(val, SYS_FAR);
374 break;
375 case SYS_AFSR0_EL1:
376 write_sysreg_el1(val, SYS_AFSR0);
377 break;
378 case SYS_AFSR1_EL1:
379 write_sysreg_el1(val, SYS_AFSR1);
380 break;
381 case SYS_MAIR_EL1:
382 write_sysreg_el1(val, SYS_MAIR);
383 break;
384 case SYS_AMAIR_EL1:
385 write_sysreg_el1(val, SYS_AMAIR);
386 break;
387 case SYS_CONTEXTIDR_EL1:
388 write_sysreg_el1(val, SYS_CONTEXTIDR);
389 break;
390 default:
391 return false;
392 }
393
394 __kvm_skip_instr(vcpu);
395 return true;
396 }
397
esr_is_ptrauth_trap(u64 esr)398 static inline bool esr_is_ptrauth_trap(u64 esr)
399 {
400 switch (esr_sys64_to_sysreg(esr)) {
401 case SYS_APIAKEYLO_EL1:
402 case SYS_APIAKEYHI_EL1:
403 case SYS_APIBKEYLO_EL1:
404 case SYS_APIBKEYHI_EL1:
405 case SYS_APDAKEYLO_EL1:
406 case SYS_APDAKEYHI_EL1:
407 case SYS_APDBKEYLO_EL1:
408 case SYS_APDBKEYHI_EL1:
409 case SYS_APGAKEYLO_EL1:
410 case SYS_APGAKEYHI_EL1:
411 return true;
412 }
413
414 return false;
415 }
416
417 #define __ptrauth_save_key(ctxt, key) \
418 do { \
419 u64 __val; \
420 __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1); \
421 ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val; \
422 __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1); \
423 ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val; \
424 } while(0)
425
426 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
427
kvm_hyp_handle_ptrauth(struct kvm_vcpu * vcpu,u64 * exit_code)428 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code)
429 {
430 struct kvm_cpu_context *ctxt;
431 u64 val;
432
433 if (!vcpu_has_ptrauth(vcpu))
434 return false;
435
436 ctxt = this_cpu_ptr(&kvm_hyp_ctxt);
437 __ptrauth_save_key(ctxt, APIA);
438 __ptrauth_save_key(ctxt, APIB);
439 __ptrauth_save_key(ctxt, APDA);
440 __ptrauth_save_key(ctxt, APDB);
441 __ptrauth_save_key(ctxt, APGA);
442
443 vcpu_ptrauth_enable(vcpu);
444
445 val = read_sysreg(hcr_el2);
446 val |= (HCR_API | HCR_APK);
447 write_sysreg(val, hcr_el2);
448
449 return true;
450 }
451
kvm_hyp_handle_cntpct(struct kvm_vcpu * vcpu)452 static bool kvm_hyp_handle_cntpct(struct kvm_vcpu *vcpu)
453 {
454 struct arch_timer_context *ctxt;
455 u32 sysreg;
456 u64 val;
457
458 /*
459 * We only get here for 64bit guests, 32bit guests will hit
460 * the long and winding road all the way to the standard
461 * handling. Yes, it sucks to be irrelevant.
462 */
463 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
464
465 switch (sysreg) {
466 case SYS_CNTPCT_EL0:
467 case SYS_CNTPCTSS_EL0:
468 if (vcpu_has_nv(vcpu)) {
469 if (is_hyp_ctxt(vcpu)) {
470 ctxt = vcpu_hptimer(vcpu);
471 break;
472 }
473
474 /* Check for guest hypervisor trapping */
475 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
476 if (!vcpu_el2_e2h_is_set(vcpu))
477 val = (val & CNTHCTL_EL1PCTEN) << 10;
478
479 if (!(val & (CNTHCTL_EL1PCTEN << 10)))
480 return false;
481 }
482
483 ctxt = vcpu_ptimer(vcpu);
484 break;
485 default:
486 return false;
487 }
488
489 val = arch_timer_read_cntpct_el0();
490
491 if (ctxt->offset.vm_offset)
492 val -= *kern_hyp_va(ctxt->offset.vm_offset);
493 if (ctxt->offset.vcpu_offset)
494 val -= *kern_hyp_va(ctxt->offset.vcpu_offset);
495
496 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
497 __kvm_skip_instr(vcpu);
498 return true;
499 }
500
handle_ampere1_tcr(struct kvm_vcpu * vcpu)501 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
502 {
503 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
504 int rt = kvm_vcpu_sys_get_rt(vcpu);
505 u64 val = vcpu_get_reg(vcpu, rt);
506
507 if (sysreg != SYS_TCR_EL1)
508 return false;
509
510 /*
511 * Affected parts do not advertise support for hardware Access Flag /
512 * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
513 * control bits are still functional. The architecture requires these be
514 * RES0 on systems that do not implement FEAT_HAFDBS.
515 *
516 * Uphold the requirements of the architecture by masking guest writes
517 * to TCR_EL1.{HA,HD} here.
518 */
519 val &= ~(TCR_HD | TCR_HA);
520 write_sysreg_el1(val, SYS_TCR);
521 __kvm_skip_instr(vcpu);
522 return true;
523 }
524
kvm_hyp_handle_sysreg(struct kvm_vcpu * vcpu,u64 * exit_code)525 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
526 {
527 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
528 handle_tx2_tvm(vcpu))
529 return true;
530
531 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
532 handle_ampere1_tcr(vcpu))
533 return true;
534
535 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
536 __vgic_v3_perform_cpuif_access(vcpu) == 1)
537 return true;
538
539 if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu)))
540 return kvm_hyp_handle_ptrauth(vcpu, exit_code);
541
542 if (kvm_hyp_handle_cntpct(vcpu))
543 return true;
544
545 return false;
546 }
547
kvm_hyp_handle_cp15_32(struct kvm_vcpu * vcpu,u64 * exit_code)548 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
549 {
550 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
551 __vgic_v3_perform_cpuif_access(vcpu) == 1)
552 return true;
553
554 return false;
555 }
556
kvm_hyp_handle_memory_fault(struct kvm_vcpu * vcpu,u64 * exit_code)557 static bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu, u64 *exit_code)
558 {
559 if (!__populate_fault_info(vcpu))
560 return true;
561
562 return false;
563 }
564 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
565 __alias(kvm_hyp_handle_memory_fault);
566 static bool kvm_hyp_handle_watchpt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
567 __alias(kvm_hyp_handle_memory_fault);
568
kvm_hyp_handle_dabt_low(struct kvm_vcpu * vcpu,u64 * exit_code)569 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
570 {
571 if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
572 return true;
573
574 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
575 bool valid;
576
577 valid = kvm_vcpu_trap_get_fault_type(vcpu) == ESR_ELx_FSC_FAULT &&
578 kvm_vcpu_dabt_isvalid(vcpu) &&
579 !kvm_vcpu_abt_issea(vcpu) &&
580 !kvm_vcpu_abt_iss1tw(vcpu);
581
582 if (valid) {
583 int ret = __vgic_v2_perform_cpuif_access(vcpu);
584
585 if (ret == 1)
586 return true;
587
588 /* Promote an illegal access to an SError.*/
589 if (ret == -1)
590 *exit_code = ARM_EXCEPTION_EL1_SERROR;
591 }
592 }
593
594 return false;
595 }
596
597 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
598
599 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu);
600
601 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code);
602
603 /*
604 * Allow the hypervisor to handle the exit with an exit handler if it has one.
605 *
606 * Returns true if the hypervisor handled the exit, and control should go back
607 * to the guest, or false if it hasn't.
608 */
kvm_hyp_handle_exit(struct kvm_vcpu * vcpu,u64 * exit_code)609 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
610 {
611 const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu);
612 exit_handler_fn fn;
613
614 fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
615
616 if (fn)
617 return fn(vcpu, exit_code);
618
619 return false;
620 }
621
synchronize_vcpu_pstate(struct kvm_vcpu * vcpu,u64 * exit_code)622 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
623 {
624 /*
625 * Check for the conditions of Cortex-A510's #2077057. When these occur
626 * SPSR_EL2 can't be trusted, but isn't needed either as it is
627 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
628 * Are we single-stepping the guest, and took a PAC exception from the
629 * active-not-pending state?
630 */
631 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
632 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
633 *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
634 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
635 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
636
637 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
638 }
639
640 /*
641 * Return true when we were able to fixup the guest exit and should return to
642 * the guest, false when we should restore the host state and return to the
643 * main run loop.
644 */
fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code)645 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
646 {
647 /*
648 * Save PSTATE early so that we can evaluate the vcpu mode
649 * early on.
650 */
651 synchronize_vcpu_pstate(vcpu, exit_code);
652
653 /*
654 * Check whether we want to repaint the state one way or
655 * another.
656 */
657 early_exit_filter(vcpu, exit_code);
658
659 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
660 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
661
662 if (ARM_SERROR_PENDING(*exit_code) &&
663 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
664 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
665
666 /*
667 * HVC already have an adjusted PC, which we need to
668 * correct in order to return to after having injected
669 * the SError.
670 *
671 * SMC, on the other hand, is *trapped*, meaning its
672 * preferred return address is the SMC itself.
673 */
674 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
675 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
676 }
677
678 /*
679 * We're using the raw exception code in order to only process
680 * the trap if no SError is pending. We will come back to the
681 * same PC once the SError has been injected, and replay the
682 * trapping instruction.
683 */
684 if (*exit_code != ARM_EXCEPTION_TRAP)
685 goto exit;
686
687 /* Check if there's an exit handler and allow it to handle the exit. */
688 if (kvm_hyp_handle_exit(vcpu, exit_code))
689 goto guest;
690 exit:
691 /* Return to the host kernel and handle the exit */
692 return false;
693
694 guest:
695 /* Re-enter the guest */
696 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
697 return true;
698 }
699
__kvm_unexpected_el2_exception(void)700 static inline void __kvm_unexpected_el2_exception(void)
701 {
702 extern char __guest_exit_panic[];
703 unsigned long addr, fixup;
704 struct kvm_exception_table_entry *entry, *end;
705 unsigned long elr_el2 = read_sysreg(elr_el2);
706
707 entry = &__start___kvm_ex_table;
708 end = &__stop___kvm_ex_table;
709
710 while (entry < end) {
711 addr = (unsigned long)&entry->insn + entry->insn;
712 fixup = (unsigned long)&entry->fixup + entry->fixup;
713
714 if (addr != elr_el2) {
715 entry++;
716 continue;
717 }
718
719 write_sysreg(fixup, elr_el2);
720 return;
721 }
722
723 /* Trigger a panic after restoring the hyp context. */
724 write_sysreg(__guest_exit_panic, elr_el2);
725 }
726
727 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
728