1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include "qapi/visitor.h"
19 #include <math.h>
20 #include <sys/ioctl.h>
21 #include <sys/utsname.h>
22 #include <sys/syscall.h>
23 #include <sys/resource.h>
24 #include <sys/time.h>
25
26 #include <linux/kvm.h>
27 #include <linux/kvm_para.h>
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
30
31 #include "cpu.h"
32 #include "host-cpu.h"
33 #include "vmsr_energy.h"
34 #include "system/system.h"
35 #include "system/hw_accel.h"
36 #include "system/kvm_int.h"
37 #include "system/runstate.h"
38 #include "kvm_i386.h"
39 #include "../confidential-guest.h"
40 #include "sev.h"
41 #include "tdx.h"
42 #include "xen-emu.h"
43 #include "hyperv.h"
44 #include "hyperv-proto.h"
45
46 #include "gdbstub/enums.h"
47 #include "qemu/host-utils.h"
48 #include "qemu/main-loop.h"
49 #include "qemu/ratelimit.h"
50 #include "qemu/config-file.h"
51 #include "qemu/error-report.h"
52 #include "qemu/memalign.h"
53 #include "hw/i386/x86.h"
54 #include "hw/i386/kvm/xen_evtchn.h"
55 #include "hw/i386/pc.h"
56 #include "hw/i386/apic.h"
57 #include "hw/i386/apic_internal.h"
58 #include "hw/i386/apic-msidef.h"
59 #include "hw/i386/intel_iommu.h"
60 #include "hw/i386/topology.h"
61 #include "hw/i386/x86-iommu.h"
62 #include "hw/i386/e820_memory_layout.h"
63
64 #include "hw/xen/xen.h"
65
66 #include "hw/pci/pci.h"
67 #include "hw/pci/msi.h"
68 #include "hw/pci/msix.h"
69 #include "migration/blocker.h"
70 #include "exec/memattrs.h"
71 #include "exec/target_page.h"
72 #include "trace.h"
73
74 #include CONFIG_DEVICES
75
76 //#define DEBUG_KVM
77
78 #ifdef DEBUG_KVM
79 #define DPRINTF(fmt, ...) \
80 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define DPRINTF(fmt, ...) \
83 do { } while (0)
84 #endif
85
86 /*
87 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
88 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
89 * Since these must be part of guest physical memory, we need to allocate
90 * them, both by setting their start addresses in the kernel and by
91 * creating a corresponding e820 entry. We need 4 pages before the BIOS,
92 * so this value allows up to 16M BIOSes.
93 */
94 #define KVM_IDENTITY_BASE 0xfeffc000
95
96 /* From arch/x86/kvm/lapic.h */
97 #define KVM_APIC_BUS_CYCLE_NS 1
98 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
99
100 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
101 * 255 kvm_msr_entry structs */
102 #define MSR_BUF_SIZE 4096
103
104 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
105 typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
106 typedef struct {
107 uint32_t msr;
108 QEMURDMSRHandler *rdmsr;
109 QEMUWRMSRHandler *wrmsr;
110 } KVMMSRHandlers;
111
112 static void kvm_init_msrs(X86CPU *cpu);
113 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
114 QEMUWRMSRHandler *wrmsr);
115
116 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
117 KVM_CAP_INFO(SET_TSS_ADDR),
118 KVM_CAP_INFO(EXT_CPUID),
119 KVM_CAP_INFO(MP_STATE),
120 KVM_CAP_INFO(SIGNAL_MSI),
121 KVM_CAP_INFO(IRQ_ROUTING),
122 KVM_CAP_INFO(DEBUGREGS),
123 KVM_CAP_INFO(XSAVE),
124 KVM_CAP_INFO(VCPU_EVENTS),
125 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP),
126 KVM_CAP_INFO(MCE),
127 KVM_CAP_INFO(ADJUST_CLOCK),
128 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR),
129 KVM_CAP_LAST_INFO
130 };
131
132 static bool has_msr_star;
133 static bool has_msr_hsave_pa;
134 static bool has_msr_tsc_aux;
135 static bool has_msr_tsc_adjust;
136 static bool has_msr_tsc_deadline;
137 static bool has_msr_feature_control;
138 static bool has_msr_misc_enable;
139 static bool has_msr_smbase;
140 static bool has_msr_bndcfgs;
141 static int lm_capable_kernel;
142 static bool has_msr_hv_hypercall;
143 static bool has_msr_hv_crash;
144 static bool has_msr_hv_reset;
145 static bool has_msr_hv_vpindex;
146 static bool hv_vpindex_settable;
147 static bool has_msr_hv_runtime;
148 static bool has_msr_hv_synic;
149 static bool has_msr_hv_stimer;
150 static bool has_msr_hv_frequencies;
151 static bool has_msr_hv_reenlightenment;
152 static bool has_msr_hv_syndbg_options;
153 static bool has_msr_xss;
154 static bool has_msr_umwait;
155 static bool has_msr_spec_ctrl;
156 static bool has_tsc_scale_msr;
157 static bool has_msr_tsx_ctrl;
158 static bool has_msr_virt_ssbd;
159 static bool has_msr_smi_count;
160 static bool has_msr_arch_capabs;
161 static bool has_msr_core_capabs;
162 static bool has_msr_vmx_vmfunc;
163 static bool has_msr_ucode_rev;
164 static bool has_msr_vmx_procbased_ctls2;
165 static bool has_msr_perf_capabs;
166 static bool has_msr_pkrs;
167 static bool has_msr_hwcr;
168
169 static uint32_t has_architectural_pmu_version;
170 static uint32_t num_architectural_pmu_gp_counters;
171 static uint32_t num_architectural_pmu_fixed_counters;
172
173 static int has_xsave2;
174 static int has_xcrs;
175 static int has_sregs2;
176 static int has_exception_payload;
177 static int has_triple_fault_event;
178
179 static bool has_msr_mcg_ext_ctl;
180
181 static struct kvm_cpuid2 *cpuid_cache;
182 static struct kvm_cpuid2 *hv_cpuid_cache;
183 static struct kvm_msr_list *kvm_feature_msrs;
184
185 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES];
186
187 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
188 static RateLimit bus_lock_ratelimit_ctrl;
189 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
190
191 static const char *vm_type_name[] = {
192 [KVM_X86_DEFAULT_VM] = "default",
193 [KVM_X86_SEV_VM] = "SEV",
194 [KVM_X86_SEV_ES_VM] = "SEV-ES",
195 [KVM_X86_SNP_VM] = "SEV-SNP",
196 [KVM_X86_TDX_VM] = "TDX",
197 };
198
kvm_is_vm_type_supported(int type)199 bool kvm_is_vm_type_supported(int type)
200 {
201 uint32_t machine_types;
202
203 /*
204 * old KVM doesn't support KVM_CAP_VM_TYPES but KVM_X86_DEFAULT_VM
205 * is always supported
206 */
207 if (type == KVM_X86_DEFAULT_VM) {
208 return true;
209 }
210
211 machine_types = kvm_check_extension(KVM_STATE(current_machine->accelerator),
212 KVM_CAP_VM_TYPES);
213 return !!(machine_types & BIT(type));
214 }
215
kvm_get_vm_type(MachineState * ms)216 int kvm_get_vm_type(MachineState *ms)
217 {
218 int kvm_type = KVM_X86_DEFAULT_VM;
219
220 if (ms->cgs) {
221 if (!object_dynamic_cast(OBJECT(ms->cgs), TYPE_X86_CONFIDENTIAL_GUEST)) {
222 error_report("configuration type %s not supported for x86 guests",
223 object_get_typename(OBJECT(ms->cgs)));
224 exit(1);
225 }
226 kvm_type = x86_confidential_guest_kvm_type(
227 X86_CONFIDENTIAL_GUEST(ms->cgs));
228 }
229
230 if (!kvm_is_vm_type_supported(kvm_type)) {
231 error_report("vm-type %s not supported by KVM", vm_type_name[kvm_type]);
232 exit(1);
233 }
234
235 return kvm_type;
236 }
237
kvm_enable_hypercall(uint64_t enable_mask)238 bool kvm_enable_hypercall(uint64_t enable_mask)
239 {
240 KVMState *s = KVM_STATE(current_accel());
241
242 return !kvm_vm_enable_cap(s, KVM_CAP_EXIT_HYPERCALL, 0, enable_mask);
243 }
244
kvm_has_smm(void)245 bool kvm_has_smm(void)
246 {
247 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
248 }
249
kvm_has_adjust_clock_stable(void)250 bool kvm_has_adjust_clock_stable(void)
251 {
252 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
253
254 return (ret & KVM_CLOCK_TSC_STABLE);
255 }
256
kvm_has_exception_payload(void)257 bool kvm_has_exception_payload(void)
258 {
259 return has_exception_payload;
260 }
261
kvm_x2apic_api_set_flags(uint64_t flags)262 static bool kvm_x2apic_api_set_flags(uint64_t flags)
263 {
264 KVMState *s = KVM_STATE(current_accel());
265
266 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
267 }
268
269 #define MEMORIZE(fn, _result) \
270 ({ \
271 static bool _memorized; \
272 \
273 if (_memorized) { \
274 return _result; \
275 } \
276 _memorized = true; \
277 _result = fn; \
278 })
279
280 static bool has_x2apic_api;
281
kvm_has_x2apic_api(void)282 bool kvm_has_x2apic_api(void)
283 {
284 return has_x2apic_api;
285 }
286
kvm_enable_x2apic(void)287 bool kvm_enable_x2apic(void)
288 {
289 return MEMORIZE(
290 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
291 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
292 has_x2apic_api);
293 }
294
kvm_hv_vpindex_settable(void)295 bool kvm_hv_vpindex_settable(void)
296 {
297 return hv_vpindex_settable;
298 }
299
kvm_get_tsc(CPUState * cs)300 static int kvm_get_tsc(CPUState *cs)
301 {
302 X86CPU *cpu = X86_CPU(cs);
303 CPUX86State *env = &cpu->env;
304 uint64_t value;
305 int ret;
306
307 if (env->tsc_valid) {
308 return 0;
309 }
310
311 env->tsc_valid = !runstate_is_running();
312
313 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
314 if (ret < 0) {
315 return ret;
316 }
317
318 env->tsc = value;
319 return 0;
320 }
321
do_kvm_synchronize_tsc(CPUState * cpu,run_on_cpu_data arg)322 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
323 {
324 kvm_get_tsc(cpu);
325 }
326
kvm_synchronize_all_tsc(void)327 void kvm_synchronize_all_tsc(void)
328 {
329 CPUState *cpu;
330
331 if (kvm_enabled() && !is_tdx_vm()) {
332 CPU_FOREACH(cpu) {
333 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
334 }
335 }
336 }
337
try_get_cpuid(KVMState * s,int max)338 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
339 {
340 struct kvm_cpuid2 *cpuid;
341 int r, size;
342
343 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
344 cpuid = g_malloc0(size);
345 cpuid->nent = max;
346 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
347 if (r == 0 && cpuid->nent >= max) {
348 r = -E2BIG;
349 }
350 if (r < 0) {
351 if (r == -E2BIG) {
352 g_free(cpuid);
353 return NULL;
354 } else {
355 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
356 strerror(-r));
357 exit(1);
358 }
359 }
360 return cpuid;
361 }
362
363 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
364 * for all entries.
365 */
get_supported_cpuid(KVMState * s)366 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
367 {
368 struct kvm_cpuid2 *cpuid;
369 int max = 1;
370
371 if (cpuid_cache != NULL) {
372 return cpuid_cache;
373 }
374 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
375 max *= 2;
376 }
377 cpuid_cache = cpuid;
378 return cpuid;
379 }
380
host_tsx_broken(void)381 static bool host_tsx_broken(void)
382 {
383 int family, model, stepping;\
384 char vendor[CPUID_VENDOR_SZ + 1];
385
386 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
387
388 /* Check if we are running on a Haswell host known to have broken TSX */
389 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
390 (family == 6) &&
391 ((model == 63 && stepping < 4) ||
392 model == 60 || model == 69 || model == 70);
393 }
394
395 /* Returns the value for a specific register on the cpuid entry
396 */
cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,int reg)397 uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
398 {
399 uint32_t ret = 0;
400 switch (reg) {
401 case R_EAX:
402 ret = entry->eax;
403 break;
404 case R_EBX:
405 ret = entry->ebx;
406 break;
407 case R_ECX:
408 ret = entry->ecx;
409 break;
410 case R_EDX:
411 ret = entry->edx;
412 break;
413 }
414 return ret;
415 }
416
417 /* Find matching entry for function/index on kvm_cpuid2 struct
418 */
cpuid_find_entry(struct kvm_cpuid2 * cpuid,uint32_t function,uint32_t index)419 struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
420 uint32_t function,
421 uint32_t index)
422 {
423 int i;
424 for (i = 0; i < cpuid->nent; ++i) {
425 if (cpuid->entries[i].function == function &&
426 cpuid->entries[i].index == index) {
427 return &cpuid->entries[i];
428 }
429 }
430 /* not found: */
431 return NULL;
432 }
433
kvm_arch_get_supported_cpuid(KVMState * s,uint32_t function,uint32_t index,int reg)434 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
435 uint32_t index, int reg)
436 {
437 struct kvm_cpuid2 *cpuid;
438 uint32_t ret = 0;
439 uint32_t cpuid_1_edx, unused;
440 uint64_t bitmask;
441
442 cpuid = get_supported_cpuid(s);
443
444 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
445 if (entry) {
446 ret = cpuid_entry_get_reg(entry, reg);
447 }
448
449 /* Fixups for the data returned by KVM, below */
450
451 if (function == 1 && reg == R_EDX) {
452 /* KVM before 2.6.30 misreports the following features */
453 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
454 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */
455 ret |= CPUID_HT;
456 } else if (function == 1 && reg == R_ECX) {
457 /* We can set the hypervisor flag, even if KVM does not return it on
458 * GET_SUPPORTED_CPUID
459 */
460 ret |= CPUID_EXT_HYPERVISOR;
461 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
462 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
463 * and the irqchip is in the kernel.
464 */
465 if (kvm_irqchip_in_kernel() &&
466 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
467 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
468 }
469
470 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
471 * without the in-kernel irqchip
472 */
473 if (!kvm_irqchip_in_kernel()) {
474 ret &= ~CPUID_EXT_X2APIC;
475 }
476
477 if (enable_cpu_pm) {
478 int disable_exits = kvm_check_extension(s,
479 KVM_CAP_X86_DISABLE_EXITS);
480
481 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
482 ret |= CPUID_EXT_MONITOR;
483 }
484 }
485 } else if (function == 6 && reg == R_EAX) {
486 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
487 } else if (function == 7 && index == 0 && reg == R_EBX) {
488 /* Not new instructions, just an optimization. */
489 uint32_t ebx;
490 host_cpuid(7, 0, &unused, &ebx, &unused, &unused);
491 ret |= ebx & CPUID_7_0_EBX_ERMS;
492
493 if (host_tsx_broken()) {
494 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
495 }
496 } else if (function == 7 && index == 0 && reg == R_EDX) {
497 /* Not new instructions, just an optimization. */
498 uint32_t edx;
499 host_cpuid(7, 0, &unused, &unused, &unused, &edx);
500 ret |= edx & CPUID_7_0_EDX_FSRM;
501
502 /*
503 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
504 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
505 * returned by KVM_GET_MSR_INDEX_LIST.
506 *
507 * But also, because Windows does not like ARCH_CAPABILITIES on AMD
508 * mcahines at all, do not show the fake ARCH_CAPABILITIES MSR that
509 * KVM sets up.
510 */
511 if (!has_msr_arch_capabs || !(edx & CPUID_7_0_EDX_ARCH_CAPABILITIES)) {
512 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
513 }
514 } else if (function == 7 && index == 1 && reg == R_EAX) {
515 /* Not new instructions, just an optimization. */
516 uint32_t eax;
517 host_cpuid(7, 1, &eax, &unused, &unused, &unused);
518 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
519 } else if (function == 7 && index == 2 && reg == R_EDX) {
520 uint32_t edx;
521 host_cpuid(7, 2, &unused, &unused, &unused, &edx);
522 ret |= edx & CPUID_7_2_EDX_MCDT_NO;
523 } else if (function == 0xd && index == 0 &&
524 (reg == R_EAX || reg == R_EDX)) {
525 /*
526 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
527 * features that still have to be enabled with the arch_prctl
528 * system call. QEMU needs the full value, which is retrieved
529 * with KVM_GET_DEVICE_ATTR.
530 */
531 struct kvm_device_attr attr = {
532 .group = 0,
533 .attr = KVM_X86_XCOMP_GUEST_SUPP,
534 .addr = (unsigned long) &bitmask
535 };
536
537 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
538 if (!sys_attr) {
539 return ret;
540 }
541
542 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
543 if (rc < 0) {
544 if (rc != -ENXIO) {
545 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
546 "error: %d", rc);
547 }
548 return ret;
549 }
550 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
551 } else if (function == 0x80000001 && reg == R_ECX) {
552 /*
553 * It's safe to enable TOPOEXT even if it's not returned by
554 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
555 * us to keep CPU models including TOPOEXT runnable on older kernels.
556 */
557 ret |= CPUID_EXT3_TOPOEXT;
558 } else if (function == 0x80000001 && reg == R_EDX) {
559 /* On Intel, kvm returns cpuid according to the Intel spec,
560 * so add missing bits according to the AMD spec:
561 */
562 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
563 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
564 } else if (function == 0x80000007 && reg == R_EBX) {
565 ret |= CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR;
566 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
567 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
568 * be enabled without the in-kernel irqchip
569 */
570 if (!kvm_irqchip_in_kernel()) {
571 ret &= ~CPUID_KVM_PV_UNHALT;
572 }
573 if (kvm_irqchip_is_split()) {
574 ret |= CPUID_KVM_MSI_EXT_DEST_ID;
575 }
576 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
577 ret |= CPUID_KVM_HINTS_REALTIME;
578 }
579
580 if (current_machine->cgs) {
581 ret = x86_confidential_guest_adjust_cpuid_features(
582 X86_CONFIDENTIAL_GUEST(current_machine->cgs),
583 function, index, reg, ret);
584 }
585 return ret;
586 }
587
kvm_arch_get_supported_msr_feature(KVMState * s,uint32_t index)588 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
589 {
590 struct {
591 struct kvm_msrs info;
592 struct kvm_msr_entry entries[1];
593 } msr_data = {};
594 uint64_t value;
595 uint32_t ret, can_be_one, must_be_one;
596
597 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
598 return 0;
599 }
600
601 /* Check if requested MSR is supported feature MSR */
602 int i;
603 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
604 if (kvm_feature_msrs->indices[i] == index) {
605 break;
606 }
607 if (i == kvm_feature_msrs->nmsrs) {
608 return 0; /* if the feature MSR is not supported, simply return 0 */
609 }
610
611 msr_data.info.nmsrs = 1;
612 msr_data.entries[0].index = index;
613
614 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
615 if (ret != 1) {
616 error_report("KVM get MSR (index=0x%x) feature failed, %s",
617 index, strerror(-ret));
618 exit(1);
619 }
620
621 value = msr_data.entries[0].data;
622 switch (index) {
623 case MSR_IA32_VMX_PROCBASED_CTLS2:
624 if (!has_msr_vmx_procbased_ctls2) {
625 /* KVM forgot to add these bits for some time, do this ourselves. */
626 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
627 CPUID_XSAVE_XSAVES) {
628 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
629 }
630 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
631 CPUID_EXT_RDRAND) {
632 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
633 }
634 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
635 CPUID_7_0_EBX_INVPCID) {
636 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
637 }
638 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
639 CPUID_7_0_EBX_RDSEED) {
640 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
641 }
642 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
643 CPUID_EXT2_RDTSCP) {
644 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
645 }
646 }
647 /* fall through */
648 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
649 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
650 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
651 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
652 /*
653 * Return true for bits that can be one, but do not have to be one.
654 * The SDM tells us which bits could have a "must be one" setting,
655 * so we can do the opposite transformation in make_vmx_msr_value.
656 */
657 must_be_one = (uint32_t)value;
658 can_be_one = (uint32_t)(value >> 32);
659 return can_be_one & ~must_be_one;
660
661 default:
662 return value;
663 }
664 }
665
kvm_get_mce_cap_supported(KVMState * s,uint64_t * mce_cap,int * max_banks)666 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
667 int *max_banks)
668 {
669 *max_banks = kvm_check_extension(s, KVM_CAP_MCE);
670 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
671 }
672
kvm_mce_inject(X86CPU * cpu,hwaddr paddr,int code)673 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
674 {
675 CPUState *cs = CPU(cpu);
676 CPUX86State *env = &cpu->env;
677 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_MISCV |
678 MCI_STATUS_ADDRV;
679 uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
680 int flags = 0;
681
682 if (!IS_AMD_CPU(env)) {
683 status |= MCI_STATUS_S | MCI_STATUS_UC;
684 if (code == BUS_MCEERR_AR) {
685 status |= MCI_STATUS_AR | 0x134;
686 mcg_status |= MCG_STATUS_EIPV;
687 } else {
688 status |= 0xc0;
689 }
690 } else {
691 if (code == BUS_MCEERR_AR) {
692 status |= MCI_STATUS_UC | MCI_STATUS_POISON;
693 mcg_status |= MCG_STATUS_EIPV;
694 } else {
695 /* Setting the POISON bit for deferred errors indicates to the
696 * guest kernel that the address provided by the MCE is valid
697 * and usable which will ensure that the guest kernel will send
698 * a SIGBUS_AO signal to the guest process. This allows for
699 * more desirable behavior in the case that the guest process
700 * with poisoned memory has set the MCE_KILL_EARLY prctl flag
701 * which indicates that the process would prefer to handle or
702 * shutdown due to the poisoned memory condition before the
703 * memory has been accessed.
704 *
705 * While the POISON bit would not be set in a deferred error
706 * sent from hardware, the bit is not meaningful for deferred
707 * errors and can be reused in this scenario.
708 */
709 status |= MCI_STATUS_DEFERRED | MCI_STATUS_POISON;
710 }
711 }
712
713 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
714 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
715 * guest kernel back into env->mcg_ext_ctl.
716 */
717 cpu_synchronize_state(cs);
718 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
719 mcg_status |= MCG_STATUS_LMCE;
720 flags = 0;
721 }
722
723 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
724 (MCM_ADDR_PHYS << 6) | 0xc, flags);
725 }
726
emit_hypervisor_memory_failure(MemoryFailureAction action,bool ar)727 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
728 {
729 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
730
731 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
732 &mff);
733 }
734
hardware_memory_error(void * host_addr)735 static void hardware_memory_error(void *host_addr)
736 {
737 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
738 error_report("QEMU got Hardware memory error at addr %p", host_addr);
739 exit(1);
740 }
741
kvm_arch_on_sigbus_vcpu(CPUState * c,int code,void * addr)742 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
743 {
744 X86CPU *cpu = X86_CPU(c);
745 CPUX86State *env = &cpu->env;
746 ram_addr_t ram_addr;
747 hwaddr paddr;
748
749 /* If we get an action required MCE, it has been injected by KVM
750 * while the VM was running. An action optional MCE instead should
751 * be coming from the main thread, which qemu_init_sigbus identifies
752 * as the "early kill" thread.
753 */
754 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
755
756 if ((env->mcg_cap & MCG_SER_P) && addr) {
757 ram_addr = qemu_ram_addr_from_host(addr);
758 if (ram_addr != RAM_ADDR_INVALID &&
759 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
760 kvm_hwpoison_page_add(ram_addr);
761 kvm_mce_inject(cpu, paddr, code);
762
763 /*
764 * Use different logging severity based on error type.
765 * If there is additional MCE reporting on the hypervisor, QEMU VA
766 * could be another source to identify the PA and MCE details.
767 */
768 if (code == BUS_MCEERR_AR) {
769 error_report("Guest MCE Memory Error at QEMU addr %p and "
770 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
771 addr, paddr, "BUS_MCEERR_AR");
772 } else {
773 warn_report("Guest MCE Memory Error at QEMU addr %p and "
774 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
775 addr, paddr, "BUS_MCEERR_AO");
776 }
777
778 return;
779 }
780
781 if (code == BUS_MCEERR_AO) {
782 warn_report("Hardware memory error at addr %p of type %s "
783 "for memory used by QEMU itself instead of guest system!",
784 addr, "BUS_MCEERR_AO");
785 }
786 }
787
788 if (code == BUS_MCEERR_AR) {
789 hardware_memory_error(addr);
790 }
791
792 /* Hope we are lucky for AO MCE, just notify a event */
793 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
794 }
795
kvm_queue_exception(CPUX86State * env,int32_t exception_nr,uint8_t exception_has_payload,uint64_t exception_payload)796 static void kvm_queue_exception(CPUX86State *env,
797 int32_t exception_nr,
798 uint8_t exception_has_payload,
799 uint64_t exception_payload)
800 {
801 assert(env->exception_nr == -1);
802 assert(!env->exception_pending);
803 assert(!env->exception_injected);
804 assert(!env->exception_has_payload);
805
806 env->exception_nr = exception_nr;
807
808 if (has_exception_payload) {
809 env->exception_pending = 1;
810
811 env->exception_has_payload = exception_has_payload;
812 env->exception_payload = exception_payload;
813 } else {
814 env->exception_injected = 1;
815
816 if (exception_nr == EXCP01_DB) {
817 assert(exception_has_payload);
818 env->dr[6] = exception_payload;
819 } else if (exception_nr == EXCP0E_PAGE) {
820 assert(exception_has_payload);
821 env->cr[2] = exception_payload;
822 } else {
823 assert(!exception_has_payload);
824 }
825 }
826 }
827
cpu_update_state(void * opaque,bool running,RunState state)828 static void cpu_update_state(void *opaque, bool running, RunState state)
829 {
830 CPUX86State *env = opaque;
831
832 if (running) {
833 env->tsc_valid = false;
834 }
835 }
836
kvm_arch_vcpu_id(CPUState * cs)837 unsigned long kvm_arch_vcpu_id(CPUState *cs)
838 {
839 X86CPU *cpu = X86_CPU(cs);
840 return cpu->apic_id;
841 }
842
843 #ifndef KVM_CPUID_SIGNATURE_NEXT
844 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
845 #endif
846
hyperv_enabled(X86CPU * cpu)847 static bool hyperv_enabled(X86CPU *cpu)
848 {
849 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
850 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
851 cpu->hyperv_features || cpu->hyperv_passthrough);
852 }
853
854 /*
855 * Check whether target_freq is within conservative
856 * ntp correctable bounds (250ppm) of freq
857 */
freq_within_bounds(int freq,int target_freq)858 static inline bool freq_within_bounds(int freq, int target_freq)
859 {
860 int max_freq = freq + (freq * 250 / 1000000);
861 int min_freq = freq - (freq * 250 / 1000000);
862
863 if (target_freq >= min_freq && target_freq <= max_freq) {
864 return true;
865 }
866
867 return false;
868 }
869
kvm_arch_set_tsc_khz(CPUState * cs)870 static int kvm_arch_set_tsc_khz(CPUState *cs)
871 {
872 X86CPU *cpu = X86_CPU(cs);
873 CPUX86State *env = &cpu->env;
874 int r, cur_freq;
875 bool set_ioctl = false;
876
877 /*
878 * TSC of TD vcpu is immutable, it cannot be set/changed via vcpu scope
879 * VM_SET_TSC_KHZ, but only be initialized via VM scope VM_SET_TSC_KHZ
880 * before ioctl KVM_TDX_INIT_VM in tdx_pre_create_vcpu()
881 */
882 if (is_tdx_vm()) {
883 return 0;
884 }
885
886 if (!env->tsc_khz) {
887 return 0;
888 }
889
890 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
891 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
892
893 /*
894 * If TSC scaling is supported, attempt to set TSC frequency.
895 */
896 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
897 set_ioctl = true;
898 }
899
900 /*
901 * If desired TSC frequency is within bounds of NTP correction,
902 * attempt to set TSC frequency.
903 */
904 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
905 set_ioctl = true;
906 }
907
908 r = set_ioctl ?
909 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
910 -ENOTSUP;
911
912 if (r < 0) {
913 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
914 * TSC frequency doesn't match the one we want.
915 */
916 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
917 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
918 -ENOTSUP;
919 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
920 warn_report("TSC frequency mismatch between "
921 "VM (%" PRId64 " kHz) and host (%d kHz), "
922 "and TSC scaling unavailable",
923 env->tsc_khz, cur_freq);
924 return r;
925 }
926 }
927
928 return 0;
929 }
930
tsc_is_stable_and_known(CPUX86State * env)931 static bool tsc_is_stable_and_known(CPUX86State *env)
932 {
933 if (!env->tsc_khz) {
934 return false;
935 }
936 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
937 || env->user_tsc_khz;
938 }
939
940 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
941
942 static struct {
943 const char *desc;
944 struct {
945 uint32_t func;
946 int reg;
947 uint32_t bits;
948 } flags[2];
949 uint64_t dependencies;
950 bool skip_passthrough;
951 } kvm_hyperv_properties[] = {
952 [HYPERV_FEAT_RELAXED] = {
953 .desc = "relaxed timing (hv-relaxed)",
954 .flags = {
955 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
956 .bits = HV_RELAXED_TIMING_RECOMMENDED}
957 }
958 },
959 [HYPERV_FEAT_VAPIC] = {
960 .desc = "virtual APIC (hv-vapic)",
961 .flags = {
962 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
963 .bits = HV_APIC_ACCESS_AVAILABLE}
964 }
965 },
966 [HYPERV_FEAT_TIME] = {
967 .desc = "clocksources (hv-time)",
968 .flags = {
969 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
970 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
971 }
972 },
973 [HYPERV_FEAT_CRASH] = {
974 .desc = "crash MSRs (hv-crash)",
975 .flags = {
976 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
977 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
978 }
979 },
980 [HYPERV_FEAT_RESET] = {
981 .desc = "reset MSR (hv-reset)",
982 .flags = {
983 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
984 .bits = HV_RESET_AVAILABLE}
985 }
986 },
987 [HYPERV_FEAT_VPINDEX] = {
988 .desc = "VP_INDEX MSR (hv-vpindex)",
989 .flags = {
990 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
991 .bits = HV_VP_INDEX_AVAILABLE}
992 }
993 },
994 [HYPERV_FEAT_RUNTIME] = {
995 .desc = "VP_RUNTIME MSR (hv-runtime)",
996 .flags = {
997 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
998 .bits = HV_VP_RUNTIME_AVAILABLE}
999 }
1000 },
1001 [HYPERV_FEAT_SYNIC] = {
1002 .desc = "synthetic interrupt controller (hv-synic)",
1003 .flags = {
1004 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1005 .bits = HV_SYNIC_AVAILABLE}
1006 }
1007 },
1008 [HYPERV_FEAT_STIMER] = {
1009 .desc = "synthetic timers (hv-stimer)",
1010 .flags = {
1011 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1012 .bits = HV_SYNTIMERS_AVAILABLE}
1013 },
1014 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
1015 },
1016 [HYPERV_FEAT_FREQUENCIES] = {
1017 .desc = "frequency MSRs (hv-frequencies)",
1018 .flags = {
1019 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1020 .bits = HV_ACCESS_FREQUENCY_MSRS},
1021 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1022 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
1023 }
1024 },
1025 [HYPERV_FEAT_REENLIGHTENMENT] = {
1026 .desc = "reenlightenment MSRs (hv-reenlightenment)",
1027 .flags = {
1028 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1029 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
1030 }
1031 },
1032 [HYPERV_FEAT_TLBFLUSH] = {
1033 .desc = "paravirtualized TLB flush (hv-tlbflush)",
1034 .flags = {
1035 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1036 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
1037 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1038 },
1039 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1040 },
1041 [HYPERV_FEAT_EVMCS] = {
1042 .desc = "enlightened VMCS (hv-evmcs)",
1043 .flags = {
1044 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1045 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
1046 },
1047 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1048 },
1049 [HYPERV_FEAT_IPI] = {
1050 .desc = "paravirtualized IPI (hv-ipi)",
1051 .flags = {
1052 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1053 .bits = HV_CLUSTER_IPI_RECOMMENDED |
1054 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1055 },
1056 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1057 },
1058 [HYPERV_FEAT_STIMER_DIRECT] = {
1059 .desc = "direct mode synthetic timers (hv-stimer-direct)",
1060 .flags = {
1061 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1062 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
1063 },
1064 .dependencies = BIT(HYPERV_FEAT_STIMER)
1065 },
1066 [HYPERV_FEAT_AVIC] = {
1067 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
1068 .flags = {
1069 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1070 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
1071 }
1072 },
1073 [HYPERV_FEAT_SYNDBG] = {
1074 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
1075 .flags = {
1076 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1077 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
1078 },
1079 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED),
1080 .skip_passthrough = true,
1081 },
1082 [HYPERV_FEAT_MSR_BITMAP] = {
1083 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
1084 .flags = {
1085 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1086 .bits = HV_NESTED_MSR_BITMAP}
1087 }
1088 },
1089 [HYPERV_FEAT_XMM_INPUT] = {
1090 .desc = "XMM fast hypercall input (hv-xmm-input)",
1091 .flags = {
1092 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1093 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
1094 }
1095 },
1096 [HYPERV_FEAT_TLBFLUSH_EXT] = {
1097 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
1098 .flags = {
1099 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1100 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
1101 },
1102 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
1103 },
1104 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1105 .desc = "direct TLB flush (hv-tlbflush-direct)",
1106 .flags = {
1107 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1108 .bits = HV_NESTED_DIRECT_FLUSH}
1109 },
1110 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1111 },
1112 };
1113
try_get_hv_cpuid(CPUState * cs,int max,bool do_sys_ioctl)1114 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1115 bool do_sys_ioctl)
1116 {
1117 struct kvm_cpuid2 *cpuid;
1118 int r, size;
1119
1120 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1121 cpuid = g_malloc0(size);
1122 cpuid->nent = max;
1123
1124 if (do_sys_ioctl) {
1125 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1126 } else {
1127 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1128 }
1129 if (r == 0 && cpuid->nent >= max) {
1130 r = -E2BIG;
1131 }
1132 if (r < 0) {
1133 if (r == -E2BIG) {
1134 g_free(cpuid);
1135 return NULL;
1136 } else {
1137 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1138 strerror(-r));
1139 exit(1);
1140 }
1141 }
1142 return cpuid;
1143 }
1144
1145 /*
1146 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1147 * for all entries.
1148 */
get_supported_hv_cpuid(CPUState * cs)1149 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1150 {
1151 struct kvm_cpuid2 *cpuid;
1152 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1153 int max = 11;
1154 int i;
1155 bool do_sys_ioctl;
1156
1157 do_sys_ioctl =
1158 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
1159
1160 /*
1161 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1162 * unsupported, kvm_hyperv_expand_features() checks for that.
1163 */
1164 assert(do_sys_ioctl || cs->kvm_state);
1165
1166 /*
1167 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1168 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1169 * it and re-trying until we succeed.
1170 */
1171 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
1172 max++;
1173 }
1174
1175 /*
1176 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1177 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1178 * information early, just check for the capability and set the bit
1179 * manually.
1180 */
1181 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
1182 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1183 for (i = 0; i < cpuid->nent; i++) {
1184 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1185 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1186 }
1187 }
1188 }
1189
1190 return cpuid;
1191 }
1192
1193 /*
1194 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1195 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1196 */
get_supported_hv_cpuid_legacy(CPUState * cs)1197 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1198 {
1199 X86CPU *cpu = X86_CPU(cs);
1200 struct kvm_cpuid2 *cpuid;
1201 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1202
1203 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1204 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1205 cpuid->nent = 2;
1206
1207 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1208 entry_feat = &cpuid->entries[0];
1209 entry_feat->function = HV_CPUID_FEATURES;
1210
1211 entry_recomm = &cpuid->entries[1];
1212 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1213 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1214
1215 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1216 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1217 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1218 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1219 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1220 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1221 }
1222
1223 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1224 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1225 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1226 }
1227
1228 if (has_msr_hv_frequencies) {
1229 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1230 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1231 }
1232
1233 if (has_msr_hv_crash) {
1234 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1235 }
1236
1237 if (has_msr_hv_reenlightenment) {
1238 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1239 }
1240
1241 if (has_msr_hv_reset) {
1242 entry_feat->eax |= HV_RESET_AVAILABLE;
1243 }
1244
1245 if (has_msr_hv_vpindex) {
1246 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1247 }
1248
1249 if (has_msr_hv_runtime) {
1250 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1251 }
1252
1253 if (has_msr_hv_synic) {
1254 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1255 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1256
1257 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1258 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1259 }
1260 }
1261
1262 if (has_msr_hv_stimer) {
1263 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1264 }
1265
1266 if (has_msr_hv_syndbg_options) {
1267 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1268 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1269 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1270 }
1271
1272 if (kvm_check_extension(cs->kvm_state,
1273 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1274 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1275 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1276 }
1277
1278 if (kvm_check_extension(cs->kvm_state,
1279 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1280 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1281 }
1282
1283 if (kvm_check_extension(cs->kvm_state,
1284 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1285 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1286 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1287 }
1288
1289 return cpuid;
1290 }
1291
hv_cpuid_get_host(CPUState * cs,uint32_t func,int reg)1292 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1293 {
1294 struct kvm_cpuid_entry2 *entry;
1295 struct kvm_cpuid2 *cpuid;
1296
1297 if (hv_cpuid_cache) {
1298 cpuid = hv_cpuid_cache;
1299 } else {
1300 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1301 cpuid = get_supported_hv_cpuid(cs);
1302 } else {
1303 /*
1304 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1305 * before KVM context is created but this is only done when
1306 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1307 * KVM_CAP_HYPERV_CPUID.
1308 */
1309 assert(cs->kvm_state);
1310
1311 cpuid = get_supported_hv_cpuid_legacy(cs);
1312 }
1313 hv_cpuid_cache = cpuid;
1314 }
1315
1316 if (!cpuid) {
1317 return 0;
1318 }
1319
1320 entry = cpuid_find_entry(cpuid, func, 0);
1321 if (!entry) {
1322 return 0;
1323 }
1324
1325 return cpuid_entry_get_reg(entry, reg);
1326 }
1327
hyperv_feature_supported(CPUState * cs,int feature)1328 static bool hyperv_feature_supported(CPUState *cs, int feature)
1329 {
1330 uint32_t func, bits;
1331 int i, reg;
1332
1333 /*
1334 * kvm_hyperv_properties needs to define at least one CPUID flag which
1335 * must be used to detect the feature, it's hard to say whether it is
1336 * supported or not otherwise.
1337 */
1338 assert(kvm_hyperv_properties[feature].flags[0].func);
1339
1340 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1341
1342 func = kvm_hyperv_properties[feature].flags[i].func;
1343 reg = kvm_hyperv_properties[feature].flags[i].reg;
1344 bits = kvm_hyperv_properties[feature].flags[i].bits;
1345
1346 if (!func) {
1347 continue;
1348 }
1349
1350 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1351 return false;
1352 }
1353 }
1354
1355 return true;
1356 }
1357
1358 /* Checks that all feature dependencies are enabled */
hv_feature_check_deps(X86CPU * cpu,int feature,Error ** errp)1359 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
1360 {
1361 uint64_t deps;
1362 int dep_feat;
1363
1364 deps = kvm_hyperv_properties[feature].dependencies;
1365 while (deps) {
1366 dep_feat = ctz64(deps);
1367 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1368 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1369 kvm_hyperv_properties[feature].desc,
1370 kvm_hyperv_properties[dep_feat].desc);
1371 return false;
1372 }
1373 deps &= ~(1ull << dep_feat);
1374 }
1375
1376 return true;
1377 }
1378
hv_build_cpuid_leaf(CPUState * cs,uint32_t func,int reg)1379 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1380 {
1381 X86CPU *cpu = X86_CPU(cs);
1382 uint32_t r = 0;
1383 int i, j;
1384
1385 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1386 if (!hyperv_feat_enabled(cpu, i)) {
1387 continue;
1388 }
1389
1390 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1391 if (kvm_hyperv_properties[i].flags[j].func != func) {
1392 continue;
1393 }
1394 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1395 continue;
1396 }
1397
1398 r |= kvm_hyperv_properties[i].flags[j].bits;
1399 }
1400 }
1401
1402 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1403 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1404 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1405 r |= DEFAULT_EVMCS_VERSION;
1406 }
1407 }
1408
1409 return r;
1410 }
1411
1412 /*
1413 * Expand Hyper-V CPU features. In partucular, check that all the requested
1414 * features are supported by the host and the sanity of the configuration
1415 * (that all the required dependencies are included). Also, this takes care
1416 * of 'hv_passthrough' mode and fills the environment with all supported
1417 * Hyper-V features.
1418 */
kvm_hyperv_expand_features(X86CPU * cpu,Error ** errp)1419 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
1420 {
1421 CPUState *cs = CPU(cpu);
1422 Error *local_err = NULL;
1423 int feat;
1424
1425 if (!hyperv_enabled(cpu))
1426 return true;
1427
1428 /*
1429 * When kvm_hyperv_expand_features is called at CPU feature expansion
1430 * time per-CPU kvm_state is not available yet so we can only proceed
1431 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1432 */
1433 if (!cs->kvm_state &&
1434 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1435 return true;
1436
1437 if (cpu->hyperv_passthrough) {
1438 cpu->hyperv_vendor_id[0] =
1439 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1440 cpu->hyperv_vendor_id[1] =
1441 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1442 cpu->hyperv_vendor_id[2] =
1443 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1444 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1445 sizeof(cpu->hyperv_vendor_id) + 1);
1446 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1447 sizeof(cpu->hyperv_vendor_id));
1448 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1449
1450 cpu->hyperv_interface_id[0] =
1451 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1452 cpu->hyperv_interface_id[1] =
1453 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1454 cpu->hyperv_interface_id[2] =
1455 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1456 cpu->hyperv_interface_id[3] =
1457 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1458
1459 cpu->hyperv_ver_id_build =
1460 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1461 cpu->hyperv_ver_id_major =
1462 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1463 cpu->hyperv_ver_id_minor =
1464 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1465 cpu->hyperv_ver_id_sp =
1466 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1467 cpu->hyperv_ver_id_sb =
1468 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1469 cpu->hyperv_ver_id_sn =
1470 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
1471
1472 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1473 R_EAX);
1474 cpu->hyperv_limits[0] =
1475 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1476 cpu->hyperv_limits[1] =
1477 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1478 cpu->hyperv_limits[2] =
1479 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1480
1481 cpu->hyperv_spinlock_attempts =
1482 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1483
1484 /*
1485 * Mark feature as enabled in 'cpu->hyperv_features' as
1486 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1487 */
1488 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1489 if (hyperv_feature_supported(cs, feat) &&
1490 !kvm_hyperv_properties[feat].skip_passthrough) {
1491 cpu->hyperv_features |= BIT(feat);
1492 }
1493 }
1494 } else {
1495 /* Check features availability and dependencies */
1496 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1497 /* If the feature was not requested skip it. */
1498 if (!hyperv_feat_enabled(cpu, feat)) {
1499 continue;
1500 }
1501
1502 /* Check if the feature is supported by KVM */
1503 if (!hyperv_feature_supported(cs, feat)) {
1504 error_setg(errp, "Hyper-V %s is not supported by kernel",
1505 kvm_hyperv_properties[feat].desc);
1506 return false;
1507 }
1508
1509 /* Check dependencies */
1510 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1511 error_propagate(errp, local_err);
1512 return false;
1513 }
1514 }
1515 }
1516
1517 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1518 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1519 !cpu->hyperv_synic_kvm_only &&
1520 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1521 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1522 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1523 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1524 return false;
1525 }
1526
1527 return true;
1528 }
1529
1530 /*
1531 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1532 */
hyperv_fill_cpuids(CPUState * cs,struct kvm_cpuid_entry2 * cpuid_ent)1533 static int hyperv_fill_cpuids(CPUState *cs,
1534 struct kvm_cpuid_entry2 *cpuid_ent)
1535 {
1536 X86CPU *cpu = X86_CPU(cs);
1537 struct kvm_cpuid_entry2 *c;
1538 uint32_t signature[3];
1539 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
1540 uint32_t nested_eax =
1541 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
1542
1543 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1544 HV_CPUID_IMPLEMENT_LIMITS;
1545
1546 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1547 max_cpuid_leaf =
1548 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1549 }
1550
1551 c = &cpuid_ent[cpuid_i++];
1552 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1553 c->eax = max_cpuid_leaf;
1554 c->ebx = cpu->hyperv_vendor_id[0];
1555 c->ecx = cpu->hyperv_vendor_id[1];
1556 c->edx = cpu->hyperv_vendor_id[2];
1557
1558 c = &cpuid_ent[cpuid_i++];
1559 c->function = HV_CPUID_INTERFACE;
1560 c->eax = cpu->hyperv_interface_id[0];
1561 c->ebx = cpu->hyperv_interface_id[1];
1562 c->ecx = cpu->hyperv_interface_id[2];
1563 c->edx = cpu->hyperv_interface_id[3];
1564
1565 c = &cpuid_ent[cpuid_i++];
1566 c->function = HV_CPUID_VERSION;
1567 c->eax = cpu->hyperv_ver_id_build;
1568 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1569 cpu->hyperv_ver_id_minor;
1570 c->ecx = cpu->hyperv_ver_id_sp;
1571 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1572 (cpu->hyperv_ver_id_sn & 0xffffff);
1573
1574 c = &cpuid_ent[cpuid_i++];
1575 c->function = HV_CPUID_FEATURES;
1576 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1577 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1578 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1579
1580 /* Unconditionally required with any Hyper-V enlightenment */
1581 c->eax |= HV_HYPERCALL_AVAILABLE;
1582
1583 /* SynIC and Vmbus devices require messages/signals hypercalls */
1584 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1585 !cpu->hyperv_synic_kvm_only) {
1586 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1587 }
1588
1589
1590 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1591 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1592
1593 c = &cpuid_ent[cpuid_i++];
1594 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1595 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1596 c->ebx = cpu->hyperv_spinlock_attempts;
1597
1598 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1599 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
1600 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1601 }
1602
1603 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1604 c->eax |= HV_NO_NONARCH_CORESHARING;
1605 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1606 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1607 HV_NO_NONARCH_CORESHARING;
1608 }
1609
1610 c = &cpuid_ent[cpuid_i++];
1611 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1612 c->eax = cpu->hv_max_vps;
1613 c->ebx = cpu->hyperv_limits[0];
1614 c->ecx = cpu->hyperv_limits[1];
1615 c->edx = cpu->hyperv_limits[2];
1616
1617 if (nested_eax) {
1618 uint32_t function;
1619
1620 /* Create zeroed 0x40000006..0x40000009 leaves */
1621 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1622 function < HV_CPUID_NESTED_FEATURES; function++) {
1623 c = &cpuid_ent[cpuid_i++];
1624 c->function = function;
1625 }
1626
1627 c = &cpuid_ent[cpuid_i++];
1628 c->function = HV_CPUID_NESTED_FEATURES;
1629 c->eax = nested_eax;
1630 }
1631
1632 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1633 c = &cpuid_ent[cpuid_i++];
1634 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1635 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1636 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1637 memcpy(signature, "Microsoft VS", 12);
1638 c->eax = 0;
1639 c->ebx = signature[0];
1640 c->ecx = signature[1];
1641 c->edx = signature[2];
1642
1643 c = &cpuid_ent[cpuid_i++];
1644 c->function = HV_CPUID_SYNDBG_INTERFACE;
1645 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1646 c->eax = signature[0];
1647 c->ebx = 0;
1648 c->ecx = 0;
1649 c->edx = 0;
1650
1651 c = &cpuid_ent[cpuid_i++];
1652 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1653 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1654 c->ebx = 0;
1655 c->ecx = 0;
1656 c->edx = 0;
1657 }
1658
1659 return cpuid_i;
1660 }
1661
1662 static Error *hv_passthrough_mig_blocker;
1663 static Error *hv_no_nonarch_cs_mig_blocker;
1664
1665 /* Checks that the exposed eVMCS version range is supported by KVM */
evmcs_version_supported(uint16_t evmcs_version,uint16_t supported_evmcs_version)1666 static bool evmcs_version_supported(uint16_t evmcs_version,
1667 uint16_t supported_evmcs_version)
1668 {
1669 uint8_t min_version = evmcs_version & 0xff;
1670 uint8_t max_version = evmcs_version >> 8;
1671 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1672 uint8_t max_supported_version = supported_evmcs_version >> 8;
1673
1674 return (min_version >= min_supported_version) &&
1675 (max_version <= max_supported_version);
1676 }
1677
hyperv_init_vcpu(X86CPU * cpu)1678 static int hyperv_init_vcpu(X86CPU *cpu)
1679 {
1680 CPUState *cs = CPU(cpu);
1681 Error *local_err = NULL;
1682 int ret;
1683
1684 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1685 error_setg(&hv_passthrough_mig_blocker,
1686 "'hv-passthrough' CPU flag prevents migration, use explicit"
1687 " set of hv-* flags instead");
1688 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err);
1689 if (ret < 0) {
1690 error_report_err(local_err);
1691 return ret;
1692 }
1693 }
1694
1695 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1696 hv_no_nonarch_cs_mig_blocker == NULL) {
1697 error_setg(&hv_no_nonarch_cs_mig_blocker,
1698 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1699 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1700 " make sure SMT is disabled and/or that vCPUs are properly"
1701 " pinned)");
1702 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err);
1703 if (ret < 0) {
1704 error_report_err(local_err);
1705 return ret;
1706 }
1707 }
1708
1709 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1710 /*
1711 * the kernel doesn't support setting vp_index; assert that its value
1712 * is in sync
1713 */
1714 uint64_t value;
1715
1716 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
1717 if (ret < 0) {
1718 return ret;
1719 }
1720
1721 if (value != hyperv_vp_index(CPU(cpu))) {
1722 error_report("kernel's vp_index != QEMU's vp_index");
1723 return -ENXIO;
1724 }
1725 }
1726
1727 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1728 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1729 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1730 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1731 if (ret < 0) {
1732 error_report("failed to turn on HyperV SynIC in KVM: %s",
1733 strerror(-ret));
1734 return ret;
1735 }
1736
1737 if (!cpu->hyperv_synic_kvm_only) {
1738 ret = hyperv_x86_synic_add(cpu);
1739 if (ret < 0) {
1740 error_report("failed to create HyperV SynIC: %s",
1741 strerror(-ret));
1742 return ret;
1743 }
1744 }
1745 }
1746
1747 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1748 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1749 uint16_t supported_evmcs_version;
1750
1751 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1752 (uintptr_t)&supported_evmcs_version);
1753
1754 /*
1755 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1756 * option sets. Note: we hardcode the maximum supported eVMCS version
1757 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1758 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1759 * to be added.
1760 */
1761 if (ret < 0) {
1762 error_report("Hyper-V %s is not supported by kernel",
1763 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1764 return ret;
1765 }
1766
1767 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1768 error_report("eVMCS version range [%d..%d] is not supported by "
1769 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1770 evmcs_version >> 8, supported_evmcs_version & 0xff,
1771 supported_evmcs_version >> 8);
1772 return -ENOTSUP;
1773 }
1774 }
1775
1776 if (cpu->hyperv_enforce_cpuid) {
1777 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1778 if (ret < 0) {
1779 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1780 strerror(-ret));
1781 return ret;
1782 }
1783 }
1784
1785 /* Skip SynIC and VP_INDEX since they are hard deps already */
1786 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) &&
1787 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1788 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
1789 hyperv_x86_set_vmbus_recommended_features_enabled();
1790 }
1791
1792 return 0;
1793 }
1794
1795 static Error *invtsc_mig_blocker;
1796
kvm_init_xsave(CPUX86State * env)1797 static void kvm_init_xsave(CPUX86State *env)
1798 {
1799 if (has_xsave2) {
1800 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1801 } else {
1802 env->xsave_buf_len = sizeof(struct kvm_xsave);
1803 }
1804
1805 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1806 memset(env->xsave_buf, 0, env->xsave_buf_len);
1807 /*
1808 * The allocated storage must be large enough for all of the
1809 * possible XSAVE state components.
1810 */
1811 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1812 env->xsave_buf_len);
1813 }
1814
kvm_init_nested_state(CPUX86State * env)1815 static void kvm_init_nested_state(CPUX86State *env)
1816 {
1817 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1818 uint32_t size;
1819
1820 if (!env->nested_state) {
1821 return;
1822 }
1823
1824 size = env->nested_state->size;
1825
1826 memset(env->nested_state, 0, size);
1827 env->nested_state->size = size;
1828
1829 if (cpu_has_vmx(env)) {
1830 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1831 vmx_hdr = &env->nested_state->hdr.vmx;
1832 vmx_hdr->vmxon_pa = -1ull;
1833 vmx_hdr->vmcs12_pa = -1ull;
1834 } else if (cpu_has_svm(env)) {
1835 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1836 }
1837 }
1838
kvm_x86_build_cpuid(CPUX86State * env,struct kvm_cpuid_entry2 * entries,uint32_t cpuid_i)1839 uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries,
1840 uint32_t cpuid_i)
1841 {
1842 uint32_t limit, i, j;
1843 uint32_t unused;
1844 struct kvm_cpuid_entry2 *c;
1845
1846 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1847
1848 for (i = 0; i <= limit; i++) {
1849 j = 0;
1850 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1851 goto full;
1852 }
1853 c = &entries[cpuid_i++];
1854 switch (i) {
1855 case 2: {
1856 /* Keep reading function 2 till all the input is received */
1857 int times;
1858
1859 c->function = i;
1860 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1861 times = c->eax & 0xff;
1862 if (times > 1) {
1863 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1864 KVM_CPUID_FLAG_STATE_READ_NEXT;
1865 }
1866
1867 for (j = 1; j < times; ++j) {
1868 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1869 goto full;
1870 }
1871 c = &entries[cpuid_i++];
1872 c->function = i;
1873 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1874 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1875 }
1876 break;
1877 }
1878 case 0x1f:
1879 if (!x86_has_cpuid_0x1f(env_archcpu(env))) {
1880 cpuid_i--;
1881 break;
1882 }
1883 /* fallthrough */
1884 case 4:
1885 case 0xb:
1886 case 0xd:
1887 for (j = 0; ; j++) {
1888 c->function = i;
1889 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1890 c->index = j;
1891 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1892
1893 if (i == 4 && c->eax == 0) {
1894 break;
1895 }
1896 if (i == 0xb && !(c->ecx & 0xff00)) {
1897 break;
1898 }
1899 if (i == 0x1f && !(c->ecx & 0xff00)) {
1900 break;
1901 }
1902 if (i == 0xd && c->eax == 0) {
1903 if (j < 63) {
1904 continue;
1905 } else {
1906 cpuid_i--;
1907 break;
1908 }
1909 }
1910 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1911 goto full;
1912 }
1913 c = &entries[cpuid_i++];
1914 }
1915 break;
1916 case 0x12:
1917 for (j = 0; ; j++) {
1918 c->function = i;
1919 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1920 c->index = j;
1921 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1922
1923 if (j > 1 && (c->eax & 0xf) != 1) {
1924 break;
1925 }
1926
1927 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1928 goto full;
1929 }
1930 c = &entries[cpuid_i++];
1931 }
1932 break;
1933 case 0x7:
1934 case 0x14:
1935 case 0x1d:
1936 case 0x1e:
1937 case 0x24: {
1938 uint32_t times;
1939
1940 c->function = i;
1941 c->index = 0;
1942 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1943 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1944 times = c->eax;
1945
1946 for (j = 1; j <= times; ++j) {
1947 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1948 goto full;
1949 }
1950 c = &entries[cpuid_i++];
1951 c->function = i;
1952 c->index = j;
1953 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1954 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1955 }
1956 break;
1957 }
1958 default:
1959 c->function = i;
1960 c->flags = 0;
1961 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1962 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1963 /*
1964 * KVM already returns all zeroes if a CPUID entry is missing,
1965 * so we can omit it and avoid hitting KVM's 80-entry limit.
1966 */
1967 cpuid_i--;
1968 }
1969 break;
1970 }
1971 }
1972
1973 if (limit >= 0x0a) {
1974 uint32_t eax, edx;
1975
1976 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1977
1978 has_architectural_pmu_version = eax & 0xff;
1979 if (has_architectural_pmu_version > 0) {
1980 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1981
1982 /* Shouldn't be more than 32, since that's the number of bits
1983 * available in EBX to tell us _which_ counters are available.
1984 * Play it safe.
1985 */
1986 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1987 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1988 }
1989
1990 if (has_architectural_pmu_version > 1) {
1991 num_architectural_pmu_fixed_counters = edx & 0x1f;
1992
1993 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1994 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1995 }
1996 }
1997 }
1998 }
1999
2000 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
2001
2002 for (i = 0x80000000; i <= limit; i++) {
2003 j = 0;
2004 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2005 goto full;
2006 }
2007 c = &entries[cpuid_i++];
2008
2009 switch (i) {
2010 case 0x8000001d:
2011 /* Query for all AMD cache information leaves */
2012 for (j = 0; ; j++) {
2013 c->function = i;
2014 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2015 c->index = j;
2016 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2017
2018 if (c->eax == 0) {
2019 break;
2020 }
2021 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2022 goto full;
2023 }
2024 c = &entries[cpuid_i++];
2025 }
2026 break;
2027 default:
2028 c->function = i;
2029 c->flags = 0;
2030 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2031 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2032 /*
2033 * KVM already returns all zeroes if a CPUID entry is missing,
2034 * so we can omit it and avoid hitting KVM's 80-entry limit.
2035 */
2036 cpuid_i--;
2037 }
2038 break;
2039 }
2040 }
2041
2042 /* Call Centaur's CPUID instructions they are supported. */
2043 if (env->cpuid_xlevel2 > 0) {
2044 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2045
2046 for (i = 0xC0000000; i <= limit; i++) {
2047 j = 0;
2048 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2049 goto full;
2050 }
2051 c = &entries[cpuid_i++];
2052
2053 c->function = i;
2054 c->flags = 0;
2055 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2056 }
2057 }
2058
2059 return cpuid_i;
2060
2061 full:
2062 fprintf(stderr, "cpuid_data is full, no space for "
2063 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2064 abort();
2065 }
2066
kvm_arch_pre_create_vcpu(CPUState * cpu,Error ** errp)2067 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp)
2068 {
2069 if (is_tdx_vm()) {
2070 return tdx_pre_create_vcpu(cpu, errp);
2071 }
2072
2073 return 0;
2074 }
2075
kvm_arch_init_vcpu(CPUState * cs)2076 int kvm_arch_init_vcpu(CPUState *cs)
2077 {
2078 struct {
2079 struct kvm_cpuid2 cpuid;
2080 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
2081 } cpuid_data;
2082 /*
2083 * The kernel defines these structs with padding fields so there
2084 * should be no extra padding in our cpuid_data struct.
2085 */
2086 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
2087 sizeof(struct kvm_cpuid2) +
2088 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
2089
2090 X86CPU *cpu = X86_CPU(cs);
2091 CPUX86State *env = &cpu->env;
2092 uint32_t cpuid_i;
2093 struct kvm_cpuid_entry2 *c;
2094 uint32_t signature[3];
2095 int kvm_base = KVM_CPUID_SIGNATURE;
2096 int max_nested_state_len;
2097 int r;
2098 Error *local_err = NULL;
2099
2100 if (current_machine->cgs) {
2101 r = x86_confidential_guest_check_features(
2102 X86_CONFIDENTIAL_GUEST(current_machine->cgs), cs);
2103 if (r < 0) {
2104 return r;
2105 }
2106 }
2107
2108 memset(&cpuid_data, 0, sizeof(cpuid_data));
2109
2110 cpuid_i = 0;
2111
2112 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
2113
2114 r = kvm_arch_set_tsc_khz(cs);
2115 if (r < 0) {
2116 return r;
2117 }
2118
2119 /* vcpu's TSC frequency is either specified by user, or following
2120 * the value used by KVM if the former is not present. In the
2121 * latter case, we query it from KVM and record in env->tsc_khz,
2122 * so that vcpu's TSC frequency can be migrated later via this field.
2123 */
2124 if (!env->tsc_khz) {
2125 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
2126 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
2127 -ENOTSUP;
2128 if (r > 0) {
2129 env->tsc_khz = r;
2130 }
2131 }
2132
2133 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
2134
2135 /*
2136 * kvm_hyperv_expand_features() is called here for the second time in case
2137 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
2138 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
2139 * check which Hyper-V enlightenments are supported and which are not, we
2140 * can still proceed and check/expand Hyper-V enlightenments here so legacy
2141 * behavior is preserved.
2142 */
2143 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
2144 error_report_err(local_err);
2145 return -ENOSYS;
2146 }
2147
2148 if (hyperv_enabled(cpu)) {
2149 r = hyperv_init_vcpu(cpu);
2150 if (r) {
2151 return r;
2152 }
2153
2154 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
2155 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
2156 has_msr_hv_hypercall = true;
2157 }
2158
2159 if (cs->kvm_state->xen_version) {
2160 #ifdef CONFIG_XEN_EMU
2161 struct kvm_cpuid_entry2 *xen_max_leaf;
2162
2163 memcpy(signature, "XenVMMXenVMM", 12);
2164
2165 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
2166 c->function = kvm_base + XEN_CPUID_SIGNATURE;
2167 c->eax = kvm_base + XEN_CPUID_TIME;
2168 c->ebx = signature[0];
2169 c->ecx = signature[1];
2170 c->edx = signature[2];
2171
2172 c = &cpuid_data.entries[cpuid_i++];
2173 c->function = kvm_base + XEN_CPUID_VENDOR;
2174 c->eax = cs->kvm_state->xen_version;
2175 c->ebx = 0;
2176 c->ecx = 0;
2177 c->edx = 0;
2178
2179 c = &cpuid_data.entries[cpuid_i++];
2180 c->function = kvm_base + XEN_CPUID_HVM_MSR;
2181 /* Number of hypercall-transfer pages */
2182 c->eax = 1;
2183 /* Hypercall MSR base address */
2184 if (hyperv_enabled(cpu)) {
2185 c->ebx = XEN_HYPERCALL_MSR_HYPERV;
2186 kvm_xen_init(cs->kvm_state, c->ebx);
2187 } else {
2188 c->ebx = XEN_HYPERCALL_MSR;
2189 }
2190 c->ecx = 0;
2191 c->edx = 0;
2192
2193 c = &cpuid_data.entries[cpuid_i++];
2194 c->function = kvm_base + XEN_CPUID_TIME;
2195 c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
2196 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
2197 /* default=0 (emulate if necessary) */
2198 c->ebx = 0;
2199 /* guest tsc frequency */
2200 c->ecx = env->user_tsc_khz;
2201 /* guest tsc incarnation (migration count) */
2202 c->edx = 0;
2203
2204 c = &cpuid_data.entries[cpuid_i++];
2205 c->function = kvm_base + XEN_CPUID_HVM;
2206 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
2207 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
2208 c->function = kvm_base + XEN_CPUID_HVM;
2209
2210 if (cpu->xen_vapic) {
2211 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
2212 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
2213 }
2214
2215 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
2216
2217 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
2218 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
2219 c->ebx = cs->cpu_index;
2220 }
2221
2222 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) {
2223 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR;
2224 }
2225 }
2226
2227 r = kvm_xen_init_vcpu(cs);
2228 if (r) {
2229 return r;
2230 }
2231
2232 kvm_base += 0x100;
2233 #else /* CONFIG_XEN_EMU */
2234 /* This should never happen as kvm_arch_init() would have died first. */
2235 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
2236 abort();
2237 #endif
2238 } else if (cpu->expose_kvm) {
2239 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
2240 c = &cpuid_data.entries[cpuid_i++];
2241 c->function = KVM_CPUID_SIGNATURE | kvm_base;
2242 c->eax = KVM_CPUID_FEATURES | kvm_base;
2243 c->ebx = signature[0];
2244 c->ecx = signature[1];
2245 c->edx = signature[2];
2246
2247 c = &cpuid_data.entries[cpuid_i++];
2248 c->function = KVM_CPUID_FEATURES | kvm_base;
2249 c->eax = env->features[FEAT_KVM];
2250 c->edx = env->features[FEAT_KVM_HINTS];
2251 }
2252
2253 if (cpu->kvm_pv_enforce_cpuid) {
2254 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
2255 if (r < 0) {
2256 fprintf(stderr,
2257 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
2258 strerror(-r));
2259 abort();
2260 }
2261 }
2262
2263 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i);
2264 cpuid_data.cpuid.nent = cpuid_i;
2265
2266 if (x86_cpu_family(env->cpuid_version) >= 6
2267 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2268 (CPUID_MCE | CPUID_MCA)) {
2269 uint64_t mcg_cap, unsupported_caps;
2270 int banks;
2271 int ret;
2272
2273 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
2274 if (ret < 0) {
2275 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2276 return ret;
2277 }
2278
2279 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
2280 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2281 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
2282 return -ENOTSUP;
2283 }
2284
2285 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2286 if (unsupported_caps) {
2287 if (unsupported_caps & MCG_LMCE_P) {
2288 error_report("kvm: LMCE not supported");
2289 return -ENOTSUP;
2290 }
2291 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2292 unsupported_caps);
2293 }
2294
2295 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2296 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
2297 if (ret < 0) {
2298 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2299 return ret;
2300 }
2301 }
2302
2303 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
2304
2305 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2306 if (c) {
2307 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2308 !!(c->ecx & CPUID_EXT_SMX);
2309 }
2310
2311 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2312 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2313 has_msr_feature_control = true;
2314 }
2315
2316 if (env->mcg_cap & MCG_LMCE_P) {
2317 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2318 }
2319
2320 if (!env->user_tsc_khz) {
2321 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2322 invtsc_mig_blocker == NULL) {
2323 error_setg(&invtsc_mig_blocker,
2324 "State blocked by non-migratable CPU device"
2325 " (invtsc flag)");
2326 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err);
2327 if (r < 0) {
2328 error_report_err(local_err);
2329 return r;
2330 }
2331 }
2332 }
2333
2334 if (cpu->vmware_cpuid_freq
2335 /* Guests depend on 0x40000000 to detect this feature, so only expose
2336 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2337 && cpu->expose_kvm
2338 && kvm_base == KVM_CPUID_SIGNATURE
2339 /* TSC clock must be stable and known for this feature. */
2340 && tsc_is_stable_and_known(env)) {
2341
2342 c = &cpuid_data.entries[cpuid_i++];
2343 c->function = KVM_CPUID_SIGNATURE | 0x10;
2344 c->eax = env->tsc_khz;
2345 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
2346 c->ecx = c->edx = 0;
2347
2348 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2349 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2350 }
2351
2352 cpuid_data.cpuid.nent = cpuid_i;
2353
2354 cpuid_data.cpuid.padding = 0;
2355 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2356 if (r) {
2357 goto fail;
2358 }
2359 kvm_init_xsave(env);
2360
2361 max_nested_state_len = kvm_max_nested_state_length();
2362 if (max_nested_state_len > 0) {
2363 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
2364
2365 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
2366 env->nested_state = g_malloc0(max_nested_state_len);
2367 env->nested_state->size = max_nested_state_len;
2368
2369 kvm_init_nested_state(env);
2370 }
2371 }
2372
2373 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
2374
2375 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2376 has_msr_tsc_aux = false;
2377 }
2378
2379 kvm_init_msrs(cpu);
2380
2381 return 0;
2382
2383 fail:
2384 migrate_del_blocker(&invtsc_mig_blocker);
2385
2386 return r;
2387 }
2388
kvm_arch_destroy_vcpu(CPUState * cs)2389 int kvm_arch_destroy_vcpu(CPUState *cs)
2390 {
2391 X86CPU *cpu = X86_CPU(cs);
2392 CPUX86State *env = &cpu->env;
2393
2394 g_free(env->xsave_buf);
2395
2396 g_free(cpu->kvm_msr_buf);
2397 cpu->kvm_msr_buf = NULL;
2398
2399 g_free(env->nested_state);
2400 env->nested_state = NULL;
2401
2402 qemu_del_vm_change_state_handler(cpu->vmsentry);
2403
2404 return 0;
2405 }
2406
kvm_arch_reset_vcpu(X86CPU * cpu)2407 void kvm_arch_reset_vcpu(X86CPU *cpu)
2408 {
2409 CPUX86State *env = &cpu->env;
2410
2411 env->xcr0 = 1;
2412 if (kvm_irqchip_in_kernel()) {
2413 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
2414 KVM_MP_STATE_UNINITIALIZED;
2415 } else {
2416 env->mp_state = KVM_MP_STATE_RUNNABLE;
2417 }
2418
2419 /* enabled by default */
2420 env->poll_control_msr = 1;
2421
2422 kvm_init_nested_state(env);
2423
2424 sev_es_set_reset_vector(CPU(cpu));
2425 }
2426
kvm_arch_after_reset_vcpu(X86CPU * cpu)2427 void kvm_arch_after_reset_vcpu(X86CPU *cpu)
2428 {
2429 CPUX86State *env = &cpu->env;
2430 int i;
2431
2432 /*
2433 * Reset SynIC after all other devices have been reset to let them remove
2434 * their SINT routes first.
2435 */
2436 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2437 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2438 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2439 }
2440
2441 hyperv_x86_synic_reset(cpu);
2442 }
2443 }
2444
kvm_arch_reset_parked_vcpu(unsigned long vcpu_id,int kvm_fd)2445 void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd)
2446 {
2447 g_autofree struct kvm_msrs *msrs = NULL;
2448
2449 msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0]));
2450 msrs->entries[0].index = MSR_IA32_TSC;
2451 msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */
2452 msrs->nmsrs++;
2453
2454 if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) {
2455 warn_report("parked vCPU %lu TSC reset failed: %d",
2456 vcpu_id, errno);
2457 }
2458 }
2459
kvm_arch_do_init_vcpu(X86CPU * cpu)2460 void kvm_arch_do_init_vcpu(X86CPU *cpu)
2461 {
2462 CPUX86State *env = &cpu->env;
2463
2464 /* APs get directly into wait-for-SIPI state. */
2465 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2466 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2467 }
2468 }
2469
kvm_get_supported_feature_msrs(KVMState * s)2470 static int kvm_get_supported_feature_msrs(KVMState *s)
2471 {
2472 int ret = 0;
2473
2474 if (kvm_feature_msrs != NULL) {
2475 return 0;
2476 }
2477
2478 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2479 return 0;
2480 }
2481
2482 struct kvm_msr_list msr_list;
2483
2484 msr_list.nmsrs = 0;
2485 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2486 if (ret < 0 && ret != -E2BIG) {
2487 error_report("Fetch KVM feature MSR list failed: %s",
2488 strerror(-ret));
2489 return ret;
2490 }
2491
2492 assert(msr_list.nmsrs > 0);
2493 kvm_feature_msrs = g_malloc0(sizeof(msr_list) +
2494 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2495
2496 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2497 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2498
2499 if (ret < 0) {
2500 error_report("Fetch KVM feature MSR list failed: %s",
2501 strerror(-ret));
2502 g_free(kvm_feature_msrs);
2503 kvm_feature_msrs = NULL;
2504 return ret;
2505 }
2506
2507 return 0;
2508 }
2509
kvm_get_supported_msrs(KVMState * s)2510 static int kvm_get_supported_msrs(KVMState *s)
2511 {
2512 int ret = 0;
2513 struct kvm_msr_list msr_list, *kvm_msr_list;
2514
2515 /*
2516 * Obtain MSR list from KVM. These are the MSRs that we must
2517 * save/restore.
2518 */
2519 msr_list.nmsrs = 0;
2520 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2521 if (ret < 0 && ret != -E2BIG) {
2522 return ret;
2523 }
2524 /*
2525 * Old kernel modules had a bug and could write beyond the provided
2526 * memory. Allocate at least a safe amount of 1K.
2527 */
2528 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2529 msr_list.nmsrs *
2530 sizeof(msr_list.indices[0])));
2531
2532 kvm_msr_list->nmsrs = msr_list.nmsrs;
2533 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2534 if (ret >= 0) {
2535 int i;
2536
2537 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2538 switch (kvm_msr_list->indices[i]) {
2539 case MSR_STAR:
2540 has_msr_star = true;
2541 break;
2542 case MSR_VM_HSAVE_PA:
2543 has_msr_hsave_pa = true;
2544 break;
2545 case MSR_TSC_AUX:
2546 has_msr_tsc_aux = true;
2547 break;
2548 case MSR_TSC_ADJUST:
2549 has_msr_tsc_adjust = true;
2550 break;
2551 case MSR_IA32_TSCDEADLINE:
2552 has_msr_tsc_deadline = true;
2553 break;
2554 case MSR_IA32_SMBASE:
2555 has_msr_smbase = true;
2556 break;
2557 case MSR_SMI_COUNT:
2558 has_msr_smi_count = true;
2559 break;
2560 case MSR_IA32_MISC_ENABLE:
2561 has_msr_misc_enable = true;
2562 break;
2563 case MSR_IA32_BNDCFGS:
2564 has_msr_bndcfgs = true;
2565 break;
2566 case MSR_IA32_XSS:
2567 has_msr_xss = true;
2568 break;
2569 case MSR_IA32_UMWAIT_CONTROL:
2570 has_msr_umwait = true;
2571 break;
2572 case HV_X64_MSR_CRASH_CTL:
2573 has_msr_hv_crash = true;
2574 break;
2575 case HV_X64_MSR_RESET:
2576 has_msr_hv_reset = true;
2577 break;
2578 case HV_X64_MSR_VP_INDEX:
2579 has_msr_hv_vpindex = true;
2580 break;
2581 case HV_X64_MSR_VP_RUNTIME:
2582 has_msr_hv_runtime = true;
2583 break;
2584 case HV_X64_MSR_SCONTROL:
2585 has_msr_hv_synic = true;
2586 break;
2587 case HV_X64_MSR_STIMER0_CONFIG:
2588 has_msr_hv_stimer = true;
2589 break;
2590 case HV_X64_MSR_TSC_FREQUENCY:
2591 has_msr_hv_frequencies = true;
2592 break;
2593 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2594 has_msr_hv_reenlightenment = true;
2595 break;
2596 case HV_X64_MSR_SYNDBG_OPTIONS:
2597 has_msr_hv_syndbg_options = true;
2598 break;
2599 case MSR_IA32_SPEC_CTRL:
2600 has_msr_spec_ctrl = true;
2601 break;
2602 case MSR_AMD64_TSC_RATIO:
2603 has_tsc_scale_msr = true;
2604 break;
2605 case MSR_IA32_TSX_CTRL:
2606 has_msr_tsx_ctrl = true;
2607 break;
2608 case MSR_VIRT_SSBD:
2609 has_msr_virt_ssbd = true;
2610 break;
2611 case MSR_IA32_ARCH_CAPABILITIES:
2612 has_msr_arch_capabs = true;
2613 break;
2614 case MSR_IA32_CORE_CAPABILITY:
2615 has_msr_core_capabs = true;
2616 break;
2617 case MSR_IA32_PERF_CAPABILITIES:
2618 has_msr_perf_capabs = true;
2619 break;
2620 case MSR_IA32_VMX_VMFUNC:
2621 has_msr_vmx_vmfunc = true;
2622 break;
2623 case MSR_IA32_UCODE_REV:
2624 has_msr_ucode_rev = true;
2625 break;
2626 case MSR_IA32_VMX_PROCBASED_CTLS2:
2627 has_msr_vmx_procbased_ctls2 = true;
2628 break;
2629 case MSR_IA32_PKRS:
2630 has_msr_pkrs = true;
2631 break;
2632 case MSR_K7_HWCR:
2633 has_msr_hwcr = true;
2634 }
2635 }
2636 }
2637
2638 g_free(kvm_msr_list);
2639
2640 return ret;
2641 }
2642
kvm_rdmsr_core_thread_count(X86CPU * cpu,uint32_t msr,uint64_t * val)2643 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu,
2644 uint32_t msr,
2645 uint64_t *val)
2646 {
2647 *val = cpu_x86_get_msr_core_thread_count(cpu);
2648
2649 return true;
2650 }
2651
kvm_rdmsr_rapl_power_unit(X86CPU * cpu,uint32_t msr,uint64_t * val)2652 static bool kvm_rdmsr_rapl_power_unit(X86CPU *cpu,
2653 uint32_t msr,
2654 uint64_t *val)
2655 {
2656
2657 CPUState *cs = CPU(cpu);
2658
2659 *val = cs->kvm_state->msr_energy.msr_unit;
2660
2661 return true;
2662 }
2663
kvm_rdmsr_pkg_power_limit(X86CPU * cpu,uint32_t msr,uint64_t * val)2664 static bool kvm_rdmsr_pkg_power_limit(X86CPU *cpu,
2665 uint32_t msr,
2666 uint64_t *val)
2667 {
2668
2669 CPUState *cs = CPU(cpu);
2670
2671 *val = cs->kvm_state->msr_energy.msr_limit;
2672
2673 return true;
2674 }
2675
kvm_rdmsr_pkg_power_info(X86CPU * cpu,uint32_t msr,uint64_t * val)2676 static bool kvm_rdmsr_pkg_power_info(X86CPU *cpu,
2677 uint32_t msr,
2678 uint64_t *val)
2679 {
2680
2681 CPUState *cs = CPU(cpu);
2682
2683 *val = cs->kvm_state->msr_energy.msr_info;
2684
2685 return true;
2686 }
2687
kvm_rdmsr_pkg_energy_status(X86CPU * cpu,uint32_t msr,uint64_t * val)2688 static bool kvm_rdmsr_pkg_energy_status(X86CPU *cpu,
2689 uint32_t msr,
2690 uint64_t *val)
2691 {
2692
2693 CPUState *cs = CPU(cpu);
2694 *val = cs->kvm_state->msr_energy.msr_value[cs->cpu_index];
2695
2696 return true;
2697 }
2698
2699 static Notifier smram_machine_done;
2700 static KVMMemoryListener smram_listener;
2701 static AddressSpace smram_address_space;
2702 static MemoryRegion smram_as_root;
2703 static MemoryRegion smram_as_mem;
2704
register_smram_listener(Notifier * n,void * unused)2705 static void register_smram_listener(Notifier *n, void *unused)
2706 {
2707 MemoryRegion *smram =
2708 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2709
2710 /* Outer container... */
2711 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2712 memory_region_set_enabled(&smram_as_root, true);
2713
2714 /* ... with two regions inside: normal system memory with low
2715 * priority, and...
2716 */
2717 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2718 get_system_memory(), 0, ~0ull);
2719 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2720 memory_region_set_enabled(&smram_as_mem, true);
2721
2722 if (smram) {
2723 /* ... SMRAM with higher priority */
2724 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2725 memory_region_set_enabled(smram, true);
2726 }
2727
2728 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2729 kvm_memory_listener_register(kvm_state, &smram_listener,
2730 &smram_address_space, 1, "kvm-smram");
2731 }
2732
kvm_msr_energy_thread(void * data)2733 static void *kvm_msr_energy_thread(void *data)
2734 {
2735 KVMState *s = data;
2736 struct KVMMsrEnergy *vmsr = &s->msr_energy;
2737
2738 g_autofree vmsr_package_energy_stat *pkg_stat = NULL;
2739 g_autofree vmsr_thread_stat *thd_stat = NULL;
2740 g_autofree CPUState *cpu = NULL;
2741 g_autofree unsigned int *vpkgs_energy_stat = NULL;
2742 unsigned int num_threads = 0;
2743
2744 X86CPUTopoIDs topo_ids;
2745
2746 rcu_register_thread();
2747
2748 /* Allocate memory for each package energy status */
2749 pkg_stat = g_new0(vmsr_package_energy_stat, vmsr->host_topo.maxpkgs);
2750
2751 /* Allocate memory for thread stats */
2752 thd_stat = g_new0(vmsr_thread_stat, 1);
2753
2754 /* Allocate memory for holding virtual package energy counter */
2755 vpkgs_energy_stat = g_new0(unsigned int, vmsr->guest_vsockets);
2756
2757 /* Populate the max tick of each packages */
2758 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2759 /*
2760 * Max numbers of ticks per package
2761 * Time in second * Number of ticks/second * Number of cores/package
2762 * ex: 100 ticks/second/CPU, 12 CPUs per Package gives 1200 ticks max
2763 */
2764 vmsr->host_topo.maxticks[i] = (MSR_ENERGY_THREAD_SLEEP_US / 1000000)
2765 * sysconf(_SC_CLK_TCK)
2766 * vmsr->host_topo.pkg_cpu_count[i];
2767 }
2768
2769 while (true) {
2770 /* Get all qemu threads id */
2771 g_autofree pid_t *thread_ids
2772 = vmsr_get_thread_ids(vmsr->pid, &num_threads);
2773
2774 if (thread_ids == NULL) {
2775 goto clean;
2776 }
2777
2778 thd_stat = g_renew(vmsr_thread_stat, thd_stat, num_threads);
2779 /* Unlike g_new0, g_renew0 function doesn't exist yet... */
2780 memset(thd_stat, 0, num_threads * sizeof(vmsr_thread_stat));
2781
2782 /* Populate all the thread stats */
2783 for (int i = 0; i < num_threads; i++) {
2784 thd_stat[i].utime = g_new0(unsigned long long, 2);
2785 thd_stat[i].stime = g_new0(unsigned long long, 2);
2786 thd_stat[i].thread_id = thread_ids[i];
2787 vmsr_read_thread_stat(vmsr->pid,
2788 thd_stat[i].thread_id,
2789 &thd_stat[i].utime[0],
2790 &thd_stat[i].stime[0],
2791 &thd_stat[i].cpu_id);
2792 thd_stat[i].pkg_id =
2793 vmsr_get_physical_package_id(thd_stat[i].cpu_id);
2794 }
2795
2796 /* Retrieve all packages power plane energy counter */
2797 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2798 for (int j = 0; j < num_threads; j++) {
2799 /*
2800 * Use the first thread we found that ran on the CPU
2801 * of the package to read the packages energy counter
2802 */
2803 if (thd_stat[j].pkg_id == i) {
2804 pkg_stat[i].e_start =
2805 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2806 thd_stat[j].cpu_id,
2807 thd_stat[j].thread_id,
2808 s->msr_energy.sioc);
2809 break;
2810 }
2811 }
2812 }
2813
2814 /* Sleep a short period while the other threads are working */
2815 usleep(MSR_ENERGY_THREAD_SLEEP_US);
2816
2817 /*
2818 * Retrieve all packages power plane energy counter
2819 * Calculate the delta of all packages
2820 */
2821 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2822 for (int j = 0; j < num_threads; j++) {
2823 /*
2824 * Use the first thread we found that ran on the CPU
2825 * of the package to read the packages energy counter
2826 */
2827 if (thd_stat[j].pkg_id == i) {
2828 pkg_stat[i].e_end =
2829 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2830 thd_stat[j].cpu_id,
2831 thd_stat[j].thread_id,
2832 s->msr_energy.sioc);
2833 /*
2834 * Prevent the case we have migrate the VM
2835 * during the sleep period or any other cases
2836 * were energy counter might be lower after
2837 * the sleep period.
2838 */
2839 if (pkg_stat[i].e_end > pkg_stat[i].e_start) {
2840 pkg_stat[i].e_delta =
2841 pkg_stat[i].e_end - pkg_stat[i].e_start;
2842 } else {
2843 pkg_stat[i].e_delta = 0;
2844 }
2845 break;
2846 }
2847 }
2848 }
2849
2850 /* Delta of ticks spend by each thread between the sample */
2851 for (int i = 0; i < num_threads; i++) {
2852 vmsr_read_thread_stat(vmsr->pid,
2853 thd_stat[i].thread_id,
2854 &thd_stat[i].utime[1],
2855 &thd_stat[i].stime[1],
2856 &thd_stat[i].cpu_id);
2857
2858 if (vmsr->pid < 0) {
2859 /*
2860 * We don't count the dead thread
2861 * i.e threads that existed before the sleep
2862 * and not anymore
2863 */
2864 thd_stat[i].delta_ticks = 0;
2865 } else {
2866 vmsr_delta_ticks(thd_stat, i);
2867 }
2868 }
2869
2870 /*
2871 * Identify the vcpu threads
2872 * Calculate the number of vcpu per package
2873 */
2874 CPU_FOREACH(cpu) {
2875 for (int i = 0; i < num_threads; i++) {
2876 if (cpu->thread_id == thd_stat[i].thread_id) {
2877 thd_stat[i].is_vcpu = true;
2878 thd_stat[i].vcpu_id = cpu->cpu_index;
2879 pkg_stat[thd_stat[i].pkg_id].nb_vcpu++;
2880 thd_stat[i].acpi_id = kvm_arch_vcpu_id(cpu);
2881 break;
2882 }
2883 }
2884 }
2885
2886 /* Retrieve the virtual package number of each vCPU */
2887 for (int i = 0; i < vmsr->guest_cpu_list->len; i++) {
2888 for (int j = 0; j < num_threads; j++) {
2889 if ((thd_stat[j].acpi_id ==
2890 vmsr->guest_cpu_list->cpus[i].arch_id)
2891 && (thd_stat[j].is_vcpu == true)) {
2892 x86_topo_ids_from_apicid(thd_stat[j].acpi_id,
2893 &vmsr->guest_topo_info, &topo_ids);
2894 thd_stat[j].vpkg_id = topo_ids.pkg_id;
2895 }
2896 }
2897 }
2898
2899 /* Calculate the total energy of all non-vCPU thread */
2900 for (int i = 0; i < num_threads; i++) {
2901 if ((thd_stat[i].is_vcpu != true) &&
2902 (thd_stat[i].delta_ticks > 0)) {
2903 double temp;
2904 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2905 thd_stat[i].delta_ticks,
2906 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2907 pkg_stat[thd_stat[i].pkg_id].e_ratio
2908 += (uint64_t)lround(temp);
2909 }
2910 }
2911
2912 /* Calculate the ratio per non-vCPU thread of each package */
2913 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2914 if (pkg_stat[i].nb_vcpu > 0) {
2915 pkg_stat[i].e_ratio = pkg_stat[i].e_ratio / pkg_stat[i].nb_vcpu;
2916 }
2917 }
2918
2919 /*
2920 * Calculate the energy for each Package:
2921 * Energy Package = sum of each vCPU energy that belongs to the package
2922 */
2923 for (int i = 0; i < num_threads; i++) {
2924 if ((thd_stat[i].is_vcpu == true) && \
2925 (thd_stat[i].delta_ticks > 0)) {
2926 double temp;
2927 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2928 thd_stat[i].delta_ticks,
2929 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2930 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2931 (uint64_t)lround(temp);
2932 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2933 pkg_stat[thd_stat[i].pkg_id].e_ratio;
2934 }
2935 }
2936
2937 /*
2938 * Finally populate the vmsr register of each vCPU with the total
2939 * package value to emulate the real hardware where each CPU return the
2940 * value of the package it belongs.
2941 */
2942 for (int i = 0; i < num_threads; i++) {
2943 if ((thd_stat[i].is_vcpu == true) && \
2944 (thd_stat[i].delta_ticks > 0)) {
2945 vmsr->msr_value[thd_stat[i].vcpu_id] = \
2946 vpkgs_energy_stat[thd_stat[i].vpkg_id];
2947 }
2948 }
2949
2950 /* Freeing memory before zeroing the pointer */
2951 for (int i = 0; i < num_threads; i++) {
2952 g_free(thd_stat[i].utime);
2953 g_free(thd_stat[i].stime);
2954 }
2955 }
2956
2957 clean:
2958 rcu_unregister_thread();
2959 return NULL;
2960 }
2961
kvm_msr_energy_thread_init(KVMState * s,MachineState * ms)2962 static int kvm_msr_energy_thread_init(KVMState *s, MachineState *ms)
2963 {
2964 MachineClass *mc = MACHINE_GET_CLASS(ms);
2965 struct KVMMsrEnergy *r = &s->msr_energy;
2966
2967 /*
2968 * Sanity check
2969 * 1. Host cpu must be Intel cpu
2970 * 2. RAPL must be enabled on the Host
2971 */
2972 if (!is_host_cpu_intel()) {
2973 error_report("The RAPL feature can only be enabled on hosts "
2974 "with Intel CPU models");
2975 return -1;
2976 }
2977
2978 if (!is_rapl_enabled()) {
2979 return -1;
2980 }
2981
2982 /* Retrieve the virtual topology */
2983 vmsr_init_topo_info(&r->guest_topo_info, ms);
2984
2985 /* Retrieve the number of vcpu */
2986 r->guest_vcpus = ms->smp.cpus;
2987
2988 /* Retrieve the number of virtual sockets */
2989 r->guest_vsockets = ms->smp.sockets;
2990
2991 /* Allocate register memory (MSR_PKG_STATUS) for each vcpu */
2992 r->msr_value = g_new0(uint64_t, r->guest_vcpus);
2993
2994 /* Retrieve the CPUArchIDlist */
2995 r->guest_cpu_list = mc->possible_cpu_arch_ids(ms);
2996
2997 /* Max number of cpus on the Host */
2998 r->host_topo.maxcpus = vmsr_get_maxcpus();
2999 if (r->host_topo.maxcpus == 0) {
3000 error_report("host max cpus = 0");
3001 return -1;
3002 }
3003
3004 /* Max number of packages on the host */
3005 r->host_topo.maxpkgs = vmsr_get_max_physical_package(r->host_topo.maxcpus);
3006 if (r->host_topo.maxpkgs == 0) {
3007 error_report("host max pkgs = 0");
3008 return -1;
3009 }
3010
3011 /* Allocate memory for each package on the host */
3012 r->host_topo.pkg_cpu_count = g_new0(unsigned int, r->host_topo.maxpkgs);
3013 r->host_topo.maxticks = g_new0(unsigned int, r->host_topo.maxpkgs);
3014
3015 vmsr_count_cpus_per_package(r->host_topo.pkg_cpu_count,
3016 r->host_topo.maxpkgs);
3017 for (int i = 0; i < r->host_topo.maxpkgs; i++) {
3018 if (r->host_topo.pkg_cpu_count[i] == 0) {
3019 error_report("cpu per packages = 0 on package_%d", i);
3020 return -1;
3021 }
3022 }
3023
3024 /* Get QEMU PID*/
3025 r->pid = getpid();
3026
3027 /* Compute the socket path if necessary */
3028 if (s->msr_energy.socket_path == NULL) {
3029 s->msr_energy.socket_path = vmsr_compute_default_paths();
3030 }
3031
3032 /* Open socket with vmsr helper */
3033 s->msr_energy.sioc = vmsr_open_socket(s->msr_energy.socket_path);
3034
3035 if (s->msr_energy.sioc == NULL) {
3036 error_report("vmsr socket opening failed");
3037 return -1;
3038 }
3039
3040 /* Those MSR values should not change */
3041 r->msr_unit = vmsr_read_msr(MSR_RAPL_POWER_UNIT, 0, r->pid,
3042 s->msr_energy.sioc);
3043 r->msr_limit = vmsr_read_msr(MSR_PKG_POWER_LIMIT, 0, r->pid,
3044 s->msr_energy.sioc);
3045 r->msr_info = vmsr_read_msr(MSR_PKG_POWER_INFO, 0, r->pid,
3046 s->msr_energy.sioc);
3047 if (r->msr_unit == 0 || r->msr_limit == 0 || r->msr_info == 0) {
3048 error_report("can't read any virtual msr");
3049 return -1;
3050 }
3051
3052 qemu_thread_create(&r->msr_thr, "kvm-msr",
3053 kvm_msr_energy_thread,
3054 s, QEMU_THREAD_JOINABLE);
3055 return 0;
3056 }
3057
kvm_arch_get_default_type(MachineState * ms)3058 int kvm_arch_get_default_type(MachineState *ms)
3059 {
3060 return 0;
3061 }
3062
kvm_vm_enable_exception_payload(KVMState * s)3063 static int kvm_vm_enable_exception_payload(KVMState *s)
3064 {
3065 int ret = 0;
3066 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
3067 if (has_exception_payload) {
3068 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
3069 if (ret < 0) {
3070 error_report("kvm: Failed to enable exception payload cap: %s",
3071 strerror(-ret));
3072 }
3073 }
3074
3075 return ret;
3076 }
3077
kvm_vm_enable_triple_fault_event(KVMState * s)3078 static int kvm_vm_enable_triple_fault_event(KVMState *s)
3079 {
3080 int ret = 0;
3081 has_triple_fault_event = \
3082 kvm_check_extension(s,
3083 KVM_CAP_X86_TRIPLE_FAULT_EVENT);
3084 if (has_triple_fault_event) {
3085 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
3086 if (ret < 0) {
3087 error_report("kvm: Failed to enable triple fault event cap: %s",
3088 strerror(-ret));
3089 }
3090 }
3091 return ret;
3092 }
3093
kvm_vm_set_identity_map_addr(KVMState * s,uint64_t identity_base)3094 static int kvm_vm_set_identity_map_addr(KVMState *s, uint64_t identity_base)
3095 {
3096 return kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
3097 }
3098
kvm_vm_set_nr_mmu_pages(KVMState * s)3099 static int kvm_vm_set_nr_mmu_pages(KVMState *s)
3100 {
3101 uint64_t shadow_mem;
3102 int ret = 0;
3103 shadow_mem = object_property_get_int(OBJECT(s),
3104 "kvm-shadow-mem",
3105 &error_abort);
3106 if (shadow_mem != -1) {
3107 shadow_mem /= 4096;
3108 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
3109 }
3110 return ret;
3111 }
3112
kvm_vm_set_tss_addr(KVMState * s,uint64_t tss_base)3113 static int kvm_vm_set_tss_addr(KVMState *s, uint64_t tss_base)
3114 {
3115 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, tss_base);
3116 }
3117
kvm_vm_enable_disable_exits(KVMState * s)3118 static int kvm_vm_enable_disable_exits(KVMState *s)
3119 {
3120 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
3121
3122 if (disable_exits) {
3123 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
3124 KVM_X86_DISABLE_EXITS_HLT |
3125 KVM_X86_DISABLE_EXITS_PAUSE |
3126 KVM_X86_DISABLE_EXITS_CSTATE);
3127 }
3128
3129 return kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
3130 disable_exits);
3131 }
3132
kvm_vm_enable_bus_lock_exit(KVMState * s)3133 static int kvm_vm_enable_bus_lock_exit(KVMState *s)
3134 {
3135 int ret = 0;
3136 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
3137 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
3138 error_report("kvm: bus lock detection unsupported");
3139 return -ENOTSUP;
3140 }
3141 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
3142 KVM_BUS_LOCK_DETECTION_EXIT);
3143 if (ret < 0) {
3144 error_report("kvm: Failed to enable bus lock detection cap: %s",
3145 strerror(-ret));
3146 }
3147
3148 return ret;
3149 }
3150
kvm_vm_enable_notify_vmexit(KVMState * s)3151 static int kvm_vm_enable_notify_vmexit(KVMState *s)
3152 {
3153 int ret = 0;
3154 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE) {
3155 uint64_t notify_window_flags =
3156 ((uint64_t)s->notify_window << 32) |
3157 KVM_X86_NOTIFY_VMEXIT_ENABLED |
3158 KVM_X86_NOTIFY_VMEXIT_USER;
3159 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
3160 notify_window_flags);
3161 if (ret < 0) {
3162 error_report("kvm: Failed to enable notify vmexit cap: %s",
3163 strerror(-ret));
3164 }
3165 }
3166 return ret;
3167 }
3168
kvm_vm_enable_userspace_msr(KVMState * s)3169 static int kvm_vm_enable_userspace_msr(KVMState *s)
3170 {
3171 int ret;
3172
3173 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0,
3174 KVM_MSR_EXIT_REASON_FILTER);
3175 if (ret < 0) {
3176 error_report("Could not enable user space MSRs: %s",
3177 strerror(-ret));
3178 exit(1);
3179 }
3180
3181 ret = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT,
3182 kvm_rdmsr_core_thread_count, NULL);
3183 if (ret < 0) {
3184 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s",
3185 strerror(-ret));
3186 exit(1);
3187 }
3188
3189 return 0;
3190 }
3191
kvm_vm_enable_energy_msrs(KVMState * s)3192 static int kvm_vm_enable_energy_msrs(KVMState *s)
3193 {
3194 int ret;
3195
3196 if (s->msr_energy.enable == true) {
3197 ret = kvm_filter_msr(s, MSR_RAPL_POWER_UNIT,
3198 kvm_rdmsr_rapl_power_unit, NULL);
3199 if (ret < 0) {
3200 error_report("Could not install MSR_RAPL_POWER_UNIT handler: %s",
3201 strerror(-ret));
3202 return ret;
3203 }
3204
3205 ret = kvm_filter_msr(s, MSR_PKG_POWER_LIMIT,
3206 kvm_rdmsr_pkg_power_limit, NULL);
3207 if (ret < 0) {
3208 error_report("Could not install MSR_PKG_POWER_LIMIT handler: %s",
3209 strerror(-ret));
3210 return ret;
3211 }
3212
3213 ret = kvm_filter_msr(s, MSR_PKG_POWER_INFO,
3214 kvm_rdmsr_pkg_power_info, NULL);
3215 if (ret < 0) {
3216 error_report("Could not install MSR_PKG_POWER_INFO handler: %s",
3217 strerror(-ret));
3218 return ret;
3219 }
3220 ret = kvm_filter_msr(s, MSR_PKG_ENERGY_STATUS,
3221 kvm_rdmsr_pkg_energy_status, NULL);
3222 if (ret < 0) {
3223 error_report("Could not install MSR_PKG_ENERGY_STATUS handler: %s",
3224 strerror(-ret));
3225 return ret;
3226 }
3227 }
3228 return 0;
3229 }
3230
kvm_arch_init(MachineState * ms,KVMState * s)3231 int kvm_arch_init(MachineState *ms, KVMState *s)
3232 {
3233 int ret;
3234 struct utsname utsname;
3235 Error *local_err = NULL;
3236
3237 /*
3238 * Initialize confidential guest (SEV/TDX) context, if required
3239 */
3240 if (ms->cgs) {
3241 ret = confidential_guest_kvm_init(ms->cgs, &local_err);
3242 if (ret < 0) {
3243 error_report_err(local_err);
3244 return ret;
3245 }
3246 }
3247
3248 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
3249 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
3250
3251 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
3252
3253 ret = kvm_vm_enable_exception_payload(s);
3254 if (ret < 0) {
3255 return ret;
3256 }
3257
3258 ret = kvm_vm_enable_triple_fault_event(s);
3259 if (ret < 0) {
3260 return ret;
3261 }
3262
3263 if (s->xen_version) {
3264 #ifdef CONFIG_XEN_EMU
3265 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) {
3266 error_report("kvm: Xen support only available in PC machine");
3267 return -ENOTSUP;
3268 }
3269 /* hyperv_enabled() doesn't work yet. */
3270 uint32_t msr = XEN_HYPERCALL_MSR;
3271 ret = kvm_xen_init(s, msr);
3272 if (ret < 0) {
3273 return ret;
3274 }
3275 #else
3276 error_report("kvm: Xen support not enabled in qemu");
3277 return -ENOTSUP;
3278 #endif
3279 }
3280
3281 ret = kvm_get_supported_msrs(s);
3282 if (ret < 0) {
3283 return ret;
3284 }
3285
3286 ret = kvm_get_supported_feature_msrs(s);
3287 if (ret < 0) {
3288 return ret;
3289 }
3290
3291 uname(&utsname);
3292 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
3293
3294 ret = kvm_vm_set_identity_map_addr(s, KVM_IDENTITY_BASE);
3295 if (ret < 0) {
3296 return ret;
3297 }
3298
3299 /* Set TSS base one page after EPT identity map. */
3300 ret = kvm_vm_set_tss_addr(s, KVM_IDENTITY_BASE + 0x1000);
3301 if (ret < 0) {
3302 return ret;
3303 }
3304
3305 /* Tell fw_cfg to notify the BIOS to reserve the range. */
3306 e820_add_entry(KVM_IDENTITY_BASE, 0x4000, E820_RESERVED);
3307
3308 ret = kvm_vm_set_nr_mmu_pages(s);
3309 if (ret < 0) {
3310 return ret;
3311 }
3312
3313 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
3314 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
3315 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
3316 smram_machine_done.notify = register_smram_listener;
3317 qemu_add_machine_init_done_notifier(&smram_machine_done);
3318 }
3319
3320 if (enable_cpu_pm) {
3321 ret = kvm_vm_enable_disable_exits(s);
3322 if (ret < 0) {
3323 error_report("kvm: guest stopping CPU not supported: %s",
3324 strerror(-ret));
3325 return ret;
3326 }
3327 }
3328
3329 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
3330 X86MachineState *x86ms = X86_MACHINE(ms);
3331
3332 if (x86ms->bus_lock_ratelimit > 0) {
3333 ret = kvm_vm_enable_bus_lock_exit(s);
3334 if (ret < 0) {
3335 return ret;
3336 }
3337 ratelimit_init(&bus_lock_ratelimit_ctrl);
3338 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
3339 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
3340 }
3341 }
3342
3343 if (kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
3344 ret = kvm_vm_enable_notify_vmexit(s);
3345 if (ret < 0) {
3346 return ret;
3347 }
3348 }
3349
3350 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) {
3351 ret = kvm_vm_enable_userspace_msr(s);
3352 if (ret < 0) {
3353 return ret;
3354 }
3355
3356 if (s->msr_energy.enable == true) {
3357 ret = kvm_vm_enable_energy_msrs(s);
3358 if (ret < 0) {
3359 return ret;
3360 }
3361
3362 ret = kvm_msr_energy_thread_init(s, ms);
3363 if (ret < 0) {
3364 error_report("kvm : error RAPL feature requirement not met");
3365 return ret;
3366 }
3367 }
3368 }
3369
3370 return 0;
3371 }
3372
set_v8086_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3373 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3374 {
3375 lhs->selector = rhs->selector;
3376 lhs->base = rhs->base;
3377 lhs->limit = rhs->limit;
3378 lhs->type = 3;
3379 lhs->present = 1;
3380 lhs->dpl = 3;
3381 lhs->db = 0;
3382 lhs->s = 1;
3383 lhs->l = 0;
3384 lhs->g = 0;
3385 lhs->avl = 0;
3386 lhs->unusable = 0;
3387 }
3388
set_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3389 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3390 {
3391 unsigned flags = rhs->flags;
3392 lhs->selector = rhs->selector;
3393 lhs->base = rhs->base;
3394 lhs->limit = rhs->limit;
3395 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
3396 lhs->present = (flags & DESC_P_MASK) != 0;
3397 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
3398 lhs->db = (flags >> DESC_B_SHIFT) & 1;
3399 lhs->s = (flags & DESC_S_MASK) != 0;
3400 lhs->l = (flags >> DESC_L_SHIFT) & 1;
3401 lhs->g = (flags & DESC_G_MASK) != 0;
3402 lhs->avl = (flags & DESC_AVL_MASK) != 0;
3403 lhs->unusable = !lhs->present;
3404 lhs->padding = 0;
3405 }
3406
get_seg(SegmentCache * lhs,const struct kvm_segment * rhs)3407 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
3408 {
3409 lhs->selector = rhs->selector;
3410 lhs->base = rhs->base;
3411 lhs->limit = rhs->limit;
3412 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
3413 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
3414 (rhs->dpl << DESC_DPL_SHIFT) |
3415 (rhs->db << DESC_B_SHIFT) |
3416 (rhs->s * DESC_S_MASK) |
3417 (rhs->l << DESC_L_SHIFT) |
3418 (rhs->g * DESC_G_MASK) |
3419 (rhs->avl * DESC_AVL_MASK);
3420 }
3421
kvm_getput_reg(__u64 * kvm_reg,target_ulong * qemu_reg,int set)3422 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
3423 {
3424 if (set) {
3425 *kvm_reg = *qemu_reg;
3426 } else {
3427 *qemu_reg = *kvm_reg;
3428 }
3429 }
3430
kvm_getput_regs(X86CPU * cpu,int set)3431 static int kvm_getput_regs(X86CPU *cpu, int set)
3432 {
3433 CPUX86State *env = &cpu->env;
3434 struct kvm_regs regs;
3435 int ret = 0;
3436
3437 if (!set) {
3438 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s);
3439 if (ret < 0) {
3440 return ret;
3441 }
3442 }
3443
3444 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
3445 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
3446 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
3447 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
3448 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
3449 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
3450 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
3451 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
3452 #ifdef TARGET_X86_64
3453 kvm_getput_reg(®s.r8, &env->regs[8], set);
3454 kvm_getput_reg(®s.r9, &env->regs[9], set);
3455 kvm_getput_reg(®s.r10, &env->regs[10], set);
3456 kvm_getput_reg(®s.r11, &env->regs[11], set);
3457 kvm_getput_reg(®s.r12, &env->regs[12], set);
3458 kvm_getput_reg(®s.r13, &env->regs[13], set);
3459 kvm_getput_reg(®s.r14, &env->regs[14], set);
3460 kvm_getput_reg(®s.r15, &env->regs[15], set);
3461 #endif
3462
3463 kvm_getput_reg(®s.rflags, &env->eflags, set);
3464 kvm_getput_reg(®s.rip, &env->eip, set);
3465
3466 if (set) {
3467 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s);
3468 }
3469
3470 return ret;
3471 }
3472
kvm_put_xsave(X86CPU * cpu)3473 static int kvm_put_xsave(X86CPU *cpu)
3474 {
3475 CPUX86State *env = &cpu->env;
3476 void *xsave = env->xsave_buf;
3477
3478 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
3479
3480 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
3481 }
3482
kvm_put_xcrs(X86CPU * cpu)3483 static int kvm_put_xcrs(X86CPU *cpu)
3484 {
3485 CPUX86State *env = &cpu->env;
3486 struct kvm_xcrs xcrs = {};
3487
3488 if (!has_xcrs) {
3489 return 0;
3490 }
3491
3492 xcrs.nr_xcrs = 1;
3493 xcrs.flags = 0;
3494 xcrs.xcrs[0].xcr = 0;
3495 xcrs.xcrs[0].value = env->xcr0;
3496 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
3497 }
3498
kvm_put_sregs(X86CPU * cpu)3499 static int kvm_put_sregs(X86CPU *cpu)
3500 {
3501 CPUX86State *env = &cpu->env;
3502 struct kvm_sregs sregs;
3503
3504 /*
3505 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
3506 * always followed by KVM_SET_VCPU_EVENTS.
3507 */
3508 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
3509
3510 if ((env->eflags & VM_MASK)) {
3511 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3512 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3513 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3514 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3515 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3516 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3517 } else {
3518 set_seg(&sregs.cs, &env->segs[R_CS]);
3519 set_seg(&sregs.ds, &env->segs[R_DS]);
3520 set_seg(&sregs.es, &env->segs[R_ES]);
3521 set_seg(&sregs.fs, &env->segs[R_FS]);
3522 set_seg(&sregs.gs, &env->segs[R_GS]);
3523 set_seg(&sregs.ss, &env->segs[R_SS]);
3524 }
3525
3526 set_seg(&sregs.tr, &env->tr);
3527 set_seg(&sregs.ldt, &env->ldt);
3528
3529 sregs.idt.limit = env->idt.limit;
3530 sregs.idt.base = env->idt.base;
3531 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3532 sregs.gdt.limit = env->gdt.limit;
3533 sregs.gdt.base = env->gdt.base;
3534 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3535
3536 sregs.cr0 = env->cr[0];
3537 sregs.cr2 = env->cr[2];
3538 sregs.cr3 = env->cr[3];
3539 sregs.cr4 = env->cr[4];
3540
3541 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3542 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3543
3544 sregs.efer = env->efer;
3545
3546 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
3547 }
3548
kvm_put_sregs2(X86CPU * cpu)3549 static int kvm_put_sregs2(X86CPU *cpu)
3550 {
3551 CPUX86State *env = &cpu->env;
3552 struct kvm_sregs2 sregs;
3553 int i;
3554
3555 sregs.flags = 0;
3556
3557 if ((env->eflags & VM_MASK)) {
3558 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3559 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3560 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3561 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3562 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3563 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3564 } else {
3565 set_seg(&sregs.cs, &env->segs[R_CS]);
3566 set_seg(&sregs.ds, &env->segs[R_DS]);
3567 set_seg(&sregs.es, &env->segs[R_ES]);
3568 set_seg(&sregs.fs, &env->segs[R_FS]);
3569 set_seg(&sregs.gs, &env->segs[R_GS]);
3570 set_seg(&sregs.ss, &env->segs[R_SS]);
3571 }
3572
3573 set_seg(&sregs.tr, &env->tr);
3574 set_seg(&sregs.ldt, &env->ldt);
3575
3576 sregs.idt.limit = env->idt.limit;
3577 sregs.idt.base = env->idt.base;
3578 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3579 sregs.gdt.limit = env->gdt.limit;
3580 sregs.gdt.base = env->gdt.base;
3581 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3582
3583 sregs.cr0 = env->cr[0];
3584 sregs.cr2 = env->cr[2];
3585 sregs.cr3 = env->cr[3];
3586 sregs.cr4 = env->cr[4];
3587
3588 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3589 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3590
3591 sregs.efer = env->efer;
3592
3593 if (env->pdptrs_valid) {
3594 for (i = 0; i < 4; i++) {
3595 sregs.pdptrs[i] = env->pdptrs[i];
3596 }
3597 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
3598 }
3599
3600 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
3601 }
3602
3603
kvm_msr_buf_reset(X86CPU * cpu)3604 static void kvm_msr_buf_reset(X86CPU *cpu)
3605 {
3606 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
3607 }
3608
kvm_msr_entry_add(X86CPU * cpu,uint32_t index,uint64_t value)3609 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
3610 {
3611 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
3612 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
3613 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
3614
3615 assert((void *)(entry + 1) <= limit);
3616
3617 entry->index = index;
3618 entry->reserved = 0;
3619 entry->data = value;
3620 msrs->nmsrs++;
3621 }
3622
kvm_put_one_msr(X86CPU * cpu,int index,uint64_t value)3623 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
3624 {
3625 kvm_msr_buf_reset(cpu);
3626 kvm_msr_entry_add(cpu, index, value);
3627
3628 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3629 }
3630
kvm_get_one_msr(X86CPU * cpu,int index,uint64_t * value)3631 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
3632 {
3633 int ret;
3634 struct {
3635 struct kvm_msrs info;
3636 struct kvm_msr_entry entries[1];
3637 } msr_data = {
3638 .info.nmsrs = 1,
3639 .entries[0].index = index,
3640 };
3641
3642 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
3643 if (ret < 0) {
3644 return ret;
3645 }
3646 assert(ret == 1);
3647 *value = msr_data.entries[0].data;
3648 return ret;
3649 }
kvm_put_apicbase(X86CPU * cpu,uint64_t value)3650 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
3651 {
3652 int ret;
3653
3654 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
3655 assert(ret == 1);
3656 }
3657
kvm_put_tscdeadline_msr(X86CPU * cpu)3658 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
3659 {
3660 CPUX86State *env = &cpu->env;
3661 int ret;
3662
3663 if (!has_msr_tsc_deadline) {
3664 return 0;
3665 }
3666
3667 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
3668 if (ret < 0) {
3669 return ret;
3670 }
3671
3672 assert(ret == 1);
3673 return 0;
3674 }
3675
3676 /*
3677 * Provide a separate write service for the feature control MSR in order to
3678 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
3679 * before writing any other state because forcibly leaving nested mode
3680 * invalidates the VCPU state.
3681 */
kvm_put_msr_feature_control(X86CPU * cpu)3682 static int kvm_put_msr_feature_control(X86CPU *cpu)
3683 {
3684 int ret;
3685
3686 if (!has_msr_feature_control) {
3687 return 0;
3688 }
3689
3690 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
3691 cpu->env.msr_ia32_feature_control);
3692 if (ret < 0) {
3693 return ret;
3694 }
3695
3696 assert(ret == 1);
3697 return 0;
3698 }
3699
make_vmx_msr_value(uint32_t index,uint32_t features)3700 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
3701 {
3702 uint32_t default1, can_be_one, can_be_zero;
3703 uint32_t must_be_one;
3704
3705 switch (index) {
3706 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3707 default1 = 0x00000016;
3708 break;
3709 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3710 default1 = 0x0401e172;
3711 break;
3712 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3713 default1 = 0x000011ff;
3714 break;
3715 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3716 default1 = 0x00036dff;
3717 break;
3718 case MSR_IA32_VMX_PROCBASED_CTLS2:
3719 default1 = 0;
3720 break;
3721 default:
3722 abort();
3723 }
3724
3725 /* If a feature bit is set, the control can be either set or clear.
3726 * Otherwise the value is limited to either 0 or 1 by default1.
3727 */
3728 can_be_one = features | default1;
3729 can_be_zero = features | ~default1;
3730 must_be_one = ~can_be_zero;
3731
3732 /*
3733 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3734 * Bit 32:63 -> 1 if the control bit can be one.
3735 */
3736 return must_be_one | (((uint64_t)can_be_one) << 32);
3737 }
3738
kvm_msr_entry_add_vmx(X86CPU * cpu,FeatureWordArray f)3739 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3740 {
3741 uint64_t kvm_vmx_basic =
3742 kvm_arch_get_supported_msr_feature(kvm_state,
3743 MSR_IA32_VMX_BASIC);
3744
3745 if (!kvm_vmx_basic) {
3746 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3747 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3748 */
3749 return;
3750 }
3751
3752 uint64_t kvm_vmx_misc =
3753 kvm_arch_get_supported_msr_feature(kvm_state,
3754 MSR_IA32_VMX_MISC);
3755 uint64_t kvm_vmx_ept_vpid =
3756 kvm_arch_get_supported_msr_feature(kvm_state,
3757 MSR_IA32_VMX_EPT_VPID_CAP);
3758
3759 /*
3760 * If the guest is 64-bit, a value of 1 is allowed for the host address
3761 * space size vmexit control.
3762 */
3763 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3764 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3765
3766 /*
3767 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3768 * not change them for backwards compatibility.
3769 */
3770 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3771 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3772 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3773 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3774
3775 /*
3776 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3777 * change in the future but are always zero for now, clear them to be
3778 * future proof. Bits 32-63 in theory could change, though KVM does
3779 * not support dual-monitor treatment and probably never will; mask
3780 * them out as well.
3781 */
3782 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3783 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3784 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3785
3786 /*
3787 * EPT memory types should not change either, so we do not bother
3788 * adding features for them.
3789 */
3790 uint64_t fixed_vmx_ept_mask =
3791 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3792 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3793 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3794
3795 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3796 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3797 f[FEAT_VMX_PROCBASED_CTLS]));
3798 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3799 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3800 f[FEAT_VMX_PINBASED_CTLS]));
3801 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3802 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3803 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3804 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3805 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3806 f[FEAT_VMX_ENTRY_CTLS]));
3807 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3808 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3809 f[FEAT_VMX_SECONDARY_CTLS]));
3810 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3811 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3812 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3813 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3814 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3815 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3816 if (has_msr_vmx_vmfunc) {
3817 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3818 }
3819
3820 /*
3821 * Just to be safe, write these with constant values. The CRn_FIXED1
3822 * MSRs are generated by KVM based on the vCPU's CPUID.
3823 */
3824 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3825 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3826 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3827 CR4_VMXE_MASK);
3828
3829 if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3830 /* FRED injected-event data (0x2052). */
3831 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52);
3832 } else if (f[FEAT_VMX_EXIT_CTLS] &
3833 VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) {
3834 /* Secondary VM-exit controls (0x2044). */
3835 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x44);
3836 } else if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3837 /* TSC multiplier (0x2032). */
3838 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3839 } else {
3840 /* Preemption timer (0x482E). */
3841 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3842 }
3843 }
3844
kvm_msr_entry_add_perf(X86CPU * cpu,FeatureWordArray f)3845 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3846 {
3847 uint64_t kvm_perf_cap =
3848 kvm_arch_get_supported_msr_feature(kvm_state,
3849 MSR_IA32_PERF_CAPABILITIES);
3850
3851 if (kvm_perf_cap) {
3852 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3853 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3854 }
3855 }
3856
kvm_buf_set_msrs(X86CPU * cpu)3857 static int kvm_buf_set_msrs(X86CPU *cpu)
3858 {
3859 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3860 if (ret < 0) {
3861 return ret;
3862 }
3863
3864 if (ret < cpu->kvm_msr_buf->nmsrs) {
3865 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3866 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3867 (uint32_t)e->index, (uint64_t)e->data);
3868 }
3869
3870 assert(ret == cpu->kvm_msr_buf->nmsrs);
3871 return 0;
3872 }
3873
kvm_init_msrs(X86CPU * cpu)3874 static void kvm_init_msrs(X86CPU *cpu)
3875 {
3876 CPUX86State *env = &cpu->env;
3877
3878 kvm_msr_buf_reset(cpu);
3879
3880 if (!is_tdx_vm()) {
3881 if (has_msr_arch_capabs) {
3882 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3883 env->features[FEAT_ARCH_CAPABILITIES]);
3884 }
3885
3886 if (has_msr_core_capabs) {
3887 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3888 env->features[FEAT_CORE_CAPABILITY]);
3889 }
3890
3891 if (has_msr_perf_capabs && cpu->enable_pmu) {
3892 kvm_msr_entry_add_perf(cpu, env->features);
3893 }
3894
3895 /*
3896 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3897 * all kernels with MSR features should have them.
3898 */
3899 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3900 kvm_msr_entry_add_vmx(cpu, env->features);
3901 }
3902 }
3903
3904 if (has_msr_ucode_rev) {
3905 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3906 }
3907 assert(kvm_buf_set_msrs(cpu) == 0);
3908 }
3909
kvm_put_msrs(X86CPU * cpu,int level)3910 static int kvm_put_msrs(X86CPU *cpu, int level)
3911 {
3912 CPUX86State *env = &cpu->env;
3913 int i;
3914
3915 kvm_msr_buf_reset(cpu);
3916
3917 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3918 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3919 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3920 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
3921 if (has_msr_star) {
3922 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
3923 }
3924 if (has_msr_hsave_pa) {
3925 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
3926 }
3927 if (has_msr_tsc_aux) {
3928 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
3929 }
3930 if (has_msr_tsc_adjust) {
3931 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
3932 }
3933 if (has_msr_misc_enable) {
3934 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
3935 env->msr_ia32_misc_enable);
3936 }
3937 if (has_msr_smbase) {
3938 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
3939 }
3940 if (has_msr_smi_count) {
3941 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3942 }
3943 if (has_msr_pkrs) {
3944 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3945 }
3946 if (has_msr_bndcfgs) {
3947 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
3948 }
3949 if (has_msr_xss) {
3950 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
3951 }
3952 if (has_msr_umwait) {
3953 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3954 }
3955 if (has_msr_spec_ctrl) {
3956 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3957 }
3958 if (has_tsc_scale_msr) {
3959 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3960 }
3961
3962 if (has_msr_tsx_ctrl) {
3963 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3964 }
3965 if (has_msr_virt_ssbd) {
3966 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3967 }
3968 if (has_msr_hwcr) {
3969 kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->msr_hwcr);
3970 }
3971
3972 #ifdef TARGET_X86_64
3973 if (lm_capable_kernel) {
3974 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3975 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3976 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3977 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
3978 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3979 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0);
3980 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1);
3981 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2);
3982 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3);
3983 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvls);
3984 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1);
3985 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2);
3986 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3);
3987 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config);
3988 }
3989 }
3990 #endif
3991
3992 /*
3993 * The following MSRs have side effects on the guest or are too heavy
3994 * for normal writeback. Limit them to reset or full state updates.
3995 */
3996 if (level >= KVM_PUT_RESET_STATE) {
3997 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3998 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
3999 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
4000 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
4001 }
4002 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4003 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
4004 }
4005 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4006 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
4007 }
4008 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4009 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
4010 }
4011 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4012 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
4013 }
4014
4015 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4016 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
4017 }
4018
4019 if (has_architectural_pmu_version > 0) {
4020 if (has_architectural_pmu_version > 1) {
4021 /* Stop the counter. */
4022 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4023 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4024 }
4025
4026 /* Set the counter values. */
4027 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4028 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
4029 env->msr_fixed_counters[i]);
4030 }
4031 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4032 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
4033 env->msr_gp_counters[i]);
4034 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
4035 env->msr_gp_evtsel[i]);
4036 }
4037 if (has_architectural_pmu_version > 1) {
4038 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
4039 env->msr_global_status);
4040 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
4041 env->msr_global_ovf_ctrl);
4042
4043 /* Now start the PMU. */
4044 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
4045 env->msr_fixed_ctr_ctrl);
4046 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
4047 env->msr_global_ctrl);
4048 }
4049 }
4050 /*
4051 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
4052 * only sync them to KVM on the first cpu
4053 */
4054 if (current_cpu == first_cpu) {
4055 if (has_msr_hv_hypercall) {
4056 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
4057 env->msr_hv_guest_os_id);
4058 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
4059 env->msr_hv_hypercall);
4060 }
4061 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4062 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
4063 env->msr_hv_tsc);
4064 }
4065 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4066 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
4067 env->msr_hv_reenlightenment_control);
4068 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
4069 env->msr_hv_tsc_emulation_control);
4070 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
4071 env->msr_hv_tsc_emulation_status);
4072 }
4073 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
4074 has_msr_hv_syndbg_options) {
4075 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
4076 hyperv_syndbg_query_options());
4077 }
4078 }
4079 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4080 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
4081 env->msr_hv_vapic);
4082 }
4083 if (has_msr_hv_crash) {
4084 int j;
4085
4086 for (j = 0; j < HV_CRASH_PARAMS; j++)
4087 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
4088 env->msr_hv_crash_params[j]);
4089
4090 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
4091 }
4092 if (has_msr_hv_runtime) {
4093 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
4094 }
4095 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
4096 && hv_vpindex_settable) {
4097 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
4098 hyperv_vp_index(CPU(cpu)));
4099 }
4100 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4101 int j;
4102
4103 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
4104
4105 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
4106 env->msr_hv_synic_control);
4107 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
4108 env->msr_hv_synic_evt_page);
4109 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
4110 env->msr_hv_synic_msg_page);
4111
4112 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
4113 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
4114 env->msr_hv_synic_sint[j]);
4115 }
4116 }
4117 if (has_msr_hv_stimer) {
4118 int j;
4119
4120 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
4121 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
4122 env->msr_hv_stimer_config[j]);
4123 }
4124
4125 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
4126 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
4127 env->msr_hv_stimer_count[j]);
4128 }
4129 }
4130 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4131 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
4132
4133 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
4134 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
4135 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
4136 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
4137 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
4138 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
4139 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
4140 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
4141 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
4142 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
4143 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
4144 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
4145 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4146 /* The CPU GPs if we write to a bit above the physical limit of
4147 * the host CPU (and KVM emulates that)
4148 */
4149 uint64_t mask = env->mtrr_var[i].mask;
4150 mask &= phys_mask;
4151
4152 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
4153 env->mtrr_var[i].base);
4154 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
4155 }
4156 }
4157 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4158 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
4159 0x14, 1, R_EAX) & 0x7;
4160
4161 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
4162 env->msr_rtit_ctrl);
4163 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
4164 env->msr_rtit_status);
4165 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
4166 env->msr_rtit_output_base);
4167 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
4168 env->msr_rtit_output_mask);
4169 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
4170 env->msr_rtit_cr3_match);
4171 for (i = 0; i < addr_num; i++) {
4172 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
4173 env->msr_rtit_addrs[i]);
4174 }
4175 }
4176
4177 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4178 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
4179 env->msr_ia32_sgxlepubkeyhash[0]);
4180 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
4181 env->msr_ia32_sgxlepubkeyhash[1]);
4182 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
4183 env->msr_ia32_sgxlepubkeyhash[2]);
4184 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
4185 env->msr_ia32_sgxlepubkeyhash[3]);
4186 }
4187
4188 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4189 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
4190 env->msr_xfd);
4191 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
4192 env->msr_xfd_err);
4193 }
4194
4195 if (kvm_enabled() && cpu->enable_pmu &&
4196 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4197 uint64_t depth;
4198 int ret;
4199
4200 /*
4201 * Only migrate Arch LBR states when the host Arch LBR depth
4202 * equals that of source guest's, this is to avoid mismatch
4203 * of guest/host config for the msr hence avoid unexpected
4204 * misbehavior.
4205 */
4206 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4207
4208 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
4209 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
4210 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
4211
4212 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4213 if (!env->lbr_records[i].from) {
4214 continue;
4215 }
4216 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
4217 env->lbr_records[i].from);
4218 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
4219 env->lbr_records[i].to);
4220 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
4221 env->lbr_records[i].info);
4222 }
4223 }
4224 }
4225
4226 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
4227 * kvm_put_msr_feature_control. */
4228 }
4229
4230 if (env->mcg_cap) {
4231 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
4232 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
4233 if (has_msr_mcg_ext_ctl) {
4234 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
4235 }
4236 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4237 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
4238 }
4239 }
4240
4241 return kvm_buf_set_msrs(cpu);
4242 }
4243
4244
kvm_get_xsave(X86CPU * cpu)4245 static int kvm_get_xsave(X86CPU *cpu)
4246 {
4247 CPUX86State *env = &cpu->env;
4248 void *xsave = env->xsave_buf;
4249 unsigned long type;
4250 int ret;
4251
4252 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
4253 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
4254 if (ret < 0) {
4255 return ret;
4256 }
4257 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
4258
4259 return 0;
4260 }
4261
kvm_get_xcrs(X86CPU * cpu)4262 static int kvm_get_xcrs(X86CPU *cpu)
4263 {
4264 CPUX86State *env = &cpu->env;
4265 int i, ret;
4266 struct kvm_xcrs xcrs;
4267
4268 if (!has_xcrs) {
4269 return 0;
4270 }
4271
4272 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
4273 if (ret < 0) {
4274 return ret;
4275 }
4276
4277 for (i = 0; i < xcrs.nr_xcrs; i++) {
4278 /* Only support xcr0 now */
4279 if (xcrs.xcrs[i].xcr == 0) {
4280 env->xcr0 = xcrs.xcrs[i].value;
4281 break;
4282 }
4283 }
4284 return 0;
4285 }
4286
kvm_get_sregs(X86CPU * cpu)4287 static int kvm_get_sregs(X86CPU *cpu)
4288 {
4289 CPUX86State *env = &cpu->env;
4290 struct kvm_sregs sregs;
4291 int ret;
4292
4293 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
4294 if (ret < 0) {
4295 return ret;
4296 }
4297
4298 /*
4299 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
4300 * always preceded by KVM_GET_VCPU_EVENTS.
4301 */
4302
4303 get_seg(&env->segs[R_CS], &sregs.cs);
4304 get_seg(&env->segs[R_DS], &sregs.ds);
4305 get_seg(&env->segs[R_ES], &sregs.es);
4306 get_seg(&env->segs[R_FS], &sregs.fs);
4307 get_seg(&env->segs[R_GS], &sregs.gs);
4308 get_seg(&env->segs[R_SS], &sregs.ss);
4309
4310 get_seg(&env->tr, &sregs.tr);
4311 get_seg(&env->ldt, &sregs.ldt);
4312
4313 env->idt.limit = sregs.idt.limit;
4314 env->idt.base = sregs.idt.base;
4315 env->gdt.limit = sregs.gdt.limit;
4316 env->gdt.base = sregs.gdt.base;
4317
4318 env->cr[0] = sregs.cr0;
4319 env->cr[2] = sregs.cr2;
4320 env->cr[3] = sregs.cr3;
4321 env->cr[4] = sregs.cr4;
4322
4323 env->efer = sregs.efer;
4324 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4325 env->cr[0] & CR0_PG_MASK) {
4326 env->efer |= MSR_EFER_LMA;
4327 }
4328
4329 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4330 x86_update_hflags(env);
4331
4332 return 0;
4333 }
4334
kvm_get_sregs2(X86CPU * cpu)4335 static int kvm_get_sregs2(X86CPU *cpu)
4336 {
4337 CPUX86State *env = &cpu->env;
4338 struct kvm_sregs2 sregs;
4339 int i, ret;
4340
4341 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
4342 if (ret < 0) {
4343 return ret;
4344 }
4345
4346 get_seg(&env->segs[R_CS], &sregs.cs);
4347 get_seg(&env->segs[R_DS], &sregs.ds);
4348 get_seg(&env->segs[R_ES], &sregs.es);
4349 get_seg(&env->segs[R_FS], &sregs.fs);
4350 get_seg(&env->segs[R_GS], &sregs.gs);
4351 get_seg(&env->segs[R_SS], &sregs.ss);
4352
4353 get_seg(&env->tr, &sregs.tr);
4354 get_seg(&env->ldt, &sregs.ldt);
4355
4356 env->idt.limit = sregs.idt.limit;
4357 env->idt.base = sregs.idt.base;
4358 env->gdt.limit = sregs.gdt.limit;
4359 env->gdt.base = sregs.gdt.base;
4360
4361 env->cr[0] = sregs.cr0;
4362 env->cr[2] = sregs.cr2;
4363 env->cr[3] = sregs.cr3;
4364 env->cr[4] = sregs.cr4;
4365
4366 env->efer = sregs.efer;
4367 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4368 env->cr[0] & CR0_PG_MASK) {
4369 env->efer |= MSR_EFER_LMA;
4370 }
4371
4372 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
4373
4374 if (env->pdptrs_valid) {
4375 for (i = 0; i < 4; i++) {
4376 env->pdptrs[i] = sregs.pdptrs[i];
4377 }
4378 }
4379
4380 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4381 x86_update_hflags(env);
4382
4383 return 0;
4384 }
4385
kvm_get_msrs(X86CPU * cpu)4386 static int kvm_get_msrs(X86CPU *cpu)
4387 {
4388 CPUX86State *env = &cpu->env;
4389 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
4390 int ret, i;
4391 uint64_t mtrr_top_bits;
4392
4393 kvm_msr_buf_reset(cpu);
4394
4395 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
4396 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
4397 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
4398 kvm_msr_entry_add(cpu, MSR_PAT, 0);
4399 if (has_msr_star) {
4400 kvm_msr_entry_add(cpu, MSR_STAR, 0);
4401 }
4402 if (has_msr_hsave_pa) {
4403 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
4404 }
4405 if (has_msr_tsc_aux) {
4406 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
4407 }
4408 if (has_msr_tsc_adjust) {
4409 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
4410 }
4411 if (has_msr_tsc_deadline) {
4412 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
4413 }
4414 if (has_msr_misc_enable) {
4415 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
4416 }
4417 if (has_msr_smbase) {
4418 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
4419 }
4420 if (has_msr_smi_count) {
4421 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
4422 }
4423 if (has_msr_feature_control) {
4424 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
4425 }
4426 if (has_msr_pkrs) {
4427 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
4428 }
4429 if (has_msr_bndcfgs) {
4430 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
4431 }
4432 if (has_msr_xss) {
4433 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
4434 }
4435 if (has_msr_umwait) {
4436 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
4437 }
4438 if (has_msr_spec_ctrl) {
4439 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
4440 }
4441 if (has_tsc_scale_msr) {
4442 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
4443 }
4444
4445 if (has_msr_tsx_ctrl) {
4446 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
4447 }
4448 if (has_msr_virt_ssbd) {
4449 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
4450 }
4451 if (!env->tsc_valid) {
4452 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
4453 env->tsc_valid = !runstate_is_running();
4454 }
4455 if (has_msr_hwcr) {
4456 kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
4457 }
4458
4459 #ifdef TARGET_X86_64
4460 if (lm_capable_kernel) {
4461 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
4462 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
4463 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
4464 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
4465 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
4466 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0);
4467 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0);
4468 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0);
4469 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0);
4470 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0);
4471 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0);
4472 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0);
4473 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0);
4474 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0);
4475 }
4476 }
4477 #endif
4478 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
4479 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
4480 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
4481 }
4482 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4483 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
4484 }
4485 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4486 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
4487 }
4488 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4489 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
4490 }
4491 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4492 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
4493 }
4494 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4495 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
4496 }
4497 if (has_architectural_pmu_version > 0) {
4498 if (has_architectural_pmu_version > 1) {
4499 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4500 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4501 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
4502 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
4503 }
4504 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4505 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
4506 }
4507 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4508 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
4509 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
4510 }
4511 }
4512
4513 if (env->mcg_cap) {
4514 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
4515 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
4516 if (has_msr_mcg_ext_ctl) {
4517 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
4518 }
4519 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4520 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
4521 }
4522 }
4523
4524 if (has_msr_hv_hypercall) {
4525 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
4526 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
4527 }
4528 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4529 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
4530 }
4531 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4532 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
4533 }
4534 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4535 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
4536 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
4537 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
4538 }
4539 if (has_msr_hv_syndbg_options) {
4540 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
4541 }
4542 if (has_msr_hv_crash) {
4543 int j;
4544
4545 for (j = 0; j < HV_CRASH_PARAMS; j++) {
4546 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
4547 }
4548 }
4549 if (has_msr_hv_runtime) {
4550 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
4551 }
4552 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4553 uint32_t msr;
4554
4555 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
4556 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
4557 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
4558 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
4559 kvm_msr_entry_add(cpu, msr, 0);
4560 }
4561 }
4562 if (has_msr_hv_stimer) {
4563 uint32_t msr;
4564
4565 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
4566 msr++) {
4567 kvm_msr_entry_add(cpu, msr, 0);
4568 }
4569 }
4570 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4571 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
4572 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
4573 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
4574 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
4575 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
4576 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
4577 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
4578 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
4579 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
4580 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
4581 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
4582 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
4583 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4584 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
4585 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
4586 }
4587 }
4588
4589 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4590 int addr_num =
4591 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
4592
4593 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
4594 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
4595 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
4596 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
4597 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
4598 for (i = 0; i < addr_num; i++) {
4599 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
4600 }
4601 }
4602
4603 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4604 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
4605 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
4606 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
4607 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
4608 }
4609
4610 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4611 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
4612 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
4613 }
4614
4615 if (kvm_enabled() && cpu->enable_pmu &&
4616 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4617 uint64_t depth;
4618
4619 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4620 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
4621 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
4622 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
4623
4624 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4625 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
4626 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
4627 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
4628 }
4629 }
4630 }
4631
4632 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
4633 if (ret < 0) {
4634 return ret;
4635 }
4636
4637 if (ret < cpu->kvm_msr_buf->nmsrs) {
4638 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
4639 error_report("error: failed to get MSR 0x%" PRIx32,
4640 (uint32_t)e->index);
4641 }
4642
4643 assert(ret == cpu->kvm_msr_buf->nmsrs);
4644 /*
4645 * MTRR masks: Each mask consists of 5 parts
4646 * a 10..0: must be zero
4647 * b 11 : valid bit
4648 * c n-1.12: actual mask bits
4649 * d 51..n: reserved must be zero
4650 * e 63.52: reserved must be zero
4651 *
4652 * 'n' is the number of physical bits supported by the CPU and is
4653 * apparently always <= 52. We know our 'n' but don't know what
4654 * the destinations 'n' is; it might be smaller, in which case
4655 * it masks (c) on loading. It might be larger, in which case
4656 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
4657 * we're migrating to.
4658 */
4659
4660 if (cpu->fill_mtrr_mask) {
4661 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
4662 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
4663 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
4664 } else {
4665 mtrr_top_bits = 0;
4666 }
4667
4668 for (i = 0; i < ret; i++) {
4669 uint32_t index = msrs[i].index;
4670 switch (index) {
4671 case MSR_IA32_SYSENTER_CS:
4672 env->sysenter_cs = msrs[i].data;
4673 break;
4674 case MSR_IA32_SYSENTER_ESP:
4675 env->sysenter_esp = msrs[i].data;
4676 break;
4677 case MSR_IA32_SYSENTER_EIP:
4678 env->sysenter_eip = msrs[i].data;
4679 break;
4680 case MSR_PAT:
4681 env->pat = msrs[i].data;
4682 break;
4683 case MSR_STAR:
4684 env->star = msrs[i].data;
4685 break;
4686 #ifdef TARGET_X86_64
4687 case MSR_CSTAR:
4688 env->cstar = msrs[i].data;
4689 break;
4690 case MSR_KERNELGSBASE:
4691 env->kernelgsbase = msrs[i].data;
4692 break;
4693 case MSR_FMASK:
4694 env->fmask = msrs[i].data;
4695 break;
4696 case MSR_LSTAR:
4697 env->lstar = msrs[i].data;
4698 break;
4699 case MSR_IA32_FRED_RSP0:
4700 env->fred_rsp0 = msrs[i].data;
4701 break;
4702 case MSR_IA32_FRED_RSP1:
4703 env->fred_rsp1 = msrs[i].data;
4704 break;
4705 case MSR_IA32_FRED_RSP2:
4706 env->fred_rsp2 = msrs[i].data;
4707 break;
4708 case MSR_IA32_FRED_RSP3:
4709 env->fred_rsp3 = msrs[i].data;
4710 break;
4711 case MSR_IA32_FRED_STKLVLS:
4712 env->fred_stklvls = msrs[i].data;
4713 break;
4714 case MSR_IA32_FRED_SSP1:
4715 env->fred_ssp1 = msrs[i].data;
4716 break;
4717 case MSR_IA32_FRED_SSP2:
4718 env->fred_ssp2 = msrs[i].data;
4719 break;
4720 case MSR_IA32_FRED_SSP3:
4721 env->fred_ssp3 = msrs[i].data;
4722 break;
4723 case MSR_IA32_FRED_CONFIG:
4724 env->fred_config = msrs[i].data;
4725 break;
4726 #endif
4727 case MSR_IA32_TSC:
4728 env->tsc = msrs[i].data;
4729 break;
4730 case MSR_TSC_AUX:
4731 env->tsc_aux = msrs[i].data;
4732 break;
4733 case MSR_TSC_ADJUST:
4734 env->tsc_adjust = msrs[i].data;
4735 break;
4736 case MSR_IA32_TSCDEADLINE:
4737 env->tsc_deadline = msrs[i].data;
4738 break;
4739 case MSR_VM_HSAVE_PA:
4740 env->vm_hsave = msrs[i].data;
4741 break;
4742 case MSR_KVM_SYSTEM_TIME:
4743 env->system_time_msr = msrs[i].data;
4744 break;
4745 case MSR_KVM_WALL_CLOCK:
4746 env->wall_clock_msr = msrs[i].data;
4747 break;
4748 case MSR_MCG_STATUS:
4749 env->mcg_status = msrs[i].data;
4750 break;
4751 case MSR_MCG_CTL:
4752 env->mcg_ctl = msrs[i].data;
4753 break;
4754 case MSR_MCG_EXT_CTL:
4755 env->mcg_ext_ctl = msrs[i].data;
4756 break;
4757 case MSR_IA32_MISC_ENABLE:
4758 env->msr_ia32_misc_enable = msrs[i].data;
4759 break;
4760 case MSR_IA32_SMBASE:
4761 env->smbase = msrs[i].data;
4762 break;
4763 case MSR_SMI_COUNT:
4764 env->msr_smi_count = msrs[i].data;
4765 break;
4766 case MSR_IA32_FEATURE_CONTROL:
4767 env->msr_ia32_feature_control = msrs[i].data;
4768 break;
4769 case MSR_IA32_BNDCFGS:
4770 env->msr_bndcfgs = msrs[i].data;
4771 break;
4772 case MSR_IA32_XSS:
4773 env->xss = msrs[i].data;
4774 break;
4775 case MSR_IA32_UMWAIT_CONTROL:
4776 env->umwait = msrs[i].data;
4777 break;
4778 case MSR_IA32_PKRS:
4779 env->pkrs = msrs[i].data;
4780 break;
4781 default:
4782 if (msrs[i].index >= MSR_MC0_CTL &&
4783 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4784 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
4785 }
4786 break;
4787 case MSR_KVM_ASYNC_PF_EN:
4788 env->async_pf_en_msr = msrs[i].data;
4789 break;
4790 case MSR_KVM_ASYNC_PF_INT:
4791 env->async_pf_int_msr = msrs[i].data;
4792 break;
4793 case MSR_KVM_PV_EOI_EN:
4794 env->pv_eoi_en_msr = msrs[i].data;
4795 break;
4796 case MSR_KVM_STEAL_TIME:
4797 env->steal_time_msr = msrs[i].data;
4798 break;
4799 case MSR_KVM_POLL_CONTROL: {
4800 env->poll_control_msr = msrs[i].data;
4801 break;
4802 }
4803 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4804 env->msr_fixed_ctr_ctrl = msrs[i].data;
4805 break;
4806 case MSR_CORE_PERF_GLOBAL_CTRL:
4807 env->msr_global_ctrl = msrs[i].data;
4808 break;
4809 case MSR_CORE_PERF_GLOBAL_STATUS:
4810 env->msr_global_status = msrs[i].data;
4811 break;
4812 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4813 env->msr_global_ovf_ctrl = msrs[i].data;
4814 break;
4815 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4816 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4817 break;
4818 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4819 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4820 break;
4821 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4822 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4823 break;
4824 case HV_X64_MSR_HYPERCALL:
4825 env->msr_hv_hypercall = msrs[i].data;
4826 break;
4827 case HV_X64_MSR_GUEST_OS_ID:
4828 env->msr_hv_guest_os_id = msrs[i].data;
4829 break;
4830 case HV_X64_MSR_APIC_ASSIST_PAGE:
4831 env->msr_hv_vapic = msrs[i].data;
4832 break;
4833 case HV_X64_MSR_REFERENCE_TSC:
4834 env->msr_hv_tsc = msrs[i].data;
4835 break;
4836 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4837 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4838 break;
4839 case HV_X64_MSR_VP_RUNTIME:
4840 env->msr_hv_runtime = msrs[i].data;
4841 break;
4842 case HV_X64_MSR_SCONTROL:
4843 env->msr_hv_synic_control = msrs[i].data;
4844 break;
4845 case HV_X64_MSR_SIEFP:
4846 env->msr_hv_synic_evt_page = msrs[i].data;
4847 break;
4848 case HV_X64_MSR_SIMP:
4849 env->msr_hv_synic_msg_page = msrs[i].data;
4850 break;
4851 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4852 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
4853 break;
4854 case HV_X64_MSR_STIMER0_CONFIG:
4855 case HV_X64_MSR_STIMER1_CONFIG:
4856 case HV_X64_MSR_STIMER2_CONFIG:
4857 case HV_X64_MSR_STIMER3_CONFIG:
4858 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4859 msrs[i].data;
4860 break;
4861 case HV_X64_MSR_STIMER0_COUNT:
4862 case HV_X64_MSR_STIMER1_COUNT:
4863 case HV_X64_MSR_STIMER2_COUNT:
4864 case HV_X64_MSR_STIMER3_COUNT:
4865 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4866 msrs[i].data;
4867 break;
4868 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4869 env->msr_hv_reenlightenment_control = msrs[i].data;
4870 break;
4871 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4872 env->msr_hv_tsc_emulation_control = msrs[i].data;
4873 break;
4874 case HV_X64_MSR_TSC_EMULATION_STATUS:
4875 env->msr_hv_tsc_emulation_status = msrs[i].data;
4876 break;
4877 case HV_X64_MSR_SYNDBG_OPTIONS:
4878 env->msr_hv_syndbg_options = msrs[i].data;
4879 break;
4880 case MSR_MTRRdefType:
4881 env->mtrr_deftype = msrs[i].data;
4882 break;
4883 case MSR_MTRRfix64K_00000:
4884 env->mtrr_fixed[0] = msrs[i].data;
4885 break;
4886 case MSR_MTRRfix16K_80000:
4887 env->mtrr_fixed[1] = msrs[i].data;
4888 break;
4889 case MSR_MTRRfix16K_A0000:
4890 env->mtrr_fixed[2] = msrs[i].data;
4891 break;
4892 case MSR_MTRRfix4K_C0000:
4893 env->mtrr_fixed[3] = msrs[i].data;
4894 break;
4895 case MSR_MTRRfix4K_C8000:
4896 env->mtrr_fixed[4] = msrs[i].data;
4897 break;
4898 case MSR_MTRRfix4K_D0000:
4899 env->mtrr_fixed[5] = msrs[i].data;
4900 break;
4901 case MSR_MTRRfix4K_D8000:
4902 env->mtrr_fixed[6] = msrs[i].data;
4903 break;
4904 case MSR_MTRRfix4K_E0000:
4905 env->mtrr_fixed[7] = msrs[i].data;
4906 break;
4907 case MSR_MTRRfix4K_E8000:
4908 env->mtrr_fixed[8] = msrs[i].data;
4909 break;
4910 case MSR_MTRRfix4K_F0000:
4911 env->mtrr_fixed[9] = msrs[i].data;
4912 break;
4913 case MSR_MTRRfix4K_F8000:
4914 env->mtrr_fixed[10] = msrs[i].data;
4915 break;
4916 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4917 if (index & 1) {
4918 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4919 mtrr_top_bits;
4920 } else {
4921 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4922 }
4923 break;
4924 case MSR_IA32_SPEC_CTRL:
4925 env->spec_ctrl = msrs[i].data;
4926 break;
4927 case MSR_AMD64_TSC_RATIO:
4928 env->amd_tsc_scale_msr = msrs[i].data;
4929 break;
4930 case MSR_IA32_TSX_CTRL:
4931 env->tsx_ctrl = msrs[i].data;
4932 break;
4933 case MSR_VIRT_SSBD:
4934 env->virt_ssbd = msrs[i].data;
4935 break;
4936 case MSR_IA32_RTIT_CTL:
4937 env->msr_rtit_ctrl = msrs[i].data;
4938 break;
4939 case MSR_IA32_RTIT_STATUS:
4940 env->msr_rtit_status = msrs[i].data;
4941 break;
4942 case MSR_IA32_RTIT_OUTPUT_BASE:
4943 env->msr_rtit_output_base = msrs[i].data;
4944 break;
4945 case MSR_IA32_RTIT_OUTPUT_MASK:
4946 env->msr_rtit_output_mask = msrs[i].data;
4947 break;
4948 case MSR_IA32_RTIT_CR3_MATCH:
4949 env->msr_rtit_cr3_match = msrs[i].data;
4950 break;
4951 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4952 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4953 break;
4954 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4955 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4956 msrs[i].data;
4957 break;
4958 case MSR_IA32_XFD:
4959 env->msr_xfd = msrs[i].data;
4960 break;
4961 case MSR_IA32_XFD_ERR:
4962 env->msr_xfd_err = msrs[i].data;
4963 break;
4964 case MSR_ARCH_LBR_CTL:
4965 env->msr_lbr_ctl = msrs[i].data;
4966 break;
4967 case MSR_ARCH_LBR_DEPTH:
4968 env->msr_lbr_depth = msrs[i].data;
4969 break;
4970 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4971 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4972 break;
4973 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4974 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4975 break;
4976 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4977 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4978 break;
4979 case MSR_K7_HWCR:
4980 env->msr_hwcr = msrs[i].data;
4981 break;
4982 }
4983 }
4984
4985 return 0;
4986 }
4987
kvm_put_mp_state(X86CPU * cpu)4988 static int kvm_put_mp_state(X86CPU *cpu)
4989 {
4990 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
4991
4992 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
4993 }
4994
kvm_get_mp_state(X86CPU * cpu)4995 static int kvm_get_mp_state(X86CPU *cpu)
4996 {
4997 CPUState *cs = CPU(cpu);
4998 CPUX86State *env = &cpu->env;
4999 struct kvm_mp_state mp_state;
5000 int ret;
5001
5002 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
5003 if (ret < 0) {
5004 return ret;
5005 }
5006 env->mp_state = mp_state.mp_state;
5007 if (kvm_irqchip_in_kernel()) {
5008 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
5009 }
5010 return 0;
5011 }
5012
kvm_get_apic(X86CPU * cpu)5013 static int kvm_get_apic(X86CPU *cpu)
5014 {
5015 DeviceState *apic = cpu->apic_state;
5016 struct kvm_lapic_state kapic;
5017 int ret;
5018
5019 if (apic && kvm_irqchip_in_kernel()) {
5020 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
5021 if (ret < 0) {
5022 return ret;
5023 }
5024
5025 kvm_get_apic_state(apic, &kapic);
5026 }
5027 return 0;
5028 }
5029
kvm_put_vcpu_events(X86CPU * cpu,int level)5030 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
5031 {
5032 CPUState *cs = CPU(cpu);
5033 CPUX86State *env = &cpu->env;
5034 struct kvm_vcpu_events events = {};
5035
5036 events.flags = 0;
5037
5038 if (has_exception_payload) {
5039 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5040 events.exception.pending = env->exception_pending;
5041 events.exception_has_payload = env->exception_has_payload;
5042 events.exception_payload = env->exception_payload;
5043 }
5044 events.exception.nr = env->exception_nr;
5045 events.exception.injected = env->exception_injected;
5046 events.exception.has_error_code = env->has_error_code;
5047 events.exception.error_code = env->error_code;
5048
5049 events.interrupt.injected = (env->interrupt_injected >= 0);
5050 events.interrupt.nr = env->interrupt_injected;
5051 events.interrupt.soft = env->soft_interrupt;
5052
5053 events.nmi.injected = env->nmi_injected;
5054 events.nmi.pending = env->nmi_pending;
5055 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
5056
5057 events.sipi_vector = env->sipi_vector;
5058
5059 if (has_msr_smbase) {
5060 events.flags |= KVM_VCPUEVENT_VALID_SMM;
5061 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
5062 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
5063 if (kvm_irqchip_in_kernel()) {
5064 /* As soon as these are moved to the kernel, remove them
5065 * from cs->interrupt_request.
5066 */
5067 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
5068 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
5069 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
5070 } else {
5071 /* Keep these in cs->interrupt_request. */
5072 events.smi.pending = 0;
5073 events.smi.latched_init = 0;
5074 }
5075 }
5076
5077 if (level >= KVM_PUT_RESET_STATE) {
5078 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
5079 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
5080 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
5081 }
5082 }
5083
5084 if (has_triple_fault_event) {
5085 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5086 events.triple_fault.pending = env->triple_fault_pending;
5087 }
5088
5089 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
5090 }
5091
kvm_get_vcpu_events(X86CPU * cpu)5092 static int kvm_get_vcpu_events(X86CPU *cpu)
5093 {
5094 CPUX86State *env = &cpu->env;
5095 struct kvm_vcpu_events events;
5096 int ret;
5097
5098 memset(&events, 0, sizeof(events));
5099 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
5100 if (ret < 0) {
5101 return ret;
5102 }
5103
5104 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5105 env->exception_pending = events.exception.pending;
5106 env->exception_has_payload = events.exception_has_payload;
5107 env->exception_payload = events.exception_payload;
5108 } else {
5109 env->exception_pending = 0;
5110 env->exception_has_payload = false;
5111 }
5112 env->exception_injected = events.exception.injected;
5113 env->exception_nr =
5114 (env->exception_pending || env->exception_injected) ?
5115 events.exception.nr : -1;
5116 env->has_error_code = events.exception.has_error_code;
5117 env->error_code = events.exception.error_code;
5118
5119 env->interrupt_injected =
5120 events.interrupt.injected ? events.interrupt.nr : -1;
5121 env->soft_interrupt = events.interrupt.soft;
5122
5123 env->nmi_injected = events.nmi.injected;
5124 env->nmi_pending = events.nmi.pending;
5125 if (events.nmi.masked) {
5126 env->hflags2 |= HF2_NMI_MASK;
5127 } else {
5128 env->hflags2 &= ~HF2_NMI_MASK;
5129 }
5130
5131 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
5132 if (events.smi.smm) {
5133 env->hflags |= HF_SMM_MASK;
5134 } else {
5135 env->hflags &= ~HF_SMM_MASK;
5136 }
5137 if (events.smi.pending) {
5138 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5139 } else {
5140 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5141 }
5142 if (events.smi.smm_inside_nmi) {
5143 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
5144 } else {
5145 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
5146 }
5147 if (events.smi.latched_init) {
5148 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5149 } else {
5150 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5151 }
5152 }
5153
5154 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5155 env->triple_fault_pending = events.triple_fault.pending;
5156 }
5157
5158 env->sipi_vector = events.sipi_vector;
5159
5160 return 0;
5161 }
5162
kvm_put_debugregs(X86CPU * cpu)5163 static int kvm_put_debugregs(X86CPU *cpu)
5164 {
5165 CPUX86State *env = &cpu->env;
5166 struct kvm_debugregs dbgregs;
5167 int i;
5168
5169 memset(&dbgregs, 0, sizeof(dbgregs));
5170 for (i = 0; i < 4; i++) {
5171 dbgregs.db[i] = env->dr[i];
5172 }
5173 dbgregs.dr6 = env->dr[6];
5174 dbgregs.dr7 = env->dr[7];
5175 dbgregs.flags = 0;
5176
5177 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
5178 }
5179
kvm_get_debugregs(X86CPU * cpu)5180 static int kvm_get_debugregs(X86CPU *cpu)
5181 {
5182 CPUX86State *env = &cpu->env;
5183 struct kvm_debugregs dbgregs;
5184 int i, ret;
5185
5186 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
5187 if (ret < 0) {
5188 return ret;
5189 }
5190 for (i = 0; i < 4; i++) {
5191 env->dr[i] = dbgregs.db[i];
5192 }
5193 env->dr[4] = env->dr[6] = dbgregs.dr6;
5194 env->dr[5] = env->dr[7] = dbgregs.dr7;
5195
5196 return 0;
5197 }
5198
kvm_put_nested_state(X86CPU * cpu)5199 static int kvm_put_nested_state(X86CPU *cpu)
5200 {
5201 CPUX86State *env = &cpu->env;
5202 int max_nested_state_len = kvm_max_nested_state_length();
5203
5204 if (!env->nested_state) {
5205 return 0;
5206 }
5207
5208 /*
5209 * Copy flags that are affected by reset from env->hflags and env->hflags2.
5210 */
5211 if (env->hflags & HF_GUEST_MASK) {
5212 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
5213 } else {
5214 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
5215 }
5216
5217 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
5218 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
5219 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
5220 } else {
5221 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
5222 }
5223
5224 assert(env->nested_state->size <= max_nested_state_len);
5225 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
5226 }
5227
kvm_get_nested_state(X86CPU * cpu)5228 static int kvm_get_nested_state(X86CPU *cpu)
5229 {
5230 CPUX86State *env = &cpu->env;
5231 int max_nested_state_len = kvm_max_nested_state_length();
5232 int ret;
5233
5234 if (!env->nested_state) {
5235 return 0;
5236 }
5237
5238 /*
5239 * It is possible that migration restored a smaller size into
5240 * nested_state->hdr.size than what our kernel support.
5241 * We preserve migration origin nested_state->hdr.size for
5242 * call to KVM_SET_NESTED_STATE but wish that our next call
5243 * to KVM_GET_NESTED_STATE will use max size our kernel support.
5244 */
5245 env->nested_state->size = max_nested_state_len;
5246
5247 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
5248 if (ret < 0) {
5249 return ret;
5250 }
5251
5252 /*
5253 * Copy flags that are affected by reset to env->hflags and env->hflags2.
5254 */
5255 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
5256 env->hflags |= HF_GUEST_MASK;
5257 } else {
5258 env->hflags &= ~HF_GUEST_MASK;
5259 }
5260
5261 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
5262 if (cpu_has_svm(env)) {
5263 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
5264 env->hflags2 |= HF2_GIF_MASK;
5265 } else {
5266 env->hflags2 &= ~HF2_GIF_MASK;
5267 }
5268 }
5269
5270 return ret;
5271 }
5272
kvm_arch_put_registers(CPUState * cpu,int level,Error ** errp)5273 int kvm_arch_put_registers(CPUState *cpu, int level, Error **errp)
5274 {
5275 X86CPU *x86_cpu = X86_CPU(cpu);
5276 int ret;
5277
5278 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
5279
5280 /*
5281 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
5282 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
5283 * precede kvm_put_nested_state() when 'real' nested state is set.
5284 */
5285 if (level >= KVM_PUT_RESET_STATE) {
5286 ret = kvm_put_msr_feature_control(x86_cpu);
5287 if (ret < 0) {
5288 error_setg_errno(errp, -ret, "Failed to set feature control MSR");
5289 return ret;
5290 }
5291 }
5292
5293 /* must be before kvm_put_nested_state so that EFER.SVME is set */
5294 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
5295 if (ret < 0) {
5296 error_setg_errno(errp, -ret, "Failed to set special registers");
5297 return ret;
5298 }
5299
5300 if (level >= KVM_PUT_RESET_STATE) {
5301 ret = kvm_put_nested_state(x86_cpu);
5302 if (ret < 0) {
5303 error_setg_errno(errp, -ret, "Failed to set nested state");
5304 return ret;
5305 }
5306 }
5307
5308 if (level == KVM_PUT_FULL_STATE) {
5309 /* We don't check for kvm_arch_set_tsc_khz() errors here,
5310 * because TSC frequency mismatch shouldn't abort migration,
5311 * unless the user explicitly asked for a more strict TSC
5312 * setting (e.g. using an explicit "tsc-freq" option).
5313 */
5314 kvm_arch_set_tsc_khz(cpu);
5315 }
5316
5317 #ifdef CONFIG_XEN_EMU
5318 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) {
5319 ret = kvm_put_xen_state(cpu);
5320 if (ret < 0) {
5321 error_setg_errno(errp, -ret, "Failed to set Xen state");
5322 return ret;
5323 }
5324 }
5325 #endif
5326
5327 ret = kvm_getput_regs(x86_cpu, 1);
5328 if (ret < 0) {
5329 error_setg_errno(errp, -ret, "Failed to set general purpose registers");
5330 return ret;
5331 }
5332 ret = kvm_put_xsave(x86_cpu);
5333 if (ret < 0) {
5334 error_setg_errno(errp, -ret, "Failed to set XSAVE");
5335 return ret;
5336 }
5337 ret = kvm_put_xcrs(x86_cpu);
5338 if (ret < 0) {
5339 error_setg_errno(errp, -ret, "Failed to set XCRs");
5340 return ret;
5341 }
5342 ret = kvm_put_msrs(x86_cpu, level);
5343 if (ret < 0) {
5344 error_setg_errno(errp, -ret, "Failed to set MSRs");
5345 return ret;
5346 }
5347 ret = kvm_put_vcpu_events(x86_cpu, level);
5348 if (ret < 0) {
5349 error_setg_errno(errp, -ret, "Failed to set vCPU events");
5350 return ret;
5351 }
5352 if (level >= KVM_PUT_RESET_STATE) {
5353 ret = kvm_put_mp_state(x86_cpu);
5354 if (ret < 0) {
5355 error_setg_errno(errp, -ret, "Failed to set MP state");
5356 return ret;
5357 }
5358 }
5359
5360 ret = kvm_put_tscdeadline_msr(x86_cpu);
5361 if (ret < 0) {
5362 error_setg_errno(errp, -ret, "Failed to set TSC deadline MSR");
5363 return ret;
5364 }
5365 ret = kvm_put_debugregs(x86_cpu);
5366 if (ret < 0) {
5367 error_setg_errno(errp, -ret, "Failed to set debug registers");
5368 return ret;
5369 }
5370 return 0;
5371 }
5372
kvm_arch_get_registers(CPUState * cs,Error ** errp)5373 int kvm_arch_get_registers(CPUState *cs, Error **errp)
5374 {
5375 X86CPU *cpu = X86_CPU(cs);
5376 int ret;
5377
5378 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
5379
5380 ret = kvm_get_vcpu_events(cpu);
5381 if (ret < 0) {
5382 error_setg_errno(errp, -ret, "Failed to get vCPU events");
5383 goto out;
5384 }
5385 /*
5386 * KVM_GET_MPSTATE can modify CS and RIP, call it before
5387 * KVM_GET_REGS and KVM_GET_SREGS.
5388 */
5389 ret = kvm_get_mp_state(cpu);
5390 if (ret < 0) {
5391 error_setg_errno(errp, -ret, "Failed to get MP state");
5392 goto out;
5393 }
5394 ret = kvm_getput_regs(cpu, 0);
5395 if (ret < 0) {
5396 error_setg_errno(errp, -ret, "Failed to get general purpose registers");
5397 goto out;
5398 }
5399 ret = kvm_get_xsave(cpu);
5400 if (ret < 0) {
5401 error_setg_errno(errp, -ret, "Failed to get XSAVE");
5402 goto out;
5403 }
5404 ret = kvm_get_xcrs(cpu);
5405 if (ret < 0) {
5406 error_setg_errno(errp, -ret, "Failed to get XCRs");
5407 goto out;
5408 }
5409 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
5410 if (ret < 0) {
5411 error_setg_errno(errp, -ret, "Failed to get special registers");
5412 goto out;
5413 }
5414 ret = kvm_get_msrs(cpu);
5415 if (ret < 0) {
5416 error_setg_errno(errp, -ret, "Failed to get MSRs");
5417 goto out;
5418 }
5419 ret = kvm_get_apic(cpu);
5420 if (ret < 0) {
5421 error_setg_errno(errp, -ret, "Failed to get APIC");
5422 goto out;
5423 }
5424 ret = kvm_get_debugregs(cpu);
5425 if (ret < 0) {
5426 error_setg_errno(errp, -ret, "Failed to get debug registers");
5427 goto out;
5428 }
5429 ret = kvm_get_nested_state(cpu);
5430 if (ret < 0) {
5431 error_setg_errno(errp, -ret, "Failed to get nested state");
5432 goto out;
5433 }
5434 #ifdef CONFIG_XEN_EMU
5435 if (xen_mode == XEN_EMULATE) {
5436 ret = kvm_get_xen_state(cs);
5437 if (ret < 0) {
5438 error_setg_errno(errp, -ret, "Failed to get Xen state");
5439 goto out;
5440 }
5441 }
5442 #endif
5443 ret = 0;
5444 out:
5445 cpu_sync_bndcs_hflags(&cpu->env);
5446 return ret;
5447 }
5448
kvm_arch_pre_run(CPUState * cpu,struct kvm_run * run)5449 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
5450 {
5451 X86CPU *x86_cpu = X86_CPU(cpu);
5452 CPUX86State *env = &x86_cpu->env;
5453 int ret;
5454
5455 /* Inject NMI */
5456 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
5457 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
5458 bql_lock();
5459 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
5460 bql_unlock();
5461 DPRINTF("injected NMI\n");
5462 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
5463 if (ret < 0) {
5464 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
5465 strerror(-ret));
5466 }
5467 }
5468 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
5469 bql_lock();
5470 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
5471 bql_unlock();
5472 DPRINTF("injected SMI\n");
5473 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
5474 if (ret < 0) {
5475 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
5476 strerror(-ret));
5477 }
5478 }
5479 }
5480
5481 if (!kvm_pic_in_kernel()) {
5482 bql_lock();
5483 }
5484
5485 /* Force the VCPU out of its inner loop to process any INIT requests
5486 * or (for userspace APIC, but it is cheap to combine the checks here)
5487 * pending TPR access reports.
5488 */
5489 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
5490 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
5491 !(env->hflags & HF_SMM_MASK)) {
5492 cpu->exit_request = 1;
5493 }
5494 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
5495 cpu->exit_request = 1;
5496 }
5497 }
5498
5499 if (!kvm_pic_in_kernel()) {
5500 /* Try to inject an interrupt if the guest can accept it */
5501 if (run->ready_for_interrupt_injection &&
5502 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
5503 (env->eflags & IF_MASK)) {
5504 int irq;
5505
5506 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
5507 irq = cpu_get_pic_interrupt(env);
5508 if (irq >= 0) {
5509 struct kvm_interrupt intr;
5510
5511 intr.irq = irq;
5512 DPRINTF("injected interrupt %d\n", irq);
5513 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
5514 if (ret < 0) {
5515 fprintf(stderr,
5516 "KVM: injection failed, interrupt lost (%s)\n",
5517 strerror(-ret));
5518 }
5519 }
5520 }
5521
5522 /* If we have an interrupt but the guest is not ready to receive an
5523 * interrupt, request an interrupt window exit. This will
5524 * cause a return to userspace as soon as the guest is ready to
5525 * receive interrupts. */
5526 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
5527 run->request_interrupt_window = 1;
5528 } else {
5529 run->request_interrupt_window = 0;
5530 }
5531
5532 DPRINTF("setting tpr\n");
5533 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
5534
5535 bql_unlock();
5536 }
5537 }
5538
kvm_rate_limit_on_bus_lock(void)5539 static void kvm_rate_limit_on_bus_lock(void)
5540 {
5541 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
5542
5543 if (delay_ns) {
5544 g_usleep(delay_ns / SCALE_US);
5545 }
5546 }
5547
kvm_arch_post_run(CPUState * cpu,struct kvm_run * run)5548 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
5549 {
5550 X86CPU *x86_cpu = X86_CPU(cpu);
5551 CPUX86State *env = &x86_cpu->env;
5552
5553 if (run->flags & KVM_RUN_X86_SMM) {
5554 env->hflags |= HF_SMM_MASK;
5555 } else {
5556 env->hflags &= ~HF_SMM_MASK;
5557 }
5558 if (run->if_flag) {
5559 env->eflags |= IF_MASK;
5560 } else {
5561 env->eflags &= ~IF_MASK;
5562 }
5563 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
5564 kvm_rate_limit_on_bus_lock();
5565 }
5566
5567 #ifdef CONFIG_XEN_EMU
5568 /*
5569 * If the callback is asserted as a GSI (or PCI INTx) then check if
5570 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert
5571 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC
5572 * EOI and only resample then, exactly how the VFIO eventfd pairs
5573 * are designed to work for level triggered interrupts.
5574 */
5575 if (x86_cpu->env.xen_callback_asserted) {
5576 kvm_xen_maybe_deassert_callback(cpu);
5577 }
5578 #endif
5579
5580 /* We need to protect the apic state against concurrent accesses from
5581 * different threads in case the userspace irqchip is used. */
5582 if (!kvm_irqchip_in_kernel()) {
5583 bql_lock();
5584 }
5585 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
5586 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
5587 if (!kvm_irqchip_in_kernel()) {
5588 bql_unlock();
5589 }
5590 return cpu_get_mem_attrs(env);
5591 }
5592
kvm_arch_process_async_events(CPUState * cs)5593 int kvm_arch_process_async_events(CPUState *cs)
5594 {
5595 X86CPU *cpu = X86_CPU(cs);
5596 CPUX86State *env = &cpu->env;
5597
5598 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
5599 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
5600 assert(env->mcg_cap);
5601
5602 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
5603
5604 kvm_cpu_synchronize_state(cs);
5605
5606 if (env->exception_nr == EXCP08_DBLE) {
5607 /* this means triple fault */
5608 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
5609 cs->exit_request = 1;
5610 return 0;
5611 }
5612 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
5613 env->has_error_code = 0;
5614
5615 cs->halted = 0;
5616 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
5617 env->mp_state = KVM_MP_STATE_RUNNABLE;
5618 }
5619 }
5620
5621 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
5622 !(env->hflags & HF_SMM_MASK)) {
5623 kvm_cpu_synchronize_state(cs);
5624 do_cpu_init(cpu);
5625 }
5626
5627 if (kvm_irqchip_in_kernel()) {
5628 return 0;
5629 }
5630
5631 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
5632 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
5633 apic_poll_irq(cpu->apic_state);
5634 }
5635 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5636 (env->eflags & IF_MASK)) ||
5637 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5638 cs->halted = 0;
5639 }
5640 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
5641 kvm_cpu_synchronize_state(cs);
5642 do_cpu_sipi(cpu);
5643 }
5644 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
5645 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
5646 kvm_cpu_synchronize_state(cs);
5647 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
5648 env->tpr_access_type);
5649 }
5650
5651 return cs->halted;
5652 }
5653
kvm_handle_halt(X86CPU * cpu)5654 static int kvm_handle_halt(X86CPU *cpu)
5655 {
5656 CPUState *cs = CPU(cpu);
5657 CPUX86State *env = &cpu->env;
5658
5659 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5660 (env->eflags & IF_MASK)) &&
5661 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5662 cs->halted = 1;
5663 return EXCP_HLT;
5664 }
5665
5666 return 0;
5667 }
5668
kvm_handle_tpr_access(X86CPU * cpu)5669 static int kvm_handle_tpr_access(X86CPU *cpu)
5670 {
5671 CPUState *cs = CPU(cpu);
5672 struct kvm_run *run = cs->kvm_run;
5673
5674 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
5675 run->tpr_access.is_write ? TPR_ACCESS_WRITE
5676 : TPR_ACCESS_READ);
5677 return 1;
5678 }
5679
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5680 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5681 {
5682 static const uint8_t int3 = 0xcc;
5683
5684 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
5685 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
5686 return -EINVAL;
5687 }
5688 return 0;
5689 }
5690
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5691 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5692 {
5693 uint8_t int3;
5694
5695 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
5696 return -EINVAL;
5697 }
5698 if (int3 != 0xcc) {
5699 return 0;
5700 }
5701 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
5702 return -EINVAL;
5703 }
5704 return 0;
5705 }
5706
5707 static struct {
5708 target_ulong addr;
5709 int len;
5710 int type;
5711 } hw_breakpoint[4];
5712
5713 static int nb_hw_breakpoint;
5714
find_hw_breakpoint(target_ulong addr,int len,int type)5715 static int find_hw_breakpoint(target_ulong addr, int len, int type)
5716 {
5717 int n;
5718
5719 for (n = 0; n < nb_hw_breakpoint; n++) {
5720 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
5721 (hw_breakpoint[n].len == len || len == -1)) {
5722 return n;
5723 }
5724 }
5725 return -1;
5726 }
5727
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)5728 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
5729 {
5730 switch (type) {
5731 case GDB_BREAKPOINT_HW:
5732 len = 1;
5733 break;
5734 case GDB_WATCHPOINT_WRITE:
5735 case GDB_WATCHPOINT_ACCESS:
5736 switch (len) {
5737 case 1:
5738 break;
5739 case 2:
5740 case 4:
5741 case 8:
5742 if (addr & (len - 1)) {
5743 return -EINVAL;
5744 }
5745 break;
5746 default:
5747 return -EINVAL;
5748 }
5749 break;
5750 default:
5751 return -ENOSYS;
5752 }
5753
5754 if (nb_hw_breakpoint == 4) {
5755 return -ENOBUFS;
5756 }
5757 if (find_hw_breakpoint(addr, len, type) >= 0) {
5758 return -EEXIST;
5759 }
5760 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5761 hw_breakpoint[nb_hw_breakpoint].len = len;
5762 hw_breakpoint[nb_hw_breakpoint].type = type;
5763 nb_hw_breakpoint++;
5764
5765 return 0;
5766 }
5767
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)5768 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
5769 {
5770 int n;
5771
5772 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
5773 if (n < 0) {
5774 return -ENOENT;
5775 }
5776 nb_hw_breakpoint--;
5777 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5778
5779 return 0;
5780 }
5781
kvm_arch_remove_all_hw_breakpoints(void)5782 void kvm_arch_remove_all_hw_breakpoints(void)
5783 {
5784 nb_hw_breakpoint = 0;
5785 }
5786
5787 static CPUWatchpoint hw_watchpoint;
5788
kvm_handle_debug(X86CPU * cpu,struct kvm_debug_exit_arch * arch_info)5789 static int kvm_handle_debug(X86CPU *cpu,
5790 struct kvm_debug_exit_arch *arch_info)
5791 {
5792 CPUState *cs = CPU(cpu);
5793 CPUX86State *env = &cpu->env;
5794 int ret = 0;
5795 int n;
5796
5797 if (arch_info->exception == EXCP01_DB) {
5798 if (arch_info->dr6 & DR6_BS) {
5799 if (cs->singlestep_enabled) {
5800 ret = EXCP_DEBUG;
5801 }
5802 } else {
5803 for (n = 0; n < 4; n++) {
5804 if (arch_info->dr6 & (1 << n)) {
5805 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5806 case 0x0:
5807 ret = EXCP_DEBUG;
5808 break;
5809 case 0x1:
5810 ret = EXCP_DEBUG;
5811 cs->watchpoint_hit = &hw_watchpoint;
5812 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5813 hw_watchpoint.flags = BP_MEM_WRITE;
5814 break;
5815 case 0x3:
5816 ret = EXCP_DEBUG;
5817 cs->watchpoint_hit = &hw_watchpoint;
5818 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5819 hw_watchpoint.flags = BP_MEM_ACCESS;
5820 break;
5821 }
5822 }
5823 }
5824 }
5825 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
5826 ret = EXCP_DEBUG;
5827 }
5828 if (ret == 0) {
5829 cpu_synchronize_state(cs);
5830 assert(env->exception_nr == -1);
5831
5832 /* pass to guest */
5833 kvm_queue_exception(env, arch_info->exception,
5834 arch_info->exception == EXCP01_DB,
5835 arch_info->dr6);
5836 env->has_error_code = 0;
5837 }
5838
5839 return ret;
5840 }
5841
kvm_arch_update_guest_debug(CPUState * cpu,struct kvm_guest_debug * dbg)5842 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
5843 {
5844 const uint8_t type_code[] = {
5845 [GDB_BREAKPOINT_HW] = 0x0,
5846 [GDB_WATCHPOINT_WRITE] = 0x1,
5847 [GDB_WATCHPOINT_ACCESS] = 0x3
5848 };
5849 const uint8_t len_code[] = {
5850 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5851 };
5852 int n;
5853
5854 if (kvm_sw_breakpoints_active(cpu)) {
5855 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
5856 }
5857 if (nb_hw_breakpoint > 0) {
5858 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5859 dbg->arch.debugreg[7] = 0x0600;
5860 for (n = 0; n < nb_hw_breakpoint; n++) {
5861 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5862 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5863 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
5864 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
5865 }
5866 }
5867 }
5868
kvm_install_msr_filters(KVMState * s)5869 static int kvm_install_msr_filters(KVMState *s)
5870 {
5871 uint64_t zero = 0;
5872 struct kvm_msr_filter filter = {
5873 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW,
5874 };
5875 int i, j = 0;
5876
5877 QEMU_BUILD_BUG_ON(ARRAY_SIZE(msr_handlers) != ARRAY_SIZE(filter.ranges));
5878 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5879 KVMMSRHandlers *handler = &msr_handlers[i];
5880 if (handler->msr) {
5881 struct kvm_msr_filter_range *range = &filter.ranges[j++];
5882
5883 *range = (struct kvm_msr_filter_range) {
5884 .flags = 0,
5885 .nmsrs = 1,
5886 .base = handler->msr,
5887 .bitmap = (__u8 *)&zero,
5888 };
5889
5890 if (handler->rdmsr) {
5891 range->flags |= KVM_MSR_FILTER_READ;
5892 }
5893
5894 if (handler->wrmsr) {
5895 range->flags |= KVM_MSR_FILTER_WRITE;
5896 }
5897 }
5898 }
5899
5900 return kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter);
5901 }
5902
kvm_filter_msr(KVMState * s,uint32_t msr,QEMURDMSRHandler * rdmsr,QEMUWRMSRHandler * wrmsr)5903 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
5904 QEMUWRMSRHandler *wrmsr)
5905 {
5906 int i, ret;
5907
5908 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5909 if (!msr_handlers[i].msr) {
5910 msr_handlers[i] = (KVMMSRHandlers) {
5911 .msr = msr,
5912 .rdmsr = rdmsr,
5913 .wrmsr = wrmsr,
5914 };
5915
5916 ret = kvm_install_msr_filters(s);
5917 if (ret) {
5918 msr_handlers[i] = (KVMMSRHandlers) { };
5919 return ret;
5920 }
5921
5922 return 0;
5923 }
5924 }
5925
5926 return -EINVAL;
5927 }
5928
kvm_handle_rdmsr(X86CPU * cpu,struct kvm_run * run)5929 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run)
5930 {
5931 int i;
5932 bool r;
5933
5934 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5935 KVMMSRHandlers *handler = &msr_handlers[i];
5936 if (run->msr.index == handler->msr) {
5937 if (handler->rdmsr) {
5938 r = handler->rdmsr(cpu, handler->msr,
5939 (uint64_t *)&run->msr.data);
5940 run->msr.error = r ? 0 : 1;
5941 return 0;
5942 }
5943 }
5944 }
5945
5946 g_assert_not_reached();
5947 }
5948
kvm_handle_wrmsr(X86CPU * cpu,struct kvm_run * run)5949 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run)
5950 {
5951 int i;
5952 bool r;
5953
5954 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5955 KVMMSRHandlers *handler = &msr_handlers[i];
5956 if (run->msr.index == handler->msr) {
5957 if (handler->wrmsr) {
5958 r = handler->wrmsr(cpu, handler->msr, run->msr.data);
5959 run->msr.error = r ? 0 : 1;
5960 return 0;
5961 }
5962 }
5963 }
5964
5965 g_assert_not_reached();
5966 }
5967
5968 static bool has_sgx_provisioning;
5969
__kvm_enable_sgx_provisioning(KVMState * s)5970 static bool __kvm_enable_sgx_provisioning(KVMState *s)
5971 {
5972 int fd, ret;
5973
5974 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5975 return false;
5976 }
5977
5978 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5979 if (fd < 0) {
5980 return false;
5981 }
5982
5983 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5984 if (ret) {
5985 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5986 exit(1);
5987 }
5988 close(fd);
5989 return true;
5990 }
5991
kvm_enable_sgx_provisioning(KVMState * s)5992 bool kvm_enable_sgx_provisioning(KVMState *s)
5993 {
5994 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
5995 }
5996
host_supports_vmx(void)5997 static bool host_supports_vmx(void)
5998 {
5999 uint32_t ecx, unused;
6000
6001 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
6002 return ecx & CPUID_EXT_VMX;
6003 }
6004
6005 /*
6006 * Currently the handling here only supports use of KVM_HC_MAP_GPA_RANGE
6007 * to service guest-initiated memory attribute update requests so that
6008 * KVM_SET_MEMORY_ATTRIBUTES can update whether or not a page should be
6009 * backed by the private memory pool provided by guest_memfd, and as such
6010 * is only applicable to guest_memfd-backed guests (e.g. SNP/TDX).
6011 *
6012 * Other other use-cases for KVM_HC_MAP_GPA_RANGE, such as for SEV live
6013 * migration, are not implemented here currently.
6014 *
6015 * For the guest_memfd use-case, these exits will generally be synthesized
6016 * by KVM based on platform-specific hypercalls, like GHCB requests in the
6017 * case of SEV-SNP, and not issued directly within the guest though the
6018 * KVM_HC_MAP_GPA_RANGE hypercall. So in this case, KVM_HC_MAP_GPA_RANGE is
6019 * not actually advertised to guests via the KVM CPUID feature bit, as
6020 * opposed to SEV live migration where it would be. Since it is unlikely the
6021 * SEV live migration use-case would be useful for guest-memfd backed guests,
6022 * because private/shared page tracking is already provided through other
6023 * means, these 2 use-cases should be treated as being mutually-exclusive.
6024 */
kvm_handle_hc_map_gpa_range(X86CPU * cpu,struct kvm_run * run)6025 static int kvm_handle_hc_map_gpa_range(X86CPU *cpu, struct kvm_run *run)
6026 {
6027 struct kvm_pre_fault_memory mem;
6028 uint64_t gpa, size, attributes;
6029 int ret;
6030
6031 if (!machine_require_guest_memfd(current_machine))
6032 return -EINVAL;
6033
6034 gpa = run->hypercall.args[0];
6035 size = run->hypercall.args[1] * TARGET_PAGE_SIZE;
6036 attributes = run->hypercall.args[2];
6037
6038 trace_kvm_hc_map_gpa_range(gpa, size, attributes, run->hypercall.flags);
6039
6040 ret = kvm_convert_memory(gpa, size, attributes & KVM_MAP_GPA_RANGE_ENCRYPTED);
6041 if (ret || !kvm_pre_fault_memory_supported) {
6042 return ret;
6043 }
6044
6045 /*
6046 * Opportunistically pre-fault memory in. Failures are ignored so that any
6047 * errors in faulting in the memory will get captured in KVM page fault
6048 * path when the guest first accesses the page.
6049 */
6050 memset(&mem, 0, sizeof(mem));
6051 mem.gpa = gpa;
6052 mem.size = size;
6053 while (mem.size) {
6054 if (kvm_vcpu_ioctl(CPU(cpu), KVM_PRE_FAULT_MEMORY, &mem)) {
6055 break;
6056 }
6057 }
6058
6059 return 0;
6060 }
6061
kvm_handle_hypercall(X86CPU * cpu,struct kvm_run * run)6062 static int kvm_handle_hypercall(X86CPU *cpu, struct kvm_run *run)
6063 {
6064 if (run->hypercall.nr == KVM_HC_MAP_GPA_RANGE)
6065 return kvm_handle_hc_map_gpa_range(cpu, run);
6066
6067 return -EINVAL;
6068 }
6069
6070 #define VMX_INVALID_GUEST_STATE 0x80000021
6071
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)6072 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
6073 {
6074 X86CPU *cpu = X86_CPU(cs);
6075 uint64_t code;
6076 int ret;
6077 bool ctx_invalid;
6078 KVMState *state;
6079
6080 switch (run->exit_reason) {
6081 case KVM_EXIT_HLT:
6082 DPRINTF("handle_hlt\n");
6083 bql_lock();
6084 ret = kvm_handle_halt(cpu);
6085 bql_unlock();
6086 break;
6087 case KVM_EXIT_SET_TPR:
6088 ret = 0;
6089 break;
6090 case KVM_EXIT_TPR_ACCESS:
6091 bql_lock();
6092 ret = kvm_handle_tpr_access(cpu);
6093 bql_unlock();
6094 break;
6095 case KVM_EXIT_FAIL_ENTRY:
6096 code = run->fail_entry.hardware_entry_failure_reason;
6097 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
6098 code);
6099 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
6100 fprintf(stderr,
6101 "\nIf you're running a guest on an Intel machine without "
6102 "unrestricted mode\n"
6103 "support, the failure can be most likely due to the guest "
6104 "entering an invalid\n"
6105 "state for Intel VT. For example, the guest maybe running "
6106 "in big real mode\n"
6107 "which is not supported on less recent Intel processors."
6108 "\n\n");
6109 }
6110 ret = -1;
6111 break;
6112 case KVM_EXIT_EXCEPTION:
6113 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
6114 run->ex.exception, run->ex.error_code);
6115 ret = -1;
6116 break;
6117 case KVM_EXIT_DEBUG:
6118 DPRINTF("kvm_exit_debug\n");
6119 bql_lock();
6120 ret = kvm_handle_debug(cpu, &run->debug.arch);
6121 bql_unlock();
6122 break;
6123 case KVM_EXIT_HYPERV:
6124 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
6125 break;
6126 case KVM_EXIT_IOAPIC_EOI:
6127 ioapic_eoi_broadcast(run->eoi.vector);
6128 ret = 0;
6129 break;
6130 case KVM_EXIT_X86_BUS_LOCK:
6131 /* already handled in kvm_arch_post_run */
6132 ret = 0;
6133 break;
6134 case KVM_EXIT_NOTIFY:
6135 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
6136 state = KVM_STATE(current_accel());
6137 if (ctx_invalid ||
6138 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
6139 warn_report("KVM internal error: Encountered a notify exit "
6140 "with invalid context in guest.");
6141 ret = -1;
6142 } else {
6143 warn_report_once("KVM: Encountered a notify exit with valid "
6144 "context in guest. "
6145 "The guest could be misbehaving.");
6146 ret = 0;
6147 }
6148 break;
6149 case KVM_EXIT_X86_RDMSR:
6150 /* We only enable MSR filtering, any other exit is bogus */
6151 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6152 ret = kvm_handle_rdmsr(cpu, run);
6153 break;
6154 case KVM_EXIT_X86_WRMSR:
6155 /* We only enable MSR filtering, any other exit is bogus */
6156 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6157 ret = kvm_handle_wrmsr(cpu, run);
6158 break;
6159 #ifdef CONFIG_XEN_EMU
6160 case KVM_EXIT_XEN:
6161 ret = kvm_xen_handle_exit(cpu, &run->xen);
6162 break;
6163 #endif
6164 case KVM_EXIT_HYPERCALL:
6165 ret = kvm_handle_hypercall(cpu, run);
6166 break;
6167 case KVM_EXIT_SYSTEM_EVENT:
6168 switch (run->system_event.type) {
6169 case KVM_SYSTEM_EVENT_TDX_FATAL:
6170 ret = tdx_handle_report_fatal_error(cpu, run);
6171 break;
6172 default:
6173 ret = -1;
6174 break;
6175 }
6176 break;
6177 case KVM_EXIT_TDX:
6178 /*
6179 * run->tdx is already set up for the case where userspace
6180 * does not handle the TDVMCALL.
6181 */
6182 switch (run->tdx.nr) {
6183 case TDVMCALL_GET_QUOTE:
6184 tdx_handle_get_quote(cpu, run);
6185 break;
6186 case TDVMCALL_GET_TD_VM_CALL_INFO:
6187 tdx_handle_get_tdvmcall_info(cpu, run);
6188 break;
6189 case TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT:
6190 tdx_handle_setup_event_notify_interrupt(cpu, run);
6191 break;
6192 }
6193 ret = 0;
6194 break;
6195 default:
6196 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
6197 ret = -1;
6198 break;
6199 }
6200
6201 return ret;
6202 }
6203
kvm_arch_stop_on_emulation_error(CPUState * cs)6204 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
6205 {
6206 X86CPU *cpu = X86_CPU(cs);
6207 CPUX86State *env = &cpu->env;
6208
6209 kvm_cpu_synchronize_state(cs);
6210 return !(env->cr[0] & CR0_PE_MASK) ||
6211 ((env->segs[R_CS].selector & 3) != 3);
6212 }
6213
kvm_arch_init_irq_routing(KVMState * s)6214 void kvm_arch_init_irq_routing(KVMState *s)
6215 {
6216 /* We know at this point that we're using the in-kernel
6217 * irqchip, so we can use irqfds, and on x86 we know
6218 * we can use msi via irqfd and GSI routing.
6219 */
6220 kvm_msi_via_irqfd_allowed = true;
6221 kvm_gsi_routing_allowed = true;
6222
6223 if (kvm_irqchip_is_split()) {
6224 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
6225 int i;
6226
6227 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
6228 MSI routes for signaling interrupts to the local apics. */
6229 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
6230 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
6231 error_report("Could not enable split IRQ mode.");
6232 exit(1);
6233 }
6234 }
6235 kvm_irqchip_commit_route_changes(&c);
6236 }
6237 }
6238
kvm_arch_irqchip_create(KVMState * s)6239 int kvm_arch_irqchip_create(KVMState *s)
6240 {
6241 int ret;
6242 if (kvm_kernel_irqchip_split()) {
6243 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
6244 if (ret) {
6245 error_report("Could not enable split irqchip mode: %s",
6246 strerror(-ret));
6247 exit(1);
6248 } else {
6249 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
6250 kvm_split_irqchip = true;
6251 return 1;
6252 }
6253 } else {
6254 return 0;
6255 }
6256 }
6257
kvm_swizzle_msi_ext_dest_id(uint64_t address)6258 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
6259 {
6260 CPUX86State *env;
6261 uint64_t ext_id;
6262
6263 if (!first_cpu) {
6264 return address;
6265 }
6266 env = &X86_CPU(first_cpu)->env;
6267 if (!(env->features[FEAT_KVM] & CPUID_KVM_MSI_EXT_DEST_ID)) {
6268 return address;
6269 }
6270
6271 /*
6272 * If the remappable format bit is set, or the upper bits are
6273 * already set in address_hi, or the low extended bits aren't
6274 * there anyway, do nothing.
6275 */
6276 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
6277 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
6278 return address;
6279 }
6280
6281 address &= ~ext_id;
6282 address |= ext_id << 35;
6283 return address;
6284 }
6285
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)6286 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
6287 uint64_t address, uint32_t data, PCIDevice *dev)
6288 {
6289 X86IOMMUState *iommu = x86_iommu_get_default();
6290
6291 if (iommu) {
6292 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
6293
6294 if (class->int_remap) {
6295 int ret;
6296 MSIMessage src, dst;
6297
6298 src.address = route->u.msi.address_hi;
6299 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
6300 src.address |= route->u.msi.address_lo;
6301 src.data = route->u.msi.data;
6302
6303 ret = class->int_remap(iommu, &src, &dst, dev ? \
6304 pci_requester_id(dev) : \
6305 X86_IOMMU_SID_INVALID);
6306 if (ret) {
6307 trace_kvm_x86_fixup_msi_error(route->gsi);
6308 return 1;
6309 }
6310
6311 /*
6312 * Handled untranslated compatibility format interrupt with
6313 * extended destination ID in the low bits 11-5. */
6314 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
6315
6316 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
6317 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
6318 route->u.msi.data = dst.data;
6319 return 0;
6320 }
6321 }
6322
6323 #ifdef CONFIG_XEN_EMU
6324 if (xen_mode == XEN_EMULATE) {
6325 int handled = xen_evtchn_translate_pirq_msi(route, address, data);
6326
6327 /*
6328 * If it was a PIRQ and successfully routed (handled == 0) or it was
6329 * an error (handled < 0), return. If it wasn't a PIRQ, keep going.
6330 */
6331 if (handled <= 0) {
6332 return handled;
6333 }
6334 }
6335 #endif
6336
6337 address = kvm_swizzle_msi_ext_dest_id(address);
6338 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
6339 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
6340 return 0;
6341 }
6342
6343 typedef struct MSIRouteEntry MSIRouteEntry;
6344
6345 struct MSIRouteEntry {
6346 PCIDevice *dev; /* Device pointer */
6347 int vector; /* MSI/MSIX vector index */
6348 int virq; /* Virtual IRQ index */
6349 QLIST_ENTRY(MSIRouteEntry) list;
6350 };
6351
6352 /* List of used GSI routes */
6353 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
6354 QLIST_HEAD_INITIALIZER(msi_route_list);
6355
kvm_update_msi_routes_all(void * private,bool global,uint32_t index,uint32_t mask)6356 void kvm_update_msi_routes_all(void *private, bool global,
6357 uint32_t index, uint32_t mask)
6358 {
6359 int cnt = 0, vector;
6360 MSIRouteEntry *entry;
6361 MSIMessage msg;
6362 PCIDevice *dev;
6363
6364 /* TODO: explicit route update */
6365 QLIST_FOREACH(entry, &msi_route_list, list) {
6366 cnt++;
6367 vector = entry->vector;
6368 dev = entry->dev;
6369 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
6370 msg = msix_get_message(dev, vector);
6371 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
6372 msg = msi_get_message(dev, vector);
6373 } else {
6374 /*
6375 * Either MSI/MSIX is disabled for the device, or the
6376 * specific message was masked out. Skip this one.
6377 */
6378 continue;
6379 }
6380 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
6381 }
6382 kvm_irqchip_commit_routes(kvm_state);
6383 trace_kvm_x86_update_msi_routes(cnt);
6384 }
6385
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)6386 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
6387 int vector, PCIDevice *dev)
6388 {
6389 static bool notify_list_inited = false;
6390 MSIRouteEntry *entry;
6391
6392 if (!dev) {
6393 /* These are (possibly) IOAPIC routes only used for split
6394 * kernel irqchip mode, while what we are housekeeping are
6395 * PCI devices only. */
6396 return 0;
6397 }
6398
6399 entry = g_new0(MSIRouteEntry, 1);
6400 entry->dev = dev;
6401 entry->vector = vector;
6402 entry->virq = route->gsi;
6403 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
6404
6405 trace_kvm_x86_add_msi_route(route->gsi);
6406
6407 if (!notify_list_inited) {
6408 /* For the first time we do add route, add ourselves into
6409 * IOMMU's IEC notify list if needed. */
6410 X86IOMMUState *iommu = x86_iommu_get_default();
6411 if (iommu) {
6412 x86_iommu_iec_register_notifier(iommu,
6413 kvm_update_msi_routes_all,
6414 NULL);
6415 }
6416 notify_list_inited = true;
6417 }
6418 return 0;
6419 }
6420
kvm_arch_release_virq_post(int virq)6421 int kvm_arch_release_virq_post(int virq)
6422 {
6423 MSIRouteEntry *entry, *next;
6424 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
6425 if (entry->virq == virq) {
6426 trace_kvm_x86_remove_msi_route(virq);
6427 QLIST_REMOVE(entry, list);
6428 g_free(entry);
6429 break;
6430 }
6431 }
6432 return 0;
6433 }
6434
kvm_arch_msi_data_to_gsi(uint32_t data)6435 int kvm_arch_msi_data_to_gsi(uint32_t data)
6436 {
6437 abort();
6438 }
6439
kvm_has_waitpkg(void)6440 bool kvm_has_waitpkg(void)
6441 {
6442 return has_msr_umwait;
6443 }
6444
6445 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
6446
kvm_request_xsave_components(X86CPU * cpu,uint64_t mask)6447 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
6448 {
6449 KVMState *s = kvm_state;
6450 uint64_t supported;
6451
6452 mask &= XSTATE_DYNAMIC_MASK;
6453 if (!mask) {
6454 return;
6455 }
6456 /*
6457 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
6458 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
6459 * about them already because they are not supported features.
6460 */
6461 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
6462 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
6463 mask &= supported;
6464
6465 while (mask) {
6466 int bit = ctz64(mask);
6467 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
6468 if (rc) {
6469 /*
6470 * Older kernel version (<5.17) do not support
6471 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
6472 * any dynamic feature from kvm_arch_get_supported_cpuid.
6473 */
6474 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
6475 "for feature bit %d", bit);
6476 }
6477 mask &= ~BIT_ULL(bit);
6478 }
6479 }
6480
kvm_arch_get_notify_vmexit(Object * obj,Error ** errp)6481 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
6482 {
6483 KVMState *s = KVM_STATE(obj);
6484 return s->notify_vmexit;
6485 }
6486
kvm_arch_set_notify_vmexit(Object * obj,int value,Error ** errp)6487 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
6488 {
6489 KVMState *s = KVM_STATE(obj);
6490
6491 if (s->fd != -1) {
6492 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6493 return;
6494 }
6495
6496 s->notify_vmexit = value;
6497 }
6498
kvm_arch_get_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6499 static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
6500 const char *name, void *opaque,
6501 Error **errp)
6502 {
6503 KVMState *s = KVM_STATE(obj);
6504 uint32_t value = s->notify_window;
6505
6506 visit_type_uint32(v, name, &value, errp);
6507 }
6508
kvm_arch_set_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6509 static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
6510 const char *name, void *opaque,
6511 Error **errp)
6512 {
6513 KVMState *s = KVM_STATE(obj);
6514 uint32_t value;
6515
6516 if (s->fd != -1) {
6517 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6518 return;
6519 }
6520
6521 if (!visit_type_uint32(v, name, &value, errp)) {
6522 return;
6523 }
6524
6525 s->notify_window = value;
6526 }
6527
kvm_arch_get_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6528 static void kvm_arch_get_xen_version(Object *obj, Visitor *v,
6529 const char *name, void *opaque,
6530 Error **errp)
6531 {
6532 KVMState *s = KVM_STATE(obj);
6533 uint32_t value = s->xen_version;
6534
6535 visit_type_uint32(v, name, &value, errp);
6536 }
6537
kvm_arch_set_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6538 static void kvm_arch_set_xen_version(Object *obj, Visitor *v,
6539 const char *name, void *opaque,
6540 Error **errp)
6541 {
6542 KVMState *s = KVM_STATE(obj);
6543 Error *error = NULL;
6544 uint32_t value;
6545
6546 visit_type_uint32(v, name, &value, &error);
6547 if (error) {
6548 error_propagate(errp, error);
6549 return;
6550 }
6551
6552 s->xen_version = value;
6553 if (value && xen_mode == XEN_DISABLED) {
6554 xen_mode = XEN_EMULATE;
6555 }
6556 }
6557
kvm_arch_get_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6558 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v,
6559 const char *name, void *opaque,
6560 Error **errp)
6561 {
6562 KVMState *s = KVM_STATE(obj);
6563 uint16_t value = s->xen_gnttab_max_frames;
6564
6565 visit_type_uint16(v, name, &value, errp);
6566 }
6567
kvm_arch_set_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6568 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v,
6569 const char *name, void *opaque,
6570 Error **errp)
6571 {
6572 KVMState *s = KVM_STATE(obj);
6573 Error *error = NULL;
6574 uint16_t value;
6575
6576 visit_type_uint16(v, name, &value, &error);
6577 if (error) {
6578 error_propagate(errp, error);
6579 return;
6580 }
6581
6582 s->xen_gnttab_max_frames = value;
6583 }
6584
kvm_arch_get_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6585 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6586 const char *name, void *opaque,
6587 Error **errp)
6588 {
6589 KVMState *s = KVM_STATE(obj);
6590 uint16_t value = s->xen_evtchn_max_pirq;
6591
6592 visit_type_uint16(v, name, &value, errp);
6593 }
6594
kvm_arch_set_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6595 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6596 const char *name, void *opaque,
6597 Error **errp)
6598 {
6599 KVMState *s = KVM_STATE(obj);
6600 Error *error = NULL;
6601 uint16_t value;
6602
6603 visit_type_uint16(v, name, &value, &error);
6604 if (error) {
6605 error_propagate(errp, error);
6606 return;
6607 }
6608
6609 s->xen_evtchn_max_pirq = value;
6610 }
6611
kvm_arch_accel_class_init(ObjectClass * oc)6612 void kvm_arch_accel_class_init(ObjectClass *oc)
6613 {
6614 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
6615 &NotifyVmexitOption_lookup,
6616 kvm_arch_get_notify_vmexit,
6617 kvm_arch_set_notify_vmexit);
6618 object_class_property_set_description(oc, "notify-vmexit",
6619 "Enable notify VM exit");
6620
6621 object_class_property_add(oc, "notify-window", "uint32",
6622 kvm_arch_get_notify_window,
6623 kvm_arch_set_notify_window,
6624 NULL, NULL);
6625 object_class_property_set_description(oc, "notify-window",
6626 "Clock cycles without an event window "
6627 "after which a notification VM exit occurs");
6628
6629 object_class_property_add(oc, "xen-version", "uint32",
6630 kvm_arch_get_xen_version,
6631 kvm_arch_set_xen_version,
6632 NULL, NULL);
6633 object_class_property_set_description(oc, "xen-version",
6634 "Xen version to be emulated "
6635 "(in XENVER_version form "
6636 "e.g. 0x4000a for 4.10)");
6637
6638 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16",
6639 kvm_arch_get_xen_gnttab_max_frames,
6640 kvm_arch_set_xen_gnttab_max_frames,
6641 NULL, NULL);
6642 object_class_property_set_description(oc, "xen-gnttab-max-frames",
6643 "Maximum number of grant table frames");
6644
6645 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16",
6646 kvm_arch_get_xen_evtchn_max_pirq,
6647 kvm_arch_set_xen_evtchn_max_pirq,
6648 NULL, NULL);
6649 object_class_property_set_description(oc, "xen-evtchn-max-pirq",
6650 "Maximum number of Xen PIRQs");
6651 }
6652
kvm_set_max_apic_id(uint32_t max_apic_id)6653 void kvm_set_max_apic_id(uint32_t max_apic_id)
6654 {
6655 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id);
6656 }
6657