1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #ifndef RVU_H
9 #define RVU_H
10 
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13 
14 #include "rvu_struct.h"
15 #include "rvu_devlink.h"
16 #include "common.h"
17 #include "mbox.h"
18 #include "npc.h"
19 #include "rvu_reg.h"
20 #include "ptp.h"
21 
22 /* PCI device IDs */
23 #define	PCI_DEVID_OCTEONTX2_RVU_AF		0xA065
24 #define	PCI_DEVID_OCTEONTX2_LBK			0xA061
25 
26 /* Subsystem Device ID */
27 #define PCI_SUBSYS_DEVID_98XX                  0xB100
28 #define PCI_SUBSYS_DEVID_96XX                  0xB200
29 #define PCI_SUBSYS_DEVID_CN10K_A	       0xB900
30 #define PCI_SUBSYS_DEVID_CNF10K_A	       0xBA00
31 #define PCI_SUBSYS_DEVID_CNF10K_B              0xBC00
32 #define PCI_SUBSYS_DEVID_CN10K_B               0xBD00
33 
34 /* PCI BAR nos */
35 #define	PCI_AF_REG_BAR_NUM			0
36 #define	PCI_PF_REG_BAR_NUM			2
37 #define	PCI_MBOX_BAR_NUM			4
38 
39 #define NAME_SIZE				32
40 #define MAX_NIX_BLKS				2
41 #define MAX_CPT_BLKS				2
42 
43 /* PF_FUNC */
44 #define RVU_PFVF_PF_SHIFT	10
45 #define RVU_PFVF_PF_MASK	0x3F
46 #define RVU_PFVF_FUNC_SHIFT	0
47 #define RVU_PFVF_FUNC_MASK	0x3FF
48 
49 #ifdef CONFIG_DEBUG_FS
50 struct dump_ctx {
51 	int	lf;
52 	int	id;
53 	bool	all;
54 };
55 
56 struct cpt_ctx {
57 	int blkaddr;
58 	struct rvu *rvu;
59 };
60 
61 struct rvu_debugfs {
62 	struct dentry *root;
63 	struct dentry *cgx_root;
64 	struct dentry *cgx;
65 	struct dentry *lmac;
66 	struct dentry *npa;
67 	struct dentry *nix;
68 	struct dentry *npc;
69 	struct dentry *cpt;
70 	struct dentry *mcs_root;
71 	struct dentry *mcs;
72 	struct dentry *mcs_rx;
73 	struct dentry *mcs_tx;
74 	struct dump_ctx npa_aura_ctx;
75 	struct dump_ctx npa_pool_ctx;
76 	struct dump_ctx nix_cq_ctx;
77 	struct dump_ctx nix_rq_ctx;
78 	struct dump_ctx nix_sq_ctx;
79 	struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
80 	int npa_qsize_id;
81 	int nix_qsize_id;
82 };
83 #endif
84 
85 struct rvu_work {
86 	struct	work_struct work;
87 	struct	rvu *rvu;
88 	int num_msgs;
89 	int up_num_msgs;
90 };
91 
92 struct rsrc_bmap {
93 	unsigned long *bmap;	/* Pointer to resource bitmap */
94 	u16  max;		/* Max resource id or count */
95 };
96 
97 struct rvu_block {
98 	struct rsrc_bmap	lf;
99 	struct admin_queue	*aq; /* NIX/NPA AQ */
100 	u16  *fn_map; /* LF to pcifunc mapping */
101 	bool multislot;
102 	bool implemented;
103 	u8   addr;  /* RVU_BLOCK_ADDR_E */
104 	u8   type;  /* RVU_BLOCK_TYPE_E */
105 	u8   lfshift;
106 	u64  lookup_reg;
107 	u64  pf_lfcnt_reg;
108 	u64  vf_lfcnt_reg;
109 	u64  lfcfg_reg;
110 	u64  msixcfg_reg;
111 	u64  lfreset_reg;
112 	unsigned char name[NAME_SIZE];
113 	struct rvu *rvu;
114 	u64 cpt_flt_eng_map[3];
115 	u64 cpt_rcvrd_eng_map[3];
116 };
117 
118 struct nix_mcast {
119 	struct qmem	*mce_ctx;
120 	struct qmem	*mcast_buf;
121 	int		replay_pkind;
122 	int		next_free_mce;
123 	struct mutex	mce_lock; /* Serialize MCE updates */
124 };
125 
126 struct nix_mce_list {
127 	struct hlist_head	head;
128 	int			count;
129 	int			max;
130 };
131 
132 /* layer metadata to uniquely identify a packet header field */
133 struct npc_layer_mdata {
134 	u8 lid;
135 	u8 ltype;
136 	u8 hdr;
137 	u8 key;
138 	u8 len;
139 };
140 
141 /* Structure to represent a field present in the
142  * generated key. A key field may present anywhere and can
143  * be of any size in the generated key. Once this structure
144  * is populated for fields of interest then field's presence
145  * and location (if present) can be known.
146  */
147 struct npc_key_field {
148 	/* Masks where all set bits indicate position
149 	 * of a field in the key
150 	 */
151 	u64 kw_mask[NPC_MAX_KWS_IN_KEY];
152 	/* Number of words in the key a field spans. If a field is
153 	 * of 16 bytes and key offset is 4 then the field will use
154 	 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
155 	 * nr_kws will be 3(KW0, KW1 and KW2).
156 	 */
157 	int nr_kws;
158 	/* used by packet header fields */
159 	struct npc_layer_mdata layer_mdata;
160 };
161 
162 struct npc_mcam {
163 	struct rsrc_bmap counters;
164 	struct mutex	lock;	/* MCAM entries and counters update lock */
165 	unsigned long	*bmap;		/* bitmap, 0 => bmap_entries */
166 	unsigned long	*bmap_reverse;	/* Reverse bitmap, bmap_entries => 0 */
167 	u16	bmap_entries;	/* Number of unreserved MCAM entries */
168 	u16	bmap_fcnt;	/* MCAM entries free count */
169 	u16	*entry2pfvf_map;
170 	u16	*entry2cntr_map;
171 	u16	*cntr2pfvf_map;
172 	u16	*cntr_refcnt;
173 	u16	*entry2target_pffunc;
174 	u8	keysize;	/* MCAM keysize 112/224/448 bits */
175 	u8	banks;		/* Number of MCAM banks */
176 	u8	banks_per_entry;/* Number of keywords in key */
177 	u16	banksize;	/* Number of MCAM entries in each bank */
178 	u16	total_entries;	/* Total number of MCAM entries */
179 	u16	nixlf_offset;	/* Offset of nixlf rsvd uncast entries */
180 	u16	pf_offset;	/* Offset of PF's rsvd bcast, promisc entries */
181 	u16	lprio_count;
182 	u16	lprio_start;
183 	u16	hprio_count;
184 	u16	hprio_end;
185 	u16     rx_miss_act_cntr; /* Counter for RX MISS action */
186 	/* fields present in the generated key */
187 	struct npc_key_field	tx_key_fields[NPC_KEY_FIELDS_MAX];
188 	struct npc_key_field	rx_key_fields[NPC_KEY_FIELDS_MAX];
189 	u64	tx_features;
190 	u64	rx_features;
191 	struct list_head mcam_rules;
192 };
193 
194 /* Structure for per RVU func info ie PF/VF */
195 struct rvu_pfvf {
196 	bool		npalf; /* Only one NPALF per RVU_FUNC */
197 	bool		nixlf; /* Only one NIXLF per RVU_FUNC */
198 	u16		sso;
199 	u16		ssow;
200 	u16		cptlfs;
201 	u16		timlfs;
202 	u16		cpt1_lfs;
203 	u8		cgx_lmac;
204 
205 	/* Block LF's MSIX vector info */
206 	struct rsrc_bmap msix;      /* Bitmap for MSIX vector alloc */
207 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
208 	u16		 *msix_lfmap; /* Vector to block LF mapping */
209 
210 	/* NPA contexts */
211 	struct qmem	*aura_ctx;
212 	struct qmem	*pool_ctx;
213 	struct qmem	*npa_qints_ctx;
214 	unsigned long	*aura_bmap;
215 	unsigned long	*pool_bmap;
216 
217 	/* NIX contexts */
218 	struct qmem	*rq_ctx;
219 	struct qmem	*sq_ctx;
220 	struct qmem	*cq_ctx;
221 	struct qmem	*rss_ctx;
222 	struct qmem	*cq_ints_ctx;
223 	struct qmem	*nix_qints_ctx;
224 	unsigned long	*sq_bmap;
225 	unsigned long	*rq_bmap;
226 	unsigned long	*cq_bmap;
227 
228 	u16		rx_chan_base;
229 	u16		tx_chan_base;
230 	u8              rx_chan_cnt; /* total number of RX channels */
231 	u8              tx_chan_cnt; /* total number of TX channels */
232 	u16		maxlen;
233 	u16		minlen;
234 
235 	bool		hw_rx_tstamp_en; /* Is rx_tstamp enabled */
236 	u8		mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
237 	u8		default_mac[ETH_ALEN]; /* MAC address from FWdata */
238 
239 	/* Broadcast/Multicast/Promisc pkt replication info */
240 	u16			bcast_mce_idx;
241 	u16			mcast_mce_idx;
242 	u16			promisc_mce_idx;
243 	struct nix_mce_list	bcast_mce_list;
244 	struct nix_mce_list	mcast_mce_list;
245 	struct nix_mce_list	promisc_mce_list;
246 	bool			use_mce_list;
247 
248 	struct rvu_npc_mcam_rule *def_ucast_rule;
249 
250 	bool	cgx_in_use; /* this PF/VF using CGX? */
251 	int	cgx_users;  /* number of cgx users - used only by PFs */
252 
253 	int     intf_mode;
254 	u8	nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
255 	u8	nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
256 	u8	nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
257 	u8	lbkid;	     /* NIX0/1 lbk link ID */
258 	u64     lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
259 	u64     lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
260 	unsigned long flags;
261 	struct  sdp_node_info *sdp_info;
262 };
263 
264 enum rvu_pfvf_flags {
265 	NIXLF_INITIALIZED = 0,
266 	PF_SET_VF_MAC,
267 	PF_SET_VF_CFG,
268 	PF_SET_VF_TRUSTED,
269 };
270 
271 #define RVU_CLEAR_VF_PERM  ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
272 
273 struct nix_txsch {
274 	struct rsrc_bmap schq;
275 	u8   lvl;
276 #define NIX_TXSCHQ_FREE		      BIT_ULL(1)
277 #define NIX_TXSCHQ_CFG_DONE	      BIT_ULL(0)
278 #define TXSCH_MAP_FUNC(__pfvf_map)    ((__pfvf_map) & 0xFFFF)
279 #define TXSCH_MAP_FLAGS(__pfvf_map)   ((__pfvf_map) >> 16)
280 #define TXSCH_MAP(__func, __flags)    (((__func) & 0xFFFF) | ((__flags) << 16))
281 #define TXSCH_SET_FLAG(__pfvf_map, flag)    ((__pfvf_map) | ((flag) << 16))
282 	u32  *pfvf_map;
283 };
284 
285 struct nix_mark_format {
286 	u8 total;
287 	u8 in_use;
288 	u32 *cfg;
289 };
290 
291 /* smq(flush) to tl1 cir/pir info */
292 struct nix_smq_tree_ctx {
293 	u16 schq;
294 	u64 cir_off;
295 	u64 cir_val;
296 	u64 pir_off;
297 	u64 pir_val;
298 };
299 
300 /* smq flush context */
301 struct nix_smq_flush_ctx {
302 	int smq;
303 	struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
304 };
305 
306 struct npc_pkind {
307 	struct rsrc_bmap rsrc;
308 	u32	*pfchan_map;
309 };
310 
311 struct nix_flowkey {
312 #define NIX_FLOW_KEY_ALG_MAX 32
313 	u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
314 	int in_use;
315 };
316 
317 struct nix_lso {
318 	u8 total;
319 	u8 in_use;
320 };
321 
322 struct nix_txvlan {
323 #define NIX_TX_VTAG_DEF_MAX 0x400
324 	struct rsrc_bmap rsrc;
325 	u16 *entry2pfvf_map;
326 	struct mutex rsrc_lock; /* Serialize resource alloc/free */
327 };
328 
329 struct nix_ipolicer {
330 	struct rsrc_bmap band_prof;
331 	u16 *pfvf_map;
332 	u16 *match_id;
333 	u16 *ref_count;
334 };
335 
336 struct nix_hw {
337 	int blkaddr;
338 	struct rvu *rvu;
339 	struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
340 	struct nix_mcast mcast;
341 	struct nix_flowkey flowkey;
342 	struct nix_mark_format mark_format;
343 	struct nix_lso lso;
344 	struct nix_txvlan txvlan;
345 	struct nix_ipolicer *ipolicer;
346 	u64    *tx_credits;
347 	u8	cc_mcs_cnt;
348 };
349 
350 /* RVU block's capabilities or functionality,
351  * which vary by silicon version/skew.
352  */
353 struct hw_cap {
354 	/* Transmit side supported functionality */
355 	u8	nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
356 	u16	nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
357 	u16	nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
358 	u16	nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
359 	bool	nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
360 	bool	nix_shaping;		 /* Is shaping and coloring supported */
361 	bool    nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
362 	bool	nix_tx_link_bp;		 /* Can link backpressure TL queues ? */
363 	bool	nix_rx_multicast;	 /* Rx packet replication support */
364 	bool	nix_common_dwrr_mtu;	 /* Common DWRR MTU for quantum config */
365 	bool	per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
366 	bool	programmable_chans; /* Channels programmable ? */
367 	bool	ipolicer;
368 	bool	nix_multiple_dwrr_mtu;   /* Multiple DWRR_MTU to choose from */
369 	bool	npc_hash_extract; /* Hash extract enabled ? */
370 	bool	npc_exact_match_enabled; /* Exact match supported ? */
371 };
372 
373 struct rvu_hwinfo {
374 	u8	total_pfs;   /* MAX RVU PFs HW supports */
375 	u16	total_vfs;   /* Max RVU VFs HW supports */
376 	u16	max_vfs_per_pf; /* Max VFs that can be attached to a PF */
377 	u8	cgx;
378 	u8	lmac_per_cgx;
379 	u16	cgx_chan_base;	/* CGX base channel number */
380 	u16	lbk_chan_base;	/* LBK base channel number */
381 	u16	sdp_chan_base;	/* SDP base channel number */
382 	u16	cpt_chan_base;	/* CPT base channel number */
383 	u8	cgx_links;
384 	u8	lbk_links;
385 	u8	sdp_links;
386 	u8	cpt_links;	/* Number of CPT links */
387 	u8	npc_kpus;          /* No of parser units */
388 	u8	npc_pkinds;        /* No of port kinds */
389 	u8	npc_intfs;         /* No of interfaces */
390 	u8	npc_kpu_entries;   /* No of KPU entries */
391 	u16	npc_counters;	   /* No of match stats counters */
392 	u32	lbk_bufsize;	   /* FIFO size supported by LBK */
393 	bool	npc_ext_set;	   /* Extended register set */
394 	u64     npc_stat_ena;      /* Match stats enable bit */
395 
396 	struct hw_cap    cap;
397 	struct rvu_block block[BLK_COUNT]; /* Block info */
398 	struct nix_hw    *nix;
399 	struct rvu	 *rvu;
400 	struct npc_pkind pkind;
401 	struct npc_mcam  mcam;
402 	struct npc_exact_table *table;
403 };
404 
405 struct mbox_wq_info {
406 	struct otx2_mbox mbox;
407 	struct rvu_work *mbox_wrk;
408 
409 	struct otx2_mbox mbox_up;
410 	struct rvu_work *mbox_wrk_up;
411 
412 	struct workqueue_struct *mbox_wq;
413 };
414 
415 struct rvu_fwdata {
416 #define RVU_FWDATA_HEADER_MAGIC	0xCFDA	/* Custom Firmware Data*/
417 #define RVU_FWDATA_VERSION	0x0001
418 	u32 header_magic;
419 	u32 version;		/* version id */
420 
421 	/* MAC address */
422 #define PF_MACNUM_MAX	32
423 #define VF_MACNUM_MAX	256
424 	u64 pf_macs[PF_MACNUM_MAX];
425 	u64 vf_macs[VF_MACNUM_MAX];
426 	u64 sclk;
427 	u64 rclk;
428 	u64 mcam_addr;
429 	u64 mcam_sz;
430 	u64 msixtr_base;
431 	u32 ptp_ext_clk_rate;
432 	u32 ptp_ext_tstamp;
433 #define FWDATA_RESERVED_MEM 1022
434 	u64 reserved[FWDATA_RESERVED_MEM];
435 #define CGX_MAX         9
436 #define CGX_LMACS_MAX   4
437 #define CGX_LMACS_USX   8
438 	union {
439 		struct cgx_lmac_fwdata_s
440 			cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
441 		struct cgx_lmac_fwdata_s
442 			cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX];
443 	};
444 	/* Do not add new fields below this line */
445 };
446 
447 struct ptp;
448 
449 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
450  * source where it came from.
451  */
452 struct npc_kpu_profile_adapter {
453 	const char			*name;
454 	u64				version;
455 	const struct npc_lt_def_cfg	*lt_def;
456 	const struct npc_kpu_profile_action	*ikpu; /* array[pkinds] */
457 	const struct npc_kpu_profile	*kpu; /* array[kpus] */
458 	struct npc_mcam_kex		*mkex;
459 	struct npc_mcam_kex_hash	*mkex_hash;
460 	bool				custom;
461 	size_t				pkinds;
462 	size_t				kpus;
463 };
464 
465 #define RVU_SWITCH_LBK_CHAN	63
466 
467 struct rvu_switch {
468 	struct mutex switch_lock; /* Serialize flow installation */
469 	u32 used_entries;
470 	u16 *entry2pcifunc;
471 	u16 mode;
472 	u16 start_entry;
473 };
474 
475 struct rvu {
476 	void __iomem		*afreg_base;
477 	void __iomem		*pfreg_base;
478 	struct pci_dev		*pdev;
479 	struct device		*dev;
480 	struct rvu_hwinfo       *hw;
481 	struct rvu_pfvf		*pf;
482 	struct rvu_pfvf		*hwvf;
483 	struct mutex		rsrc_lock; /* Serialize resource alloc/free */
484 	struct mutex		alias_lock; /* Serialize bar2 alias access */
485 	int			vfs; /* Number of VFs attached to RVU */
486 	int			nix_blkaddr[MAX_NIX_BLKS];
487 
488 	/* Mbox */
489 	struct mbox_wq_info	afpf_wq_info;
490 	struct mbox_wq_info	afvf_wq_info;
491 
492 	/* PF FLR */
493 	struct rvu_work		*flr_wrk;
494 	struct workqueue_struct *flr_wq;
495 	struct mutex		flr_lock; /* Serialize FLRs */
496 
497 	/* MSI-X */
498 	u16			num_vec;
499 	char			*irq_name;
500 	bool			*irq_allocated;
501 	dma_addr_t		msix_base_iova;
502 	u64			msixtr_base_phy; /* Register reset value */
503 
504 	/* CGX */
505 #define PF_CGXMAP_BASE		1 /* PF 0 is reserved for RVU PF */
506 	u16			cgx_mapped_vfs; /* maximum CGX mapped VFs */
507 	u8			cgx_mapped_pfs;
508 	u8			cgx_cnt_max;	 /* CGX port count max */
509 	u8			*pf2cgxlmac_map; /* pf to cgx_lmac map */
510 	u64			*cgxlmac2pf_map; /* bitmap of mapped pfs for
511 						  * every cgx lmac port
512 						  */
513 	unsigned long		pf_notify_bmap; /* Flags for PF notification */
514 	void			**cgx_idmap; /* cgx id to cgx data map table */
515 	struct			work_struct cgx_evh_work;
516 	struct			workqueue_struct *cgx_evh_wq;
517 	spinlock_t		cgx_evq_lock; /* cgx event queue lock */
518 	struct list_head	cgx_evq_head; /* cgx event queue head */
519 	struct mutex		cgx_cfg_lock; /* serialize cgx configuration */
520 
521 	char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
522 	char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
523 
524 	/* Firmware data */
525 	struct rvu_fwdata	*fwdata;
526 	void			*kpu_fwdata;
527 	size_t			kpu_fwdata_sz;
528 	void __iomem		*kpu_prfl_addr;
529 
530 	/* NPC KPU data */
531 	struct npc_kpu_profile_adapter kpu;
532 
533 	struct ptp		*ptp;
534 
535 	int			mcs_blk_cnt;
536 	int			cpt_pf_num;
537 
538 #ifdef CONFIG_DEBUG_FS
539 	struct rvu_debugfs	rvu_dbg;
540 #endif
541 	struct rvu_devlink	*rvu_dl;
542 
543 	/* RVU switch implementation over NPC with DMAC rules */
544 	struct rvu_switch	rswitch;
545 
546 	struct			work_struct mcs_intr_work;
547 	struct			workqueue_struct *mcs_intr_wq;
548 	struct list_head	mcs_intrq_head;
549 	/* mcs interrupt queue lock */
550 	spinlock_t		mcs_intrq_lock;
551 	/* CPT interrupt lock */
552 	spinlock_t		cpt_intr_lock;
553 
554 	struct mutex		mbox_lock; /* Serialize mbox up and down msgs */
555 };
556 
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)557 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
558 {
559 	writeq(val, rvu->afreg_base + ((block << 28) | offset));
560 }
561 
rvu_read64(struct rvu * rvu,u64 block,u64 offset)562 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
563 {
564 	return readq(rvu->afreg_base + ((block << 28) | offset));
565 }
566 
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)567 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
568 {
569 	writeq(val, rvu->pfreg_base + offset);
570 }
571 
rvupf_read64(struct rvu * rvu,u64 offset)572 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
573 {
574 	return readq(rvu->pfreg_base + offset);
575 }
576 
rvu_bar2_sel_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)577 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
578 {
579 	/* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of
580 	 * write operation.
581 	 */
582 	rvu_write64(rvu, block, offset, val);
583 	rvu_read64(rvu, block, offset);
584 	/* Barrier to ensure read completes before accessing LF registers */
585 	mb();
586 }
587 
588 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)589 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
590 {
591 	struct pci_dev *pdev = rvu->pdev;
592 	/* 96XX A0/B0, 95XX A0/A1/B0 chips */
593 	return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
594 		(pdev->revision == 0x10) || (pdev->revision == 0x11) ||
595 		(pdev->revision == 0x14));
596 }
597 
is_rvu_96xx_A0(struct rvu * rvu)598 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
599 {
600 	struct pci_dev *pdev = rvu->pdev;
601 
602 	return (pdev->revision == 0x00);
603 }
604 
is_rvu_96xx_B0(struct rvu * rvu)605 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
606 {
607 	struct pci_dev *pdev = rvu->pdev;
608 
609 	return (pdev->revision == 0x00) || (pdev->revision == 0x01);
610 }
611 
is_rvu_95xx_A0(struct rvu * rvu)612 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
613 {
614 	struct pci_dev *pdev = rvu->pdev;
615 
616 	return (pdev->revision == 0x10) || (pdev->revision == 0x11);
617 }
618 
619 /* REVID for PCIe devices.
620  * Bits 0..1: minor pass, bit 3..2: major pass
621  * bits 7..4: midr id
622  */
623 #define PCI_REVISION_ID_96XX		0x00
624 #define PCI_REVISION_ID_95XX		0x10
625 #define PCI_REVISION_ID_95XXN		0x20
626 #define PCI_REVISION_ID_98XX		0x30
627 #define PCI_REVISION_ID_95XXMM		0x40
628 #define PCI_REVISION_ID_95XXO		0xE0
629 
is_rvu_otx2(struct rvu * rvu)630 static inline bool is_rvu_otx2(struct rvu *rvu)
631 {
632 	struct pci_dev *pdev = rvu->pdev;
633 
634 	u8 midr = pdev->revision & 0xF0;
635 
636 	return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
637 		midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
638 		midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
639 }
640 
is_cnf10ka_a0(struct rvu * rvu)641 static inline bool is_cnf10ka_a0(struct rvu *rvu)
642 {
643 	struct pci_dev *pdev = rvu->pdev;
644 
645 	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A &&
646 	    (pdev->revision & 0x0F) == 0x0)
647 		return true;
648 	return false;
649 }
650 
is_rvu_npc_hash_extract_en(struct rvu * rvu)651 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
652 {
653 	u64 npc_const3;
654 
655 	npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
656 	if (!(npc_const3 & BIT_ULL(62)))
657 		return false;
658 
659 	return true;
660 }
661 
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)662 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
663 				   u8 lmacid, u8 chan)
664 {
665 	u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
666 	u16 cgx_chans = nix_const & 0xFFULL;
667 	struct rvu_hwinfo *hw = rvu->hw;
668 
669 	if (!hw->cap.programmable_chans)
670 		return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
671 
672 	return rvu->hw->cgx_chan_base +
673 		(cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
674 }
675 
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)676 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
677 				   u8 chan)
678 {
679 	u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
680 	u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
681 	struct rvu_hwinfo *hw = rvu->hw;
682 
683 	if (!hw->cap.programmable_chans)
684 		return NIX_CHAN_LBK_CHX(lbkid, chan);
685 
686 	return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
687 }
688 
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)689 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
690 {
691 	struct rvu_hwinfo *hw = rvu->hw;
692 
693 	if (!hw->cap.programmable_chans)
694 		return NIX_CHAN_SDP_CHX(chan);
695 
696 	return hw->sdp_chan_base + chan;
697 }
698 
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)699 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
700 {
701 	return rvu->hw->cpt_chan_base + chan;
702 }
703 
is_rvu_supports_nix1(struct rvu * rvu)704 static inline bool is_rvu_supports_nix1(struct rvu *rvu)
705 {
706 	struct pci_dev *pdev = rvu->pdev;
707 
708 	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
709 		return true;
710 
711 	return false;
712 }
713 
714 /* Function Prototypes
715  * RVU
716  */
is_afvf(u16 pcifunc)717 static inline bool is_afvf(u16 pcifunc)
718 {
719 	return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
720 }
721 
is_vf(u16 pcifunc)722 static inline bool is_vf(u16 pcifunc)
723 {
724 	return !!(pcifunc & RVU_PFVF_FUNC_MASK);
725 }
726 
727 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)728 static inline bool is_pffunc_af(u16 pcifunc)
729 {
730 	return !pcifunc;
731 }
732 
is_rvu_fwdata_valid(struct rvu * rvu)733 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
734 {
735 	return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
736 		(rvu->fwdata->version == RVU_FWDATA_VERSION);
737 }
738 
739 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
740 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
741 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
742 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
743 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
744 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
745 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
746 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
747 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
748 int rvu_get_pf(u16 pcifunc);
749 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
750 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
751 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
752 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
753 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
754 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
755 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
756 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
757 int rvu_get_num_lbk_chans(void);
758 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
759 			      u16 global_slot, u16 *slot_in_block);
760 
761 /* RVU HW reg validation */
762 enum regmap_block {
763 	TXSCHQ_HWREGMAP = 0,
764 	MAX_HWREGMAP,
765 };
766 
767 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
768 
769 /* NPA/NIX AQ APIs */
770 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
771 		 int qsize, int inst_size, int res_size);
772 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
773 
774 /* SDP APIs */
775 int rvu_sdp_init(struct rvu *rvu);
776 bool is_sdp_pfvf(u16 pcifunc);
777 bool is_sdp_pf(u16 pcifunc);
778 bool is_sdp_vf(u16 pcifunc);
779 
780 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)781 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
782 {
783 	return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
784 		!is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
785 }
786 
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)787 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
788 {
789 	*cgx_id = (map >> 4) & 0xF;
790 	*lmac_id = (map & 0xF);
791 }
792 
is_cgx_vf(struct rvu * rvu,u16 pcifunc)793 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
794 {
795 	return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
796 		is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
797 }
798 
799 #define M(_name, _id, fn_name, req, rsp)				\
800 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
801 MBOX_MESSAGES
802 #undef M
803 
804 int rvu_cgx_init(struct rvu *rvu);
805 int rvu_cgx_exit(struct rvu *rvu);
806 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
807 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
808 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
809 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
810 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
811 			   int rxtxflag, u64 *stat);
812 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
813 
814 /* NPA APIs */
815 int rvu_npa_init(struct rvu *rvu);
816 void rvu_npa_freemem(struct rvu *rvu);
817 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
818 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
819 			struct npa_aq_enq_rsp *rsp);
820 
821 /* NIX APIs */
822 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
823 int rvu_nix_init(struct rvu *rvu);
824 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
825 				int blkaddr, u32 cfg);
826 void rvu_nix_freemem(struct rvu *rvu);
827 int rvu_get_nixlf_count(struct rvu *rvu);
828 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
829 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
830 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
831 			struct nix_mce_list *mce_list,
832 			int mce_idx, int mcam_index, bool add);
833 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
834 		      struct nix_mce_list **mce_list, int *mce_idx);
835 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
836 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
837 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
838 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
839 			struct nix_hw **nix_hw, int *blkaddr);
840 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
841 				 u16 rq_idx, u16 match_id);
842 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
843 			struct nix_cn10k_aq_enq_req *aq_req,
844 			struct nix_cn10k_aq_enq_rsp *aq_rsp,
845 			u16 pcifunc, u8 ctype, u32 qidx);
846 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
847 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type);
848 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
849 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
850 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,
851 			struct nix_txsch *txsch, bool enable);
852 
853 /* NPC APIs */
854 void rvu_npc_freemem(struct rvu *rvu);
855 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
856 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
857 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
858 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
859 				 int nixlf, u64 chan, u8 *mac_addr);
860 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
861 				   int nixlf, u64 chan, u8 chan_cnt);
862 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
863 				  bool enable);
864 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
865 				       int nixlf, u64 chan);
866 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
867 				bool enable);
868 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
869 				    u64 chan);
870 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
871 				   bool enable);
872 
873 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
874 				  int nixlf, int type, bool enable);
875 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
876 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
877 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
878 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
879 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
880 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
881 				    int group, int alg_idx, int mcam_index);
882 
883 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
884 				       int blkaddr, int *alloc_cnt,
885 				       int *enable_cnt);
886 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
887 					 int blkaddr, int *alloc_cnt,
888 					 int *enable_cnt);
889 bool is_npc_intf_tx(u8 intf);
890 bool is_npc_intf_rx(u8 intf);
891 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
892 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
893 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
894 const char *npc_get_field_name(u8 hdr);
895 int npc_get_bank(struct npc_mcam *mcam, int index);
896 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
897 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
898 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
899 			   int blkaddr, int index, bool enable);
900 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
901 			 int blkaddr, u16 src, struct mcam_entry *entry,
902 			 u8 *intf, u8 *ena);
903 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
904 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
905 u32  rvu_cgx_get_fifolen(struct rvu *rvu);
906 void *rvu_first_cgx_pdata(struct rvu *rvu);
907 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
908 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
909 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);
910 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
911 			       u16 pfc_en);
912 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
913 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc);
914 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
915 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
916 			     int type);
917 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
918 			   int index);
919 int rvu_npc_init(struct rvu *rvu);
920 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
921 			       u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
922 			       u64 bcast_mcast_val, u64 bcast_mcast_mask);
923 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
924 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
925 
926 /* CPT APIs */
927 int rvu_cpt_register_interrupts(struct rvu *rvu);
928 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
929 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
930 			int slot);
931 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
932 int rvu_cpt_init(struct rvu *rvu);
933 
934 #define NDC_AF_BANK_MASK       GENMASK_ULL(7, 0)
935 #define NDC_AF_BANK_LINE_MASK  GENMASK_ULL(31, 16)
936 
937 /* CN10K RVU */
938 int rvu_set_channels_base(struct rvu *rvu);
939 void rvu_program_channels(struct rvu *rvu);
940 
941 /* CN10K NIX */
942 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
943 
944 /* CN10K RVU - LMT*/
945 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
946 
947 #ifdef CONFIG_DEBUG_FS
948 void rvu_dbg_init(struct rvu *rvu);
949 void rvu_dbg_exit(struct rvu *rvu);
950 #else
rvu_dbg_init(struct rvu * rvu)951 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)952 static inline void rvu_dbg_exit(struct rvu *rvu) {}
953 #endif
954 
955 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
956 
957 /* RVU Switch */
958 void rvu_switch_enable(struct rvu *rvu);
959 void rvu_switch_disable(struct rvu *rvu);
960 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
961 
962 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
963 			   u64 pkind, u8 var_len_off, u8 var_len_off_mask,
964 			   u8 shift_dir);
965 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
966 
967 /* CN10K MCS */
968 int rvu_mcs_init(struct rvu *rvu);
969 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
970 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena);
971 void rvu_mcs_exit(struct rvu *rvu);
972 
973 #endif /* RVU_H */
974