xref: /openbmc/linux/drivers/pwm/pwm-bcm-kona.c (revision 51352c09)
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Broadcom Corporation
3 
4 #include <linux/clk.h>
5 #include <linux/delay.h>
6 #include <linux/err.h>
7 #include <linux/io.h>
8 #include <linux/ioport.h>
9 #include <linux/math64.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pwm.h>
14 #include <linux/slab.h>
15 #include <linux/types.h>
16 
17 /*
18  * The Kona PWM has some unusual characteristics.  Here are the main points.
19  *
20  * 1) There is no disable bit and the hardware docs advise programming a zero
21  *    duty to achieve output equivalent to that of a normal disable operation.
22  *
23  * 2) Changes to prescale, duty, period, and polarity do not take effect until
24  *    a subsequent rising edge of the trigger bit.
25  *
26  * 3) If the smooth bit and trigger bit are both low, the output is a constant
27  *    high signal.  Otherwise, the earlier waveform continues to be output.
28  *
29  * 4) If the smooth bit is set on the rising edge of the trigger bit, output
30  *    will transition to the new settings on a period boundary (which could be
31  *    seconds away).  If the smooth bit is clear, new settings will be applied
32  *    as soon as possible (the hardware always has a 400ns delay).
33  *
34  * 5) When the external clock that feeds the PWM is disabled, output is pegged
35  *    high or low depending on its state at that exact instant.
36  */
37 
38 #define PWM_CONTROL_OFFSET			0x00000000
39 #define PWM_CONTROL_SMOOTH_SHIFT(chan)		(24 + (chan))
40 #define PWM_CONTROL_TYPE_SHIFT(chan)		(16 + (chan))
41 #define PWM_CONTROL_POLARITY_SHIFT(chan)	(8 + (chan))
42 #define PWM_CONTROL_TRIGGER_SHIFT(chan)		(chan)
43 
44 #define PRESCALE_OFFSET				0x00000004
45 #define PRESCALE_SHIFT(chan)			((chan) << 2)
46 #define PRESCALE_MASK(chan)			(0x7 << PRESCALE_SHIFT(chan))
47 #define PRESCALE_MIN				0x00000000
48 #define PRESCALE_MAX				0x00000007
49 
50 #define PERIOD_COUNT_OFFSET(chan)		(0x00000008 + ((chan) << 3))
51 #define PERIOD_COUNT_MIN			0x00000002
52 #define PERIOD_COUNT_MAX			0x00ffffff
53 
54 #define DUTY_CYCLE_HIGH_OFFSET(chan)		(0x0000000c + ((chan) << 3))
55 #define DUTY_CYCLE_HIGH_MIN			0x00000000
56 #define DUTY_CYCLE_HIGH_MAX			0x00ffffff
57 
58 struct kona_pwmc {
59 	struct pwm_chip chip;
60 	void __iomem *base;
61 	struct clk *clk;
62 };
63 
to_kona_pwmc(struct pwm_chip * chip)64 static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *chip)
65 {
66 	return container_of(chip, struct kona_pwmc, chip);
67 }
68 
69 /*
70  * Clear trigger bit but set smooth bit to maintain old output.
71  */
kona_pwmc_prepare_for_settings(struct kona_pwmc * kp,unsigned int chan)72 static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
73 	unsigned int chan)
74 {
75 	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
76 
77 	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
78 	value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
79 	writel(value, kp->base + PWM_CONTROL_OFFSET);
80 
81 	/*
82 	 * There must be a min 400ns delay between clearing trigger and setting
83 	 * it. Failing to do this may result in no PWM signal.
84 	 */
85 	ndelay(400);
86 }
87 
kona_pwmc_apply_settings(struct kona_pwmc * kp,unsigned int chan)88 static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
89 {
90 	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
91 
92 	/* Set trigger bit and clear smooth bit to apply new settings */
93 	value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
94 	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
95 	writel(value, kp->base + PWM_CONTROL_OFFSET);
96 
97 	/* Trigger bit must be held high for at least 400 ns. */
98 	ndelay(400);
99 }
100 
kona_pwmc_config(struct pwm_chip * chip,struct pwm_device * pwm,u64 duty_ns,u64 period_ns)101 static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
102 			    u64 duty_ns, u64 period_ns)
103 {
104 	struct kona_pwmc *kp = to_kona_pwmc(chip);
105 	u64 div, rate;
106 	unsigned long prescale = PRESCALE_MIN, pc, dc;
107 	unsigned int value, chan = pwm->hwpwm;
108 
109 	/*
110 	 * Find period count, duty count and prescale to suit duty_ns and
111 	 * period_ns. This is done according to formulas described below:
112 	 *
113 	 * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
114 	 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
115 	 *
116 	 * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
117 	 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
118 	 */
119 
120 	rate = clk_get_rate(kp->clk);
121 
122 	while (1) {
123 		div = 1000000000;
124 		div *= 1 + prescale;
125 		pc = mul_u64_u64_div_u64(rate, period_ns, div);
126 		dc = mul_u64_u64_div_u64(rate, duty_ns, div);
127 
128 		/* If duty_ns or period_ns are not achievable then return */
129 		if (pc < PERIOD_COUNT_MIN)
130 			return -EINVAL;
131 
132 		/* If pc and dc are in bounds, the calculation is done */
133 		if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
134 			break;
135 
136 		/* Otherwise, increase prescale and recalculate pc and dc */
137 		if (++prescale > PRESCALE_MAX)
138 			return -EINVAL;
139 	}
140 
141 	kona_pwmc_prepare_for_settings(kp, chan);
142 
143 	value = readl(kp->base + PRESCALE_OFFSET);
144 	value &= ~PRESCALE_MASK(chan);
145 	value |= prescale << PRESCALE_SHIFT(chan);
146 	writel(value, kp->base + PRESCALE_OFFSET);
147 
148 	writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
149 
150 	writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
151 
152 	kona_pwmc_apply_settings(kp, chan);
153 
154 	return 0;
155 }
156 
kona_pwmc_set_polarity(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)157 static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
158 				  enum pwm_polarity polarity)
159 {
160 	struct kona_pwmc *kp = to_kona_pwmc(chip);
161 	unsigned int chan = pwm->hwpwm;
162 	unsigned int value;
163 	int ret;
164 
165 	ret = clk_prepare_enable(kp->clk);
166 	if (ret < 0) {
167 		dev_err(chip->dev, "failed to enable clock: %d\n", ret);
168 		return ret;
169 	}
170 
171 	kona_pwmc_prepare_for_settings(kp, chan);
172 
173 	value = readl(kp->base + PWM_CONTROL_OFFSET);
174 
175 	if (polarity == PWM_POLARITY_NORMAL)
176 		value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
177 	else
178 		value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));
179 
180 	writel(value, kp->base + PWM_CONTROL_OFFSET);
181 
182 	kona_pwmc_apply_settings(kp, chan);
183 
184 	clk_disable_unprepare(kp->clk);
185 
186 	return 0;
187 }
188 
kona_pwmc_enable(struct pwm_chip * chip,struct pwm_device * pwm)189 static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
190 {
191 	struct kona_pwmc *kp = to_kona_pwmc(chip);
192 	int ret;
193 
194 	ret = clk_prepare_enable(kp->clk);
195 	if (ret < 0) {
196 		dev_err(chip->dev, "failed to enable clock: %d\n", ret);
197 		return ret;
198 	}
199 
200 	return 0;
201 }
202 
kona_pwmc_disable(struct pwm_chip * chip,struct pwm_device * pwm)203 static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
204 {
205 	struct kona_pwmc *kp = to_kona_pwmc(chip);
206 	unsigned int chan = pwm->hwpwm;
207 	unsigned int value;
208 
209 	kona_pwmc_prepare_for_settings(kp, chan);
210 
211 	/* Simulate a disable by configuring for zero duty */
212 	writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
213 	writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
214 
215 	/* Set prescale to 0 for this channel */
216 	value = readl(kp->base + PRESCALE_OFFSET);
217 	value &= ~PRESCALE_MASK(chan);
218 	writel(value, kp->base + PRESCALE_OFFSET);
219 
220 	kona_pwmc_apply_settings(kp, chan);
221 
222 	clk_disable_unprepare(kp->clk);
223 }
224 
kona_pwmc_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)225 static int kona_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
226 			   const struct pwm_state *state)
227 {
228 	int err;
229 	struct kona_pwmc *kp = to_kona_pwmc(chip);
230 	bool enabled = pwm->state.enabled;
231 
232 	if (state->polarity != pwm->state.polarity) {
233 		if (enabled) {
234 			kona_pwmc_disable(chip, pwm);
235 			enabled = false;
236 		}
237 
238 		err = kona_pwmc_set_polarity(chip, pwm, state->polarity);
239 		if (err)
240 			return err;
241 
242 		pwm->state.polarity = state->polarity;
243 	}
244 
245 	if (!state->enabled) {
246 		if (enabled)
247 			kona_pwmc_disable(chip, pwm);
248 		return 0;
249 	} else if (!enabled) {
250 		/*
251 		 * This is a bit special here, usually the PWM should only be
252 		 * enabled when duty and period are setup. But before this
253 		 * driver was converted to .apply it was done the other way
254 		 * around and so this behaviour was kept even though this might
255 		 * result in a glitch. This might be improvable by someone with
256 		 * hardware and/or documentation.
257 		 */
258 		err = kona_pwmc_enable(chip, pwm);
259 		if (err)
260 			return err;
261 	}
262 
263 	err = kona_pwmc_config(pwm->chip, pwm, state->duty_cycle, state->period);
264 	if (err && !pwm->state.enabled)
265 		clk_disable_unprepare(kp->clk);
266 
267 	return err;
268 }
269 
270 static const struct pwm_ops kona_pwm_ops = {
271 	.apply = kona_pwmc_apply,
272 	.owner = THIS_MODULE,
273 };
274 
kona_pwmc_probe(struct platform_device * pdev)275 static int kona_pwmc_probe(struct platform_device *pdev)
276 {
277 	struct kona_pwmc *kp;
278 	unsigned int chan;
279 	unsigned int value = 0;
280 	int ret = 0;
281 
282 	kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
283 	if (kp == NULL)
284 		return -ENOMEM;
285 
286 	kp->chip.dev = &pdev->dev;
287 	kp->chip.ops = &kona_pwm_ops;
288 	kp->chip.npwm = 6;
289 
290 	kp->base = devm_platform_ioremap_resource(pdev, 0);
291 	if (IS_ERR(kp->base))
292 		return PTR_ERR(kp->base);
293 
294 	kp->clk = devm_clk_get(&pdev->dev, NULL);
295 	if (IS_ERR(kp->clk)) {
296 		dev_err(&pdev->dev, "failed to get clock: %ld\n",
297 			PTR_ERR(kp->clk));
298 		return PTR_ERR(kp->clk);
299 	}
300 
301 	ret = clk_prepare_enable(kp->clk);
302 	if (ret < 0) {
303 		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
304 		return ret;
305 	}
306 
307 	/* Set push/pull for all channels */
308 	for (chan = 0; chan < kp->chip.npwm; chan++)
309 		value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
310 
311 	writel(value, kp->base + PWM_CONTROL_OFFSET);
312 
313 	clk_disable_unprepare(kp->clk);
314 
315 	ret = devm_pwmchip_add(&pdev->dev, &kp->chip);
316 	if (ret < 0)
317 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
318 
319 	return ret;
320 }
321 
322 static const struct of_device_id bcm_kona_pwmc_dt[] = {
323 	{ .compatible = "brcm,kona-pwm" },
324 	{ },
325 };
326 MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
327 
328 static struct platform_driver kona_pwmc_driver = {
329 	.driver = {
330 		.name = "bcm-kona-pwm",
331 		.of_match_table = bcm_kona_pwmc_dt,
332 	},
333 	.probe = kona_pwmc_probe,
334 };
335 module_platform_driver(kona_pwmc_driver);
336 
337 MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
338 MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
339 MODULE_DESCRIPTION("Broadcom Kona PWM driver");
340 MODULE_LICENSE("GPL v2");
341