1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI K3 R5F (MCU) Remote Processor driver
4 *
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/mailbox_client.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/of_platform.h>
19 #include <linux/omap-mailbox.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/remoteproc.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25
26 #include "omap_remoteproc.h"
27 #include "remoteproc_internal.h"
28 #include "ti_sci_proc.h"
29
30 /* This address can either be for ATCM or BTCM with the other at address 0x0 */
31 #define K3_R5_TCM_DEV_ADDR 0x41010000
32
33 /* R5 TI-SCI Processor Configuration Flags */
34 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
35 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
36 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
37 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
38 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
39 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
40 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
41 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
42 /* Available from J7200 SoCs onwards */
43 #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000
44 /* Applicable to only AM64x SoCs */
45 #define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000
46
47 /* R5 TI-SCI Processor Control Flags */
48 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
49
50 /* R5 TI-SCI Processor Status Flags */
51 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
52 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
53 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
54 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
55 /* Applicable to only AM64x SoCs */
56 #define PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY 0x00000200
57
58 /**
59 * struct k3_r5_mem - internal memory structure
60 * @cpu_addr: MPU virtual address of the memory region
61 * @bus_addr: Bus address used to access the memory region
62 * @dev_addr: Device address from remoteproc view
63 * @size: Size of the memory region
64 */
65 struct k3_r5_mem {
66 void __iomem *cpu_addr;
67 phys_addr_t bus_addr;
68 u32 dev_addr;
69 size_t size;
70 };
71
72 /*
73 * All cluster mode values are not applicable on all SoCs. The following
74 * are the modes supported on various SoCs:
75 * Split mode : AM65x, J721E, J7200 and AM64x SoCs
76 * LockStep mode : AM65x, J721E and J7200 SoCs
77 * Single-CPU mode : AM64x SoCs only
78 * Single-Core mode : AM62x, AM62A SoCs
79 */
80 enum cluster_mode {
81 CLUSTER_MODE_SPLIT = 0,
82 CLUSTER_MODE_LOCKSTEP,
83 CLUSTER_MODE_SINGLECPU,
84 CLUSTER_MODE_SINGLECORE
85 };
86
87 /**
88 * struct k3_r5_soc_data - match data to handle SoC variations
89 * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
90 * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
91 * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode
92 * @is_single_core: flag to denote if SoC/IP has only single core R5
93 */
94 struct k3_r5_soc_data {
95 bool tcm_is_double;
96 bool tcm_ecc_autoinit;
97 bool single_cpu_mode;
98 bool is_single_core;
99 };
100
101 /**
102 * struct k3_r5_cluster - K3 R5F Cluster structure
103 * @dev: cached device pointer
104 * @mode: Mode to configure the Cluster - Split or LockStep
105 * @cores: list of R5 cores within the cluster
106 * @core_transition: wait queue to sync core state changes
107 * @soc_data: SoC-specific feature data for a R5FSS
108 */
109 struct k3_r5_cluster {
110 struct device *dev;
111 enum cluster_mode mode;
112 struct list_head cores;
113 wait_queue_head_t core_transition;
114 const struct k3_r5_soc_data *soc_data;
115 };
116
117 /**
118 * struct k3_r5_core - K3 R5 core structure
119 * @elem: linked list item
120 * @dev: cached device pointer
121 * @rproc: rproc handle representing this core
122 * @mem: internal memory regions data
123 * @sram: on-chip SRAM memory regions data
124 * @num_mems: number of internal memory regions
125 * @num_sram: number of on-chip SRAM memory regions
126 * @reset: reset control handle
127 * @tsp: TI-SCI processor control handle
128 * @ti_sci: TI-SCI handle
129 * @ti_sci_id: TI-SCI device identifier
130 * @atcm_enable: flag to control ATCM enablement
131 * @btcm_enable: flag to control BTCM enablement
132 * @loczrama: flag to dictate which TCM is at device address 0x0
133 * @released_from_reset: flag to signal when core is out of reset
134 */
135 struct k3_r5_core {
136 struct list_head elem;
137 struct device *dev;
138 struct rproc *rproc;
139 struct k3_r5_mem *mem;
140 struct k3_r5_mem *sram;
141 int num_mems;
142 int num_sram;
143 struct reset_control *reset;
144 struct ti_sci_proc *tsp;
145 const struct ti_sci_handle *ti_sci;
146 u32 ti_sci_id;
147 u32 atcm_enable;
148 u32 btcm_enable;
149 u32 loczrama;
150 bool released_from_reset;
151 };
152
153 /**
154 * struct k3_r5_rproc - K3 remote processor state
155 * @dev: cached device pointer
156 * @cluster: cached pointer to parent cluster structure
157 * @mbox: mailbox channel handle
158 * @client: mailbox client to request the mailbox channel
159 * @rproc: rproc handle
160 * @core: cached pointer to r5 core structure being used
161 * @rmem: reserved memory regions data
162 * @num_rmems: number of reserved memory regions
163 */
164 struct k3_r5_rproc {
165 struct device *dev;
166 struct k3_r5_cluster *cluster;
167 struct mbox_chan *mbox;
168 struct mbox_client client;
169 struct rproc *rproc;
170 struct k3_r5_core *core;
171 struct k3_r5_mem *rmem;
172 int num_rmems;
173 };
174
175 /**
176 * k3_r5_rproc_mbox_callback() - inbound mailbox message handler
177 * @client: mailbox client pointer used for requesting the mailbox channel
178 * @data: mailbox payload
179 *
180 * This handler is invoked by the OMAP mailbox driver whenever a mailbox
181 * message is received. Usually, the mailbox payload simply contains
182 * the index of the virtqueue that is kicked by the remote processor,
183 * and we let remoteproc core handle it.
184 *
185 * In addition to virtqueue indices, we also have some out-of-band values
186 * that indicate different events. Those values are deliberately very
187 * large so they don't coincide with virtqueue indices.
188 */
k3_r5_rproc_mbox_callback(struct mbox_client * client,void * data)189 static void k3_r5_rproc_mbox_callback(struct mbox_client *client, void *data)
190 {
191 struct k3_r5_rproc *kproc = container_of(client, struct k3_r5_rproc,
192 client);
193 struct device *dev = kproc->rproc->dev.parent;
194 const char *name = kproc->rproc->name;
195 u32 msg = omap_mbox_message(data);
196
197 dev_dbg(dev, "mbox msg: 0x%x\n", msg);
198
199 switch (msg) {
200 case RP_MBOX_CRASH:
201 /*
202 * remoteproc detected an exception, but error recovery is not
203 * supported. So, just log this for now
204 */
205 dev_err(dev, "K3 R5F rproc %s crashed\n", name);
206 break;
207 case RP_MBOX_ECHO_REPLY:
208 dev_info(dev, "received echo reply from %s\n", name);
209 break;
210 default:
211 /* silently handle all other valid messages */
212 if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG)
213 return;
214 if (msg > kproc->rproc->max_notifyid) {
215 dev_dbg(dev, "dropping unknown message 0x%x", msg);
216 return;
217 }
218 /* msg contains the index of the triggered vring */
219 if (rproc_vq_interrupt(kproc->rproc, msg) == IRQ_NONE)
220 dev_dbg(dev, "no message was found in vqid %d\n", msg);
221 }
222 }
223
224 /* kick a virtqueue */
k3_r5_rproc_kick(struct rproc * rproc,int vqid)225 static void k3_r5_rproc_kick(struct rproc *rproc, int vqid)
226 {
227 struct k3_r5_rproc *kproc = rproc->priv;
228 struct device *dev = rproc->dev.parent;
229 mbox_msg_t msg = (mbox_msg_t)vqid;
230 int ret;
231
232 /* send the index of the triggered virtqueue in the mailbox payload */
233 ret = mbox_send_message(kproc->mbox, (void *)msg);
234 if (ret < 0)
235 dev_err(dev, "failed to send mailbox message, status = %d\n",
236 ret);
237 }
238
k3_r5_split_reset(struct k3_r5_core * core)239 static int k3_r5_split_reset(struct k3_r5_core *core)
240 {
241 int ret;
242
243 ret = reset_control_assert(core->reset);
244 if (ret) {
245 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
246 ret);
247 return ret;
248 }
249
250 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
251 core->ti_sci_id);
252 if (ret) {
253 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
254 ret);
255 if (reset_control_deassert(core->reset))
256 dev_warn(core->dev, "local-reset deassert back failed\n");
257 }
258
259 return ret;
260 }
261
k3_r5_split_release(struct k3_r5_core * core)262 static int k3_r5_split_release(struct k3_r5_core *core)
263 {
264 int ret;
265
266 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
267 core->ti_sci_id);
268 if (ret) {
269 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
270 ret);
271 return ret;
272 }
273
274 ret = reset_control_deassert(core->reset);
275 if (ret) {
276 dev_err(core->dev, "local-reset deassert failed, ret = %d\n",
277 ret);
278 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
279 core->ti_sci_id))
280 dev_warn(core->dev, "module-reset assert back failed\n");
281 }
282
283 return ret;
284 }
285
k3_r5_lockstep_reset(struct k3_r5_cluster * cluster)286 static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster)
287 {
288 struct k3_r5_core *core;
289 int ret;
290
291 /* assert local reset on all applicable cores */
292 list_for_each_entry(core, &cluster->cores, elem) {
293 ret = reset_control_assert(core->reset);
294 if (ret) {
295 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
296 ret);
297 core = list_prev_entry(core, elem);
298 goto unroll_local_reset;
299 }
300 }
301
302 /* disable PSC modules on all applicable cores */
303 list_for_each_entry(core, &cluster->cores, elem) {
304 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
305 core->ti_sci_id);
306 if (ret) {
307 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
308 ret);
309 goto unroll_module_reset;
310 }
311 }
312
313 return 0;
314
315 unroll_module_reset:
316 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {
317 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
318 core->ti_sci_id))
319 dev_warn(core->dev, "module-reset assert back failed\n");
320 }
321 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
322 unroll_local_reset:
323 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
324 if (reset_control_deassert(core->reset))
325 dev_warn(core->dev, "local-reset deassert back failed\n");
326 }
327
328 return ret;
329 }
330
k3_r5_lockstep_release(struct k3_r5_cluster * cluster)331 static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster)
332 {
333 struct k3_r5_core *core;
334 int ret;
335
336 /* enable PSC modules on all applicable cores */
337 list_for_each_entry_reverse(core, &cluster->cores, elem) {
338 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
339 core->ti_sci_id);
340 if (ret) {
341 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
342 ret);
343 core = list_next_entry(core, elem);
344 goto unroll_module_reset;
345 }
346 }
347
348 /* deassert local reset on all applicable cores */
349 list_for_each_entry_reverse(core, &cluster->cores, elem) {
350 ret = reset_control_deassert(core->reset);
351 if (ret) {
352 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
353 ret);
354 goto unroll_local_reset;
355 }
356 }
357
358 return 0;
359
360 unroll_local_reset:
361 list_for_each_entry_continue(core, &cluster->cores, elem) {
362 if (reset_control_assert(core->reset))
363 dev_warn(core->dev, "local-reset assert back failed\n");
364 }
365 core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
366 unroll_module_reset:
367 list_for_each_entry_from(core, &cluster->cores, elem) {
368 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
369 core->ti_sci_id))
370 dev_warn(core->dev, "module-reset assert back failed\n");
371 }
372
373 return ret;
374 }
375
k3_r5_core_halt(struct k3_r5_core * core)376 static inline int k3_r5_core_halt(struct k3_r5_core *core)
377 {
378 return ti_sci_proc_set_control(core->tsp,
379 PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
380 }
381
k3_r5_core_run(struct k3_r5_core * core)382 static inline int k3_r5_core_run(struct k3_r5_core *core)
383 {
384 return ti_sci_proc_set_control(core->tsp,
385 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
386 }
387
k3_r5_rproc_request_mbox(struct rproc * rproc)388 static int k3_r5_rproc_request_mbox(struct rproc *rproc)
389 {
390 struct k3_r5_rproc *kproc = rproc->priv;
391 struct mbox_client *client = &kproc->client;
392 struct device *dev = kproc->dev;
393 int ret;
394
395 client->dev = dev;
396 client->tx_done = NULL;
397 client->rx_callback = k3_r5_rproc_mbox_callback;
398 client->tx_block = false;
399 client->knows_txdone = false;
400
401 kproc->mbox = mbox_request_channel(client, 0);
402 if (IS_ERR(kproc->mbox)) {
403 ret = -EBUSY;
404 dev_err(dev, "mbox_request_channel failed: %ld\n",
405 PTR_ERR(kproc->mbox));
406 return ret;
407 }
408
409 /*
410 * Ping the remote processor, this is only for sanity-sake for now;
411 * there is no functional effect whatsoever.
412 *
413 * Note that the reply will _not_ arrive immediately: this message
414 * will wait in the mailbox fifo until the remote processor is booted.
415 */
416 ret = mbox_send_message(kproc->mbox, (void *)RP_MBOX_ECHO_REQUEST);
417 if (ret < 0) {
418 dev_err(dev, "mbox_send_message failed: %d\n", ret);
419 mbox_free_channel(kproc->mbox);
420 return ret;
421 }
422
423 return 0;
424 }
425
426 /*
427 * The R5F cores have controls for both a reset and a halt/run. The code
428 * execution from DDR requires the initial boot-strapping code to be run
429 * from the internal TCMs. This function is used to release the resets on
430 * applicable cores to allow loading into the TCMs. The .prepare() ops is
431 * invoked by remoteproc core before any firmware loading, and is followed
432 * by the .start() ops after loading to actually let the R5 cores run.
433 *
434 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to
435 * execute code, but combines the TCMs from both cores. The resets for both
436 * cores need to be released to make this possible, as the TCMs are in general
437 * private to each core. Only Core0 needs to be unhalted for running the
438 * cluster in this mode. The function uses the same reset logic as LockStep
439 * mode for this (though the behavior is agnostic of the reset release order).
440 * This callback is invoked only in remoteproc mode.
441 */
k3_r5_rproc_prepare(struct rproc * rproc)442 static int k3_r5_rproc_prepare(struct rproc *rproc)
443 {
444 struct k3_r5_rproc *kproc = rproc->priv;
445 struct k3_r5_cluster *cluster = kproc->cluster;
446 struct k3_r5_core *core = kproc->core;
447 struct device *dev = kproc->dev;
448 u32 ctrl = 0, cfg = 0, stat = 0;
449 u64 boot_vec = 0;
450 bool mem_init_dis;
451 int ret;
452
453 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, &stat);
454 if (ret < 0)
455 return ret;
456 mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
457
458 /* Re-use LockStep-mode reset logic for Single-CPU mode */
459 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
460 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
461 k3_r5_lockstep_release(cluster) : k3_r5_split_release(core);
462 if (ret) {
463 dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",
464 ret);
465 return ret;
466 }
467 core->released_from_reset = true;
468 wake_up_interruptible(&cluster->core_transition);
469
470 /*
471 * Newer IP revisions like on J7200 SoCs support h/w auto-initialization
472 * of TCMs, so there is no need to perform the s/w memzero. This bit is
473 * configurable through System Firmware, the default value does perform
474 * auto-init, but account for it in case it is disabled
475 */
476 if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) {
477 dev_dbg(dev, "leveraging h/w init for TCM memories\n");
478 return 0;
479 }
480
481 /*
482 * Zero out both TCMs unconditionally (access from v8 Arm core is not
483 * affected by ATCM & BTCM enable configuration values) so that ECC
484 * can be effective on all TCM addresses.
485 */
486 dev_dbg(dev, "zeroing out ATCM memory\n");
487 memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
488
489 dev_dbg(dev, "zeroing out BTCM memory\n");
490 memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
491
492 return 0;
493 }
494
495 /*
496 * This function implements the .unprepare() ops and performs the complimentary
497 * operations to that of the .prepare() ops. The function is used to assert the
498 * resets on all applicable cores for the rproc device (depending on LockStep
499 * or Split mode). This completes the second portion of powering down the R5F
500 * cores. The cores themselves are only halted in the .stop() ops, and the
501 * .unprepare() ops is invoked by the remoteproc core after the remoteproc is
502 * stopped.
503 *
504 * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from
505 * both cores. The access is made possible only with releasing the resets for
506 * both cores, but with only Core0 unhalted. This function re-uses the same
507 * reset assert logic as LockStep mode for this mode (though the behavior is
508 * agnostic of the reset assert order). This callback is invoked only in
509 * remoteproc mode.
510 */
k3_r5_rproc_unprepare(struct rproc * rproc)511 static int k3_r5_rproc_unprepare(struct rproc *rproc)
512 {
513 struct k3_r5_rproc *kproc = rproc->priv;
514 struct k3_r5_cluster *cluster = kproc->cluster;
515 struct k3_r5_core *core = kproc->core;
516 struct device *dev = kproc->dev;
517 int ret;
518
519 /* Re-use LockStep-mode reset logic for Single-CPU mode */
520 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
521 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
522 k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(core);
523 if (ret)
524 dev_err(dev, "unable to disable cores, ret = %d\n", ret);
525
526 return ret;
527 }
528
529 /*
530 * The R5F start sequence includes two different operations
531 * 1. Configure the boot vector for R5F core(s)
532 * 2. Unhalt/Run the R5F core(s)
533 *
534 * The sequence is different between LockStep and Split modes. The LockStep
535 * mode requires the boot vector to be configured only for Core0, and then
536 * unhalt both the cores to start the execution - Core1 needs to be unhalted
537 * first followed by Core0. The Split-mode requires that Core0 to be maintained
538 * always in a higher power state that Core1 (implying Core1 needs to be started
539 * always only after Core0 is started).
540 *
541 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
542 * code, so only Core0 needs to be unhalted. The function uses the same logic
543 * flow as Split-mode for this. This callback is invoked only in remoteproc
544 * mode.
545 */
k3_r5_rproc_start(struct rproc * rproc)546 static int k3_r5_rproc_start(struct rproc *rproc)
547 {
548 struct k3_r5_rproc *kproc = rproc->priv;
549 struct k3_r5_cluster *cluster = kproc->cluster;
550 struct device *dev = kproc->dev;
551 struct k3_r5_core *core0, *core;
552 u32 boot_addr;
553 int ret;
554
555 ret = k3_r5_rproc_request_mbox(rproc);
556 if (ret)
557 return ret;
558
559 boot_addr = rproc->bootaddr;
560 /* TODO: add boot_addr sanity checking */
561 dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr);
562
563 /* boot vector need not be programmed for Core1 in LockStep mode */
564 core = kproc->core;
565 ret = ti_sci_proc_set_config(core->tsp, boot_addr, 0, 0);
566 if (ret)
567 goto put_mbox;
568
569 /* unhalt/run all applicable cores */
570 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
571 list_for_each_entry_reverse(core, &cluster->cores, elem) {
572 ret = k3_r5_core_run(core);
573 if (ret)
574 goto unroll_core_run;
575 }
576 } else {
577 /* do not allow core 1 to start before core 0 */
578 core0 = list_first_entry(&cluster->cores, struct k3_r5_core,
579 elem);
580 if (core != core0 && core0->rproc->state == RPROC_OFFLINE) {
581 dev_err(dev, "%s: can not start core 1 before core 0\n",
582 __func__);
583 ret = -EPERM;
584 goto put_mbox;
585 }
586
587 ret = k3_r5_core_run(core);
588 if (ret)
589 goto put_mbox;
590 }
591
592 return 0;
593
594 unroll_core_run:
595 list_for_each_entry_continue(core, &cluster->cores, elem) {
596 if (k3_r5_core_halt(core))
597 dev_warn(core->dev, "core halt back failed\n");
598 }
599 put_mbox:
600 mbox_free_channel(kproc->mbox);
601 return ret;
602 }
603
604 /*
605 * The R5F stop function includes the following operations
606 * 1. Halt R5F core(s)
607 *
608 * The sequence is different between LockStep and Split modes, and the order
609 * of cores the operations are performed are also in general reverse to that
610 * of the start function. The LockStep mode requires each operation to be
611 * performed first on Core0 followed by Core1. The Split-mode requires that
612 * Core0 to be maintained always in a higher power state that Core1 (implying
613 * Core1 needs to be stopped first before Core0).
614 *
615 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
616 * code, so only Core0 needs to be halted. The function uses the same logic
617 * flow as Split-mode for this.
618 *
619 * Note that the R5F halt operation in general is not effective when the R5F
620 * core is running, but is needed to make sure the core won't run after
621 * deasserting the reset the subsequent time. The asserting of reset can
622 * be done here, but is preferred to be done in the .unprepare() ops - this
623 * maintains the symmetric behavior between the .start(), .stop(), .prepare()
624 * and .unprepare() ops, and also balances them well between sysfs 'state'
625 * flow and device bind/unbind or module removal. This callback is invoked
626 * only in remoteproc mode.
627 */
k3_r5_rproc_stop(struct rproc * rproc)628 static int k3_r5_rproc_stop(struct rproc *rproc)
629 {
630 struct k3_r5_rproc *kproc = rproc->priv;
631 struct k3_r5_cluster *cluster = kproc->cluster;
632 struct device *dev = kproc->dev;
633 struct k3_r5_core *core1, *core = kproc->core;
634 int ret;
635
636 /* halt all applicable cores */
637 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
638 list_for_each_entry(core, &cluster->cores, elem) {
639 ret = k3_r5_core_halt(core);
640 if (ret) {
641 core = list_prev_entry(core, elem);
642 goto unroll_core_halt;
643 }
644 }
645 } else {
646 /* do not allow core 0 to stop before core 1 */
647 core1 = list_last_entry(&cluster->cores, struct k3_r5_core,
648 elem);
649 if (core != core1 && core1->rproc->state != RPROC_OFFLINE) {
650 dev_err(dev, "%s: can not stop core 0 before core 1\n",
651 __func__);
652 ret = -EPERM;
653 goto out;
654 }
655
656 ret = k3_r5_core_halt(core);
657 if (ret)
658 goto out;
659 }
660
661 mbox_free_channel(kproc->mbox);
662
663 return 0;
664
665 unroll_core_halt:
666 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
667 if (k3_r5_core_run(core))
668 dev_warn(core->dev, "core run back failed\n");
669 }
670 out:
671 return ret;
672 }
673
674 /*
675 * Attach to a running R5F remote processor (IPC-only mode)
676 *
677 * The R5F attach callback only needs to request the mailbox, the remote
678 * processor is already booted, so there is no need to issue any TI-SCI
679 * commands to boot the R5F cores in IPC-only mode. This callback is invoked
680 * only in IPC-only mode.
681 */
k3_r5_rproc_attach(struct rproc * rproc)682 static int k3_r5_rproc_attach(struct rproc *rproc)
683 {
684 struct k3_r5_rproc *kproc = rproc->priv;
685 struct device *dev = kproc->dev;
686 int ret;
687
688 ret = k3_r5_rproc_request_mbox(rproc);
689 if (ret)
690 return ret;
691
692 dev_info(dev, "R5F core initialized in IPC-only mode\n");
693 return 0;
694 }
695
696 /*
697 * Detach from a running R5F remote processor (IPC-only mode)
698 *
699 * The R5F detach callback performs the opposite operation to attach callback
700 * and only needs to release the mailbox, the R5F cores are not stopped and
701 * will be left in booted state in IPC-only mode. This callback is invoked
702 * only in IPC-only mode.
703 */
k3_r5_rproc_detach(struct rproc * rproc)704 static int k3_r5_rproc_detach(struct rproc *rproc)
705 {
706 struct k3_r5_rproc *kproc = rproc->priv;
707 struct device *dev = kproc->dev;
708
709 mbox_free_channel(kproc->mbox);
710 dev_info(dev, "R5F core deinitialized in IPC-only mode\n");
711 return 0;
712 }
713
714 /*
715 * This function implements the .get_loaded_rsc_table() callback and is used
716 * to provide the resource table for the booted R5F in IPC-only mode. The K3 R5F
717 * firmwares follow a design-by-contract approach and are expected to have the
718 * resource table at the base of the DDR region reserved for firmware usage.
719 * This provides flexibility for the remote processor to be booted by different
720 * bootloaders that may or may not have the ability to publish the resource table
721 * address and size through a DT property. This callback is invoked only in
722 * IPC-only mode.
723 */
k3_r5_get_loaded_rsc_table(struct rproc * rproc,size_t * rsc_table_sz)724 static struct resource_table *k3_r5_get_loaded_rsc_table(struct rproc *rproc,
725 size_t *rsc_table_sz)
726 {
727 struct k3_r5_rproc *kproc = rproc->priv;
728 struct device *dev = kproc->dev;
729
730 if (!kproc->rmem[0].cpu_addr) {
731 dev_err(dev, "memory-region #1 does not exist, loaded rsc table can't be found");
732 return ERR_PTR(-ENOMEM);
733 }
734
735 /*
736 * NOTE: The resource table size is currently hard-coded to a maximum
737 * of 256 bytes. The most common resource table usage for K3 firmwares
738 * is to only have the vdev resource entry and an optional trace entry.
739 * The exact size could be computed based on resource table address, but
740 * the hard-coded value suffices to support the IPC-only mode.
741 */
742 *rsc_table_sz = 256;
743 return (struct resource_table *)kproc->rmem[0].cpu_addr;
744 }
745
746 /*
747 * Internal Memory translation helper
748 *
749 * Custom function implementing the rproc .da_to_va ops to provide address
750 * translation (device address to kernel virtual address) for internal RAMs
751 * present in a DSP or IPU device). The translated addresses can be used
752 * either by the remoteproc core for loading, or by any rpmsg bus drivers.
753 */
k3_r5_rproc_da_to_va(struct rproc * rproc,u64 da,size_t len,bool * is_iomem)754 static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
755 {
756 struct k3_r5_rproc *kproc = rproc->priv;
757 struct k3_r5_core *core = kproc->core;
758 void __iomem *va = NULL;
759 phys_addr_t bus_addr;
760 u32 dev_addr, offset;
761 size_t size;
762 int i;
763
764 if (len == 0)
765 return NULL;
766
767 /* handle both R5 and SoC views of ATCM and BTCM */
768 for (i = 0; i < core->num_mems; i++) {
769 bus_addr = core->mem[i].bus_addr;
770 dev_addr = core->mem[i].dev_addr;
771 size = core->mem[i].size;
772
773 /* handle R5-view addresses of TCMs */
774 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
775 offset = da - dev_addr;
776 va = core->mem[i].cpu_addr + offset;
777 return (__force void *)va;
778 }
779
780 /* handle SoC-view addresses of TCMs */
781 if (da >= bus_addr && ((da + len) <= (bus_addr + size))) {
782 offset = da - bus_addr;
783 va = core->mem[i].cpu_addr + offset;
784 return (__force void *)va;
785 }
786 }
787
788 /* handle any SRAM regions using SoC-view addresses */
789 for (i = 0; i < core->num_sram; i++) {
790 dev_addr = core->sram[i].dev_addr;
791 size = core->sram[i].size;
792
793 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
794 offset = da - dev_addr;
795 va = core->sram[i].cpu_addr + offset;
796 return (__force void *)va;
797 }
798 }
799
800 /* handle static DDR reserved memory regions */
801 for (i = 0; i < kproc->num_rmems; i++) {
802 dev_addr = kproc->rmem[i].dev_addr;
803 size = kproc->rmem[i].size;
804
805 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
806 offset = da - dev_addr;
807 va = kproc->rmem[i].cpu_addr + offset;
808 return (__force void *)va;
809 }
810 }
811
812 return NULL;
813 }
814
815 static const struct rproc_ops k3_r5_rproc_ops = {
816 .prepare = k3_r5_rproc_prepare,
817 .unprepare = k3_r5_rproc_unprepare,
818 .start = k3_r5_rproc_start,
819 .stop = k3_r5_rproc_stop,
820 .kick = k3_r5_rproc_kick,
821 .da_to_va = k3_r5_rproc_da_to_va,
822 };
823
824 /*
825 * Internal R5F Core configuration
826 *
827 * Each R5FSS has a cluster-level setting for configuring the processor
828 * subsystem either in a safety/fault-tolerant LockStep mode or a performance
829 * oriented Split mode on most SoCs. A fewer SoCs support a non-safety mode
830 * as an alternate for LockStep mode that exercises only a single R5F core
831 * called Single-CPU mode. Each R5F core has a number of settings to either
832 * enable/disable each of the TCMs, control which TCM appears at the R5F core's
833 * address 0x0. These settings need to be configured before the resets for the
834 * corresponding core are released. These settings are all protected and managed
835 * by the System Processor.
836 *
837 * This function is used to pre-configure these settings for each R5F core, and
838 * the configuration is all done through various ti_sci_proc functions that
839 * communicate with the System Processor. The function also ensures that both
840 * the cores are halted before the .prepare() step.
841 *
842 * The function is called from k3_r5_cluster_rproc_init() and is invoked either
843 * once (in LockStep mode or Single-CPU modes) or twice (in Split mode). Support
844 * for LockStep-mode is dictated by an eFUSE register bit, and the config
845 * settings retrieved from DT are adjusted accordingly as per the permitted
846 * cluster mode. Another eFUSE register bit dictates if the R5F cluster only
847 * supports a Single-CPU mode. All cluster level settings like Cluster mode and
848 * TEINIT (exception handling state dictating ARM or Thumb mode) can only be set
849 * and retrieved using Core0.
850 *
851 * The function behavior is different based on the cluster mode. The R5F cores
852 * are configured independently as per their individual settings in Split mode.
853 * They are identically configured in LockStep mode using the primary Core0
854 * settings. However, some individual settings cannot be set in LockStep mode.
855 * This is overcome by switching to Split-mode initially and then programming
856 * both the cores with the same settings, before reconfiguing again for
857 * LockStep mode.
858 */
k3_r5_rproc_configure(struct k3_r5_rproc * kproc)859 static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc)
860 {
861 struct k3_r5_cluster *cluster = kproc->cluster;
862 struct device *dev = kproc->dev;
863 struct k3_r5_core *core0, *core, *temp;
864 u32 ctrl = 0, cfg = 0, stat = 0;
865 u32 set_cfg = 0, clr_cfg = 0;
866 u64 boot_vec = 0;
867 bool lockstep_en;
868 bool single_cpu;
869 int ret;
870
871 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
872 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
873 cluster->mode == CLUSTER_MODE_SINGLECPU ||
874 cluster->mode == CLUSTER_MODE_SINGLECORE) {
875 core = core0;
876 } else {
877 core = kproc->core;
878 }
879
880 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
881 &stat);
882 if (ret < 0)
883 return ret;
884
885 dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n",
886 boot_vec, cfg, ctrl, stat);
887
888 single_cpu = !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY);
889 lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);
890
891 /* Override to single CPU mode if set in status flag */
892 if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) {
893 dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n");
894 cluster->mode = CLUSTER_MODE_SINGLECPU;
895 }
896
897 /* Override to split mode if lockstep enable bit is not set in status flag */
898 if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) {
899 dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n");
900 cluster->mode = CLUSTER_MODE_SPLIT;
901 }
902
903 /* always enable ARM mode and set boot vector to 0 */
904 boot_vec = 0x0;
905 if (core == core0) {
906 clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT;
907 /*
908 * Single-CPU configuration bit can only be configured
909 * on Core0 and system firmware will NACK any requests
910 * with the bit configured, so program it only on
911 * permitted cores
912 */
913 if (cluster->mode == CLUSTER_MODE_SINGLECPU ||
914 cluster->mode == CLUSTER_MODE_SINGLECORE) {
915 set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE;
916 } else {
917 /*
918 * LockStep configuration bit is Read-only on Split-mode
919 * _only_ devices and system firmware will NACK any
920 * requests with the bit configured, so program it only
921 * on permitted devices
922 */
923 if (lockstep_en)
924 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
925 }
926 }
927
928 if (core->atcm_enable)
929 set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
930 else
931 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
932
933 if (core->btcm_enable)
934 set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
935 else
936 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
937
938 if (core->loczrama)
939 set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
940 else
941 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
942
943 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
944 /*
945 * work around system firmware limitations to make sure both
946 * cores are programmed symmetrically in LockStep. LockStep
947 * and TEINIT config is only allowed with Core0.
948 */
949 list_for_each_entry(temp, &cluster->cores, elem) {
950 ret = k3_r5_core_halt(temp);
951 if (ret)
952 goto out;
953
954 if (temp != core) {
955 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
956 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT;
957 }
958 ret = ti_sci_proc_set_config(temp->tsp, boot_vec,
959 set_cfg, clr_cfg);
960 if (ret)
961 goto out;
962 }
963
964 set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
965 clr_cfg = 0;
966 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
967 set_cfg, clr_cfg);
968 } else {
969 ret = k3_r5_core_halt(core);
970 if (ret)
971 goto out;
972
973 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
974 set_cfg, clr_cfg);
975 }
976
977 out:
978 return ret;
979 }
980
k3_r5_reserved_mem_init(struct k3_r5_rproc * kproc)981 static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc)
982 {
983 struct device *dev = kproc->dev;
984 struct device_node *np = dev_of_node(dev);
985 struct device_node *rmem_np;
986 struct reserved_mem *rmem;
987 int num_rmems;
988 int ret, i;
989
990 num_rmems = of_property_count_elems_of_size(np, "memory-region",
991 sizeof(phandle));
992 if (num_rmems <= 0) {
993 dev_err(dev, "device does not have reserved memory regions, ret = %d\n",
994 num_rmems);
995 return -EINVAL;
996 }
997 if (num_rmems < 2) {
998 dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n",
999 num_rmems);
1000 return -EINVAL;
1001 }
1002
1003 /* use reserved memory region 0 for vring DMA allocations */
1004 ret = of_reserved_mem_device_init_by_idx(dev, np, 0);
1005 if (ret) {
1006 dev_err(dev, "device cannot initialize DMA pool, ret = %d\n",
1007 ret);
1008 return ret;
1009 }
1010
1011 num_rmems--;
1012 kproc->rmem = kcalloc(num_rmems, sizeof(*kproc->rmem), GFP_KERNEL);
1013 if (!kproc->rmem) {
1014 ret = -ENOMEM;
1015 goto release_rmem;
1016 }
1017
1018 /* use remaining reserved memory regions for static carveouts */
1019 for (i = 0; i < num_rmems; i++) {
1020 rmem_np = of_parse_phandle(np, "memory-region", i + 1);
1021 if (!rmem_np) {
1022 ret = -EINVAL;
1023 goto unmap_rmem;
1024 }
1025
1026 rmem = of_reserved_mem_lookup(rmem_np);
1027 if (!rmem) {
1028 of_node_put(rmem_np);
1029 ret = -EINVAL;
1030 goto unmap_rmem;
1031 }
1032 of_node_put(rmem_np);
1033
1034 kproc->rmem[i].bus_addr = rmem->base;
1035 /*
1036 * R5Fs do not have an MMU, but have a Region Address Translator
1037 * (RAT) module that provides a fixed entry translation between
1038 * the 32-bit processor addresses to 64-bit bus addresses. The
1039 * RAT is programmable only by the R5F cores. Support for RAT
1040 * is currently not supported, so 64-bit address regions are not
1041 * supported. The absence of MMUs implies that the R5F device
1042 * addresses/supported memory regions are restricted to 32-bit
1043 * bus addresses, and are identical
1044 */
1045 kproc->rmem[i].dev_addr = (u32)rmem->base;
1046 kproc->rmem[i].size = rmem->size;
1047 kproc->rmem[i].cpu_addr = ioremap_wc(rmem->base, rmem->size);
1048 if (!kproc->rmem[i].cpu_addr) {
1049 dev_err(dev, "failed to map reserved memory#%d at %pa of size %pa\n",
1050 i + 1, &rmem->base, &rmem->size);
1051 ret = -ENOMEM;
1052 goto unmap_rmem;
1053 }
1054
1055 dev_dbg(dev, "reserved memory%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1056 i + 1, &kproc->rmem[i].bus_addr,
1057 kproc->rmem[i].size, kproc->rmem[i].cpu_addr,
1058 kproc->rmem[i].dev_addr);
1059 }
1060 kproc->num_rmems = num_rmems;
1061
1062 return 0;
1063
1064 unmap_rmem:
1065 for (i--; i >= 0; i--)
1066 iounmap(kproc->rmem[i].cpu_addr);
1067 kfree(kproc->rmem);
1068 release_rmem:
1069 of_reserved_mem_device_release(dev);
1070 return ret;
1071 }
1072
k3_r5_reserved_mem_exit(struct k3_r5_rproc * kproc)1073 static void k3_r5_reserved_mem_exit(struct k3_r5_rproc *kproc)
1074 {
1075 int i;
1076
1077 for (i = 0; i < kproc->num_rmems; i++)
1078 iounmap(kproc->rmem[i].cpu_addr);
1079 kfree(kproc->rmem);
1080
1081 of_reserved_mem_device_release(kproc->dev);
1082 }
1083
1084 /*
1085 * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
1086 * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
1087 * cores are usable in Split-mode, but only the Core0 TCMs can be used in
1088 * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
1089 * leveraging the Core1 TCMs as well in certain modes where they would have
1090 * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs, Single-CPU mode on
1091 * AM64x SoCs). This is done by making a Core1 TCM visible immediately after the
1092 * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for
1093 * the Core0 TCMs, and the dts representation reflects this increased size on
1094 * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only
1095 * half the original size in Split mode.
1096 */
k3_r5_adjust_tcm_sizes(struct k3_r5_rproc * kproc)1097 static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc)
1098 {
1099 struct k3_r5_cluster *cluster = kproc->cluster;
1100 struct k3_r5_core *core = kproc->core;
1101 struct device *cdev = core->dev;
1102 struct k3_r5_core *core0;
1103
1104 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1105 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1106 cluster->mode == CLUSTER_MODE_SINGLECORE ||
1107 !cluster->soc_data->tcm_is_double)
1108 return;
1109
1110 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1111 if (core == core0) {
1112 WARN_ON(core->mem[0].size != SZ_64K);
1113 WARN_ON(core->mem[1].size != SZ_64K);
1114
1115 core->mem[0].size /= 2;
1116 core->mem[1].size /= 2;
1117
1118 dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
1119 core->mem[0].size, core->mem[1].size);
1120 }
1121 }
1122
1123 /*
1124 * This function checks and configures a R5F core for IPC-only or remoteproc
1125 * mode. The driver is configured to be in IPC-only mode for a R5F core when
1126 * the core has been loaded and started by a bootloader. The IPC-only mode is
1127 * detected by querying the System Firmware for reset, power on and halt status
1128 * and ensuring that the core is running. Any incomplete steps at bootloader
1129 * are validated and errored out.
1130 *
1131 * In IPC-only mode, the driver state flags for ATCM, BTCM and LOCZRAMA settings
1132 * and cluster mode parsed originally from kernel DT are updated to reflect the
1133 * actual values configured by bootloader. The driver internal device memory
1134 * addresses for TCMs are also updated.
1135 */
k3_r5_rproc_configure_mode(struct k3_r5_rproc * kproc)1136 static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc)
1137 {
1138 struct k3_r5_cluster *cluster = kproc->cluster;
1139 struct k3_r5_core *core = kproc->core;
1140 struct device *cdev = core->dev;
1141 bool r_state = false, c_state = false, lockstep_en = false, single_cpu = false;
1142 u32 ctrl = 0, cfg = 0, stat = 0, halted = 0;
1143 u64 boot_vec = 0;
1144 u32 atcm_enable, btcm_enable, loczrama;
1145 struct k3_r5_core *core0;
1146 enum cluster_mode mode = cluster->mode;
1147 int ret;
1148
1149 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1150
1151 ret = core->ti_sci->ops.dev_ops.is_on(core->ti_sci, core->ti_sci_id,
1152 &r_state, &c_state);
1153 if (ret) {
1154 dev_err(cdev, "failed to get initial state, mode cannot be determined, ret = %d\n",
1155 ret);
1156 return ret;
1157 }
1158 if (r_state != c_state) {
1159 dev_warn(cdev, "R5F core may have been powered on by a different host, programmed state (%d) != actual state (%d)\n",
1160 r_state, c_state);
1161 }
1162
1163 ret = reset_control_status(core->reset);
1164 if (ret < 0) {
1165 dev_err(cdev, "failed to get initial local reset status, ret = %d\n",
1166 ret);
1167 return ret;
1168 }
1169
1170 /*
1171 * Skip the waiting mechanism for sequential power-on of cores if the
1172 * core has already been booted by another entity.
1173 */
1174 core->released_from_reset = c_state;
1175
1176 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
1177 &stat);
1178 if (ret < 0) {
1179 dev_err(cdev, "failed to get initial processor status, ret = %d\n",
1180 ret);
1181 return ret;
1182 }
1183 atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0;
1184 btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0;
1185 loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0;
1186 single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0;
1187 lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0;
1188
1189 if (single_cpu && mode != CLUSTER_MODE_SINGLECORE)
1190 mode = CLUSTER_MODE_SINGLECPU;
1191 if (lockstep_en)
1192 mode = CLUSTER_MODE_LOCKSTEP;
1193
1194 halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT;
1195
1196 /*
1197 * IPC-only mode detection requires both local and module resets to
1198 * be deasserted and R5F core to be unhalted. Local reset status is
1199 * irrelevant if module reset is asserted (POR value has local reset
1200 * deasserted), and is deemed as remoteproc mode
1201 */
1202 if (c_state && !ret && !halted) {
1203 dev_info(cdev, "configured R5F for IPC-only mode\n");
1204 kproc->rproc->state = RPROC_DETACHED;
1205 ret = 1;
1206 /* override rproc ops with only required IPC-only mode ops */
1207 kproc->rproc->ops->prepare = NULL;
1208 kproc->rproc->ops->unprepare = NULL;
1209 kproc->rproc->ops->start = NULL;
1210 kproc->rproc->ops->stop = NULL;
1211 kproc->rproc->ops->attach = k3_r5_rproc_attach;
1212 kproc->rproc->ops->detach = k3_r5_rproc_detach;
1213 kproc->rproc->ops->get_loaded_rsc_table =
1214 k3_r5_get_loaded_rsc_table;
1215 } else if (!c_state) {
1216 dev_info(cdev, "configured R5F for remoteproc mode\n");
1217 ret = 0;
1218 } else {
1219 dev_err(cdev, "mismatched mode: local_reset = %s, module_reset = %s, core_state = %s\n",
1220 !ret ? "deasserted" : "asserted",
1221 c_state ? "deasserted" : "asserted",
1222 halted ? "halted" : "unhalted");
1223 ret = -EINVAL;
1224 }
1225
1226 /* fixup TCMs, cluster & core flags to actual values in IPC-only mode */
1227 if (ret > 0) {
1228 if (core == core0)
1229 cluster->mode = mode;
1230 core->atcm_enable = atcm_enable;
1231 core->btcm_enable = btcm_enable;
1232 core->loczrama = loczrama;
1233 core->mem[0].dev_addr = loczrama ? 0 : K3_R5_TCM_DEV_ADDR;
1234 core->mem[1].dev_addr = loczrama ? K3_R5_TCM_DEV_ADDR : 0;
1235 }
1236
1237 return ret;
1238 }
1239
k3_r5_cluster_rproc_init(struct platform_device * pdev)1240 static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
1241 {
1242 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1243 struct device *dev = &pdev->dev;
1244 struct k3_r5_rproc *kproc;
1245 struct k3_r5_core *core, *core1;
1246 struct device *cdev;
1247 const char *fw_name;
1248 struct rproc *rproc;
1249 int ret, ret1;
1250
1251 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1252 list_for_each_entry(core, &cluster->cores, elem) {
1253 cdev = core->dev;
1254 ret = rproc_of_parse_firmware(cdev, 0, &fw_name);
1255 if (ret) {
1256 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
1257 ret);
1258 goto out;
1259 }
1260
1261 rproc = rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops,
1262 fw_name, sizeof(*kproc));
1263 if (!rproc) {
1264 ret = -ENOMEM;
1265 goto out;
1266 }
1267
1268 /* K3 R5s have a Region Address Translator (RAT) but no MMU */
1269 rproc->has_iommu = false;
1270 /* error recovery is not supported at present */
1271 rproc->recovery_disabled = true;
1272
1273 kproc = rproc->priv;
1274 kproc->cluster = cluster;
1275 kproc->core = core;
1276 kproc->dev = cdev;
1277 kproc->rproc = rproc;
1278 core->rproc = rproc;
1279
1280 ret = k3_r5_rproc_configure_mode(kproc);
1281 if (ret < 0)
1282 goto err_config;
1283 if (ret)
1284 goto init_rmem;
1285
1286 ret = k3_r5_rproc_configure(kproc);
1287 if (ret) {
1288 dev_err(dev, "initial configure failed, ret = %d\n",
1289 ret);
1290 goto err_config;
1291 }
1292
1293 init_rmem:
1294 k3_r5_adjust_tcm_sizes(kproc);
1295
1296 ret = k3_r5_reserved_mem_init(kproc);
1297 if (ret) {
1298 dev_err(dev, "reserved memory init failed, ret = %d\n",
1299 ret);
1300 goto err_config;
1301 }
1302
1303 ret = rproc_add(rproc);
1304 if (ret) {
1305 dev_err(dev, "rproc_add failed, ret = %d\n", ret);
1306 goto err_add;
1307 }
1308
1309 /* create only one rproc in lockstep, single-cpu or
1310 * single core mode
1311 */
1312 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1313 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1314 cluster->mode == CLUSTER_MODE_SINGLECORE)
1315 break;
1316
1317 /*
1318 * R5 cores require to be powered on sequentially, core0
1319 * should be in higher power state than core1 in a cluster
1320 * So, wait for current core to power up before proceeding
1321 * to next core and put timeout of 2sec for each core.
1322 *
1323 * This waiting mechanism is necessary because
1324 * rproc_auto_boot_callback() for core1 can be called before
1325 * core0 due to thread execution order.
1326 */
1327 ret = wait_event_interruptible_timeout(cluster->core_transition,
1328 core->released_from_reset,
1329 msecs_to_jiffies(2000));
1330 if (ret <= 0) {
1331 dev_err(dev,
1332 "Timed out waiting for %s core to power up!\n",
1333 rproc->name);
1334 return ret;
1335 }
1336 }
1337
1338 return 0;
1339
1340 err_split:
1341 if (rproc->state == RPROC_ATTACHED) {
1342 ret1 = rproc_detach(rproc);
1343 if (ret1) {
1344 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n",
1345 ret1);
1346 return ret1;
1347 }
1348 }
1349
1350 rproc_del(rproc);
1351 err_add:
1352 k3_r5_reserved_mem_exit(kproc);
1353 err_config:
1354 rproc_free(rproc);
1355 core->rproc = NULL;
1356 out:
1357 /* undo core0 upon any failures on core1 in split-mode */
1358 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) {
1359 core = list_prev_entry(core, elem);
1360 rproc = core->rproc;
1361 kproc = rproc->priv;
1362 goto err_split;
1363 }
1364 return ret;
1365 }
1366
k3_r5_cluster_rproc_exit(void * data)1367 static void k3_r5_cluster_rproc_exit(void *data)
1368 {
1369 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1370 struct k3_r5_rproc *kproc;
1371 struct k3_r5_core *core;
1372 struct rproc *rproc;
1373 int ret;
1374
1375 /*
1376 * lockstep mode and single-cpu modes have only one rproc associated
1377 * with first core, whereas split-mode has two rprocs associated with
1378 * each core, and requires that core1 be powered down first
1379 */
1380 core = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1381 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
1382 list_first_entry(&cluster->cores, struct k3_r5_core, elem) :
1383 list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1384
1385 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
1386 rproc = core->rproc;
1387 kproc = rproc->priv;
1388
1389 if (rproc->state == RPROC_ATTACHED) {
1390 ret = rproc_detach(rproc);
1391 if (ret) {
1392 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", ret);
1393 return;
1394 }
1395 }
1396
1397 rproc_del(rproc);
1398
1399 k3_r5_reserved_mem_exit(kproc);
1400
1401 rproc_free(rproc);
1402 core->rproc = NULL;
1403 }
1404 }
1405
k3_r5_core_of_get_internal_memories(struct platform_device * pdev,struct k3_r5_core * core)1406 static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
1407 struct k3_r5_core *core)
1408 {
1409 static const char * const mem_names[] = {"atcm", "btcm"};
1410 struct device *dev = &pdev->dev;
1411 struct resource *res;
1412 int num_mems;
1413 int i;
1414
1415 num_mems = ARRAY_SIZE(mem_names);
1416 core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);
1417 if (!core->mem)
1418 return -ENOMEM;
1419
1420 for (i = 0; i < num_mems; i++) {
1421 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1422 mem_names[i]);
1423 if (!res) {
1424 dev_err(dev, "found no memory resource for %s\n",
1425 mem_names[i]);
1426 return -EINVAL;
1427 }
1428 if (!devm_request_mem_region(dev, res->start,
1429 resource_size(res),
1430 dev_name(dev))) {
1431 dev_err(dev, "could not request %s region for resource\n",
1432 mem_names[i]);
1433 return -EBUSY;
1434 }
1435
1436 /*
1437 * TCMs are designed in general to support RAM-like backing
1438 * memories. So, map these as Normal Non-Cached memories. This
1439 * also avoids/fixes any potential alignment faults due to
1440 * unaligned data accesses when using memcpy() or memset()
1441 * functions (normally seen with device type memory).
1442 */
1443 core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,
1444 resource_size(res));
1445 if (!core->mem[i].cpu_addr) {
1446 dev_err(dev, "failed to map %s memory\n", mem_names[i]);
1447 return -ENOMEM;
1448 }
1449 core->mem[i].bus_addr = res->start;
1450
1451 /*
1452 * TODO:
1453 * The R5F cores can place ATCM & BTCM anywhere in its address
1454 * based on the corresponding Region Registers in the System
1455 * Control coprocessor. For now, place ATCM and BTCM at
1456 * addresses 0 and 0x41010000 (same as the bus address on AM65x
1457 * SoCs) based on loczrama setting
1458 */
1459 if (!strcmp(mem_names[i], "atcm")) {
1460 core->mem[i].dev_addr = core->loczrama ?
1461 0 : K3_R5_TCM_DEV_ADDR;
1462 } else {
1463 core->mem[i].dev_addr = core->loczrama ?
1464 K3_R5_TCM_DEV_ADDR : 0;
1465 }
1466 core->mem[i].size = resource_size(res);
1467
1468 dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1469 mem_names[i], &core->mem[i].bus_addr,
1470 core->mem[i].size, core->mem[i].cpu_addr,
1471 core->mem[i].dev_addr);
1472 }
1473 core->num_mems = num_mems;
1474
1475 return 0;
1476 }
1477
k3_r5_core_of_get_sram_memories(struct platform_device * pdev,struct k3_r5_core * core)1478 static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
1479 struct k3_r5_core *core)
1480 {
1481 struct device_node *np = pdev->dev.of_node;
1482 struct device *dev = &pdev->dev;
1483 struct device_node *sram_np;
1484 struct resource res;
1485 int num_sram;
1486 int i, ret;
1487
1488 num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
1489 if (num_sram <= 0) {
1490 dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
1491 num_sram);
1492 return 0;
1493 }
1494
1495 core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
1496 if (!core->sram)
1497 return -ENOMEM;
1498
1499 for (i = 0; i < num_sram; i++) {
1500 sram_np = of_parse_phandle(np, "sram", i);
1501 if (!sram_np)
1502 return -EINVAL;
1503
1504 if (!of_device_is_available(sram_np)) {
1505 of_node_put(sram_np);
1506 return -EINVAL;
1507 }
1508
1509 ret = of_address_to_resource(sram_np, 0, &res);
1510 of_node_put(sram_np);
1511 if (ret)
1512 return -EINVAL;
1513
1514 core->sram[i].bus_addr = res.start;
1515 core->sram[i].dev_addr = res.start;
1516 core->sram[i].size = resource_size(&res);
1517 core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
1518 resource_size(&res));
1519 if (!core->sram[i].cpu_addr) {
1520 dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
1521 i, &res.start);
1522 return -ENOMEM;
1523 }
1524
1525 dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1526 i, &core->sram[i].bus_addr,
1527 core->sram[i].size, core->sram[i].cpu_addr,
1528 core->sram[i].dev_addr);
1529 }
1530 core->num_sram = num_sram;
1531
1532 return 0;
1533 }
1534
1535 static
k3_r5_core_of_get_tsp(struct device * dev,const struct ti_sci_handle * sci)1536 struct ti_sci_proc *k3_r5_core_of_get_tsp(struct device *dev,
1537 const struct ti_sci_handle *sci)
1538 {
1539 struct ti_sci_proc *tsp;
1540 u32 temp[2];
1541 int ret;
1542
1543 ret = of_property_read_u32_array(dev_of_node(dev), "ti,sci-proc-ids",
1544 temp, 2);
1545 if (ret < 0)
1546 return ERR_PTR(ret);
1547
1548 tsp = devm_kzalloc(dev, sizeof(*tsp), GFP_KERNEL);
1549 if (!tsp)
1550 return ERR_PTR(-ENOMEM);
1551
1552 tsp->dev = dev;
1553 tsp->sci = sci;
1554 tsp->ops = &sci->ops.proc_ops;
1555 tsp->proc_id = temp[0];
1556 tsp->host_id = temp[1];
1557
1558 return tsp;
1559 }
1560
k3_r5_core_of_init(struct platform_device * pdev)1561 static int k3_r5_core_of_init(struct platform_device *pdev)
1562 {
1563 struct device *dev = &pdev->dev;
1564 struct device_node *np = dev_of_node(dev);
1565 struct k3_r5_core *core;
1566 int ret;
1567
1568 if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL))
1569 return -ENOMEM;
1570
1571 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
1572 if (!core) {
1573 ret = -ENOMEM;
1574 goto err;
1575 }
1576
1577 core->dev = dev;
1578 /*
1579 * Use SoC Power-on-Reset values as default if no DT properties are
1580 * used to dictate the TCM configurations
1581 */
1582 core->atcm_enable = 0;
1583 core->btcm_enable = 1;
1584 core->loczrama = 1;
1585
1586 ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable);
1587 if (ret < 0 && ret != -EINVAL) {
1588 dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n",
1589 ret);
1590 goto err;
1591 }
1592
1593 ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable);
1594 if (ret < 0 && ret != -EINVAL) {
1595 dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n",
1596 ret);
1597 goto err;
1598 }
1599
1600 ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama);
1601 if (ret < 0 && ret != -EINVAL) {
1602 dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret);
1603 goto err;
1604 }
1605
1606 core->ti_sci = devm_ti_sci_get_by_phandle(dev, "ti,sci");
1607 if (IS_ERR(core->ti_sci)) {
1608 ret = PTR_ERR(core->ti_sci);
1609 if (ret != -EPROBE_DEFER) {
1610 dev_err(dev, "failed to get ti-sci handle, ret = %d\n",
1611 ret);
1612 }
1613 core->ti_sci = NULL;
1614 goto err;
1615 }
1616
1617 ret = of_property_read_u32(np, "ti,sci-dev-id", &core->ti_sci_id);
1618 if (ret) {
1619 dev_err(dev, "missing 'ti,sci-dev-id' property\n");
1620 goto err;
1621 }
1622
1623 core->reset = devm_reset_control_get_exclusive(dev, NULL);
1624 if (IS_ERR_OR_NULL(core->reset)) {
1625 ret = PTR_ERR_OR_ZERO(core->reset);
1626 if (!ret)
1627 ret = -ENODEV;
1628 if (ret != -EPROBE_DEFER) {
1629 dev_err(dev, "failed to get reset handle, ret = %d\n",
1630 ret);
1631 }
1632 goto err;
1633 }
1634
1635 core->tsp = k3_r5_core_of_get_tsp(dev, core->ti_sci);
1636 if (IS_ERR(core->tsp)) {
1637 ret = PTR_ERR(core->tsp);
1638 dev_err(dev, "failed to construct ti-sci proc control, ret = %d\n",
1639 ret);
1640 goto err;
1641 }
1642
1643 ret = k3_r5_core_of_get_internal_memories(pdev, core);
1644 if (ret) {
1645 dev_err(dev, "failed to get internal memories, ret = %d\n",
1646 ret);
1647 goto err;
1648 }
1649
1650 ret = k3_r5_core_of_get_sram_memories(pdev, core);
1651 if (ret) {
1652 dev_err(dev, "failed to get sram memories, ret = %d\n", ret);
1653 goto err;
1654 }
1655
1656 ret = ti_sci_proc_request(core->tsp);
1657 if (ret < 0) {
1658 dev_err(dev, "ti_sci_proc_request failed, ret = %d\n", ret);
1659 goto err;
1660 }
1661
1662 platform_set_drvdata(pdev, core);
1663 devres_close_group(dev, k3_r5_core_of_init);
1664
1665 return 0;
1666
1667 err:
1668 devres_release_group(dev, k3_r5_core_of_init);
1669 return ret;
1670 }
1671
1672 /*
1673 * free the resources explicitly since driver model is not being used
1674 * for the child R5F devices
1675 */
k3_r5_core_of_exit(struct platform_device * pdev)1676 static void k3_r5_core_of_exit(struct platform_device *pdev)
1677 {
1678 struct k3_r5_core *core = platform_get_drvdata(pdev);
1679 struct device *dev = &pdev->dev;
1680 int ret;
1681
1682 ret = ti_sci_proc_release(core->tsp);
1683 if (ret)
1684 dev_err(dev, "failed to release proc, ret = %d\n", ret);
1685
1686 platform_set_drvdata(pdev, NULL);
1687 devres_release_group(dev, k3_r5_core_of_init);
1688 }
1689
k3_r5_cluster_of_exit(void * data)1690 static void k3_r5_cluster_of_exit(void *data)
1691 {
1692 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1693 struct platform_device *cpdev;
1694 struct k3_r5_core *core, *temp;
1695
1696 list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {
1697 list_del(&core->elem);
1698 cpdev = to_platform_device(core->dev);
1699 k3_r5_core_of_exit(cpdev);
1700 }
1701 }
1702
k3_r5_cluster_of_init(struct platform_device * pdev)1703 static int k3_r5_cluster_of_init(struct platform_device *pdev)
1704 {
1705 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1706 struct device *dev = &pdev->dev;
1707 struct device_node *np = dev_of_node(dev);
1708 struct platform_device *cpdev;
1709 struct device_node *child;
1710 struct k3_r5_core *core;
1711 int ret;
1712
1713 for_each_available_child_of_node(np, child) {
1714 cpdev = of_find_device_by_node(child);
1715 if (!cpdev) {
1716 ret = -ENODEV;
1717 dev_err(dev, "could not get R5 core platform device\n");
1718 of_node_put(child);
1719 goto fail;
1720 }
1721
1722 ret = k3_r5_core_of_init(cpdev);
1723 if (ret) {
1724 dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n",
1725 ret);
1726 put_device(&cpdev->dev);
1727 of_node_put(child);
1728 goto fail;
1729 }
1730
1731 core = platform_get_drvdata(cpdev);
1732 put_device(&cpdev->dev);
1733 list_add_tail(&core->elem, &cluster->cores);
1734 }
1735
1736 return 0;
1737
1738 fail:
1739 k3_r5_cluster_of_exit(pdev);
1740 return ret;
1741 }
1742
k3_r5_probe(struct platform_device * pdev)1743 static int k3_r5_probe(struct platform_device *pdev)
1744 {
1745 struct device *dev = &pdev->dev;
1746 struct device_node *np = dev_of_node(dev);
1747 struct k3_r5_cluster *cluster;
1748 const struct k3_r5_soc_data *data;
1749 int ret;
1750 int num_cores;
1751
1752 data = of_device_get_match_data(&pdev->dev);
1753 if (!data) {
1754 dev_err(dev, "SoC-specific data is not defined\n");
1755 return -ENODEV;
1756 }
1757
1758 cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
1759 if (!cluster)
1760 return -ENOMEM;
1761
1762 cluster->dev = dev;
1763 cluster->soc_data = data;
1764 INIT_LIST_HEAD(&cluster->cores);
1765 init_waitqueue_head(&cluster->core_transition);
1766
1767 ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode);
1768 if (ret < 0 && ret != -EINVAL) {
1769 dev_err(dev, "invalid format for ti,cluster-mode, ret = %d\n",
1770 ret);
1771 return ret;
1772 }
1773
1774 if (ret == -EINVAL) {
1775 /*
1776 * default to most common efuse configurations - Split-mode on AM64x
1777 * and LockStep-mode on all others
1778 * default to most common efuse configurations -
1779 * Split-mode on AM64x
1780 * Single core on AM62x
1781 * LockStep-mode on all others
1782 */
1783 if (!data->is_single_core)
1784 cluster->mode = data->single_cpu_mode ?
1785 CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP;
1786 else
1787 cluster->mode = CLUSTER_MODE_SINGLECORE;
1788 }
1789
1790 if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) ||
1791 (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core)) {
1792 dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode);
1793 return -EINVAL;
1794 }
1795
1796 num_cores = of_get_available_child_count(np);
1797 if (num_cores != 2 && !data->is_single_core) {
1798 dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n",
1799 num_cores);
1800 return -ENODEV;
1801 }
1802
1803 if (num_cores != 1 && data->is_single_core) {
1804 dev_err(dev, "SoC supports only single core R5 but num_cores is set to %d\n",
1805 num_cores);
1806 return -ENODEV;
1807 }
1808
1809 platform_set_drvdata(pdev, cluster);
1810
1811 ret = devm_of_platform_populate(dev);
1812 if (ret) {
1813 dev_err(dev, "devm_of_platform_populate failed, ret = %d\n",
1814 ret);
1815 return ret;
1816 }
1817
1818 ret = k3_r5_cluster_of_init(pdev);
1819 if (ret) {
1820 dev_err(dev, "k3_r5_cluster_of_init failed, ret = %d\n", ret);
1821 return ret;
1822 }
1823
1824 ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev);
1825 if (ret)
1826 return ret;
1827
1828 ret = k3_r5_cluster_rproc_init(pdev);
1829 if (ret) {
1830 dev_err(dev, "k3_r5_cluster_rproc_init failed, ret = %d\n",
1831 ret);
1832 return ret;
1833 }
1834
1835 ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev);
1836 if (ret)
1837 return ret;
1838
1839 return 0;
1840 }
1841
1842 static const struct k3_r5_soc_data am65_j721e_soc_data = {
1843 .tcm_is_double = false,
1844 .tcm_ecc_autoinit = false,
1845 .single_cpu_mode = false,
1846 .is_single_core = false,
1847 };
1848
1849 static const struct k3_r5_soc_data j7200_j721s2_soc_data = {
1850 .tcm_is_double = true,
1851 .tcm_ecc_autoinit = true,
1852 .single_cpu_mode = false,
1853 .is_single_core = false,
1854 };
1855
1856 static const struct k3_r5_soc_data am64_soc_data = {
1857 .tcm_is_double = true,
1858 .tcm_ecc_autoinit = true,
1859 .single_cpu_mode = true,
1860 .is_single_core = false,
1861 };
1862
1863 static const struct k3_r5_soc_data am62_soc_data = {
1864 .tcm_is_double = false,
1865 .tcm_ecc_autoinit = true,
1866 .single_cpu_mode = false,
1867 .is_single_core = true,
1868 };
1869
1870 static const struct of_device_id k3_r5_of_match[] = {
1871 { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, },
1872 { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, },
1873 { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, },
1874 { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, },
1875 { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, },
1876 { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, },
1877 { /* sentinel */ },
1878 };
1879 MODULE_DEVICE_TABLE(of, k3_r5_of_match);
1880
1881 static struct platform_driver k3_r5_rproc_driver = {
1882 .probe = k3_r5_probe,
1883 .driver = {
1884 .name = "k3_r5_rproc",
1885 .of_match_table = k3_r5_of_match,
1886 },
1887 };
1888
1889 module_platform_driver(k3_r5_rproc_driver);
1890
1891 MODULE_LICENSE("GPL v2");
1892 MODULE_DESCRIPTION("TI K3 R5F remote processor driver");
1893 MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
1894