1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * J-Core SoC PIT/clocksource driver
4  *
5  * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
6  */
7 
8 #include <linux/kernel.h>
9 #include <linux/slab.h>
10 #include <linux/interrupt.h>
11 #include <linux/clockchips.h>
12 #include <linux/clocksource.h>
13 #include <linux/sched_clock.h>
14 #include <linux/cpu.h>
15 #include <linux/cpuhotplug.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 
19 #define PIT_IRQ_SHIFT		12
20 #define PIT_PRIO_SHIFT		20
21 #define PIT_ENABLE_SHIFT	26
22 #define PIT_PRIO_MASK		0xf
23 
24 #define REG_PITEN		0x00
25 #define REG_THROT		0x10
26 #define REG_COUNT		0x14
27 #define REG_BUSPD		0x18
28 #define REG_SECHI		0x20
29 #define REG_SECLO		0x24
30 #define REG_NSEC		0x28
31 
32 struct jcore_pit {
33 	struct clock_event_device	ced;
34 	void __iomem			*base;
35 	unsigned long			periodic_delta;
36 	u32				enable_val;
37 };
38 
39 static void __iomem *jcore_pit_base;
40 static struct jcore_pit __percpu *jcore_pit_percpu;
41 
jcore_sched_clock_read(void)42 static notrace u64 jcore_sched_clock_read(void)
43 {
44 	u32 seclo, nsec, seclo0;
45 	__iomem void *base = jcore_pit_base;
46 
47 	seclo = readl(base + REG_SECLO);
48 	do {
49 		seclo0 = seclo;
50 		nsec  = readl(base + REG_NSEC);
51 		seclo = readl(base + REG_SECLO);
52 	} while (seclo0 != seclo);
53 
54 	return seclo * NSEC_PER_SEC + nsec;
55 }
56 
jcore_clocksource_read(struct clocksource * cs)57 static u64 jcore_clocksource_read(struct clocksource *cs)
58 {
59 	return jcore_sched_clock_read();
60 }
61 
jcore_pit_disable(struct jcore_pit * pit)62 static int jcore_pit_disable(struct jcore_pit *pit)
63 {
64 	writel(0, pit->base + REG_PITEN);
65 	return 0;
66 }
67 
jcore_pit_set(unsigned long delta,struct jcore_pit * pit)68 static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
69 {
70 	jcore_pit_disable(pit);
71 	writel(delta, pit->base + REG_THROT);
72 	writel(pit->enable_val, pit->base + REG_PITEN);
73 	return 0;
74 }
75 
jcore_pit_set_state_shutdown(struct clock_event_device * ced)76 static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
77 {
78 	struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
79 
80 	return jcore_pit_disable(pit);
81 }
82 
jcore_pit_set_state_oneshot(struct clock_event_device * ced)83 static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
84 {
85 	struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
86 
87 	return jcore_pit_disable(pit);
88 }
89 
jcore_pit_set_state_periodic(struct clock_event_device * ced)90 static int jcore_pit_set_state_periodic(struct clock_event_device *ced)
91 {
92 	struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
93 
94 	return jcore_pit_set(pit->periodic_delta, pit);
95 }
96 
jcore_pit_set_next_event(unsigned long delta,struct clock_event_device * ced)97 static int jcore_pit_set_next_event(unsigned long delta,
98 				    struct clock_event_device *ced)
99 {
100 	struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
101 
102 	return jcore_pit_set(delta, pit);
103 }
104 
jcore_pit_local_init(unsigned cpu)105 static int jcore_pit_local_init(unsigned cpu)
106 {
107 	struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
108 	unsigned buspd, freq;
109 
110 	pr_info("Local J-Core PIT init on cpu %u\n", cpu);
111 
112 	buspd = readl(pit->base + REG_BUSPD);
113 	freq = DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd);
114 	pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);
115 
116 	clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);
117 
118 	return 0;
119 }
120 
jcore_timer_interrupt(int irq,void * dev_id)121 static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)
122 {
123 	struct jcore_pit *pit = this_cpu_ptr(dev_id);
124 
125 	if (clockevent_state_oneshot(&pit->ced))
126 		jcore_pit_disable(pit);
127 
128 	pit->ced.event_handler(&pit->ced);
129 
130 	return IRQ_HANDLED;
131 }
132 
jcore_pit_init(struct device_node * node)133 static int __init jcore_pit_init(struct device_node *node)
134 {
135 	int err;
136 	unsigned pit_irq, cpu;
137 	unsigned long hwirq;
138 	u32 irqprio, enable_val;
139 
140 	jcore_pit_base = of_iomap(node, 0);
141 	if (!jcore_pit_base) {
142 		pr_err("Error: Cannot map base address for J-Core PIT\n");
143 		return -ENXIO;
144 	}
145 
146 	pit_irq = irq_of_parse_and_map(node, 0);
147 	if (!pit_irq) {
148 		pr_err("Error: J-Core PIT has no IRQ\n");
149 		return -ENXIO;
150 	}
151 
152 	pr_info("Initializing J-Core PIT at %p IRQ %d\n",
153 		jcore_pit_base, pit_irq);
154 
155 	err = clocksource_mmio_init(jcore_pit_base, "jcore_pit_cs",
156 				    NSEC_PER_SEC, 400, 32,
157 				    jcore_clocksource_read);
158 	if (err) {
159 		pr_err("Error registering clocksource device: %d\n", err);
160 		return err;
161 	}
162 
163 	sched_clock_register(jcore_sched_clock_read, 32, NSEC_PER_SEC);
164 
165 	jcore_pit_percpu = alloc_percpu(struct jcore_pit);
166 	if (!jcore_pit_percpu) {
167 		pr_err("Failed to allocate memory for clock event device\n");
168 		return -ENOMEM;
169 	}
170 
171 	err = request_irq(pit_irq, jcore_timer_interrupt,
172 			  IRQF_TIMER | IRQF_PERCPU,
173 			  "jcore_pit", jcore_pit_percpu);
174 	if (err) {
175 		pr_err("pit irq request failed: %d\n", err);
176 		free_percpu(jcore_pit_percpu);
177 		return err;
178 	}
179 
180 	/*
181 	 * The J-Core PIT is not hard-wired to a particular IRQ, but
182 	 * integrated with the interrupt controller such that the IRQ it
183 	 * generates is programmable, as follows:
184 	 *
185 	 * The bit layout of the PIT enable register is:
186 	 *
187 	 *	.....e..ppppiiiiiiii............
188 	 *
189 	 * where the .'s indicate unrelated/unused bits, e is enable,
190 	 * p is priority, and i is hard irq number.
191 	 *
192 	 * For the PIT included in AIC1 (obsolete but still in use),
193 	 * any hard irq (trap number) can be programmed via the 8
194 	 * iiiiiiii bits, and a priority (0-15) is programmable
195 	 * separately in the pppp bits.
196 	 *
197 	 * For the PIT included in AIC2 (current), the programming
198 	 * interface is equivalent modulo interrupt mapping. This is
199 	 * why a different compatible tag was not used. However only
200 	 * traps 64-127 (the ones actually intended to be used for
201 	 * interrupts, rather than syscalls/exceptions/etc.) can be
202 	 * programmed (the high 2 bits of i are ignored) and the
203 	 * priority pppp is <<2'd and or'd onto the irq number. This
204 	 * choice seems to have been made on the hardware engineering
205 	 * side under an assumption that preserving old AIC1 priority
206 	 * mappings was important. Future models will likely ignore
207 	 * the pppp field.
208 	 */
209 	hwirq = irq_get_irq_data(pit_irq)->hwirq;
210 	irqprio = (hwirq >> 2) & PIT_PRIO_MASK;
211 	enable_val = (1U << PIT_ENABLE_SHIFT)
212 		   | (hwirq << PIT_IRQ_SHIFT)
213 		   | (irqprio << PIT_PRIO_SHIFT);
214 
215 	for_each_present_cpu(cpu) {
216 		struct jcore_pit *pit = per_cpu_ptr(jcore_pit_percpu, cpu);
217 
218 		pit->base = of_iomap(node, cpu);
219 		if (!pit->base) {
220 			pr_err("Unable to map PIT for cpu %u\n", cpu);
221 			continue;
222 		}
223 
224 		pit->ced.name = "jcore_pit";
225 		pit->ced.features = CLOCK_EVT_FEAT_PERIODIC
226 				  | CLOCK_EVT_FEAT_ONESHOT
227 				  | CLOCK_EVT_FEAT_PERCPU;
228 		pit->ced.cpumask = cpumask_of(cpu);
229 		pit->ced.rating = 400;
230 		pit->ced.irq = pit_irq;
231 		pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;
232 		pit->ced.set_state_periodic = jcore_pit_set_state_periodic;
233 		pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;
234 		pit->ced.set_next_event = jcore_pit_set_next_event;
235 
236 		pit->enable_val = enable_val;
237 	}
238 
239 	cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,
240 			  "clockevents/jcore:starting",
241 			  jcore_pit_local_init, NULL);
242 
243 	return 0;
244 }
245 
246 TIMER_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);
247