1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
6 */
7 #include <linux/devcoredump.h>
8 #include "iwl-drv.h"
9 #include "runtime.h"
10 #include "dbg.h"
11 #include "debugfs.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
15 #include "iwl-fh.h"
16 /**
17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
18 *
19 * @fwrt_ptr: pointer to the buffer coming from fwrt
20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
21 * transport's data.
22 * @trans_len: length of the valid data in trans_ptr
23 * @fwrt_len: length of the valid data in fwrt_ptr
24 */
25 struct iwl_fw_dump_ptrs {
26 struct iwl_trans_dump_data *trans_ptr;
27 void *fwrt_ptr;
28 u32 fwrt_len;
29 };
30
31 #define RADIO_REG_MAX_READ 0x2ad
iwl_read_radio_regs(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
33 struct iwl_fw_error_dump_data **dump_data)
34 {
35 u8 *pos = (void *)(*dump_data)->data;
36 int i;
37
38 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
39
40 if (!iwl_trans_grab_nic_access(fwrt->trans))
41 return;
42
43 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
44 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
45
46 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
47 u32 rd_cmd = RADIO_RSP_RD_CMD;
48
49 rd_cmd |= i << RADIO_RSP_ADDR_POS;
50 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
51 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
52
53 pos++;
54 }
55
56 *dump_data = iwl_fw_error_next_data(*dump_data);
57
58 iwl_trans_release_nic_access(fwrt->trans);
59 }
60
iwl_fwrt_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
62 struct iwl_fw_error_dump_data **dump_data,
63 int size, u32 offset, int fifo_num)
64 {
65 struct iwl_fw_error_dump_fifo *fifo_hdr;
66 u32 *fifo_data;
67 u32 fifo_len;
68 int i;
69
70 fifo_hdr = (void *)(*dump_data)->data;
71 fifo_data = (void *)fifo_hdr->data;
72 fifo_len = size;
73
74 /* No need to try to read the data if the length is 0 */
75 if (fifo_len == 0)
76 return;
77
78 /* Add a TLV for the RXF */
79 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
80 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
81
82 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
83 fifo_hdr->available_bytes =
84 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
85 RXF_RD_D_SPACE + offset));
86 fifo_hdr->wr_ptr =
87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
88 RXF_RD_WR_PTR + offset));
89 fifo_hdr->rd_ptr =
90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
91 RXF_RD_RD_PTR + offset));
92 fifo_hdr->fence_ptr =
93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
94 RXF_RD_FENCE_PTR + offset));
95 fifo_hdr->fence_mode =
96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
97 RXF_SET_FENCE_MODE + offset));
98
99 /* Lock fence */
100 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
101 /* Set fence pointer to the same place like WR pointer */
102 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
103 /* Set fence offset */
104 iwl_trans_write_prph(fwrt->trans,
105 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
106
107 /* Read FIFO */
108 fifo_len /= sizeof(u32); /* Size in DWORDS */
109 for (i = 0; i < fifo_len; i++)
110 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
111 RXF_FIFO_RD_FENCE_INC +
112 offset);
113 *dump_data = iwl_fw_error_next_data(*dump_data);
114 }
115
iwl_fwrt_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
117 struct iwl_fw_error_dump_data **dump_data,
118 int size, u32 offset, int fifo_num)
119 {
120 struct iwl_fw_error_dump_fifo *fifo_hdr;
121 u32 *fifo_data;
122 u32 fifo_len;
123 int i;
124
125 fifo_hdr = (void *)(*dump_data)->data;
126 fifo_data = (void *)fifo_hdr->data;
127 fifo_len = size;
128
129 /* No need to try to read the data if the length is 0 */
130 if (fifo_len == 0)
131 return;
132
133 /* Add a TLV for the FIFO */
134 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
135 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
136
137 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
138 fifo_hdr->available_bytes =
139 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
140 TXF_FIFO_ITEM_CNT + offset));
141 fifo_hdr->wr_ptr =
142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
143 TXF_WR_PTR + offset));
144 fifo_hdr->rd_ptr =
145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
146 TXF_RD_PTR + offset));
147 fifo_hdr->fence_ptr =
148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
149 TXF_FENCE_PTR + offset));
150 fifo_hdr->fence_mode =
151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
152 TXF_LOCK_FENCE + offset));
153
154 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
155 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
156 TXF_WR_PTR + offset);
157
158 /* Dummy-read to advance the read pointer to the head */
159 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
160
161 /* Read FIFO */
162 for (i = 0; i < fifo_len / sizeof(u32); i++)
163 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
164 TXF_READ_MODIFY_DATA +
165 offset);
166
167 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
168 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
169 fifo_data, fifo_len);
170
171 *dump_data = iwl_fw_error_next_data(*dump_data);
172 }
173
iwl_fw_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)174 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
175 struct iwl_fw_error_dump_data **dump_data)
176 {
177 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
178
179 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
180
181 if (!iwl_trans_grab_nic_access(fwrt->trans))
182 return;
183
184 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
185 /* Pull RXF1 */
186 iwl_fwrt_dump_rxf(fwrt, dump_data,
187 cfg->lmac[0].rxfifo1_size, 0, 0);
188 /* Pull RXF2 */
189 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
190 RXF_DIFF_FROM_PREV +
191 fwrt->trans->trans_cfg->umac_prph_offset, 1);
192 /* Pull LMAC2 RXF1 */
193 if (fwrt->smem_cfg.num_lmacs > 1)
194 iwl_fwrt_dump_rxf(fwrt, dump_data,
195 cfg->lmac[1].rxfifo1_size,
196 LMAC2_PRPH_OFFSET, 2);
197 }
198
199 iwl_trans_release_nic_access(fwrt->trans);
200 }
201
iwl_fw_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)202 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
203 struct iwl_fw_error_dump_data **dump_data)
204 {
205 struct iwl_fw_error_dump_fifo *fifo_hdr;
206 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
207 u32 *fifo_data;
208 u32 fifo_len;
209 int i, j;
210
211 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
212
213 if (!iwl_trans_grab_nic_access(fwrt->trans))
214 return;
215
216 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
217 /* Pull TXF data from LMAC1 */
218 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
219 /* Mark the number of TXF we're pulling now */
220 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
221 iwl_fwrt_dump_txf(fwrt, dump_data,
222 cfg->lmac[0].txfifo_size[i], 0, i);
223 }
224
225 /* Pull TXF data from LMAC2 */
226 if (fwrt->smem_cfg.num_lmacs > 1) {
227 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
228 i++) {
229 /* Mark the number of TXF we're pulling now */
230 iwl_trans_write_prph(fwrt->trans,
231 TXF_LARC_NUM +
232 LMAC2_PRPH_OFFSET, i);
233 iwl_fwrt_dump_txf(fwrt, dump_data,
234 cfg->lmac[1].txfifo_size[i],
235 LMAC2_PRPH_OFFSET,
236 i + cfg->num_txfifo_entries);
237 }
238 }
239 }
240
241 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
242 fw_has_capa(&fwrt->fw->ucode_capa,
243 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
244 /* Pull UMAC internal TXF data from all TXFs */
245 for (i = 0;
246 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
247 i++) {
248 fifo_hdr = (void *)(*dump_data)->data;
249 fifo_data = (void *)fifo_hdr->data;
250 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
251
252 /* No need to try to read the data if the length is 0 */
253 if (fifo_len == 0)
254 continue;
255
256 /* Add a TLV for the internal FIFOs */
257 (*dump_data)->type =
258 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
259 (*dump_data)->len =
260 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
261
262 fifo_hdr->fifo_num = cpu_to_le32(i);
263
264 /* Mark the number of TXF we're pulling now */
265 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
266 fwrt->smem_cfg.num_txfifo_entries);
267
268 fifo_hdr->available_bytes =
269 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
270 TXF_CPU2_FIFO_ITEM_CNT));
271 fifo_hdr->wr_ptr =
272 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
273 TXF_CPU2_WR_PTR));
274 fifo_hdr->rd_ptr =
275 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
276 TXF_CPU2_RD_PTR));
277 fifo_hdr->fence_ptr =
278 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
279 TXF_CPU2_FENCE_PTR));
280 fifo_hdr->fence_mode =
281 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
282 TXF_CPU2_LOCK_FENCE));
283
284 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
285 iwl_trans_write_prph(fwrt->trans,
286 TXF_CPU2_READ_MODIFY_ADDR,
287 TXF_CPU2_WR_PTR);
288
289 /* Dummy-read to advance the read pointer to head */
290 iwl_trans_read_prph(fwrt->trans,
291 TXF_CPU2_READ_MODIFY_DATA);
292
293 /* Read FIFO */
294 fifo_len /= sizeof(u32); /* Size in DWORDS */
295 for (j = 0; j < fifo_len; j++)
296 fifo_data[j] =
297 iwl_trans_read_prph(fwrt->trans,
298 TXF_CPU2_READ_MODIFY_DATA);
299 *dump_data = iwl_fw_error_next_data(*dump_data);
300 }
301 }
302
303 iwl_trans_release_nic_access(fwrt->trans);
304 }
305
306 struct iwl_prph_range {
307 u32 start, end;
308 };
309
310 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
311 { .start = 0x00a00000, .end = 0x00a00000 },
312 { .start = 0x00a0000c, .end = 0x00a00024 },
313 { .start = 0x00a0002c, .end = 0x00a0003c },
314 { .start = 0x00a00410, .end = 0x00a00418 },
315 { .start = 0x00a00420, .end = 0x00a00420 },
316 { .start = 0x00a00428, .end = 0x00a00428 },
317 { .start = 0x00a00430, .end = 0x00a0043c },
318 { .start = 0x00a00444, .end = 0x00a00444 },
319 { .start = 0x00a004c0, .end = 0x00a004cc },
320 { .start = 0x00a004d8, .end = 0x00a004d8 },
321 { .start = 0x00a004e0, .end = 0x00a004f0 },
322 { .start = 0x00a00840, .end = 0x00a00840 },
323 { .start = 0x00a00850, .end = 0x00a00858 },
324 { .start = 0x00a01004, .end = 0x00a01008 },
325 { .start = 0x00a01010, .end = 0x00a01010 },
326 { .start = 0x00a01018, .end = 0x00a01018 },
327 { .start = 0x00a01024, .end = 0x00a01024 },
328 { .start = 0x00a0102c, .end = 0x00a01034 },
329 { .start = 0x00a0103c, .end = 0x00a01040 },
330 { .start = 0x00a01048, .end = 0x00a01094 },
331 { .start = 0x00a01c00, .end = 0x00a01c20 },
332 { .start = 0x00a01c58, .end = 0x00a01c58 },
333 { .start = 0x00a01c7c, .end = 0x00a01c7c },
334 { .start = 0x00a01c28, .end = 0x00a01c54 },
335 { .start = 0x00a01c5c, .end = 0x00a01c5c },
336 { .start = 0x00a01c60, .end = 0x00a01cdc },
337 { .start = 0x00a01ce0, .end = 0x00a01d0c },
338 { .start = 0x00a01d18, .end = 0x00a01d20 },
339 { .start = 0x00a01d2c, .end = 0x00a01d30 },
340 { .start = 0x00a01d40, .end = 0x00a01d5c },
341 { .start = 0x00a01d80, .end = 0x00a01d80 },
342 { .start = 0x00a01d98, .end = 0x00a01d9c },
343 { .start = 0x00a01da8, .end = 0x00a01da8 },
344 { .start = 0x00a01db8, .end = 0x00a01df4 },
345 { .start = 0x00a01dc0, .end = 0x00a01dfc },
346 { .start = 0x00a01e00, .end = 0x00a01e2c },
347 { .start = 0x00a01e40, .end = 0x00a01e60 },
348 { .start = 0x00a01e68, .end = 0x00a01e6c },
349 { .start = 0x00a01e74, .end = 0x00a01e74 },
350 { .start = 0x00a01e84, .end = 0x00a01e90 },
351 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
352 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
353 { .start = 0x00a01f00, .end = 0x00a01f1c },
354 { .start = 0x00a01f44, .end = 0x00a01ffc },
355 { .start = 0x00a02000, .end = 0x00a02048 },
356 { .start = 0x00a02068, .end = 0x00a020f0 },
357 { .start = 0x00a02100, .end = 0x00a02118 },
358 { .start = 0x00a02140, .end = 0x00a0214c },
359 { .start = 0x00a02168, .end = 0x00a0218c },
360 { .start = 0x00a021c0, .end = 0x00a021c0 },
361 { .start = 0x00a02400, .end = 0x00a02410 },
362 { .start = 0x00a02418, .end = 0x00a02420 },
363 { .start = 0x00a02428, .end = 0x00a0242c },
364 { .start = 0x00a02434, .end = 0x00a02434 },
365 { .start = 0x00a02440, .end = 0x00a02460 },
366 { .start = 0x00a02468, .end = 0x00a024b0 },
367 { .start = 0x00a024c8, .end = 0x00a024cc },
368 { .start = 0x00a02500, .end = 0x00a02504 },
369 { .start = 0x00a0250c, .end = 0x00a02510 },
370 { .start = 0x00a02540, .end = 0x00a02554 },
371 { .start = 0x00a02580, .end = 0x00a025f4 },
372 { .start = 0x00a02600, .end = 0x00a0260c },
373 { .start = 0x00a02648, .end = 0x00a02650 },
374 { .start = 0x00a02680, .end = 0x00a02680 },
375 { .start = 0x00a026c0, .end = 0x00a026d0 },
376 { .start = 0x00a02700, .end = 0x00a0270c },
377 { .start = 0x00a02804, .end = 0x00a02804 },
378 { .start = 0x00a02818, .end = 0x00a0281c },
379 { .start = 0x00a02c00, .end = 0x00a02db4 },
380 { .start = 0x00a02df4, .end = 0x00a02fb0 },
381 { .start = 0x00a03000, .end = 0x00a03014 },
382 { .start = 0x00a0301c, .end = 0x00a0302c },
383 { .start = 0x00a03034, .end = 0x00a03038 },
384 { .start = 0x00a03040, .end = 0x00a03048 },
385 { .start = 0x00a03060, .end = 0x00a03068 },
386 { .start = 0x00a03070, .end = 0x00a03074 },
387 { .start = 0x00a0307c, .end = 0x00a0307c },
388 { .start = 0x00a03080, .end = 0x00a03084 },
389 { .start = 0x00a0308c, .end = 0x00a03090 },
390 { .start = 0x00a03098, .end = 0x00a03098 },
391 { .start = 0x00a030a0, .end = 0x00a030a0 },
392 { .start = 0x00a030a8, .end = 0x00a030b4 },
393 { .start = 0x00a030bc, .end = 0x00a030bc },
394 { .start = 0x00a030c0, .end = 0x00a0312c },
395 { .start = 0x00a03c00, .end = 0x00a03c5c },
396 { .start = 0x00a04400, .end = 0x00a04454 },
397 { .start = 0x00a04460, .end = 0x00a04474 },
398 { .start = 0x00a044c0, .end = 0x00a044ec },
399 { .start = 0x00a04500, .end = 0x00a04504 },
400 { .start = 0x00a04510, .end = 0x00a04538 },
401 { .start = 0x00a04540, .end = 0x00a04548 },
402 { .start = 0x00a04560, .end = 0x00a0457c },
403 { .start = 0x00a04590, .end = 0x00a04598 },
404 { .start = 0x00a045c0, .end = 0x00a045f4 },
405 };
406
407 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
408 { .start = 0x00a05c00, .end = 0x00a05c18 },
409 { .start = 0x00a05400, .end = 0x00a056e8 },
410 { .start = 0x00a08000, .end = 0x00a098bc },
411 { .start = 0x00a02400, .end = 0x00a02758 },
412 { .start = 0x00a04764, .end = 0x00a0476c },
413 { .start = 0x00a04770, .end = 0x00a04774 },
414 { .start = 0x00a04620, .end = 0x00a04624 },
415 };
416
417 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = {
418 { .start = 0x00a00000, .end = 0x00a00000 },
419 { .start = 0x00a0000c, .end = 0x00a00024 },
420 { .start = 0x00a0002c, .end = 0x00a00034 },
421 { .start = 0x00a0003c, .end = 0x00a0003c },
422 { .start = 0x00a00410, .end = 0x00a00418 },
423 { .start = 0x00a00420, .end = 0x00a00420 },
424 { .start = 0x00a00428, .end = 0x00a00428 },
425 { .start = 0x00a00430, .end = 0x00a0043c },
426 { .start = 0x00a00444, .end = 0x00a00444 },
427 { .start = 0x00a00840, .end = 0x00a00840 },
428 { .start = 0x00a00850, .end = 0x00a00858 },
429 { .start = 0x00a01004, .end = 0x00a01008 },
430 { .start = 0x00a01010, .end = 0x00a01010 },
431 { .start = 0x00a01018, .end = 0x00a01018 },
432 { .start = 0x00a01024, .end = 0x00a01024 },
433 { .start = 0x00a0102c, .end = 0x00a01034 },
434 { .start = 0x00a0103c, .end = 0x00a01040 },
435 { .start = 0x00a01048, .end = 0x00a01050 },
436 { .start = 0x00a01058, .end = 0x00a01058 },
437 { .start = 0x00a01060, .end = 0x00a01070 },
438 { .start = 0x00a0108c, .end = 0x00a0108c },
439 { .start = 0x00a01c20, .end = 0x00a01c28 },
440 { .start = 0x00a01d10, .end = 0x00a01d10 },
441 { .start = 0x00a01e28, .end = 0x00a01e2c },
442 { .start = 0x00a01e60, .end = 0x00a01e60 },
443 { .start = 0x00a01e80, .end = 0x00a01e80 },
444 { .start = 0x00a01ea0, .end = 0x00a01ea0 },
445 { .start = 0x00a02000, .end = 0x00a0201c },
446 { .start = 0x00a02024, .end = 0x00a02024 },
447 { .start = 0x00a02040, .end = 0x00a02048 },
448 { .start = 0x00a020c0, .end = 0x00a020e0 },
449 { .start = 0x00a02400, .end = 0x00a02404 },
450 { .start = 0x00a0240c, .end = 0x00a02414 },
451 { .start = 0x00a0241c, .end = 0x00a0243c },
452 { .start = 0x00a02448, .end = 0x00a024bc },
453 { .start = 0x00a024c4, .end = 0x00a024cc },
454 { .start = 0x00a02508, .end = 0x00a02508 },
455 { .start = 0x00a02510, .end = 0x00a02514 },
456 { .start = 0x00a0251c, .end = 0x00a0251c },
457 { .start = 0x00a0252c, .end = 0x00a0255c },
458 { .start = 0x00a02564, .end = 0x00a025a0 },
459 { .start = 0x00a025a8, .end = 0x00a025b4 },
460 { .start = 0x00a025c0, .end = 0x00a025c0 },
461 { .start = 0x00a025e8, .end = 0x00a025f4 },
462 { .start = 0x00a02c08, .end = 0x00a02c18 },
463 { .start = 0x00a02c2c, .end = 0x00a02c38 },
464 { .start = 0x00a02c68, .end = 0x00a02c78 },
465 { .start = 0x00a03000, .end = 0x00a03000 },
466 { .start = 0x00a03010, .end = 0x00a03014 },
467 { .start = 0x00a0301c, .end = 0x00a0302c },
468 { .start = 0x00a03034, .end = 0x00a03038 },
469 { .start = 0x00a03040, .end = 0x00a03044 },
470 { .start = 0x00a03060, .end = 0x00a03068 },
471 { .start = 0x00a03070, .end = 0x00a03070 },
472 { .start = 0x00a0307c, .end = 0x00a03084 },
473 { .start = 0x00a0308c, .end = 0x00a03090 },
474 { .start = 0x00a03098, .end = 0x00a03098 },
475 { .start = 0x00a030a0, .end = 0x00a030a0 },
476 { .start = 0x00a030a8, .end = 0x00a030b4 },
477 { .start = 0x00a030bc, .end = 0x00a030c0 },
478 { .start = 0x00a030c8, .end = 0x00a030f4 },
479 { .start = 0x00a03100, .end = 0x00a0312c },
480 { .start = 0x00a03c00, .end = 0x00a03c5c },
481 { .start = 0x00a04400, .end = 0x00a04454 },
482 { .start = 0x00a04460, .end = 0x00a04474 },
483 { .start = 0x00a044c0, .end = 0x00a044ec },
484 { .start = 0x00a04500, .end = 0x00a04504 },
485 { .start = 0x00a04510, .end = 0x00a04538 },
486 { .start = 0x00a04540, .end = 0x00a04548 },
487 { .start = 0x00a04560, .end = 0x00a04560 },
488 { .start = 0x00a04570, .end = 0x00a0457c },
489 { .start = 0x00a04590, .end = 0x00a04590 },
490 { .start = 0x00a04598, .end = 0x00a04598 },
491 { .start = 0x00a045c0, .end = 0x00a045f4 },
492 { .start = 0x00a05c18, .end = 0x00a05c1c },
493 { .start = 0x00a0c000, .end = 0x00a0c018 },
494 { .start = 0x00a0c020, .end = 0x00a0c028 },
495 { .start = 0x00a0c038, .end = 0x00a0c094 },
496 { .start = 0x00a0c0c0, .end = 0x00a0c104 },
497 { .start = 0x00a0c10c, .end = 0x00a0c118 },
498 { .start = 0x00a0c150, .end = 0x00a0c174 },
499 { .start = 0x00a0c17c, .end = 0x00a0c188 },
500 { .start = 0x00a0c190, .end = 0x00a0c198 },
501 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
502 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
503 };
504
505 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = {
506 { .start = 0x00d03c00, .end = 0x00d03c64 },
507 { .start = 0x00d05c18, .end = 0x00d05c1c },
508 { .start = 0x00d0c000, .end = 0x00d0c174 },
509 };
510
iwl_read_prph_block(struct iwl_trans * trans,u32 start,u32 len_bytes,__le32 * data)511 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
512 u32 len_bytes, __le32 *data)
513 {
514 u32 i;
515
516 for (i = 0; i < len_bytes; i += 4)
517 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
518 }
519
iwl_dump_prph(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)520 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
521 const struct iwl_prph_range *iwl_prph_dump_addr,
522 u32 range_len, void *ptr)
523 {
524 struct iwl_fw_error_dump_prph *prph;
525 struct iwl_trans *trans = fwrt->trans;
526 struct iwl_fw_error_dump_data **data =
527 (struct iwl_fw_error_dump_data **)ptr;
528 u32 i;
529
530 if (!data)
531 return;
532
533 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
534
535 if (!iwl_trans_grab_nic_access(trans))
536 return;
537
538 for (i = 0; i < range_len; i++) {
539 /* The range includes both boundaries */
540 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
541 iwl_prph_dump_addr[i].start + 4;
542
543 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
544 (*data)->len = cpu_to_le32(sizeof(*prph) +
545 num_bytes_in_chunk);
546 prph = (void *)(*data)->data;
547 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
548
549 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
550 /* our range is inclusive, hence + 4 */
551 iwl_prph_dump_addr[i].end -
552 iwl_prph_dump_addr[i].start + 4,
553 (void *)prph->data);
554
555 *data = iwl_fw_error_next_data(*data);
556 }
557
558 iwl_trans_release_nic_access(trans);
559 }
560
561 /*
562 * alloc_sgtable - allocates (chained) scatterlist in the given size,
563 * fills it with pages and returns it
564 * @size: the size (in bytes) of the table
565 */
alloc_sgtable(ssize_t size)566 static struct scatterlist *alloc_sgtable(ssize_t size)
567 {
568 struct scatterlist *result = NULL, *prev;
569 int nents, i, n_prev;
570
571 nents = DIV_ROUND_UP(size, PAGE_SIZE);
572
573 #define N_ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(*result))
574 /*
575 * We need an additional entry for table chaining,
576 * this ensures the loop can finish i.e. we can
577 * fit at least two entries per page (obviously,
578 * many more really fit.)
579 */
580 BUILD_BUG_ON(N_ENTRIES_PER_PAGE < 2);
581
582 while (nents > 0) {
583 struct scatterlist *new, *iter;
584 int n_fill, n_alloc;
585
586 if (nents <= N_ENTRIES_PER_PAGE) {
587 /* last needed table */
588 n_fill = nents;
589 n_alloc = nents;
590 nents = 0;
591 } else {
592 /* fill a page with entries */
593 n_alloc = N_ENTRIES_PER_PAGE;
594 /* reserve one for chaining */
595 n_fill = n_alloc - 1;
596 nents -= n_fill;
597 }
598
599 new = kcalloc(n_alloc, sizeof(*new), GFP_KERNEL);
600 if (!new) {
601 if (result)
602 _devcd_free_sgtable(result);
603 return NULL;
604 }
605 sg_init_table(new, n_alloc);
606
607 if (!result)
608 result = new;
609 else
610 sg_chain(prev, n_prev, new);
611 prev = new;
612 n_prev = n_alloc;
613
614 for_each_sg(new, iter, n_fill, i) {
615 struct page *new_page = alloc_page(GFP_KERNEL);
616
617 if (!new_page) {
618 _devcd_free_sgtable(result);
619 return NULL;
620 }
621
622 sg_set_page(iter, new_page, PAGE_SIZE, 0);
623 }
624 }
625
626 return result;
627 }
628
iwl_fw_get_prph_len(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)629 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt,
630 const struct iwl_prph_range *iwl_prph_dump_addr,
631 u32 range_len, void *ptr)
632 {
633 u32 *prph_len = (u32 *)ptr;
634 int i, num_bytes_in_chunk;
635
636 if (!prph_len)
637 return;
638
639 for (i = 0; i < range_len; i++) {
640 /* The range includes both boundaries */
641 num_bytes_in_chunk =
642 iwl_prph_dump_addr[i].end -
643 iwl_prph_dump_addr[i].start + 4;
644
645 *prph_len += sizeof(struct iwl_fw_error_dump_data) +
646 sizeof(struct iwl_fw_error_dump_prph) +
647 num_bytes_in_chunk;
648 }
649 }
650
iwl_fw_prph_handler(struct iwl_fw_runtime * fwrt,void * ptr,void (* handler)(struct iwl_fw_runtime *,const struct iwl_prph_range *,u32,void *))651 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr,
652 void (*handler)(struct iwl_fw_runtime *,
653 const struct iwl_prph_range *,
654 u32, void *))
655 {
656 u32 range_len;
657
658 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
659 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210);
660 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr);
661 } else if (fwrt->trans->trans_cfg->device_family >=
662 IWL_DEVICE_FAMILY_22000) {
663 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000);
664 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr);
665 } else {
666 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm);
667 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr);
668
669 if (fwrt->trans->trans_cfg->mq_rx_supported) {
670 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000);
671 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr);
672 }
673 }
674 }
675
iwl_fw_dump_mem(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,u32 len,u32 ofs,u32 type)676 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
677 struct iwl_fw_error_dump_data **dump_data,
678 u32 len, u32 ofs, u32 type)
679 {
680 struct iwl_fw_error_dump_mem *dump_mem;
681
682 if (!len)
683 return;
684
685 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
686 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
687 dump_mem = (void *)(*dump_data)->data;
688 dump_mem->type = cpu_to_le32(type);
689 dump_mem->offset = cpu_to_le32(ofs);
690 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
691 *dump_data = iwl_fw_error_next_data(*dump_data);
692
693 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
694 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs,
695 dump_mem->data, len);
696
697 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
698 }
699
700 #define ADD_LEN(len, item_len, const_len) \
701 do {size_t item = item_len; len += (!!item) * const_len + item; } \
702 while (0)
703
iwl_fw_rxf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)704 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt,
705 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
706 {
707 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
708 sizeof(struct iwl_fw_error_dump_fifo);
709 u32 fifo_len = 0;
710 int i;
711
712 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF))
713 return 0;
714
715 /* Count RXF2 size */
716 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
717
718 /* Count RXF1 sizes */
719 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
720 mem_cfg->num_lmacs = MAX_NUM_LMAC;
721
722 for (i = 0; i < mem_cfg->num_lmacs; i++)
723 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
724
725 return fifo_len;
726 }
727
iwl_fw_txf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)728 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt,
729 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
730 {
731 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
732 sizeof(struct iwl_fw_error_dump_fifo);
733 u32 fifo_len = 0;
734 int i;
735
736 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF))
737 goto dump_internal_txf;
738
739 /* Count TXF sizes */
740 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
741 mem_cfg->num_lmacs = MAX_NUM_LMAC;
742
743 for (i = 0; i < mem_cfg->num_lmacs; i++) {
744 int j;
745
746 for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
747 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
748 hdr_len);
749 }
750
751 dump_internal_txf:
752 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
753 fw_has_capa(&fwrt->fw->ucode_capa,
754 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
755 goto out;
756
757 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
758 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
759
760 out:
761 return fifo_len;
762 }
763
iwl_dump_paging(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** data)764 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt,
765 struct iwl_fw_error_dump_data **data)
766 {
767 int i;
768
769 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
770 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
771 struct iwl_fw_error_dump_paging *paging;
772 struct page *pages =
773 fwrt->fw_paging_db[i].fw_paging_block;
774 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
775
776 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
777 (*data)->len = cpu_to_le32(sizeof(*paging) +
778 PAGING_BLOCK_SIZE);
779 paging = (void *)(*data)->data;
780 paging->index = cpu_to_le32(i);
781 dma_sync_single_for_cpu(fwrt->trans->dev, addr,
782 PAGING_BLOCK_SIZE,
783 DMA_BIDIRECTIONAL);
784 memcpy(paging->data, page_address(pages),
785 PAGING_BLOCK_SIZE);
786 dma_sync_single_for_device(fwrt->trans->dev, addr,
787 PAGING_BLOCK_SIZE,
788 DMA_BIDIRECTIONAL);
789 (*data) = iwl_fw_error_next_data(*data);
790
791 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
792 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
793 fwrt->fw_paging_db[i].fw_offs,
794 paging->data,
795 PAGING_BLOCK_SIZE);
796 }
797 }
798
799 static struct iwl_fw_error_dump_file *
iwl_fw_error_dump_file(struct iwl_fw_runtime * fwrt,struct iwl_fw_dump_ptrs * fw_error_dump,struct iwl_fwrt_dump_data * data)800 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
801 struct iwl_fw_dump_ptrs *fw_error_dump,
802 struct iwl_fwrt_dump_data *data)
803 {
804 struct iwl_fw_error_dump_file *dump_file;
805 struct iwl_fw_error_dump_data *dump_data;
806 struct iwl_fw_error_dump_info *dump_info;
807 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
808 struct iwl_fw_error_dump_trigger_desc *dump_trig;
809 u32 sram_len, sram_ofs;
810 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
811 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
812 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
813 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
814 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
815 0 : fwrt->trans->cfg->dccm2_len;
816 int i;
817
818 /* SRAM - include stack CCM if driver knows the values for it */
819 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) {
820 const struct fw_img *img;
821
822 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX)
823 return NULL;
824 img = &fwrt->fw->img[fwrt->cur_fw_img];
825 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
826 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
827 } else {
828 sram_ofs = fwrt->trans->cfg->dccm_offset;
829 sram_len = fwrt->trans->cfg->dccm_len;
830 }
831
832 /* reading RXF/TXF sizes */
833 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
834 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg);
835 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg);
836
837 /* Make room for PRPH registers */
838 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH))
839 iwl_fw_prph_handler(fwrt, &prph_len,
840 iwl_fw_get_prph_len);
841
842 if (fwrt->trans->trans_cfg->device_family ==
843 IWL_DEVICE_FAMILY_7000 &&
844 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG))
845 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
846 }
847
848 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
849
850 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO))
851 file_len += sizeof(*dump_data) + sizeof(*dump_info);
852 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG))
853 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
854
855 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
856 size_t hdr_len = sizeof(*dump_data) +
857 sizeof(struct iwl_fw_error_dump_mem);
858
859 /* Dump SRAM only if no mem_tlvs */
860 if (!fwrt->fw->dbg.n_mem_tlv)
861 ADD_LEN(file_len, sram_len, hdr_len);
862
863 /* Make room for all mem types that exist */
864 ADD_LEN(file_len, smem_len, hdr_len);
865 ADD_LEN(file_len, sram2_len, hdr_len);
866
867 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
868 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
869 }
870
871 /* Make room for fw's virtual image pages, if it exists */
872 if (iwl_fw_dbg_is_paging_enabled(fwrt))
873 file_len += fwrt->num_of_paging_blk *
874 (sizeof(*dump_data) +
875 sizeof(struct iwl_fw_error_dump_paging) +
876 PAGING_BLOCK_SIZE);
877
878 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
879 file_len += sizeof(*dump_data) +
880 fwrt->trans->cfg->d3_debug_data_length * 2;
881 }
882
883 /* If we only want a monitor dump, reset the file length */
884 if (data->monitor_only) {
885 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
886 sizeof(*dump_info) + sizeof(*dump_smem_cfg);
887 }
888
889 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
890 data->desc)
891 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
892 data->desc->len;
893
894 dump_file = vzalloc(file_len);
895 if (!dump_file)
896 return NULL;
897
898 fw_error_dump->fwrt_ptr = dump_file;
899
900 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
901 dump_data = (void *)dump_file->data;
902
903 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
904 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
905 dump_data->len = cpu_to_le32(sizeof(*dump_info));
906 dump_info = (void *)dump_data->data;
907 dump_info->hw_type =
908 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
909 dump_info->hw_step =
910 cpu_to_le32(fwrt->trans->hw_rev_step);
911 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
912 sizeof(dump_info->fw_human_readable));
913 strncpy(dump_info->dev_human_readable, fwrt->trans->name,
914 sizeof(dump_info->dev_human_readable) - 1);
915 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name,
916 sizeof(dump_info->bus_human_readable) - 1);
917 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs;
918 dump_info->lmac_err_id[0] =
919 cpu_to_le32(fwrt->dump.lmac_err_id[0]);
920 if (fwrt->smem_cfg.num_lmacs > 1)
921 dump_info->lmac_err_id[1] =
922 cpu_to_le32(fwrt->dump.lmac_err_id[1]);
923 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id);
924
925 dump_data = iwl_fw_error_next_data(dump_data);
926 }
927
928 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) {
929 /* Dump shared memory configuration */
930 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
931 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
932 dump_smem_cfg = (void *)dump_data->data;
933 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
934 dump_smem_cfg->num_txfifo_entries =
935 cpu_to_le32(mem_cfg->num_txfifo_entries);
936 for (i = 0; i < MAX_NUM_LMAC; i++) {
937 int j;
938 u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
939
940 for (j = 0; j < TX_FIFO_MAX_NUM; j++)
941 dump_smem_cfg->lmac[i].txfifo_size[j] =
942 cpu_to_le32(txf_size[j]);
943 dump_smem_cfg->lmac[i].rxfifo1_size =
944 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
945 }
946 dump_smem_cfg->rxfifo2_size =
947 cpu_to_le32(mem_cfg->rxfifo2_size);
948 dump_smem_cfg->internal_txfifo_addr =
949 cpu_to_le32(mem_cfg->internal_txfifo_addr);
950 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
951 dump_smem_cfg->internal_txfifo_size[i] =
952 cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
953 }
954
955 dump_data = iwl_fw_error_next_data(dump_data);
956 }
957
958 /* We only dump the FIFOs if the FW is in error state */
959 if (fifo_len) {
960 iwl_fw_dump_rxf(fwrt, &dump_data);
961 iwl_fw_dump_txf(fwrt, &dump_data);
962 }
963
964 if (radio_len)
965 iwl_read_radio_regs(fwrt, &dump_data);
966
967 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
968 data->desc) {
969 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
970 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
971 data->desc->len);
972 dump_trig = (void *)dump_data->data;
973 memcpy(dump_trig, &data->desc->trig_desc,
974 sizeof(*dump_trig) + data->desc->len);
975
976 dump_data = iwl_fw_error_next_data(dump_data);
977 }
978
979 /* In case we only want monitor dump, skip to dump trasport data */
980 if (data->monitor_only)
981 goto out;
982
983 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
984 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
985 fwrt->fw->dbg.mem_tlv;
986
987 if (!fwrt->fw->dbg.n_mem_tlv)
988 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
989 IWL_FW_ERROR_DUMP_MEM_SRAM);
990
991 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
992 u32 len = le32_to_cpu(fw_dbg_mem[i].len);
993 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
994
995 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
996 le32_to_cpu(fw_dbg_mem[i].data_type));
997 }
998
999 iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
1000 fwrt->trans->cfg->smem_offset,
1001 IWL_FW_ERROR_DUMP_MEM_SMEM);
1002
1003 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
1004 fwrt->trans->cfg->dccm2_offset,
1005 IWL_FW_ERROR_DUMP_MEM_SRAM);
1006 }
1007
1008 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
1009 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr;
1010 size_t data_size = fwrt->trans->cfg->d3_debug_data_length;
1011
1012 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
1013 dump_data->len = cpu_to_le32(data_size * 2);
1014
1015 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
1016
1017 kfree(fwrt->dump.d3_debug_data);
1018 fwrt->dump.d3_debug_data = NULL;
1019
1020 iwl_trans_read_mem_bytes(fwrt->trans, addr,
1021 dump_data->data + data_size,
1022 data_size);
1023
1024 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
1025 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr,
1026 dump_data->data + data_size,
1027 data_size);
1028
1029 dump_data = iwl_fw_error_next_data(dump_data);
1030 }
1031
1032 /* Dump fw's virtual image */
1033 if (iwl_fw_dbg_is_paging_enabled(fwrt))
1034 iwl_dump_paging(fwrt, &dump_data);
1035
1036 if (prph_len)
1037 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph);
1038
1039 out:
1040 dump_file->file_len = cpu_to_le32(file_len);
1041 return dump_file;
1042 }
1043
1044 /**
1045 * struct iwl_dump_ini_region_data - region data
1046 * @reg_tlv: region TLV
1047 * @dump_data: dump data
1048 */
1049 struct iwl_dump_ini_region_data {
1050 struct iwl_ucode_tlv *reg_tlv;
1051 struct iwl_fwrt_dump_data *dump_data;
1052 };
1053
1054 static int
iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1055 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt,
1056 struct iwl_dump_ini_region_data *reg_data,
1057 void *range_ptr, u32 range_len, int idx)
1058 {
1059 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1060 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1061 __le32 *val = range->data;
1062 u32 prph_val;
1063 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1064 le32_to_cpu(reg->dev_addr.offset);
1065 int i;
1066
1067 range->internal_base_addr = cpu_to_le32(addr);
1068 range->range_data_size = reg->dev_addr.size;
1069 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1070 prph_val = iwl_read_prph(fwrt->trans, addr + i);
1071 if (iwl_trans_is_hw_error_value(prph_val))
1072 return -EBUSY;
1073 *val++ = cpu_to_le32(prph_val);
1074 }
1075
1076 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1077 }
1078
1079 static int
iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1080 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
1081 struct iwl_dump_ini_region_data *reg_data,
1082 void *range_ptr, u32 range_len, int idx)
1083 {
1084 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1085 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1086 __le32 *val = range->data;
1087 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1;
1088 u32 indirect_rd_addr = WMAL_MRSPF_1;
1089 u32 prph_val;
1090 u32 addr = le32_to_cpu(reg->addrs[idx]);
1091 u32 dphy_state;
1092 u32 dphy_addr;
1093 int i;
1094
1095 range->internal_base_addr = cpu_to_le32(addr);
1096 range->range_data_size = reg->dev_addr.size;
1097
1098 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
1099 indirect_wr_addr = WMAL_INDRCT_CMD1;
1100
1101 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset);
1102 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset);
1103
1104 if (!iwl_trans_grab_nic_access(fwrt->trans))
1105 return -EBUSY;
1106
1107 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW :
1108 WFPM_LMAC1_PS_CTL_RW;
1109 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
1110
1111 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1112 if (dphy_state == HBUS_TIMEOUT ||
1113 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
1114 WFPM_PHYRF_STATE_ON) {
1115 *val++ = cpu_to_le32(WFPM_DPHY_OFF);
1116 continue;
1117 }
1118
1119 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr,
1120 WMAL_INDRCT_CMD(addr + i));
1121 prph_val = iwl_read_prph_no_grab(fwrt->trans,
1122 indirect_rd_addr);
1123 *val++ = cpu_to_le32(prph_val);
1124 }
1125
1126 iwl_trans_release_nic_access(fwrt->trans);
1127 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1128 }
1129
iwl_dump_ini_csr_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1130 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt,
1131 struct iwl_dump_ini_region_data *reg_data,
1132 void *range_ptr, u32 range_len, int idx)
1133 {
1134 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1135 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1136 __le32 *val = range->data;
1137 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1138 le32_to_cpu(reg->dev_addr.offset);
1139 int i;
1140
1141 range->internal_base_addr = cpu_to_le32(addr);
1142 range->range_data_size = reg->dev_addr.size;
1143 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)
1144 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i));
1145
1146 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1147 }
1148
iwl_dump_ini_config_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1149 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt,
1150 struct iwl_dump_ini_region_data *reg_data,
1151 void *range_ptr, u32 range_len, int idx)
1152 {
1153 struct iwl_trans *trans = fwrt->trans;
1154 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1155 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1156 __le32 *val = range->data;
1157 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1158 le32_to_cpu(reg->dev_addr.offset);
1159 int i;
1160
1161 /* we shouldn't get here if the trans doesn't have read_config32 */
1162 if (WARN_ON_ONCE(!trans->ops->read_config32))
1163 return -EOPNOTSUPP;
1164
1165 range->internal_base_addr = cpu_to_le32(addr);
1166 range->range_data_size = reg->dev_addr.size;
1167 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1168 int ret;
1169 u32 tmp;
1170
1171 ret = trans->ops->read_config32(trans, addr + i, &tmp);
1172 if (ret < 0)
1173 return ret;
1174
1175 *val++ = cpu_to_le32(tmp);
1176 }
1177
1178 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1179 }
1180
iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1181 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt,
1182 struct iwl_dump_ini_region_data *reg_data,
1183 void *range_ptr, u32 range_len, int idx)
1184 {
1185 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1186 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1187 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1188 le32_to_cpu(reg->dev_addr.offset);
1189
1190 range->internal_base_addr = cpu_to_le32(addr);
1191 range->range_data_size = reg->dev_addr.size;
1192 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1193 le32_to_cpu(reg->dev_addr.size));
1194
1195 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM &&
1196 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1197 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1198 range->data,
1199 le32_to_cpu(reg->dev_addr.size));
1200
1201 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1202 }
1203
_iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,void * range_ptr,u32 range_len,int idx)1204 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1205 void *range_ptr, u32 range_len, int idx)
1206 {
1207 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block;
1208 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1209 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys;
1210 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size;
1211
1212 range->page_num = cpu_to_le32(idx);
1213 range->range_data_size = cpu_to_le32(page_size);
1214 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size,
1215 DMA_BIDIRECTIONAL);
1216 memcpy(range->data, page_address(page), page_size);
1217 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size,
1218 DMA_BIDIRECTIONAL);
1219
1220 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1221 }
1222
iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1223 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1224 struct iwl_dump_ini_region_data *reg_data,
1225 void *range_ptr, u32 range_len, int idx)
1226 {
1227 struct iwl_fw_ini_error_dump_range *range;
1228 u32 page_size;
1229
1230 /* all paged index start from 1 to skip CSS section */
1231 idx++;
1232
1233 if (!fwrt->trans->trans_cfg->gen2)
1234 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx);
1235
1236 range = range_ptr;
1237 page_size = fwrt->trans->init_dram.paging[idx].size;
1238
1239 range->page_num = cpu_to_le32(idx);
1240 range->range_data_size = cpu_to_le32(page_size);
1241 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block,
1242 page_size);
1243
1244 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1245 }
1246
1247 static int
iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1248 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt,
1249 struct iwl_dump_ini_region_data *reg_data,
1250 void *range_ptr, u32 range_len, int idx)
1251 {
1252 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1253 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1254 struct iwl_dram_data *frag;
1255 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1256
1257 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx];
1258
1259 range->dram_base_addr = cpu_to_le64(frag->physical);
1260 range->range_data_size = cpu_to_le32(frag->size);
1261
1262 memcpy(range->data, frag->block, frag->size);
1263
1264 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1265 }
1266
iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1267 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt,
1268 struct iwl_dump_ini_region_data *reg_data,
1269 void *range_ptr, u32 range_len, int idx)
1270 {
1271 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1272 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1273 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr);
1274
1275 range->internal_base_addr = cpu_to_le32(addr);
1276 range->range_data_size = reg->internal_buffer.size;
1277 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1278 le32_to_cpu(reg->internal_buffer.size));
1279
1280 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1281 }
1282
iwl_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,int idx)1283 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1284 struct iwl_dump_ini_region_data *reg_data, int idx)
1285 {
1286 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1287 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1288 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
1289 int txf_num = cfg->num_txfifo_entries;
1290 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size);
1291 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);
1292
1293 if (!idx) {
1294 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) {
1295 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",
1296 le32_to_cpu(reg->fifos.offset));
1297 return false;
1298 }
1299
1300 iter->internal_txf = 0;
1301 iter->fifo_size = 0;
1302 iter->fifo = -1;
1303 if (le32_to_cpu(reg->fifos.offset))
1304 iter->lmac = 1;
1305 else
1306 iter->lmac = 0;
1307 }
1308
1309 if (!iter->internal_txf) {
1310 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) {
1311 iter->fifo_size =
1312 cfg->lmac[iter->lmac].txfifo_size[iter->fifo];
1313 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1314 return true;
1315 }
1316 iter->fifo--;
1317 }
1318
1319 iter->internal_txf = 1;
1320
1321 if (!fw_has_capa(&fwrt->fw->ucode_capa,
1322 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
1323 return false;
1324
1325 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) {
1326 iter->fifo_size =
1327 cfg->internal_txfifo_size[iter->fifo - txf_num];
1328 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1329 return true;
1330 }
1331
1332 return false;
1333 }
1334
iwl_dump_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1335 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1336 struct iwl_dump_ini_region_data *reg_data,
1337 void *range_ptr, u32 range_len, int idx)
1338 {
1339 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1340 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1341 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1342 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1343 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1344 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1345 u32 registers_size = registers_num * sizeof(*reg_dump);
1346 __le32 *data;
1347 int i;
1348
1349 if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
1350 return -EIO;
1351
1352 if (!iwl_trans_grab_nic_access(fwrt->trans))
1353 return -EBUSY;
1354
1355 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
1356 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1357 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
1358
1359 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
1360
1361 /*
1362 * read txf registers. for each register, write to the dump the
1363 * register address and its value
1364 */
1365 for (i = 0; i < registers_num; i++) {
1366 addr = le32_to_cpu(reg->addrs[i]) + offs;
1367
1368 reg_dump->addr = cpu_to_le32(addr);
1369 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1370 addr));
1371
1372 reg_dump++;
1373 }
1374
1375 if (reg->fifos.hdr_only) {
1376 range->range_data_size = cpu_to_le32(registers_size);
1377 goto out;
1378 }
1379
1380 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
1381 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
1382 TXF_WR_PTR + offs);
1383
1384 /* Dummy-read to advance the read pointer to the head */
1385 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
1386
1387 /* Read FIFO */
1388 addr = TXF_READ_MODIFY_DATA + offs;
1389 data = (void *)reg_dump;
1390 for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1391 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1392
1393 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1394 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1395 reg_dump, iter->fifo_size);
1396
1397 out:
1398 iwl_trans_release_nic_access(fwrt->trans);
1399
1400 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1401 }
1402
1403 struct iwl_ini_rxf_data {
1404 u32 fifo_num;
1405 u32 size;
1406 u32 offset;
1407 };
1408
iwl_ini_get_rxf_data(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,struct iwl_ini_rxf_data * data)1409 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
1410 struct iwl_dump_ini_region_data *reg_data,
1411 struct iwl_ini_rxf_data *data)
1412 {
1413 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1414 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);
1415 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]);
1416 u8 fifo_idx;
1417
1418 if (!data)
1419 return;
1420
1421 memset(data, 0, sizeof(*data));
1422
1423 /* make sure only one bit is set in only one fid */
1424 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1,
1425 "fid1=%x, fid2=%x\n", fid1, fid2))
1426 return;
1427
1428 if (fid1) {
1429 fifo_idx = ffs(fid1) - 1;
1430 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n",
1431 fifo_idx))
1432 return;
1433
1434 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size;
1435 data->fifo_num = fifo_idx;
1436 } else {
1437 u8 max_idx;
1438
1439 fifo_idx = ffs(fid2) - 1;
1440 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP,
1441 SHARED_MEM_CFG_CMD, 0) <= 3)
1442 max_idx = 0;
1443 else
1444 max_idx = 1;
1445
1446 if (WARN_ONCE(fifo_idx > max_idx,
1447 "invalid umac fifo idx %d", fifo_idx))
1448 return;
1449
1450 /* use bit 31 to distinguish between umac and lmac rxf while
1451 * parsing the dump
1452 */
1453 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT;
1454
1455 switch (fifo_idx) {
1456 case 0:
1457 data->size = fwrt->smem_cfg.rxfifo2_size;
1458 data->offset = iwl_umac_prph(fwrt->trans,
1459 RXF_DIFF_FROM_PREV);
1460 break;
1461 case 1:
1462 data->size = fwrt->smem_cfg.rxfifo2_control_size;
1463 data->offset = iwl_umac_prph(fwrt->trans,
1464 RXF2C_DIFF_FROM_PREV);
1465 break;
1466 }
1467 }
1468 }
1469
iwl_dump_ini_rxf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1470 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
1471 struct iwl_dump_ini_region_data *reg_data,
1472 void *range_ptr, u32 range_len, int idx)
1473 {
1474 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1475 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1476 struct iwl_ini_rxf_data rxf_data;
1477 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1478 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1479 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1480 u32 registers_size = registers_num * sizeof(*reg_dump);
1481 __le32 *data;
1482 int i;
1483
1484 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
1485 if (!rxf_data.size)
1486 return -EIO;
1487
1488 if (!iwl_trans_grab_nic_access(fwrt->trans))
1489 return -EBUSY;
1490
1491 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
1492 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1493 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size);
1494
1495 /*
1496 * read rxf registers. for each register, write to the dump the
1497 * register address and its value
1498 */
1499 for (i = 0; i < registers_num; i++) {
1500 addr = le32_to_cpu(reg->addrs[i]) + offs;
1501
1502 reg_dump->addr = cpu_to_le32(addr);
1503 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1504 addr));
1505
1506 reg_dump++;
1507 }
1508
1509 if (reg->fifos.hdr_only) {
1510 range->range_data_size = cpu_to_le32(registers_size);
1511 goto out;
1512 }
1513
1514 offs = rxf_data.offset;
1515
1516 /* Lock fence */
1517 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1518 /* Set fence pointer to the same place like WR pointer */
1519 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1520 /* Set fence offset */
1521 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs,
1522 0x0);
1523
1524 /* Read FIFO */
1525 addr = RXF_FIFO_RD_FENCE_INC + offs;
1526 data = (void *)reg_dump;
1527 for (i = 0; i < rxf_data.size; i += sizeof(*data))
1528 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1529
1530 out:
1531 iwl_trans_release_nic_access(fwrt->trans);
1532
1533 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1534 }
1535
1536 static int
iwl_dump_ini_err_table_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1537 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt,
1538 struct iwl_dump_ini_region_data *reg_data,
1539 void *range_ptr, u32 range_len, int idx)
1540 {
1541 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1542 struct iwl_fw_ini_region_err_table *err_table = ®->err_table;
1543 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1544 u32 addr = le32_to_cpu(err_table->base_addr) +
1545 le32_to_cpu(err_table->offset);
1546
1547 range->internal_base_addr = cpu_to_le32(addr);
1548 range->range_data_size = err_table->size;
1549 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1550 le32_to_cpu(err_table->size));
1551
1552 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1553 }
1554
1555 static int
iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1556 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt,
1557 struct iwl_dump_ini_region_data *reg_data,
1558 void *range_ptr, u32 range_len, int idx)
1559 {
1560 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1561 struct iwl_fw_ini_region_special_device_memory *special_mem =
1562 ®->special_mem;
1563
1564 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1565 u32 addr = le32_to_cpu(special_mem->base_addr) +
1566 le32_to_cpu(special_mem->offset);
1567
1568 range->internal_base_addr = cpu_to_le32(addr);
1569 range->range_data_size = special_mem->size;
1570 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1571 le32_to_cpu(special_mem->size));
1572
1573 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1574 }
1575
1576 static int
iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1577 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
1578 struct iwl_dump_ini_region_data *reg_data,
1579 void *range_ptr, u32 range_len, int idx)
1580 {
1581 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1582 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1583 __le32 *val = range->data;
1584 u32 prph_data;
1585 int i;
1586
1587 if (!iwl_trans_grab_nic_access(fwrt->trans))
1588 return -EBUSY;
1589
1590 range->range_data_size = reg->dev_addr.size;
1591 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
1592 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ?
1593 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
1594 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
1595 if (iwl_trans_is_hw_error_value(prph_data)) {
1596 iwl_trans_release_nic_access(fwrt->trans);
1597 return -EBUSY;
1598 }
1599 *val++ = cpu_to_le32(prph_data);
1600 }
1601 iwl_trans_release_nic_access(fwrt->trans);
1602 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1603 }
1604
iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1605 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt,
1606 struct iwl_dump_ini_region_data *reg_data,
1607 void *range_ptr, u32 range_len, int idx)
1608 {
1609 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1610 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt;
1611 u32 pkt_len;
1612
1613 if (!pkt)
1614 return -EIO;
1615
1616 pkt_len = iwl_rx_packet_payload_len(pkt);
1617
1618 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr));
1619 range->range_data_size = cpu_to_le32(pkt_len);
1620
1621 memcpy(range->data, pkt->data, pkt_len);
1622
1623 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1624 }
1625
iwl_dump_ini_imr_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1626 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt,
1627 struct iwl_dump_ini_region_data *reg_data,
1628 void *range_ptr, u32 range_len, int idx)
1629 {
1630 /* read the IMR memory and DMA it to SRAM */
1631 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1632 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr;
1633 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte;
1634 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr;
1635 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
1636 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes;
1637
1638 range->range_data_size = cpu_to_le32(size_to_dump);
1639 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr,
1640 imr_curr_addr, size_to_dump)) {
1641 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n");
1642 return -1;
1643 }
1644
1645 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump;
1646 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump;
1647
1648 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data,
1649 size_to_dump);
1650 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1651 }
1652
1653 static void *
iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1654 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt,
1655 struct iwl_dump_ini_region_data *reg_data,
1656 void *data, u32 data_len)
1657 {
1658 struct iwl_fw_ini_error_dump *dump = data;
1659
1660 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1661
1662 return dump->data;
1663 }
1664
1665 /**
1666 * mask_apply_and_normalize - applies mask on val and normalize the result
1667 *
1668 * The normalization is based on the first set bit in the mask
1669 *
1670 * @val: value
1671 * @mask: mask to apply and to normalize with
1672 */
mask_apply_and_normalize(u32 val,u32 mask)1673 static u32 mask_apply_and_normalize(u32 val, u32 mask)
1674 {
1675 return (val & mask) >> (ffs(mask) - 1);
1676 }
1677
iwl_get_mon_reg(struct iwl_fw_runtime * fwrt,u32 alloc_id,const struct iwl_fw_mon_reg * reg_info)1678 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1679 const struct iwl_fw_mon_reg *reg_info)
1680 {
1681 u32 val, offs;
1682
1683 /* The header addresses of DBGCi is calculate as follows:
1684 * DBGC1 address + (0x100 * i)
1685 */
1686 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;
1687
1688 if (!reg_info || !reg_info->addr || !reg_info->mask)
1689 return 0;
1690
1691 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs);
1692
1693 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask));
1694 }
1695
1696 static void *
iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime * fwrt,u32 alloc_id,struct iwl_fw_ini_monitor_dump * data,const struct iwl_fw_mon_regs * addrs)1697 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1698 struct iwl_fw_ini_monitor_dump *data,
1699 const struct iwl_fw_mon_regs *addrs)
1700 {
1701 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
1702 IWL_ERR(fwrt, "Failed to get monitor header\n");
1703 return NULL;
1704 }
1705
1706 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id,
1707 &addrs->write_ptr);
1708 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1709 u32 wrt_ptr = le32_to_cpu(data->write_ptr);
1710
1711 data->write_ptr = cpu_to_le32(wrt_ptr >> 2);
1712 }
1713 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id,
1714 &addrs->cycle_cnt);
1715 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
1716 &addrs->cur_frag);
1717
1718 iwl_trans_release_nic_access(fwrt->trans);
1719
1720 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1721
1722 return data->data;
1723 }
1724
1725 static void *
iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1726 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt,
1727 struct iwl_dump_ini_region_data *reg_data,
1728 void *data, u32 data_len)
1729 {
1730 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1731 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1732 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1733
1734 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump,
1735 &fwrt->trans->cfg->mon_dram_regs);
1736 }
1737
1738 static void *
iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1739 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt,
1740 struct iwl_dump_ini_region_data *reg_data,
1741 void *data, u32 data_len)
1742 {
1743 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1744 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1745 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id);
1746
1747 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump,
1748 &fwrt->trans->cfg->mon_smem_regs);
1749 }
1750
1751 static void *
iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1752 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt,
1753 struct iwl_dump_ini_region_data *reg_data,
1754 void *data, u32 data_len)
1755 {
1756 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1757
1758 return iwl_dump_ini_mon_fill_header(fwrt,
1759 /* no offset calculation later */
1760 IWL_FW_INI_ALLOCATION_ID_DBGC1,
1761 mon_dump,
1762 &fwrt->trans->cfg->mon_dbgi_regs);
1763 }
1764
1765 static void *
iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1766 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt,
1767 struct iwl_dump_ini_region_data *reg_data,
1768 void *data, u32 data_len)
1769 {
1770 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1771 struct iwl_fw_ini_err_table_dump *dump = data;
1772
1773 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1774 dump->version = reg->err_table.version;
1775
1776 return dump->data;
1777 }
1778
1779 static void *
iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1780 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt,
1781 struct iwl_dump_ini_region_data *reg_data,
1782 void *data, u32 data_len)
1783 {
1784 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1785 struct iwl_fw_ini_special_device_memory *dump = data;
1786
1787 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1788 dump->type = reg->special_mem.type;
1789 dump->version = reg->special_mem.version;
1790
1791 return dump->data;
1792 }
1793
1794 static void *
iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1795 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt,
1796 struct iwl_dump_ini_region_data *reg_data,
1797 void *data, u32 data_len)
1798 {
1799 struct iwl_fw_ini_error_dump *dump = data;
1800
1801 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1802
1803 return dump->data;
1804 }
1805
iwl_dump_ini_mem_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1806 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt,
1807 struct iwl_dump_ini_region_data *reg_data)
1808 {
1809 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1810
1811 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1812 }
1813
iwl_dump_ini_paging_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1814 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt,
1815 struct iwl_dump_ini_region_data *reg_data)
1816 {
1817 if (fwrt->trans->trans_cfg->gen2) {
1818 if (fwrt->trans->init_dram.paging_cnt)
1819 return fwrt->trans->init_dram.paging_cnt - 1;
1820 else
1821 return 0;
1822 }
1823
1824 return fwrt->num_of_paging_blk;
1825 }
1826
1827 static u32
iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1828 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt,
1829 struct iwl_dump_ini_region_data *reg_data)
1830 {
1831 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1832 struct iwl_fw_mon *fw_mon;
1833 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1834 int i;
1835
1836 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1837
1838 for (i = 0; i < fw_mon->num_frags; i++) {
1839 if (!fw_mon->frags[i].size)
1840 break;
1841
1842 ranges++;
1843 }
1844
1845 return ranges;
1846 }
1847
iwl_dump_ini_txf_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1848 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt,
1849 struct iwl_dump_ini_region_data *reg_data)
1850 {
1851 u32 num_of_fifos = 0;
1852
1853 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos))
1854 num_of_fifos++;
1855
1856 return num_of_fifos;
1857 }
1858
iwl_dump_ini_single_range(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1859 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt,
1860 struct iwl_dump_ini_region_data *reg_data)
1861 {
1862 return 1;
1863 }
1864
iwl_dump_ini_imr_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1865 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt,
1866 struct iwl_dump_ini_region_data *reg_data)
1867 {
1868 /* range is total number of pages need to copied from
1869 *IMR memory to SRAM and later from SRAM to DRAM
1870 */
1871 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable;
1872 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size;
1873 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
1874
1875 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
1876 IWL_DEBUG_INFO(fwrt,
1877 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n",
1878 imr_enable, imr_size, sram_size);
1879 return 0;
1880 }
1881
1882 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size));
1883 }
1884
iwl_dump_ini_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1885 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt,
1886 struct iwl_dump_ini_region_data *reg_data)
1887 {
1888 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1889 u32 size = le32_to_cpu(reg->dev_addr.size);
1890 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
1891
1892 if (!size || !ranges)
1893 return 0;
1894
1895 return sizeof(struct iwl_fw_ini_error_dump) + ranges *
1896 (size + sizeof(struct iwl_fw_ini_error_dump_range));
1897 }
1898
1899 static u32
iwl_dump_ini_paging_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1900 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt,
1901 struct iwl_dump_ini_region_data *reg_data)
1902 {
1903 int i;
1904 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
1905 u32 size = sizeof(struct iwl_fw_ini_error_dump);
1906
1907 /* start from 1 to skip CSS section */
1908 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) {
1909 size += range_header_len;
1910 if (fwrt->trans->trans_cfg->gen2)
1911 size += fwrt->trans->init_dram.paging[i].size;
1912 else
1913 size += fwrt->fw_paging_db[i].fw_paging_size;
1914 }
1915
1916 return size;
1917 }
1918
1919 static u32
iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1920 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt,
1921 struct iwl_dump_ini_region_data *reg_data)
1922 {
1923 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1924 struct iwl_fw_mon *fw_mon;
1925 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1926 int i;
1927
1928 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1929
1930 for (i = 0; i < fw_mon->num_frags; i++) {
1931 struct iwl_dram_data *frag = &fw_mon->frags[i];
1932
1933 if (!frag->size)
1934 break;
1935
1936 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size;
1937 }
1938
1939 if (size)
1940 size += sizeof(struct iwl_fw_ini_monitor_dump);
1941
1942 return size;
1943 }
1944
1945 static u32
iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1946 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt,
1947 struct iwl_dump_ini_region_data *reg_data)
1948 {
1949 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1950 u32 size;
1951
1952 size = le32_to_cpu(reg->internal_buffer.size);
1953 if (!size)
1954 return 0;
1955
1956 size += sizeof(struct iwl_fw_ini_monitor_dump) +
1957 sizeof(struct iwl_fw_ini_error_dump_range);
1958
1959 return size;
1960 }
1961
iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1962 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt,
1963 struct iwl_dump_ini_region_data *reg_data)
1964 {
1965 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1966 u32 size = le32_to_cpu(reg->dev_addr.size);
1967 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
1968
1969 if (!size || !ranges)
1970 return 0;
1971
1972 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges *
1973 (size + sizeof(struct iwl_fw_ini_error_dump_range));
1974 }
1975
iwl_dump_ini_txf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1976 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt,
1977 struct iwl_dump_ini_region_data *reg_data)
1978 {
1979 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1980 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1981 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1982 u32 size = 0;
1983 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) +
1984 registers_num *
1985 sizeof(struct iwl_fw_ini_error_dump_register);
1986
1987 while (iwl_ini_txf_iter(fwrt, reg_data, size)) {
1988 size += fifo_hdr;
1989 if (!reg->fifos.hdr_only)
1990 size += iter->fifo_size;
1991 }
1992
1993 if (!size)
1994 return 0;
1995
1996 return size + sizeof(struct iwl_fw_ini_error_dump);
1997 }
1998
iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1999 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt,
2000 struct iwl_dump_ini_region_data *reg_data)
2001 {
2002 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2003 struct iwl_ini_rxf_data rx_data;
2004 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
2005 u32 size = sizeof(struct iwl_fw_ini_error_dump) +
2006 sizeof(struct iwl_fw_ini_error_dump_range) +
2007 registers_num * sizeof(struct iwl_fw_ini_error_dump_register);
2008
2009 if (reg->fifos.hdr_only)
2010 return size;
2011
2012 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data);
2013 size += rx_data.size;
2014
2015 return size;
2016 }
2017
2018 static u32
iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2019 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt,
2020 struct iwl_dump_ini_region_data *reg_data)
2021 {
2022 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2023 u32 size = le32_to_cpu(reg->err_table.size);
2024
2025 if (size)
2026 size += sizeof(struct iwl_fw_ini_err_table_dump) +
2027 sizeof(struct iwl_fw_ini_error_dump_range);
2028
2029 return size;
2030 }
2031
2032 static u32
iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2033 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt,
2034 struct iwl_dump_ini_region_data *reg_data)
2035 {
2036 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2037 u32 size = le32_to_cpu(reg->special_mem.size);
2038
2039 if (size)
2040 size += sizeof(struct iwl_fw_ini_special_device_memory) +
2041 sizeof(struct iwl_fw_ini_error_dump_range);
2042
2043 return size;
2044 }
2045
2046 static u32
iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2047 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt,
2048 struct iwl_dump_ini_region_data *reg_data)
2049 {
2050 u32 size = 0;
2051
2052 if (!reg_data->dump_data->fw_pkt)
2053 return 0;
2054
2055 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt);
2056 if (size)
2057 size += sizeof(struct iwl_fw_ini_error_dump) +
2058 sizeof(struct iwl_fw_ini_error_dump_range);
2059
2060 return size;
2061 }
2062
2063 static u32
iwl_dump_ini_imr_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2064 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt,
2065 struct iwl_dump_ini_region_data *reg_data)
2066 {
2067 u32 ranges = 0;
2068 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable;
2069 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size;
2070 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
2071
2072 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
2073 IWL_DEBUG_INFO(fwrt,
2074 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n",
2075 imr_enable, imr_size, sram_size);
2076 return 0;
2077 }
2078 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data);
2079 if (!ranges) {
2080 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges);
2081 return 0;
2082 }
2083 imr_size += sizeof(struct iwl_fw_ini_error_dump) +
2084 ranges * sizeof(struct iwl_fw_ini_error_dump_range);
2085 return imr_size;
2086 }
2087
2088 /**
2089 * struct iwl_dump_ini_mem_ops - ini memory dump operations
2090 * @get_num_of_ranges: returns the number of memory ranges in the region.
2091 * @get_size: returns the total size of the region.
2092 * @fill_mem_hdr: fills region type specific headers and returns pointer to
2093 * the first range or NULL if failed to fill headers.
2094 * @fill_range: copies a given memory range into the dump.
2095 * Returns the size of the range or negative error value otherwise.
2096 */
2097 struct iwl_dump_ini_mem_ops {
2098 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt,
2099 struct iwl_dump_ini_region_data *reg_data);
2100 u32 (*get_size)(struct iwl_fw_runtime *fwrt,
2101 struct iwl_dump_ini_region_data *reg_data);
2102 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt,
2103 struct iwl_dump_ini_region_data *reg_data,
2104 void *data, u32 data_len);
2105 int (*fill_range)(struct iwl_fw_runtime *fwrt,
2106 struct iwl_dump_ini_region_data *reg_data,
2107 void *range, u32 range_len, int idx);
2108 };
2109
2110 /**
2111 * iwl_dump_ini_mem
2112 *
2113 * Creates a dump tlv and copy a memory region into it.
2114 * Returns the size of the current dump tlv or 0 if failed
2115 *
2116 * @fwrt: fw runtime struct
2117 * @list: list to add the dump tlv to
2118 * @reg_data: memory region
2119 * @ops: memory dump operations
2120 */
iwl_dump_ini_mem(struct iwl_fw_runtime * fwrt,struct list_head * list,struct iwl_dump_ini_region_data * reg_data,const struct iwl_dump_ini_mem_ops * ops)2121 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list,
2122 struct iwl_dump_ini_region_data *reg_data,
2123 const struct iwl_dump_ini_mem_ops *ops)
2124 {
2125 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2126 struct iwl_fw_ini_dump_entry *entry;
2127 struct iwl_fw_ini_error_dump_data *tlv;
2128 struct iwl_fw_ini_error_dump_header *header;
2129 u32 type = reg->type;
2130 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK);
2131 u32 num_of_ranges, i, size;
2132 u8 *range;
2133 u32 free_size;
2134 u64 header_size;
2135 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE;
2136
2137 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n",
2138 dump_policy, id, type);
2139
2140 if (le32_to_cpu(reg->hdr.version) >= 2) {
2141 u32 dp = le32_get_bits(reg->id,
2142 IWL_FW_INI_REGION_DUMP_POLICY_MASK);
2143
2144 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE &&
2145 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) {
2146 IWL_DEBUG_FW(fwrt,
2147 "WRT: no dump - type %d and policy mismatch=%d\n",
2148 dump_policy, dp);
2149 return 0;
2150 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM &&
2151 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) {
2152 IWL_DEBUG_FW(fwrt,
2153 "WRT: no dump - type %d and policy mismatch=%d\n",
2154 dump_policy, dp);
2155 return 0;
2156 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF &&
2157 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) {
2158 IWL_DEBUG_FW(fwrt,
2159 "WRT: no dump - type %d and policy mismatch=%d\n",
2160 dump_policy, dp);
2161 return 0;
2162 }
2163 }
2164
2165 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr ||
2166 !ops->fill_range) {
2167 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n");
2168 return 0;
2169 }
2170
2171 size = ops->get_size(fwrt, reg_data);
2172
2173 if (size < sizeof(*header)) {
2174 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n");
2175 return 0;
2176 }
2177
2178 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size);
2179 if (!entry)
2180 return 0;
2181
2182 entry->size = sizeof(*tlv) + size;
2183
2184 tlv = (void *)entry->data;
2185 tlv->type = reg->type;
2186 tlv->sub_type = reg->sub_type;
2187 tlv->sub_type_ver = reg->sub_type_ver;
2188 tlv->reserved = reg->reserved;
2189 tlv->len = cpu_to_le32(size);
2190
2191 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data);
2192
2193 header = (void *)tlv->data;
2194 header->region_id = cpu_to_le32(id);
2195 header->num_of_ranges = cpu_to_le32(num_of_ranges);
2196 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME);
2197 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME);
2198
2199 free_size = size;
2200 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size);
2201 if (!range) {
2202 IWL_ERR(fwrt,
2203 "WRT: Failed to fill region header: id=%d, type=%d\n",
2204 id, type);
2205 goto out_err;
2206 }
2207
2208 header_size = range - (u8 *)header;
2209
2210 if (WARN(header_size > free_size,
2211 "header size %llu > free_size %d",
2212 header_size, free_size)) {
2213 IWL_ERR(fwrt,
2214 "WRT: fill_mem_hdr used more than given free_size\n");
2215 goto out_err;
2216 }
2217
2218 free_size -= header_size;
2219
2220 for (i = 0; i < num_of_ranges; i++) {
2221 int range_size = ops->fill_range(fwrt, reg_data, range,
2222 free_size, i);
2223
2224 if (range_size < 0) {
2225 IWL_ERR(fwrt,
2226 "WRT: Failed to dump region: id=%d, type=%d\n",
2227 id, type);
2228 goto out_err;
2229 }
2230
2231 if (WARN(range_size > free_size, "range_size %d > free_size %d",
2232 range_size, free_size)) {
2233 IWL_ERR(fwrt,
2234 "WRT: fill_raged used more than given free_size\n");
2235 goto out_err;
2236 }
2237
2238 free_size -= range_size;
2239 range = range + range_size;
2240 }
2241
2242 list_add_tail(&entry->list, list);
2243
2244 return entry->size;
2245
2246 out_err:
2247 vfree(entry);
2248
2249 return 0;
2250 }
2251
iwl_dump_ini_info(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trigger,struct list_head * list)2252 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
2253 struct iwl_fw_ini_trigger_tlv *trigger,
2254 struct list_head *list)
2255 {
2256 struct iwl_fw_ini_dump_entry *entry;
2257 struct iwl_fw_error_dump_data *tlv;
2258 struct iwl_fw_ini_dump_info *dump;
2259 struct iwl_dbg_tlv_node *node;
2260 struct iwl_fw_ini_dump_cfg_name *cfg_name;
2261 u32 size = sizeof(*tlv) + sizeof(*dump);
2262 u32 num_of_cfg_names = 0;
2263 u32 hw_type;
2264
2265 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2266 size += sizeof(*cfg_name);
2267 num_of_cfg_names++;
2268 }
2269
2270 entry = vzalloc(sizeof(*entry) + size);
2271 if (!entry)
2272 return 0;
2273
2274 entry->size = size;
2275
2276 tlv = (void *)entry->data;
2277 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE);
2278 tlv->len = cpu_to_le32(size - sizeof(*tlv));
2279
2280 dump = (void *)tlv->data;
2281
2282 dump->version = cpu_to_le32(IWL_INI_DUMP_VER);
2283 dump->time_point = trigger->time_point;
2284 dump->trigger_reason = trigger->trigger_reason;
2285 dump->external_cfg_state =
2286 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg);
2287
2288 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
2289 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);
2290
2291 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step);
2292
2293 /*
2294 * Several HWs all have type == 0x42, so we'll override this value
2295 * according to the detected HW
2296 */
2297 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev);
2298 if (hw_type == IWL_AX210_HW_TYPE) {
2299 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR);
2300 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT);
2301 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT);
2302 u32 masked_bits = is_jacket | (is_cdb << 1);
2303
2304 /*
2305 * The HW type depends on certain bits in this case, so add
2306 * these bits to the HW type. We won't have collisions since we
2307 * add these bits after the highest possible bit in the mask.
2308 */
2309 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT;
2310 }
2311 dump->hw_type = cpu_to_le32(hw_type);
2312
2313 dump->rf_id_flavor =
2314 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id));
2315 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id));
2316 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id));
2317 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id));
2318
2319 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major);
2320 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor);
2321 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major);
2322 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
2323
2324 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest);
2325 dump->regions_mask = trigger->regions_mask &
2326 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk);
2327
2328 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
2329 memcpy(dump->build_tag, fwrt->fw->human_readable,
2330 sizeof(dump->build_tag));
2331
2332 cfg_name = dump->cfg_names;
2333 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names);
2334 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2335 struct iwl_fw_ini_debug_info_tlv *debug_info =
2336 (void *)node->tlv.data;
2337
2338 cfg_name->image_type = debug_info->image_type;
2339 cfg_name->cfg_name_len =
2340 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME);
2341 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name,
2342 sizeof(cfg_name->cfg_name));
2343 cfg_name++;
2344 }
2345
2346 /* add dump info TLV to the beginning of the list since it needs to be
2347 * the first TLV in the dump
2348 */
2349 list_add(&entry->list, list);
2350
2351 return entry->size;
2352 }
2353
iwl_dump_ini_file_name_info(struct iwl_fw_runtime * fwrt,struct list_head * list)2354 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt,
2355 struct list_head *list)
2356 {
2357 struct iwl_fw_ini_dump_entry *entry;
2358 struct iwl_dump_file_name_info *tlv;
2359 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext,
2360 IWL_FW_INI_MAX_NAME);
2361
2362 if (!fwrt->trans->dbg.dump_file_name_ext_valid)
2363 return 0;
2364
2365 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len);
2366 if (!entry)
2367 return 0;
2368
2369 entry->size = sizeof(*tlv) + len;
2370
2371 tlv = (void *)entry->data;
2372 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE);
2373 tlv->len = cpu_to_le32(len);
2374 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len);
2375
2376 /* add the dump file name extension tlv to the list */
2377 list_add_tail(&entry->list, list);
2378
2379 fwrt->trans->dbg.dump_file_name_ext_valid = false;
2380
2381 return entry->size;
2382 }
2383
2384 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
2385 [IWL_FW_INI_REGION_INVALID] = {},
2386 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = {
2387 .get_num_of_ranges = iwl_dump_ini_single_range,
2388 .get_size = iwl_dump_ini_mon_smem_get_size,
2389 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header,
2390 .fill_range = iwl_dump_ini_mon_smem_iter,
2391 },
2392 [IWL_FW_INI_REGION_DRAM_BUFFER] = {
2393 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges,
2394 .get_size = iwl_dump_ini_mon_dram_get_size,
2395 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header,
2396 .fill_range = iwl_dump_ini_mon_dram_iter,
2397 },
2398 [IWL_FW_INI_REGION_TXF] = {
2399 .get_num_of_ranges = iwl_dump_ini_txf_ranges,
2400 .get_size = iwl_dump_ini_txf_get_size,
2401 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2402 .fill_range = iwl_dump_ini_txf_iter,
2403 },
2404 [IWL_FW_INI_REGION_RXF] = {
2405 .get_num_of_ranges = iwl_dump_ini_single_range,
2406 .get_size = iwl_dump_ini_rxf_get_size,
2407 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2408 .fill_range = iwl_dump_ini_rxf_iter,
2409 },
2410 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = {
2411 .get_num_of_ranges = iwl_dump_ini_single_range,
2412 .get_size = iwl_dump_ini_err_table_get_size,
2413 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2414 .fill_range = iwl_dump_ini_err_table_iter,
2415 },
2416 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = {
2417 .get_num_of_ranges = iwl_dump_ini_single_range,
2418 .get_size = iwl_dump_ini_err_table_get_size,
2419 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2420 .fill_range = iwl_dump_ini_err_table_iter,
2421 },
2422 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = {
2423 .get_num_of_ranges = iwl_dump_ini_single_range,
2424 .get_size = iwl_dump_ini_fw_pkt_get_size,
2425 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2426 .fill_range = iwl_dump_ini_fw_pkt_iter,
2427 },
2428 [IWL_FW_INI_REGION_DEVICE_MEMORY] = {
2429 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2430 .get_size = iwl_dump_ini_mem_get_size,
2431 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2432 .fill_range = iwl_dump_ini_dev_mem_iter,
2433 },
2434 [IWL_FW_INI_REGION_PERIPHERY_MAC] = {
2435 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2436 .get_size = iwl_dump_ini_mem_get_size,
2437 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2438 .fill_range = iwl_dump_ini_prph_mac_iter,
2439 },
2440 [IWL_FW_INI_REGION_PERIPHERY_PHY] = {
2441 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2442 .get_size = iwl_dump_ini_mem_get_size,
2443 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2444 .fill_range = iwl_dump_ini_prph_phy_iter,
2445 },
2446 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {},
2447 [IWL_FW_INI_REGION_PAGING] = {
2448 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2449 .get_num_of_ranges = iwl_dump_ini_paging_ranges,
2450 .get_size = iwl_dump_ini_paging_get_size,
2451 .fill_range = iwl_dump_ini_paging_iter,
2452 },
2453 [IWL_FW_INI_REGION_CSR] = {
2454 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2455 .get_size = iwl_dump_ini_mem_get_size,
2456 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2457 .fill_range = iwl_dump_ini_csr_iter,
2458 },
2459 [IWL_FW_INI_REGION_DRAM_IMR] = {
2460 .get_num_of_ranges = iwl_dump_ini_imr_ranges,
2461 .get_size = iwl_dump_ini_imr_get_size,
2462 .fill_mem_hdr = iwl_dump_ini_imr_fill_header,
2463 .fill_range = iwl_dump_ini_imr_iter,
2464 },
2465 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = {
2466 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2467 .get_size = iwl_dump_ini_mem_get_size,
2468 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2469 .fill_range = iwl_dump_ini_config_iter,
2470 },
2471 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = {
2472 .get_num_of_ranges = iwl_dump_ini_single_range,
2473 .get_size = iwl_dump_ini_special_mem_get_size,
2474 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header,
2475 .fill_range = iwl_dump_ini_special_mem_iter,
2476 },
2477 [IWL_FW_INI_REGION_DBGI_SRAM] = {
2478 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2479 .get_size = iwl_dump_ini_mon_dbgi_get_size,
2480 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header,
2481 .fill_range = iwl_dump_ini_dbgi_sram_iter,
2482 },
2483 };
2484
iwl_dump_ini_trigger(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2485 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
2486 struct iwl_fwrt_dump_data *dump_data,
2487 struct list_head *list)
2488 {
2489 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2490 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point);
2491 struct iwl_dump_ini_region_data reg_data = {
2492 .dump_data = dump_data,
2493 };
2494 struct iwl_dump_ini_region_data imr_reg_data = {
2495 .dump_data = dump_data,
2496 };
2497 int i;
2498 u32 size = 0;
2499 u64 regions_mask = le64_to_cpu(trigger->regions_mask) &
2500 ~(fwrt->trans->dbg.unsupported_region_msk);
2501
2502 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask));
2503 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) <
2504 ARRAY_SIZE(fwrt->trans->dbg.active_regions));
2505
2506 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {
2507 u32 reg_type;
2508 struct iwl_fw_ini_region_tlv *reg;
2509
2510 if (!(BIT_ULL(i) & regions_mask))
2511 continue;
2512
2513 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2514 if (!reg_data.reg_tlv) {
2515 IWL_WARN(fwrt,
2516 "WRT: Unassigned region id %d, skipping\n", i);
2517 continue;
2518 }
2519
2520 reg = (void *)reg_data.reg_tlv->data;
2521 reg_type = reg->type;
2522 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops))
2523 continue;
2524
2525 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY &&
2526 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) {
2527 IWL_WARN(fwrt,
2528 "WRT: trying to collect phy prph at time point: %d, skipping\n",
2529 tp_id);
2530 continue;
2531 }
2532 /*
2533 * DRAM_IMR can be collected only for FW/HW error timepoint
2534 * when fw is not alive. In addition, it must be collected
2535 * lastly as it overwrites SRAM that can possibly contain
2536 * debug data which also need to be collected.
2537 */
2538 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) {
2539 if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT ||
2540 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR)
2541 imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2542 else
2543 IWL_INFO(fwrt,
2544 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n",
2545 tp_id);
2546 /* continue to next region */
2547 continue;
2548 }
2549
2550
2551 size += iwl_dump_ini_mem(fwrt, list, ®_data,
2552 &iwl_dump_ini_region_ops[reg_type]);
2553 }
2554 /* collect DRAM_IMR region in the last */
2555 if (imr_reg_data.reg_tlv)
2556 size += iwl_dump_ini_mem(fwrt, list, ®_data,
2557 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]);
2558
2559 if (size) {
2560 size += iwl_dump_ini_file_name_info(fwrt, list);
2561 size += iwl_dump_ini_info(fwrt, trigger, list);
2562 }
2563
2564 return size;
2565 }
2566
iwl_fw_ini_trigger_on(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trig)2567 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt,
2568 struct iwl_fw_ini_trigger_tlv *trig)
2569 {
2570 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2571 u32 usec = le32_to_cpu(trig->ignore_consec);
2572
2573 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
2574 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
2575 tp_id >= IWL_FW_INI_TIME_POINT_NUM ||
2576 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec))
2577 return false;
2578
2579 return true;
2580 }
2581
iwl_dump_ini_file_gen(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2582 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt,
2583 struct iwl_fwrt_dump_data *dump_data,
2584 struct list_head *list)
2585 {
2586 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2587 struct iwl_fw_ini_dump_entry *entry;
2588 struct iwl_fw_ini_dump_file_hdr *hdr;
2589 u32 size;
2590
2591 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) ||
2592 !le64_to_cpu(trigger->regions_mask))
2593 return 0;
2594
2595 entry = vzalloc(sizeof(*entry) + sizeof(*hdr));
2596 if (!entry)
2597 return 0;
2598
2599 entry->size = sizeof(*hdr);
2600
2601 size = iwl_dump_ini_trigger(fwrt, dump_data, list);
2602 if (!size) {
2603 vfree(entry);
2604 return 0;
2605 }
2606
2607 hdr = (void *)entry->data;
2608 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER);
2609 hdr->file_len = cpu_to_le32(size + entry->size);
2610
2611 list_add(&entry->list, list);
2612
2613 return le32_to_cpu(hdr->file_len);
2614 }
2615
iwl_fw_free_dump_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc)2616 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt,
2617 const struct iwl_fw_dump_desc *desc)
2618 {
2619 if (desc && desc != &iwl_dump_desc_assert)
2620 kfree(desc);
2621
2622 fwrt->dump.lmac_err_id[0] = 0;
2623 if (fwrt->smem_cfg.num_lmacs > 1)
2624 fwrt->dump.lmac_err_id[1] = 0;
2625 fwrt->dump.umac_err_id = 0;
2626 }
2627
iwl_fw_error_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2628 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
2629 struct iwl_fwrt_dump_data *dump_data)
2630 {
2631 struct iwl_fw_dump_ptrs fw_error_dump = {};
2632 struct iwl_fw_error_dump_file *dump_file;
2633 struct scatterlist *sg_dump_data;
2634 u32 file_len;
2635 u32 dump_mask = fwrt->fw->dbg.dump_mask;
2636
2637 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data);
2638 if (!dump_file)
2639 return;
2640
2641 if (dump_data->monitor_only)
2642 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR);
2643
2644 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask,
2645 fwrt->sanitize_ops,
2646 fwrt->sanitize_ctx);
2647 file_len = le32_to_cpu(dump_file->file_len);
2648 fw_error_dump.fwrt_len = file_len;
2649
2650 if (fw_error_dump.trans_ptr) {
2651 file_len += fw_error_dump.trans_ptr->len;
2652 dump_file->file_len = cpu_to_le32(file_len);
2653 }
2654
2655 sg_dump_data = alloc_sgtable(file_len);
2656 if (sg_dump_data) {
2657 sg_pcopy_from_buffer(sg_dump_data,
2658 sg_nents(sg_dump_data),
2659 fw_error_dump.fwrt_ptr,
2660 fw_error_dump.fwrt_len, 0);
2661 if (fw_error_dump.trans_ptr)
2662 sg_pcopy_from_buffer(sg_dump_data,
2663 sg_nents(sg_dump_data),
2664 fw_error_dump.trans_ptr->data,
2665 fw_error_dump.trans_ptr->len,
2666 fw_error_dump.fwrt_len);
2667 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2668 GFP_KERNEL);
2669 }
2670 vfree(fw_error_dump.fwrt_ptr);
2671 vfree(fw_error_dump.trans_ptr);
2672 }
2673
iwl_dump_ini_list_free(struct list_head * list)2674 static void iwl_dump_ini_list_free(struct list_head *list)
2675 {
2676 while (!list_empty(list)) {
2677 struct iwl_fw_ini_dump_entry *entry =
2678 list_entry(list->next, typeof(*entry), list);
2679
2680 list_del(&entry->list);
2681 vfree(entry);
2682 }
2683 }
2684
iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data * dump_data)2685 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data)
2686 {
2687 dump_data->trig = NULL;
2688 kfree(dump_data->fw_pkt);
2689 dump_data->fw_pkt = NULL;
2690 }
2691
iwl_fw_error_ini_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2692 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt,
2693 struct iwl_fwrt_dump_data *dump_data)
2694 {
2695 LIST_HEAD(dump_list);
2696 struct scatterlist *sg_dump_data;
2697 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list);
2698
2699 if (!file_len)
2700 return;
2701
2702 sg_dump_data = alloc_sgtable(file_len);
2703 if (sg_dump_data) {
2704 struct iwl_fw_ini_dump_entry *entry;
2705 int sg_entries = sg_nents(sg_dump_data);
2706 u32 offs = 0;
2707
2708 list_for_each_entry(entry, &dump_list, list) {
2709 sg_pcopy_from_buffer(sg_dump_data, sg_entries,
2710 entry->data, entry->size, offs);
2711 offs += entry->size;
2712 }
2713 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2714 GFP_KERNEL);
2715 }
2716 iwl_dump_ini_list_free(&dump_list);
2717 }
2718
2719 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
2720 .trig_desc = {
2721 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
2722 },
2723 };
2724 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
2725
iwl_fw_dbg_collect_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc,bool monitor_only,unsigned int delay)2726 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
2727 const struct iwl_fw_dump_desc *desc,
2728 bool monitor_only,
2729 unsigned int delay)
2730 {
2731 struct iwl_fwrt_wk_data *wk_data;
2732 unsigned long idx;
2733
2734 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2735 iwl_fw_free_dump_desc(fwrt, desc);
2736 return 0;
2737 }
2738
2739 /*
2740 * Check there is an available worker.
2741 * ffz return value is undefined if no zero exists,
2742 * so check against ~0UL first.
2743 */
2744 if (fwrt->dump.active_wks == ~0UL)
2745 return -EBUSY;
2746
2747 idx = ffz(fwrt->dump.active_wks);
2748
2749 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2750 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2751 return -EBUSY;
2752
2753 wk_data = &fwrt->dump.wks[idx];
2754
2755 if (WARN_ON(wk_data->dump_data.desc))
2756 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc);
2757
2758 wk_data->dump_data.desc = desc;
2759 wk_data->dump_data.monitor_only = monitor_only;
2760
2761 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
2762 le32_to_cpu(desc->trig_desc.type));
2763
2764 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay));
2765
2766 return 0;
2767 }
2768 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
2769
iwl_fw_dbg_error_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig_type)2770 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
2771 enum iwl_fw_dbg_trigger trig_type)
2772 {
2773 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status))
2774 return -EIO;
2775
2776 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2777 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT &&
2778 trig_type != FW_DBG_TRIGGER_DRIVER)
2779 return -EIO;
2780
2781 iwl_dbg_tlv_time_point(fwrt,
2782 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT,
2783 NULL);
2784 } else {
2785 struct iwl_fw_dump_desc *iwl_dump_error_desc;
2786 int ret;
2787
2788 iwl_dump_error_desc =
2789 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL);
2790
2791 if (!iwl_dump_error_desc)
2792 return -ENOMEM;
2793
2794 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type);
2795 iwl_dump_error_desc->len = 0;
2796
2797 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc,
2798 false, 0);
2799 if (ret) {
2800 kfree(iwl_dump_error_desc);
2801 return ret;
2802 }
2803 }
2804
2805 iwl_trans_sync_nmi(fwrt->trans);
2806
2807 return 0;
2808 }
2809 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect);
2810
iwl_fw_dbg_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig,const char * str,size_t len,struct iwl_fw_dbg_trigger_tlv * trigger)2811 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
2812 enum iwl_fw_dbg_trigger trig,
2813 const char *str, size_t len,
2814 struct iwl_fw_dbg_trigger_tlv *trigger)
2815 {
2816 struct iwl_fw_dump_desc *desc;
2817 unsigned int delay = 0;
2818 bool monitor_only = false;
2819
2820 if (trigger) {
2821 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
2822
2823 if (!le16_to_cpu(trigger->occurrences))
2824 return 0;
2825
2826 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
2827 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
2828 trig);
2829 iwl_force_nmi(fwrt->trans);
2830 return 0;
2831 }
2832
2833 trigger->occurrences = cpu_to_le16(occurrences);
2834 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
2835
2836 /* convert msec to usec */
2837 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC;
2838 }
2839
2840 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC);
2841 if (!desc)
2842 return -ENOMEM;
2843
2844
2845 desc->len = len;
2846 desc->trig_desc.type = cpu_to_le32(trig);
2847 memcpy(desc->trig_desc.data, str, len);
2848
2849 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
2850 }
2851 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
2852
iwl_fw_dbg_collect_trig(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_trigger_tlv * trigger,const char * fmt,...)2853 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
2854 struct iwl_fw_dbg_trigger_tlv *trigger,
2855 const char *fmt, ...)
2856 {
2857 int ret, len = 0;
2858 char buf[64];
2859
2860 if (iwl_trans_dbg_ini_valid(fwrt->trans))
2861 return 0;
2862
2863 if (fmt) {
2864 va_list ap;
2865
2866 buf[sizeof(buf) - 1] = '\0';
2867
2868 va_start(ap, fmt);
2869 vsnprintf(buf, sizeof(buf), fmt, ap);
2870 va_end(ap);
2871
2872 /* check for truncation */
2873 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
2874 buf[sizeof(buf) - 1] = '\0';
2875
2876 len = strlen(buf) + 1;
2877 }
2878
2879 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
2880 trigger);
2881
2882 if (ret)
2883 return ret;
2884
2885 return 0;
2886 }
2887 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
2888
iwl_fw_start_dbg_conf(struct iwl_fw_runtime * fwrt,u8 conf_id)2889 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
2890 {
2891 u8 *ptr;
2892 int ret;
2893 int i;
2894
2895 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
2896 "Invalid configuration %d\n", conf_id))
2897 return -EINVAL;
2898
2899 /* EARLY START - firmware's configuration is hard coded */
2900 if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
2901 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
2902 conf_id == FW_DBG_START_FROM_ALIVE)
2903 return 0;
2904
2905 if (!fwrt->fw->dbg.conf_tlv[conf_id])
2906 return -EINVAL;
2907
2908 if (fwrt->dump.conf != FW_DBG_INVALID)
2909 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n",
2910 fwrt->dump.conf);
2911
2912 /* Send all HCMDs for configuring the FW debug */
2913 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
2914 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
2915 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
2916 struct iwl_host_cmd hcmd = {
2917 .id = cmd->id,
2918 .len = { le16_to_cpu(cmd->len), },
2919 .data = { cmd->data, },
2920 };
2921
2922 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
2923 if (ret)
2924 return ret;
2925
2926 ptr += sizeof(*cmd);
2927 ptr += le16_to_cpu(cmd->len);
2928 }
2929
2930 fwrt->dump.conf = conf_id;
2931
2932 return 0;
2933 }
2934 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
2935
iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime * fwrt,u32 timepoint,u32 timepoint_data)2936 void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt,
2937 u32 timepoint,
2938 u32 timepoint_data)
2939 {
2940 struct iwl_dbg_dump_complete_cmd hcmd_data;
2941 struct iwl_host_cmd hcmd = {
2942 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD),
2943 .data[0] = &hcmd_data,
2944 .len[0] = sizeof(hcmd_data),
2945 };
2946
2947 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status))
2948 return;
2949
2950 if (fw_has_capa(&fwrt->fw->ucode_capa,
2951 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) {
2952 hcmd_data.tp = cpu_to_le32(timepoint);
2953 hcmd_data.tp_data = cpu_to_le32(timepoint_data);
2954 iwl_trans_send_cmd(fwrt->trans, &hcmd);
2955 }
2956 }
2957
2958 /* this function assumes dump_start was called beforehand and dump_end will be
2959 * called afterwards
2960 */
iwl_fw_dbg_collect_sync(struct iwl_fw_runtime * fwrt,u8 wk_idx)2961 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
2962 {
2963 struct iwl_fw_dbg_params params = {0};
2964 struct iwl_fwrt_dump_data *dump_data =
2965 &fwrt->dump.wks[wk_idx].dump_data;
2966 if (!test_bit(wk_idx, &fwrt->dump.active_wks))
2967 return;
2968
2969 if (!dump_data->trig) {
2970 IWL_ERR(fwrt, "dump trigger data is not set\n");
2971 goto out;
2972 }
2973
2974 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) {
2975 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n");
2976 goto out;
2977 }
2978
2979 /* there's no point in fw dump if the bus is dead */
2980 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) {
2981 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
2982 goto out;
2983 }
2984
2985 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true);
2986
2987 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n");
2988 if (iwl_trans_dbg_ini_valid(fwrt->trans))
2989 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2990 else
2991 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2992 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n");
2993
2994 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false);
2995
2996 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2997 u32 policy = le32_to_cpu(dump_data->trig->apply_policy);
2998 u32 time_point = le32_to_cpu(dump_data->trig->time_point);
2999
3000 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) {
3001 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n");
3002 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0);
3003 }
3004 }
3005
3006 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY)
3007 iwl_force_nmi(fwrt->trans);
3008
3009 out:
3010 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
3011 iwl_fw_error_dump_data_free(dump_data);
3012 } else {
3013 iwl_fw_free_dump_desc(fwrt, dump_data->desc);
3014 dump_data->desc = NULL;
3015 }
3016
3017 clear_bit(wk_idx, &fwrt->dump.active_wks);
3018 }
3019
iwl_fw_dbg_ini_collect(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,bool sync)3020 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt,
3021 struct iwl_fwrt_dump_data *dump_data,
3022 bool sync)
3023 {
3024 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig;
3025 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
3026 u32 occur, delay;
3027 unsigned long idx;
3028
3029 if (!iwl_fw_ini_trigger_on(fwrt, trig)) {
3030 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n",
3031 tp_id);
3032 return -EINVAL;
3033 }
3034
3035 delay = le32_to_cpu(trig->dump_delay);
3036 occur = le32_to_cpu(trig->occurrences);
3037 if (!occur)
3038 return 0;
3039
3040 trig->occurrences = cpu_to_le32(--occur);
3041
3042 /* Check there is an available worker.
3043 * ffz return value is undefined if no zero exists,
3044 * so check against ~0UL first.
3045 */
3046 if (fwrt->dump.active_wks == ~0UL)
3047 return -EBUSY;
3048
3049 idx = ffz(fwrt->dump.active_wks);
3050
3051 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
3052 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
3053 return -EBUSY;
3054
3055 fwrt->dump.wks[idx].dump_data = *dump_data;
3056
3057 if (sync)
3058 delay = 0;
3059
3060 IWL_WARN(fwrt,
3061 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n",
3062 tp_id, (u32)(delay / USEC_PER_MSEC));
3063
3064 if (sync)
3065 iwl_fw_dbg_collect_sync(fwrt, idx);
3066 else
3067 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay));
3068
3069 return 0;
3070 }
3071
iwl_fw_error_dump_wk(struct work_struct * work)3072 void iwl_fw_error_dump_wk(struct work_struct *work)
3073 {
3074 struct iwl_fwrt_wk_data *wks =
3075 container_of(work, typeof(*wks), wk.work);
3076 struct iwl_fw_runtime *fwrt =
3077 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]);
3078
3079 /* assumes the op mode mutex is locked in dump_start since
3080 * iwl_fw_dbg_collect_sync can't run in parallel
3081 */
3082 if (fwrt->ops && fwrt->ops->dump_start)
3083 fwrt->ops->dump_start(fwrt->ops_ctx);
3084
3085 iwl_fw_dbg_collect_sync(fwrt, wks->idx);
3086
3087 if (fwrt->ops && fwrt->ops->dump_end)
3088 fwrt->ops->dump_end(fwrt->ops_ctx);
3089 }
3090
iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime * fwrt)3091 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
3092 {
3093 const struct iwl_cfg *cfg = fwrt->trans->cfg;
3094
3095 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
3096 return;
3097
3098 if (!fwrt->dump.d3_debug_data) {
3099 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length,
3100 GFP_KERNEL);
3101 if (!fwrt->dump.d3_debug_data) {
3102 IWL_ERR(fwrt,
3103 "failed to allocate memory for D3 debug data\n");
3104 return;
3105 }
3106 }
3107
3108 /* if the buffer holds previous debug data it is overwritten */
3109 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr,
3110 fwrt->dump.d3_debug_data,
3111 cfg->d3_debug_data_length);
3112
3113 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
3114 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
3115 cfg->d3_debug_data_base_addr,
3116 fwrt->dump.d3_debug_data,
3117 cfg->d3_debug_data_length);
3118 }
3119 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);
3120
iwl_fw_dbg_stop_sync(struct iwl_fw_runtime * fwrt)3121 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt)
3122 {
3123 int i;
3124
3125 iwl_dbg_tlv_del_timers(fwrt->trans);
3126 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
3127 iwl_fw_dbg_collect_sync(fwrt, i);
3128
3129 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true);
3130 }
3131 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
3132
iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans * trans,bool suspend)3133 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend)
3134 {
3135 struct iwl_dbg_suspend_resume_cmd cmd = {
3136 .operation = suspend ?
3137 cpu_to_le32(DBGC_SUSPEND_CMD) :
3138 cpu_to_le32(DBGC_RESUME_CMD),
3139 };
3140 struct iwl_host_cmd hcmd = {
3141 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME),
3142 .data[0] = &cmd,
3143 .len[0] = sizeof(cmd),
3144 };
3145
3146 return iwl_trans_send_cmd(trans, &hcmd);
3147 }
3148
iwl_fw_dbg_stop_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)3149 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
3150 struct iwl_fw_dbg_params *params)
3151 {
3152 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
3153 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3154 return;
3155 }
3156
3157 if (params) {
3158 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);
3159 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);
3160 }
3161
3162 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
3163 /* wait for the DBGC to finish writing the internal buffer to DRAM to
3164 * avoid halting the HW while writing
3165 */
3166 usleep_range(700, 1000);
3167 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
3168 }
3169
iwl_fw_dbg_restart_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)3170 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
3171 struct iwl_fw_dbg_params *params)
3172 {
3173 if (!params)
3174 return -EIO;
3175
3176 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
3177 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3178 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3179 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3180 } else {
3181 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
3182 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
3183 }
3184
3185 return 0;
3186 }
3187
iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime * fwrt)3188 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt)
3189 {
3190 struct iwl_mvm_marker marker = {
3191 .dw_len = sizeof(struct iwl_mvm_marker) / 4,
3192 .marker_id = MARKER_ID_SYNC_CLOCK,
3193 };
3194 struct iwl_host_cmd hcmd = {
3195 .flags = CMD_ASYNC,
3196 .id = WIDE_ID(LONG_GROUP, MARKER_CMD),
3197 .dataflags = {},
3198 };
3199 struct iwl_mvm_marker_rsp *resp;
3200 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw,
3201 WIDE_ID(LONG_GROUP, MARKER_CMD),
3202 IWL_FW_CMD_VER_UNKNOWN);
3203 int ret;
3204
3205 if (cmd_ver == 1) {
3206 /* the real timestamp is taken from the ftrace clock
3207 * this is for finding the match between fw and kernel logs
3208 */
3209 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++);
3210 } else if (cmd_ver == 2) {
3211 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns());
3212 } else {
3213 IWL_DEBUG_INFO(fwrt,
3214 "Invalid version of Marker CMD. Ver = %d\n",
3215 cmd_ver);
3216 return -EINVAL;
3217 }
3218
3219 hcmd.data[0] = ▮
3220 hcmd.len[0] = sizeof(marker);
3221
3222 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
3223
3224 if (cmd_ver > 1 && hcmd.resp_pkt) {
3225 resp = (void *)hcmd.resp_pkt->data;
3226 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n",
3227 le32_to_cpu(resp->gp2));
3228 }
3229
3230 return ret;
3231 }
3232
iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_params * params,bool stop)3233 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
3234 struct iwl_fw_dbg_params *params,
3235 bool stop)
3236 {
3237 int ret __maybe_unused = 0;
3238
3239 if (!iwl_trans_fw_running(fwrt->trans))
3240 return;
3241
3242 if (fw_has_capa(&fwrt->fw->ucode_capa,
3243 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) {
3244 if (stop)
3245 iwl_fw_send_timestamp_marker_cmd(fwrt);
3246 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop);
3247 } else if (stop) {
3248 iwl_fw_dbg_stop_recording(fwrt->trans, params);
3249 } else {
3250 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params);
3251 }
3252 #ifdef CONFIG_IWLWIFI_DEBUGFS
3253 if (!ret) {
3254 if (stop)
3255 fwrt->trans->dbg.rec_on = false;
3256 else
3257 iwl_fw_set_dbg_rec_on(fwrt);
3258 }
3259 #endif
3260 }
3261 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording);
3262