1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2020-2023 Intel Corporation
4  */
5 
6 #include "ivpu_drv.h"
7 #include "ivpu_fw.h"
8 #include "ivpu_hw_37xx_reg.h"
9 #include "ivpu_hw_reg_io.h"
10 #include "ivpu_hw.h"
11 #include "ivpu_ipc.h"
12 #include "ivpu_mmu.h"
13 #include "ivpu_pm.h"
14 
15 #define TILE_FUSE_ENABLE_BOTH        0x0
16 #define TILE_SKU_BOTH_MTL            0x3630
17 
18 /* Work point configuration values */
19 #define CONFIG_1_TILE                0x01
20 #define CONFIG_2_TILE                0x02
21 #define PLL_RATIO_5_3                0x01
22 #define PLL_RATIO_4_3                0x02
23 #define WP_CONFIG(tile, ratio)       (((tile) << 8) | (ratio))
24 #define WP_CONFIG_1_TILE_5_3_RATIO   WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_5_3)
25 #define WP_CONFIG_1_TILE_4_3_RATIO   WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_4_3)
26 #define WP_CONFIG_2_TILE_5_3_RATIO   WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_5_3)
27 #define WP_CONFIG_2_TILE_4_3_RATIO   WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_4_3)
28 #define WP_CONFIG_0_TILE_PLL_OFF     WP_CONFIG(0, 0)
29 
30 #define PLL_REF_CLK_FREQ	     (50 * 1000000)
31 #define PLL_SIMULATION_FREQ	     (10 * 1000000)
32 #define PLL_DEFAULT_EPP_VALUE	     0x80
33 
34 #define TIM_SAFE_ENABLE		     0xf1d0dead
35 #define TIM_WATCHDOG_RESET_VALUE     0xffffffff
36 
37 #define TIMEOUT_US		     (150 * USEC_PER_MSEC)
38 #define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
39 #define PLL_TIMEOUT_US		     (1500 * USEC_PER_MSEC)
40 #define IDLE_TIMEOUT_US		     (500 * USEC_PER_MSEC)
41 
42 #define ICB_0_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
43 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
44 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
45 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
46 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
47 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
48 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
49 
50 #define ICB_1_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
51 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
52 			(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
53 
54 #define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
55 
56 #define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
57 			   (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR)))
58 
59 #define BUTTRESS_ALL_IRQ_MASK (BUTTRESS_IRQ_MASK | \
60 			       (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)))
61 
62 #define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
63 #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
64 
65 #define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
66 				     (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
67 				     (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
68 				     (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
69 				     (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
70 				     (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
71 				     (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
72 
ivpu_platform_to_str(u32 platform)73 static char *ivpu_platform_to_str(u32 platform)
74 {
75 	switch (platform) {
76 	case IVPU_PLATFORM_SILICON:
77 		return "IVPU_PLATFORM_SILICON";
78 	case IVPU_PLATFORM_SIMICS:
79 		return "IVPU_PLATFORM_SIMICS";
80 	case IVPU_PLATFORM_FPGA:
81 		return "IVPU_PLATFORM_FPGA";
82 	default:
83 		return "Invalid platform";
84 	}
85 }
86 
ivpu_hw_read_platform(struct ivpu_device * vdev)87 static void ivpu_hw_read_platform(struct ivpu_device *vdev)
88 {
89 	u32 gen_ctrl = REGV_RD32(VPU_37XX_HOST_SS_GEN_CTRL);
90 	u32 platform = REG_GET_FLD(VPU_37XX_HOST_SS_GEN_CTRL, PS, gen_ctrl);
91 
92 	if  (platform == IVPU_PLATFORM_SIMICS || platform == IVPU_PLATFORM_FPGA)
93 		vdev->platform = platform;
94 	else
95 		vdev->platform = IVPU_PLATFORM_SILICON;
96 
97 	ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
98 		 ivpu_platform_to_str(vdev->platform), vdev->platform);
99 }
100 
ivpu_hw_wa_init(struct ivpu_device * vdev)101 static void ivpu_hw_wa_init(struct ivpu_device *vdev)
102 {
103 	vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
104 	vdev->wa.clear_runtime_mem = false;
105 	vdev->wa.d3hot_after_power_off = true;
106 
107 	REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK);
108 	if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) {
109 		/* Writing 1s does not clear the interrupt status register */
110 		vdev->wa.interrupt_clear_with_0 = true;
111 		REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);
112 	}
113 
114 	IVPU_PRINT_WA(punit_disabled);
115 	IVPU_PRINT_WA(clear_runtime_mem);
116 	IVPU_PRINT_WA(d3hot_after_power_off);
117 	IVPU_PRINT_WA(interrupt_clear_with_0);
118 }
119 
ivpu_hw_timeouts_init(struct ivpu_device * vdev)120 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
121 {
122 	if (ivpu_is_simics(vdev) || ivpu_is_fpga(vdev)) {
123 		vdev->timeout.boot = 100000;
124 		vdev->timeout.jsm = 50000;
125 		vdev->timeout.tdr = 2000000;
126 		vdev->timeout.reschedule_suspend = 1000;
127 	} else {
128 		vdev->timeout.boot = 1000;
129 		vdev->timeout.jsm = 500;
130 		vdev->timeout.tdr = 2000;
131 		vdev->timeout.reschedule_suspend = 10;
132 	}
133 }
134 
ivpu_pll_wait_for_cmd_send(struct ivpu_device * vdev)135 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
136 {
137 	return REGB_POLL_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
138 }
139 
140 /* Send KMD initiated workpoint change */
ivpu_pll_cmd_send(struct ivpu_device * vdev,u16 min_ratio,u16 max_ratio,u16 target_ratio,u16 config)141 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
142 			     u16 target_ratio, u16 config)
143 {
144 	int ret;
145 	u32 val;
146 
147 	ret = ivpu_pll_wait_for_cmd_send(vdev);
148 	if (ret) {
149 		ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret);
150 		return ret;
151 	}
152 
153 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0);
154 	val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
155 	val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
156 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
157 
158 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1);
159 	val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
160 	val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val);
161 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
162 
163 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2);
164 	val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
165 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
166 
167 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD);
168 	val = REG_SET_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, val);
169 	REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_CMD, val);
170 
171 	ret = ivpu_pll_wait_for_cmd_send(vdev);
172 	if (ret)
173 		ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret);
174 
175 	return ret;
176 }
177 
ivpu_pll_wait_for_lock(struct ivpu_device * vdev,bool enable)178 static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable)
179 {
180 	u32 exp_val = enable ? 0x1 : 0x0;
181 
182 	if (IVPU_WA(punit_disabled))
183 		return 0;
184 
185 	return REGB_POLL_FLD(VPU_37XX_BUTTRESS_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US);
186 }
187 
ivpu_pll_wait_for_status_ready(struct ivpu_device * vdev)188 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
189 {
190 	if (IVPU_WA(punit_disabled))
191 		return 0;
192 
193 	return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
194 }
195 
ivpu_pll_init_frequency_ratios(struct ivpu_device * vdev)196 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
197 {
198 	struct ivpu_hw_info *hw = vdev->hw;
199 	u8 fuse_min_ratio, fuse_max_ratio, fuse_pn_ratio;
200 	u32 fmin_fuse, fmax_fuse;
201 
202 	fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE);
203 	fuse_min_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse);
204 	fuse_pn_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse);
205 
206 	fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE);
207 	fuse_max_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse);
208 
209 	hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio);
210 	hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio);
211 	hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
212 }
213 
ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device * vdev)214 static int ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device *vdev)
215 {
216 	return REGV_POLL_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, AON, 0, 100);
217 }
218 
ivpu_pll_drive(struct ivpu_device * vdev,bool enable)219 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
220 {
221 	struct ivpu_hw_info *hw = vdev->hw;
222 	u16 target_ratio;
223 	u16 config;
224 	int ret;
225 
226 	if (IVPU_WA(punit_disabled)) {
227 		ivpu_dbg(vdev, PM, "Skipping PLL request on %s\n",
228 			 ivpu_platform_to_str(vdev->platform));
229 		return 0;
230 	}
231 
232 	if (enable) {
233 		target_ratio = hw->pll.pn_ratio;
234 		config = hw->config;
235 	} else {
236 		target_ratio = 0;
237 		config = 0;
238 	}
239 
240 	ivpu_dbg(vdev, PM, "PLL workpoint request: config 0x%04x pll ratio 0x%x\n",
241 		 config, target_ratio);
242 
243 	ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, target_ratio, config);
244 	if (ret) {
245 		ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret);
246 		return ret;
247 	}
248 
249 	ret = ivpu_pll_wait_for_lock(vdev, enable);
250 	if (ret) {
251 		ivpu_err(vdev, "Timed out waiting for PLL lock\n");
252 		return ret;
253 	}
254 
255 	if (enable) {
256 		ret = ivpu_pll_wait_for_status_ready(vdev);
257 		if (ret) {
258 			ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
259 			return ret;
260 		}
261 
262 		ret = ivpu_hw_37xx_wait_for_vpuip_bar(vdev);
263 		if (ret) {
264 			ivpu_err(vdev, "Timed out waiting for VPUIP bar\n");
265 			return ret;
266 		}
267 	}
268 
269 	return 0;
270 }
271 
ivpu_pll_enable(struct ivpu_device * vdev)272 static int ivpu_pll_enable(struct ivpu_device *vdev)
273 {
274 	return ivpu_pll_drive(vdev, true);
275 }
276 
ivpu_pll_disable(struct ivpu_device * vdev)277 static int ivpu_pll_disable(struct ivpu_device *vdev)
278 {
279 	return ivpu_pll_drive(vdev, false);
280 }
281 
ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device * vdev)282 static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev)
283 {
284 	u32 val = 0;
285 
286 	val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val);
287 	val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val);
288 	val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val);
289 
290 	REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val);
291 }
292 
ivpu_boot_host_ss_rst_drive(struct ivpu_device * vdev,bool enable)293 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
294 {
295 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET);
296 
297 	if (enable) {
298 		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
299 		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
300 		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
301 	} else {
302 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
303 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
304 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
305 	}
306 
307 	REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val);
308 }
309 
ivpu_boot_host_ss_clk_drive(struct ivpu_device * vdev,bool enable)310 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
311 {
312 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET);
313 
314 	if (enable) {
315 		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
316 		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
317 		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
318 	} else {
319 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
320 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
321 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
322 	}
323 
324 	REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val);
325 }
326 
ivpu_boot_noc_qreqn_check(struct ivpu_device * vdev,u32 exp_val)327 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
328 {
329 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
330 
331 	if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
332 		return -EIO;
333 
334 	return 0;
335 }
336 
ivpu_boot_noc_qacceptn_check(struct ivpu_device * vdev,u32 exp_val)337 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
338 {
339 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN);
340 
341 	if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
342 		return -EIO;
343 
344 	return 0;
345 }
346 
ivpu_boot_noc_qdeny_check(struct ivpu_device * vdev,u32 exp_val)347 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
348 {
349 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY);
350 
351 	if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
352 		return -EIO;
353 
354 	return 0;
355 }
356 
ivpu_boot_top_noc_qrenqn_check(struct ivpu_device * vdev,u32 exp_val)357 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
358 {
359 	u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN);
360 
361 	if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
362 	    !REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
363 		return -EIO;
364 
365 	return 0;
366 }
367 
ivpu_boot_top_noc_qacceptn_check(struct ivpu_device * vdev,u32 exp_val)368 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
369 {
370 	u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QACCEPTN);
371 
372 	if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
373 	    !REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
374 		return -EIO;
375 
376 	return 0;
377 }
378 
ivpu_boot_top_noc_qdeny_check(struct ivpu_device * vdev,u32 exp_val)379 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
380 {
381 	u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QDENY);
382 
383 	if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
384 	    !REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
385 		return -EIO;
386 
387 	return 0;
388 }
389 
ivpu_boot_host_ss_configure(struct ivpu_device * vdev)390 static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev)
391 {
392 	ivpu_boot_host_ss_rst_clr_assert(vdev);
393 
394 	return ivpu_boot_noc_qreqn_check(vdev, 0x0);
395 }
396 
ivpu_boot_vpu_idle_gen_disable(struct ivpu_device * vdev)397 static void ivpu_boot_vpu_idle_gen_disable(struct ivpu_device *vdev)
398 {
399 	REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, 0x0);
400 }
401 
ivpu_boot_host_ss_axi_drive(struct ivpu_device * vdev,bool enable)402 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
403 {
404 	int ret;
405 	u32 val;
406 
407 	val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
408 	if (enable)
409 		val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
410 	else
411 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
412 	REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val);
413 
414 	ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
415 	if (ret) {
416 		ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
417 		return ret;
418 	}
419 
420 	ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
421 	if (ret)
422 		ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
423 
424 	return ret;
425 }
426 
ivpu_boot_host_ss_axi_enable(struct ivpu_device * vdev)427 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
428 {
429 	return ivpu_boot_host_ss_axi_drive(vdev, true);
430 }
431 
ivpu_boot_host_ss_top_noc_drive(struct ivpu_device * vdev,bool enable)432 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
433 {
434 	int ret;
435 	u32 val;
436 
437 	val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN);
438 	if (enable) {
439 		val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val);
440 		val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
441 	} else {
442 		val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val);
443 		val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
444 	}
445 	REGV_WR32(MTL_VPU_TOP_NOC_QREQN, val);
446 
447 	ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
448 	if (ret) {
449 		ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
450 		return ret;
451 	}
452 
453 	ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
454 	if (ret)
455 		ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
456 
457 	return ret;
458 }
459 
ivpu_boot_host_ss_top_noc_enable(struct ivpu_device * vdev)460 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
461 {
462 	return ivpu_boot_host_ss_top_noc_drive(vdev, true);
463 }
464 
ivpu_boot_pwr_island_trickle_drive(struct ivpu_device * vdev,bool enable)465 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
466 {
467 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
468 
469 	if (enable)
470 		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
471 	else
472 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
473 
474 	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
475 }
476 
ivpu_boot_pwr_island_drive(struct ivpu_device * vdev,bool enable)477 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable)
478 {
479 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
480 
481 	if (enable)
482 		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
483 	else
484 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
485 
486 	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
487 }
488 
ivpu_boot_wait_for_pwr_island_status(struct ivpu_device * vdev,u32 exp_val)489 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
490 {
491 	/* FPGA model (UPF) is not power aware, skipped Power Island polling */
492 	if (ivpu_is_fpga(vdev))
493 		return 0;
494 
495 	return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU,
496 			     exp_val, PWR_ISLAND_STATUS_TIMEOUT_US);
497 }
498 
ivpu_boot_pwr_island_isolation_drive(struct ivpu_device * vdev,bool enable)499 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
500 {
501 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0);
502 
503 	if (enable)
504 		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
505 	else
506 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
507 
508 	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val);
509 }
510 
ivpu_boot_dpu_active_drive(struct ivpu_device * vdev,bool enable)511 static void ivpu_boot_dpu_active_drive(struct ivpu_device *vdev, bool enable)
512 {
513 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE);
514 
515 	if (enable)
516 		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
517 	else
518 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
519 
520 	REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
521 }
522 
ivpu_boot_pwr_domain_enable(struct ivpu_device * vdev)523 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
524 {
525 	int ret;
526 
527 	ivpu_boot_pwr_island_trickle_drive(vdev, true);
528 	ivpu_boot_pwr_island_drive(vdev, true);
529 
530 	ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1);
531 	if (ret) {
532 		ivpu_err(vdev, "Timed out waiting for power island status\n");
533 		return ret;
534 	}
535 
536 	ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0);
537 	if (ret) {
538 		ivpu_err(vdev, "Failed qrenqn check %d\n", ret);
539 		return ret;
540 	}
541 
542 	ivpu_boot_host_ss_clk_drive(vdev, true);
543 	ivpu_boot_pwr_island_isolation_drive(vdev, false);
544 	ivpu_boot_host_ss_rst_drive(vdev, true);
545 	ivpu_boot_dpu_active_drive(vdev, true);
546 
547 	return ret;
548 }
549 
ivpu_boot_pwr_domain_disable(struct ivpu_device * vdev)550 static int ivpu_boot_pwr_domain_disable(struct ivpu_device *vdev)
551 {
552 	ivpu_boot_dpu_active_drive(vdev, false);
553 	ivpu_boot_pwr_island_isolation_drive(vdev, true);
554 	ivpu_boot_pwr_island_trickle_drive(vdev, false);
555 	ivpu_boot_pwr_island_drive(vdev, false);
556 
557 	return ivpu_boot_wait_for_pwr_island_status(vdev, 0x0);
558 }
559 
ivpu_boot_no_snoop_enable(struct ivpu_device * vdev)560 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
561 {
562 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
563 
564 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val);
565 	val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);
566 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);
567 
568 	REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);
569 }
570 
ivpu_boot_tbu_mmu_enable(struct ivpu_device * vdev)571 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev)
572 {
573 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV);
574 
575 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
576 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
577 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
578 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
579 
580 	REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val);
581 }
582 
ivpu_boot_soc_cpu_boot(struct ivpu_device * vdev)583 static void ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev)
584 {
585 	u32 val;
586 
587 	val = REGV_RD32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC);
588 	val = REG_SET_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val);
589 
590 	val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val);
591 	REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
592 
593 	val = REG_SET_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
594 	REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
595 
596 	val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
597 	REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
598 
599 	val = vdev->fw->entry_point >> 9;
600 	REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
601 
602 	val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val);
603 	REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
604 
605 	ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
606 		 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume");
607 }
608 
ivpu_boot_d0i3_drive(struct ivpu_device * vdev,bool enable)609 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
610 {
611 	int ret;
612 	u32 val;
613 
614 	ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
615 	if (ret) {
616 		ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
617 		return ret;
618 	}
619 
620 	val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL);
621 	if (enable)
622 		val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val);
623 	else
624 		val = REG_CLR_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val);
625 	REGB_WR32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, val);
626 
627 	ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
628 	if (ret)
629 		ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
630 
631 	return ret;
632 }
633 
ivpu_hw_37xx_info_init(struct ivpu_device * vdev)634 static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
635 {
636 	struct ivpu_hw_info *hw = vdev->hw;
637 
638 	hw->tile_fuse = TILE_FUSE_ENABLE_BOTH;
639 	hw->sku = TILE_SKU_BOTH_MTL;
640 	hw->config = WP_CONFIG_2_TILE_4_3_RATIO;
641 
642 	ivpu_pll_init_frequency_ratios(vdev);
643 
644 	ivpu_hw_init_range(&hw->ranges.global, 0x80000000, SZ_512M);
645 	ivpu_hw_init_range(&hw->ranges.user,   0xc0000000, 255 * SZ_1M);
646 	ivpu_hw_init_range(&hw->ranges.shave, 0x180000000, SZ_2G);
647 	ivpu_hw_init_range(&hw->ranges.dma,   0x200000000, SZ_8G);
648 
649 	ivpu_hw_read_platform(vdev);
650 	ivpu_hw_wa_init(vdev);
651 	ivpu_hw_timeouts_init(vdev);
652 
653 	return 0;
654 }
655 
ivpu_hw_37xx_reset(struct ivpu_device * vdev)656 static int ivpu_hw_37xx_reset(struct ivpu_device *vdev)
657 {
658 	int ret = 0;
659 
660 	if (ivpu_boot_pwr_domain_disable(vdev)) {
661 		ivpu_err(vdev, "Failed to disable power domain\n");
662 		ret = -EIO;
663 	}
664 
665 	if (ivpu_pll_disable(vdev)) {
666 		ivpu_err(vdev, "Failed to disable PLL\n");
667 		ret = -EIO;
668 	}
669 
670 	return ret;
671 }
672 
ivpu_hw_37xx_d0i3_enable(struct ivpu_device * vdev)673 static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev)
674 {
675 	int ret;
676 
677 	ret = ivpu_boot_d0i3_drive(vdev, true);
678 	if (ret)
679 		ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
680 
681 	udelay(5); /* VPU requires 5 us to complete the transition */
682 
683 	return ret;
684 }
685 
ivpu_hw_37xx_d0i3_disable(struct ivpu_device * vdev)686 static int ivpu_hw_37xx_d0i3_disable(struct ivpu_device *vdev)
687 {
688 	int ret;
689 
690 	ret = ivpu_boot_d0i3_drive(vdev, false);
691 	if (ret)
692 		ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
693 
694 	return ret;
695 }
696 
ivpu_hw_37xx_power_up(struct ivpu_device * vdev)697 static int ivpu_hw_37xx_power_up(struct ivpu_device *vdev)
698 {
699 	int ret;
700 
701 	ret = ivpu_hw_37xx_d0i3_disable(vdev);
702 	if (ret)
703 		ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
704 
705 	ret = ivpu_pll_enable(vdev);
706 	if (ret) {
707 		ivpu_err(vdev, "Failed to enable PLL: %d\n", ret);
708 		return ret;
709 	}
710 
711 	ret = ivpu_boot_host_ss_configure(vdev);
712 	if (ret) {
713 		ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
714 		return ret;
715 	}
716 
717 	/*
718 	 * The control circuitry for vpu_idle indication logic powers up active.
719 	 * To ensure unnecessary low power mode signal from LRT during bring up,
720 	 * KMD disables the circuitry prior to bringing up the Main Power island.
721 	 */
722 	ivpu_boot_vpu_idle_gen_disable(vdev);
723 
724 	ret = ivpu_boot_pwr_domain_enable(vdev);
725 	if (ret) {
726 		ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
727 		return ret;
728 	}
729 
730 	ret = ivpu_boot_host_ss_axi_enable(vdev);
731 	if (ret) {
732 		ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
733 		return ret;
734 	}
735 
736 	ret = ivpu_boot_host_ss_top_noc_enable(vdev);
737 	if (ret)
738 		ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
739 
740 	return ret;
741 }
742 
ivpu_hw_37xx_boot_fw(struct ivpu_device * vdev)743 static int ivpu_hw_37xx_boot_fw(struct ivpu_device *vdev)
744 {
745 	ivpu_boot_no_snoop_enable(vdev);
746 	ivpu_boot_tbu_mmu_enable(vdev);
747 	ivpu_boot_soc_cpu_boot(vdev);
748 
749 	return 0;
750 }
751 
ivpu_hw_37xx_is_idle(struct ivpu_device * vdev)752 static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev)
753 {
754 	u32 val;
755 
756 	if (IVPU_WA(punit_disabled))
757 		return true;
758 
759 	val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS);
760 	return REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, val) &&
761 	       REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, val);
762 }
763 
ivpu_hw_37xx_power_down(struct ivpu_device * vdev)764 static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev)
765 {
766 	int ret = 0;
767 
768 	if (!ivpu_hw_37xx_is_idle(vdev))
769 		ivpu_warn(vdev, "VPU not idle during power down\n");
770 
771 	if (ivpu_hw_37xx_reset(vdev)) {
772 		ivpu_err(vdev, "Failed to reset VPU\n");
773 		ret = -EIO;
774 	}
775 
776 	if (ivpu_hw_37xx_d0i3_enable(vdev)) {
777 		ivpu_err(vdev, "Failed to enter D0I3\n");
778 		ret = -EIO;
779 	}
780 
781 	return ret;
782 }
783 
ivpu_hw_37xx_wdt_disable(struct ivpu_device * vdev)784 static void ivpu_hw_37xx_wdt_disable(struct ivpu_device *vdev)
785 {
786 	u32 val;
787 
788 	/* Enable writing and set non-zero WDT value */
789 	REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
790 	REGV_WR32(MTL_VPU_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
791 
792 	/* Enable writing and disable watchdog timer */
793 	REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
794 	REGV_WR32(MTL_VPU_CPU_SS_TIM_WDOG_EN, 0);
795 
796 	/* Now clear the timeout interrupt */
797 	val = REGV_RD32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG);
798 	val = REG_CLR_FLD(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
799 	REGV_WR32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, val);
800 }
801 
ivpu_hw_37xx_pll_to_freq(u32 ratio,u32 config)802 static u32 ivpu_hw_37xx_pll_to_freq(u32 ratio, u32 config)
803 {
804 	u32 pll_clock = PLL_REF_CLK_FREQ * ratio;
805 	u32 cpu_clock;
806 
807 	if ((config & 0xff) == PLL_RATIO_4_3)
808 		cpu_clock = pll_clock * 2 / 4;
809 	else
810 		cpu_clock = pll_clock * 2 / 5;
811 
812 	return cpu_clock;
813 }
814 
815 /* Register indirect accesses */
ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device * vdev)816 static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev)
817 {
818 	u32 pll_curr_ratio;
819 
820 	pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL);
821 	pll_curr_ratio &= VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK;
822 
823 	if (!ivpu_is_silicon(vdev))
824 		return PLL_SIMULATION_FREQ;
825 
826 	return ivpu_hw_37xx_pll_to_freq(pll_curr_ratio, vdev->hw->config);
827 }
828 
ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device * vdev)829 static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
830 {
831 	return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET);
832 }
833 
ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device * vdev)834 static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev)
835 {
836 	return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE);
837 }
838 
ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device * vdev)839 static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
840 {
841 	return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE);
842 }
843 
ivpu_hw_37xx_reg_db_set(struct ivpu_device * vdev,u32 db_id)844 static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
845 {
846 	u32 reg_stride = MTL_VPU_CPU_SS_DOORBELL_1 - MTL_VPU_CPU_SS_DOORBELL_0;
847 	u32 val = REG_FLD(MTL_VPU_CPU_SS_DOORBELL_0, SET);
848 
849 	REGV_WR32I(MTL_VPU_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
850 }
851 
ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device * vdev)852 static u32 ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
853 {
854 	return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM);
855 }
856 
ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device * vdev)857 static u32 ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device *vdev)
858 {
859 	u32 count = REGV_RD32_SILENT(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT);
860 
861 	return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
862 }
863 
ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device * vdev,u32 vpu_addr)864 static void ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
865 {
866 	REGV_WR32(MTL_VPU_CPU_SS_TIM_IPC_FIFO, vpu_addr);
867 }
868 
ivpu_hw_37xx_irq_clear(struct ivpu_device * vdev)869 static void ivpu_hw_37xx_irq_clear(struct ivpu_device *vdev)
870 {
871 	REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK);
872 }
873 
ivpu_hw_37xx_irq_enable(struct ivpu_device * vdev)874 static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev)
875 {
876 	REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);
877 	REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK);
878 	REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
879 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
880 }
881 
ivpu_hw_37xx_irq_disable(struct ivpu_device * vdev)882 static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev)
883 {
884 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
885 	REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
886 	REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
887 	REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0);
888 }
889 
ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device * vdev)890 static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev)
891 {
892 	ivpu_err_ratelimited(vdev, "WDT NCE irq\n");
893 
894 	ivpu_pm_schedule_recovery(vdev);
895 }
896 
ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device * vdev)897 static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev)
898 {
899 	ivpu_err_ratelimited(vdev, "WDT MSS irq\n");
900 
901 	ivpu_hw_wdt_disable(vdev);
902 	ivpu_pm_schedule_recovery(vdev);
903 }
904 
ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device * vdev)905 static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev)
906 {
907 	ivpu_err_ratelimited(vdev, "NOC Firewall irq\n");
908 
909 	ivpu_pm_schedule_recovery(vdev);
910 }
911 
912 /* Handler for IRQs from VPU core (irqV) */
ivpu_hw_37xx_irqv_handler(struct ivpu_device * vdev,int irq)913 static u32 ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq)
914 {
915 	u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
916 
917 	REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status);
918 
919 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
920 		ivpu_mmu_irq_evtq_handler(vdev);
921 
922 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
923 		ivpu_ipc_irq_handler(vdev);
924 
925 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
926 		ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
927 
928 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
929 		ivpu_mmu_irq_gerr_handler(vdev);
930 
931 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
932 		ivpu_hw_37xx_irq_wdt_mss_handler(vdev);
933 
934 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
935 		ivpu_hw_37xx_irq_wdt_nce_handler(vdev);
936 
937 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
938 		ivpu_hw_37xx_irq_noc_firewall_handler(vdev);
939 
940 	return status;
941 }
942 
943 /* Handler for IRQs from Buttress core (irqB) */
ivpu_hw_37xx_irqb_handler(struct ivpu_device * vdev,int irq)944 static u32 ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq)
945 {
946 	u32 status = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
947 	bool schedule_recovery = false;
948 
949 	if (status == 0)
950 		return 0;
951 
952 	if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
953 		ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x",
954 			 REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL));
955 
956 	if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) {
957 		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
958 		REGB_WR32(VPU_37XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);
959 		schedule_recovery = true;
960 	}
961 
962 	if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, status)) {
963 		u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);
964 
965 		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
966 			 ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log),
967 			 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log),
968 			 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log));
969 		REGB_WR32(VPU_37XX_BUTTRESS_UFI_ERR_CLEAR, 0x1);
970 		schedule_recovery = true;
971 	}
972 
973 	/* This must be done after interrupts are cleared at the source. */
974 	if (IVPU_WA(interrupt_clear_with_0))
975 		/*
976 		 * Writing 1 triggers an interrupt, so we can't perform read update write.
977 		 * Clear local interrupt status by writing 0 to all bits.
978 		 */
979 		REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);
980 	else
981 		REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status);
982 
983 	if (schedule_recovery)
984 		ivpu_pm_schedule_recovery(vdev);
985 
986 	return status;
987 }
988 
ivpu_hw_37xx_irq_handler(int irq,void * ptr)989 static irqreturn_t ivpu_hw_37xx_irq_handler(int irq, void *ptr)
990 {
991 	struct ivpu_device *vdev = ptr;
992 	u32 ret_irqv, ret_irqb;
993 
994 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
995 
996 	ret_irqv = ivpu_hw_37xx_irqv_handler(vdev, irq);
997 	ret_irqb = ivpu_hw_37xx_irqb_handler(vdev, irq);
998 
999 	/* Re-enable global interrupts to re-trigger MSI for pending interrupts */
1000 	REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
1001 
1002 	return IRQ_RETVAL(ret_irqb | ret_irqv);
1003 }
1004 
ivpu_hw_37xx_diagnose_failure(struct ivpu_device * vdev)1005 static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev)
1006 {
1007 	u32 irqv = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1008 	u32 irqb = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1009 
1010 	if (ivpu_hw_37xx_reg_ipc_rx_count_get(vdev))
1011 		ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1012 
1013 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv))
1014 		ivpu_err(vdev, "WDT MSS timeout detected\n");
1015 
1016 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv))
1017 		ivpu_err(vdev, "WDT NCE timeout detected\n");
1018 
1019 	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv))
1020 		ivpu_err(vdev, "NOC Firewall irq detected\n");
1021 
1022 	if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb))
1023 		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
1024 
1025 	if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, irqb)) {
1026 		u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);
1027 
1028 		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
1029 			 ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log),
1030 			 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log),
1031 			 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log));
1032 	}
1033 }
1034 
1035 const struct ivpu_hw_ops ivpu_hw_37xx_ops = {
1036 	.info_init = ivpu_hw_37xx_info_init,
1037 	.power_up = ivpu_hw_37xx_power_up,
1038 	.is_idle = ivpu_hw_37xx_is_idle,
1039 	.power_down = ivpu_hw_37xx_power_down,
1040 	.reset = ivpu_hw_37xx_reset,
1041 	.boot_fw = ivpu_hw_37xx_boot_fw,
1042 	.wdt_disable = ivpu_hw_37xx_wdt_disable,
1043 	.diagnose_failure = ivpu_hw_37xx_diagnose_failure,
1044 	.reg_pll_freq_get = ivpu_hw_37xx_reg_pll_freq_get,
1045 	.reg_telemetry_offset_get = ivpu_hw_37xx_reg_telemetry_offset_get,
1046 	.reg_telemetry_size_get = ivpu_hw_37xx_reg_telemetry_size_get,
1047 	.reg_telemetry_enable_get = ivpu_hw_37xx_reg_telemetry_enable_get,
1048 	.reg_db_set = ivpu_hw_37xx_reg_db_set,
1049 	.reg_ipc_rx_addr_get = ivpu_hw_37xx_reg_ipc_rx_addr_get,
1050 	.reg_ipc_rx_count_get = ivpu_hw_37xx_reg_ipc_rx_count_get,
1051 	.reg_ipc_tx_set = ivpu_hw_37xx_reg_ipc_tx_set,
1052 	.irq_clear = ivpu_hw_37xx_irq_clear,
1053 	.irq_enable = ivpu_hw_37xx_irq_enable,
1054 	.irq_disable = ivpu_hw_37xx_irq_disable,
1055 	.irq_handler = ivpu_hw_37xx_irq_handler,
1056 };
1057