1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 #include "exec/cpu-interrupt.h" 8 #include "qemu/cpu-float.h" 9 10 #if !defined(TARGET_SPARC64) 11 #define TARGET_DPREGS 16 12 #define TARGET_FCCREGS 1 13 #else 14 #define TARGET_DPREGS 32 15 #define TARGET_FCCREGS 4 16 #endif 17 18 /*#define EXCP_INTERRUPT 0x100*/ 19 20 /* Windowed register indexes. */ 21 enum { 22 WREG_O0, 23 WREG_O1, 24 WREG_O2, 25 WREG_O3, 26 WREG_O4, 27 WREG_O5, 28 WREG_O6, 29 WREG_O7, 30 31 WREG_L0, 32 WREG_L1, 33 WREG_L2, 34 WREG_L3, 35 WREG_L4, 36 WREG_L5, 37 WREG_L6, 38 WREG_L7, 39 40 WREG_I0, 41 WREG_I1, 42 WREG_I2, 43 WREG_I3, 44 WREG_I4, 45 WREG_I5, 46 WREG_I6, 47 WREG_I7, 48 49 WREG_SP = WREG_O6, 50 WREG_FP = WREG_I6, 51 }; 52 53 /* trap definitions */ 54 #ifndef TARGET_SPARC64 55 #define TT_TFAULT 0x01 56 #define TT_ILL_INSN 0x02 57 #define TT_PRIV_INSN 0x03 58 #define TT_NFPU_INSN 0x04 59 #define TT_WIN_OVF 0x05 60 #define TT_WIN_UNF 0x06 61 #define TT_UNALIGNED 0x07 62 #define TT_FP_EXCP 0x08 63 #define TT_DFAULT 0x09 64 #define TT_TOVF 0x0a 65 #define TT_EXTINT 0x10 66 #define TT_CODE_ACCESS 0x21 67 #define TT_UNIMP_FLUSH 0x25 68 #define TT_DATA_ACCESS 0x29 69 #define TT_DIV_ZERO 0x2a 70 #define TT_NCP_INSN 0x24 71 #define TT_TRAP 0x80 72 #else 73 #define TT_POWER_ON_RESET 0x01 74 #define TT_TFAULT 0x08 75 #define TT_CODE_ACCESS 0x0a 76 #define TT_ILL_INSN 0x10 77 #define TT_UNIMP_FLUSH TT_ILL_INSN 78 #define TT_PRIV_INSN 0x11 79 #define TT_NFPU_INSN 0x20 80 #define TT_FP_EXCP 0x21 81 #define TT_TOVF 0x23 82 #define TT_CLRWIN 0x24 83 #define TT_DIV_ZERO 0x28 84 #define TT_DFAULT 0x30 85 #define TT_DATA_ACCESS 0x32 86 #define TT_UNALIGNED 0x34 87 #define TT_PRIV_ACT 0x37 88 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 89 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 90 #define TT_EXTINT 0x40 91 #define TT_IVEC 0x60 92 #define TT_TMISS 0x64 93 #define TT_DMISS 0x68 94 #define TT_DPROT 0x6c 95 #define TT_SPILL 0x80 96 #define TT_FILL 0xc0 97 #define TT_WOTHER (1 << 5) 98 #define TT_TRAP 0x100 99 #define TT_HTRAP 0x180 100 #endif 101 102 #define PSR_NEG_SHIFT 23 103 #define PSR_NEG (1 << PSR_NEG_SHIFT) 104 #define PSR_ZERO_SHIFT 22 105 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 106 #define PSR_OVF_SHIFT 21 107 #define PSR_OVF (1 << PSR_OVF_SHIFT) 108 #define PSR_CARRY_SHIFT 20 109 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 110 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 111 #if !defined(TARGET_SPARC64) 112 #define PSR_EF (1<<12) 113 #define PSR_PIL 0xf00 114 #define PSR_S (1<<7) 115 #define PSR_PS (1<<6) 116 #define PSR_ET (1<<5) 117 #define PSR_CWP 0x1f 118 #endif 119 120 /* Trap base register */ 121 #define TBR_BASE_MASK 0xfffff000 122 123 #if defined(TARGET_SPARC64) 124 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 125 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 126 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 127 #define PS_CLE (1<<9) /* UA2007 */ 128 #define PS_TLE (1<<8) /* UA2007 */ 129 #define PS_RMO (1<<7) 130 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 131 #define PS_PEF (1<<4) /* enable fpu */ 132 #define PS_AM (1<<3) /* address mask */ 133 #define PS_PRIV (1<<2) 134 #define PS_IE (1<<1) 135 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 136 137 #define FPRS_DL (1 << 0) 138 #define FPRS_DU (1 << 1) 139 #define FPRS_FEF (1 << 2) 140 141 #define HS_PRIV (1<<2) 142 #endif 143 144 /* Fcc */ 145 #define FSR_RD1 (1ULL << 31) 146 #define FSR_RD0 (1ULL << 30) 147 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 148 #define FSR_RD_NEAREST 0 149 #define FSR_RD_ZERO FSR_RD0 150 #define FSR_RD_POS FSR_RD1 151 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 152 153 #define FSR_NVM (1ULL << 27) 154 #define FSR_OFM (1ULL << 26) 155 #define FSR_UFM (1ULL << 25) 156 #define FSR_DZM (1ULL << 24) 157 #define FSR_NXM (1ULL << 23) 158 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 159 #define FSR_TEM_SHIFT 23 160 161 #define FSR_NVA (1ULL << 9) 162 #define FSR_OFA (1ULL << 8) 163 #define FSR_UFA (1ULL << 7) 164 #define FSR_DZA (1ULL << 6) 165 #define FSR_NXA (1ULL << 5) 166 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 167 #define FSR_AEXC_SHIFT 5 168 169 #define FSR_NVC (1ULL << 4) 170 #define FSR_OFC (1ULL << 3) 171 #define FSR_UFC (1ULL << 2) 172 #define FSR_DZC (1ULL << 1) 173 #define FSR_NXC (1ULL << 0) 174 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 175 176 #define FSR_VER_SHIFT 17 177 #define FSR_VER_MASK (7 << FSR_VER_SHIFT) 178 179 #define FSR_FTT2 (1ULL << 16) 180 #define FSR_FTT1 (1ULL << 15) 181 #define FSR_FTT0 (1ULL << 14) 182 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 183 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 184 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 185 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 186 #define FSR_FTT_INVAL_FPR (6ULL << 14) 187 188 #define FSR_QNE (1ULL << 13) 189 190 #define FSR_FCC0_SHIFT 10 191 #define FSR_FCC1_SHIFT 32 192 #define FSR_FCC2_SHIFT 34 193 #define FSR_FCC3_SHIFT 36 194 195 /* MMU */ 196 #define MMU_E (1<<0) 197 #define MMU_NF (1<<1) 198 199 #define PTE_ENTRYTYPE_MASK 3 200 #define PTE_ACCESS_MASK 0x1c 201 #define PTE_ACCESS_SHIFT 2 202 #define PTE_PPN_SHIFT 7 203 #define PTE_ADDR_MASK 0xffffff00 204 205 #define PG_ACCESSED_BIT 5 206 #define PG_MODIFIED_BIT 6 207 #define PG_CACHE_BIT 7 208 209 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 210 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 211 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 212 213 /* 3 <= NWINDOWS <= 32. */ 214 #define MIN_NWINDOWS 3 215 #define MAX_NWINDOWS 32 216 217 #ifdef TARGET_SPARC64 218 typedef struct trap_state { 219 uint64_t tpc; 220 uint64_t tnpc; 221 uint64_t tstate; 222 uint32_t tt; 223 } trap_state; 224 #endif 225 226 typedef struct sparc_def_t { 227 const char *name; 228 target_ulong iu_version; 229 uint32_t fpu_version; 230 uint32_t mmu_version; 231 uint32_t mmu_bm; 232 uint32_t mmu_ctpr_mask; 233 uint32_t mmu_cxr_mask; 234 uint32_t mmu_sfsr_mask; 235 uint32_t mmu_trcr_mask; 236 uint32_t mxcc_version; 237 uint32_t features; 238 uint32_t nwindows; 239 uint32_t maxtl; 240 } sparc_def_t; 241 242 #define FEATURE(X) CPU_FEATURE_BIT_##X, 243 enum { 244 #include "cpu-feature.h.inc" 245 }; 246 247 #undef FEATURE 248 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 249 250 enum { 251 #include "cpu-feature.h.inc" 252 }; 253 254 #undef FEATURE 255 256 #ifndef TARGET_SPARC64 257 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 258 CPU_FEATURE_FSMULD) 259 #else 260 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 261 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 262 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 263 enum { 264 mmu_us_12, // Ultrasparc < III (64 entry TLB) 265 mmu_us_3, // Ultrasparc III (512 entry TLB) 266 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 267 mmu_sun4v, // T1, T2 268 }; 269 #endif 270 271 #define TTE_VALID_BIT (1ULL << 63) 272 #define TTE_NFO_BIT (1ULL << 60) 273 #define TTE_IE_BIT (1ULL << 59) 274 #define TTE_USED_BIT (1ULL << 41) 275 #define TTE_LOCKED_BIT (1ULL << 6) 276 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 277 #define TTE_PRIV_BIT (1ULL << 2) 278 #define TTE_W_OK_BIT (1ULL << 1) 279 #define TTE_GLOBAL_BIT (1ULL << 0) 280 281 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 282 #define TTE_USED_BIT_UA2005 (1ULL << 47) 283 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 284 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 285 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 286 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 287 288 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 289 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 290 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 291 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 292 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 293 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 294 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 295 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 296 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 297 298 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 299 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 300 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 301 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 302 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 303 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 304 305 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 306 307 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 308 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 309 310 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 311 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 312 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 313 314 /* UltraSPARC T1 specific */ 315 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 316 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 317 318 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 319 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 320 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 321 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 322 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 323 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 324 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 325 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 326 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 327 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 328 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 329 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 330 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 331 332 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 333 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 334 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 335 #define SFSR_CT_SECONDARY (1ULL << 4) 336 #define SFSR_CT_NUCLEUS (2ULL << 4) 337 #define SFSR_CT_NOTRANS (3ULL << 4) 338 #define SFSR_CT_MASK (3ULL << 4) 339 340 /* Leon3 cache control */ 341 342 /* Cache control: emulate the behavior of cache control registers but without 343 any effect on the emulated */ 344 345 #define CACHE_STATE_MASK 0x3 346 #define CACHE_DISABLED 0x0 347 #define CACHE_FROZEN 0x1 348 #define CACHE_ENABLED 0x3 349 350 /* Cache Control register fields */ 351 352 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 353 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 354 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 355 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 356 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 357 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 358 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 359 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 360 361 #define CONVERT_BIT(X, SRC, DST) \ 362 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 363 364 typedef struct SparcTLBEntry { 365 uint64_t tag; 366 uint64_t tte; 367 } SparcTLBEntry; 368 369 struct CPUTimer 370 { 371 const char *name; 372 uint32_t frequency; 373 uint32_t disabled; 374 uint64_t disabled_mask; 375 uint32_t npt; 376 uint64_t npt_mask; 377 int64_t clock_offset; 378 QEMUTimer *qtimer; 379 }; 380 381 typedef struct CPUTimer CPUTimer; 382 383 typedef struct CPUArchState CPUSPARCState; 384 #if defined(TARGET_SPARC64) 385 typedef union { 386 uint64_t mmuregs[16]; 387 struct { 388 uint64_t tsb_tag_target; 389 uint64_t mmu_primary_context; 390 uint64_t mmu_secondary_context; 391 uint64_t sfsr; 392 uint64_t sfar; 393 uint64_t tsb; 394 uint64_t tag_access; 395 uint64_t virtual_watchpoint; 396 uint64_t physical_watchpoint; 397 uint64_t sun4v_ctx_config[2]; 398 uint64_t sun4v_tsb_pointers[4]; 399 }; 400 } SparcV9MMU; 401 #endif 402 struct CPUArchState { 403 target_ulong gregs[8]; /* general registers */ 404 target_ulong *regwptr; /* pointer to current register window */ 405 target_ulong pc; /* program counter */ 406 target_ulong npc; /* next program counter */ 407 target_ulong y; /* multiply/divide register */ 408 409 /* 410 * Bit 31 is for icc, bit 63 for xcc. 411 * Other bits are garbage. 412 */ 413 target_long cc_N; 414 target_long cc_V; 415 416 /* 417 * Z is represented as == 0; any non-zero value is !Z. 418 * For sparc64, the high 32-bits of icc.Z are garbage. 419 */ 420 target_ulong icc_Z; 421 #ifdef TARGET_SPARC64 422 target_ulong xcc_Z; 423 #endif 424 425 /* 426 * For sparc32, icc.C is boolean. 427 * For sparc64, xcc.C is boolean; 428 * icc.C is bit 32 with other bits garbage. 429 */ 430 target_ulong icc_C; 431 #ifdef TARGET_SPARC64 432 target_ulong xcc_C; 433 #endif 434 435 target_ulong cond; /* conditional branch result (XXX: save it in a 436 temporary register when possible) */ 437 438 /* FPU State Register, in parts */ 439 uint32_t fsr; /* rm, tem, aexc */ 440 uint32_t fsr_cexc_ftt; /* cexc, ftt */ 441 uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ 442 443 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 444 /* 445 * Single-element FPU fault queue, with address and insn, 446 * packaged into the double-word with which it is stored. 447 */ 448 uint32_t fsr_qne; /* qne */ 449 union { 450 uint64_t d; 451 struct { 452 #if HOST_BIG_ENDIAN 453 uint32_t addr; 454 uint32_t insn; 455 #else 456 uint32_t insn; 457 uint32_t addr; 458 #endif 459 } s; 460 } fq; 461 #endif 462 463 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 464 uint32_t cwp; /* index of current register window (extracted 465 from PSR) */ 466 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 467 uint32_t wim; /* window invalid mask */ 468 #endif 469 target_ulong tbr; /* trap base register */ 470 #if !defined(TARGET_SPARC64) 471 int psrs; /* supervisor mode (extracted from PSR) */ 472 int psrps; /* previous supervisor mode */ 473 int psret; /* enable traps */ 474 #endif 475 uint32_t psrpil; /* interrupt blocking level */ 476 uint32_t pil_in; /* incoming interrupt level bitmap */ 477 #if !defined(TARGET_SPARC64) 478 int psref; /* enable fpu */ 479 #endif 480 int interrupt_index; 481 /* NOTE: we allow 8 more registers to handle wrapping */ 482 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 483 484 /* Fields up to this point are cleared by a CPU reset */ 485 struct {} end_reset_fields; 486 487 /* Fields from here on are preserved across CPU reset. */ 488 target_ulong version; 489 uint32_t nwindows; 490 491 /* MMU regs */ 492 #if defined(TARGET_SPARC64) 493 uint64_t lsu; 494 #define DMMU_E 0x8 495 #define IMMU_E 0x4 496 SparcV9MMU immu; 497 SparcV9MMU dmmu; 498 SparcTLBEntry itlb[64]; 499 SparcTLBEntry dtlb[64]; 500 uint32_t mmu_version; 501 #else 502 uint32_t mmuregs[32]; 503 uint64_t mxccdata[4]; 504 uint64_t mxccregs[8]; 505 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 506 uint64_t mmubpaction; 507 uint64_t mmubpregs[4]; 508 uint64_t prom_addr; 509 #endif 510 float_status fp_status; 511 #if defined(TARGET_SPARC64) 512 #define MAXTL_MAX 8 513 #define MAXTL_MASK (MAXTL_MAX - 1) 514 trap_state ts[MAXTL_MAX]; 515 uint32_t asi; 516 uint32_t pstate; 517 uint32_t tl; 518 uint32_t maxtl; 519 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 520 uint64_t agregs[8]; /* alternate general registers */ 521 uint64_t bgregs[8]; /* backup for normal global registers */ 522 uint64_t igregs[8]; /* interrupt general registers */ 523 uint64_t mgregs[8]; /* mmu general registers */ 524 uint64_t glregs[8 * MAXTL_MAX]; 525 uint32_t fprs; 526 uint64_t tick_cmpr, stick_cmpr; 527 CPUTimer *tick, *stick; 528 #define TICK_NPT_MASK 0x8000000000000000ULL 529 #define TICK_INT_DIS 0x8000000000000000ULL 530 uint64_t gsr; 531 uint32_t gl; // UA2005 532 /* UA 2005 hyperprivileged registers */ 533 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 534 uint64_t scratch[8]; 535 CPUTimer *hstick; // UA 2005 536 /* Interrupt vector registers */ 537 uint64_t ivec_status; 538 uint64_t ivec_data[3]; 539 uint32_t softint; 540 #define SOFTINT_TIMER 1 541 #define SOFTINT_STIMER (1 << 16) 542 #define SOFTINT_INTRMASK (0xFFFE) 543 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 544 #endif 545 sparc_def_t def; 546 547 /* Leon3 */ 548 DeviceState *irq_manager; 549 void (*qemu_irq_ack)(CPUSPARCState *env, int intno); 550 uint32_t cache_control; 551 }; 552 553 /** 554 * SPARCCPU: 555 * @env: #CPUSPARCState 556 * 557 * A SPARC CPU. 558 */ 559 struct ArchCPU { 560 CPUState parent_obj; 561 562 CPUSPARCState env; 563 }; 564 565 /** 566 * SPARCCPUClass: 567 * @parent_realize: The parent class' realize handler. 568 * @parent_phases: The parent class' reset phase handlers. 569 * 570 * A SPARC CPU model. 571 */ 572 struct SPARCCPUClass { 573 CPUClass parent_class; 574 575 DeviceRealize parent_realize; 576 ResettablePhases parent_phases; 577 const sparc_def_t *cpu_def; 578 }; 579 580 #ifndef CONFIG_USER_ONLY 581 extern const VMStateDescription vmstate_sparc_cpu; 582 583 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 584 #endif 585 586 void sparc_cpu_do_interrupt(CPUState *cpu); 587 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 588 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 589 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 590 MMUAccessType access_type, 591 int mmu_idx, 592 uintptr_t retaddr); 593 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 594 595 /* cpu_init.c */ 596 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 597 /* mmu_helper.c */ 598 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 599 MMUAccessType access_type, int mmu_idx, 600 bool probe, uintptr_t retaddr); 601 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 602 void dump_mmu(CPUSPARCState *env); 603 604 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 605 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 606 uint8_t *buf, size_t len, bool is_write); 607 #endif 608 609 /* translate.c */ 610 void sparc_tcg_init(void); 611 void sparc_translate_code(CPUState *cs, TranslationBlock *tb, 612 int *max_insns, vaddr pc, void *host_pc); 613 614 /* fop_helper.c */ 615 target_ulong cpu_get_fsr(CPUSPARCState *); 616 void cpu_put_fsr(CPUSPARCState *, target_ulong); 617 618 /* win_helper.c */ 619 target_ulong cpu_get_psr(CPUSPARCState *env1); 620 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 621 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 622 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 623 #ifdef TARGET_SPARC64 624 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 625 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 626 #endif 627 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 628 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 629 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 630 631 /* sun4m.c, sun4u.c */ 632 void cpu_check_irqs(CPUSPARCState *env); 633 634 #if defined (TARGET_SPARC64) 635 636 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 637 { 638 return (x & mask) == (y & mask); 639 } 640 641 #define MMU_CONTEXT_BITS 13 642 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 643 644 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 645 uint64_t context) 646 { 647 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 648 } 649 650 #endif 651 652 /* cpu-exec.c */ 653 #if !defined(CONFIG_USER_ONLY) 654 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 655 vaddr addr, unsigned size, 656 MMUAccessType access_type, 657 int mmu_idx, MemTxAttrs attrs, 658 MemTxResult response, uintptr_t retaddr); 659 #if defined(TARGET_SPARC64) 660 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 661 int mmu_idx); 662 #endif 663 #endif 664 665 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 666 667 /* MMU modes definitions */ 668 #if defined (TARGET_SPARC64) 669 #define MMU_USER_IDX 0 670 #define MMU_USER_SECONDARY_IDX 1 671 #define MMU_KERNEL_IDX 2 672 #define MMU_KERNEL_SECONDARY_IDX 3 673 #define MMU_NUCLEUS_IDX 4 674 #define MMU_PHYS_IDX 5 675 #else 676 #define MMU_USER_IDX 0 677 #define MMU_KERNEL_IDX 1 678 #define MMU_PHYS_IDX 2 679 #endif 680 681 #if defined (TARGET_SPARC64) 682 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 683 { 684 return env1->def.features & CPU_FEATURE_HYPV; 685 } 686 687 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 688 { 689 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 690 } 691 692 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 693 { 694 return env1->pstate & PS_PRIV; 695 } 696 #else 697 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 698 { 699 return env1->psrs; 700 } 701 #endif 702 703 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 704 { 705 #if !defined (TARGET_SPARC64) 706 if (env1->psret != 0) 707 return 1; 708 #else 709 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 710 return 1; 711 } 712 #endif 713 714 return 0; 715 } 716 717 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 718 { 719 #if !defined(TARGET_SPARC64) 720 /* level 15 is non-maskable on sparc v8 */ 721 return pil == 15 || pil > env1->psrpil; 722 #else 723 return pil > env1->psrpil; 724 #endif 725 } 726 727 #ifdef TARGET_SPARC64 728 /* sun4u.c */ 729 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 730 uint64_t cpu_tick_get_count(CPUTimer *timer); 731 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 732 trap_state* cpu_tsptr(CPUSPARCState* env); 733 #endif 734 735 #define TB_FLAG_MMU_MASK 7 736 #define TB_FLAG_FPU_ENABLED (1 << 4) 737 #define TB_FLAG_AM_ENABLED (1 << 5) 738 #define TB_FLAG_SUPER (1 << 6) 739 #define TB_FLAG_HYPER (1 << 7) 740 #define TB_FLAG_FSR_QNE (1 << 8) 741 #define TB_FLAG_ASI_SHIFT 24 742 743 static inline bool tb_fpu_enabled(int tb_flags) 744 { 745 #if defined(CONFIG_USER_ONLY) 746 return true; 747 #else 748 return tb_flags & TB_FLAG_FPU_ENABLED; 749 #endif 750 } 751 752 static inline bool tb_am_enabled(int tb_flags) 753 { 754 #ifndef TARGET_SPARC64 755 return false; 756 #else 757 return tb_flags & TB_FLAG_AM_ENABLED; 758 #endif 759 } 760 761 #ifdef TARGET_SPARC64 762 /* win_helper.c */ 763 target_ulong cpu_get_ccr(CPUSPARCState *env1); 764 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 765 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 766 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 767 768 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 769 { 770 uint64_t tstate = (cpu_get_ccr(env) << 32) | 771 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 772 cpu_get_cwp64(env); 773 774 if (env->def.features & CPU_FEATURE_GL) { 775 tstate |= (env->gl & 7ULL) << 40; 776 } 777 return tstate; 778 } 779 #endif 780 781 #endif 782