1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #ifndef __ISYS_IRQ_PRIVATE_H__
17 #define __ISYS_IRQ_PRIVATE_H__
18
19 #include "isys_irq_global.h"
20 #include "isys_irq_local.h"
21
22 #if defined(ISP2401)
23
24 /* -------------------------------------------------------+
25 | Native command interface (NCI) |
26 + -------------------------------------------------------*/
27
28 /**
29 * @brief Get the isys irq status.
30 * Refer to "isys_irq.h" for details.
31 */
isys_irqc_state_get(const isys_irq_ID_t isys_irqc_id,isys_irqc_state_t * state)32 void isys_irqc_state_get(
33 const isys_irq_ID_t isys_irqc_id,
34 isys_irqc_state_t *state)
35 {
36 state->edge = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_EDGE_REG_IDX);
37 state->mask = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX);
38 state->status = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_STATUS_REG_IDX);
39 state->enable = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX);
40 state->level_no = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_LEVEL_NO_REG_IDX);
41 /*
42 ** Invalid to read/load from write-only register 'clear'
43 ** state->clear = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX);
44 */
45 }
46
47 /**
48 * @brief Dump the isys irq status.
49 * Refer to "isys_irq.h" for details.
50 */
isys_irqc_state_dump(const isys_irq_ID_t isys_irqc_id,const isys_irqc_state_t * state)51 void isys_irqc_state_dump(
52 const isys_irq_ID_t isys_irqc_id,
53 const isys_irqc_state_t *state)
54 {
55 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
56 "isys irq controller id %d\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
57 isys_irqc_id,
58 state->status, state->edge, state->mask, state->enable, state->level_no);
59 }
60
61 /* end of NCI */
62
63 /* -------------------------------------------------------+
64 | Device level interface (DLI) |
65 + -------------------------------------------------------*/
66
67 /* Support functions */
isys_irqc_reg_store(const isys_irq_ID_t isys_irqc_id,const unsigned int reg_idx,const hrt_data value)68 void isys_irqc_reg_store(
69 const isys_irq_ID_t isys_irqc_id,
70 const unsigned int reg_idx,
71 const hrt_data value)
72 {
73 unsigned int reg_addr;
74
75 assert(isys_irqc_id < N_ISYS_IRQ_ID);
76 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
77
78 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
79 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
80 "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);
81
82 ia_css_device_store_uint32(reg_addr, value);
83 }
84
isys_irqc_reg_load(const isys_irq_ID_t isys_irqc_id,const unsigned int reg_idx)85 hrt_data isys_irqc_reg_load(
86 const isys_irq_ID_t isys_irqc_id,
87 const unsigned int reg_idx)
88 {
89 unsigned int reg_addr;
90 hrt_data value;
91
92 assert(isys_irqc_id < N_ISYS_IRQ_ID);
93 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
94
95 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
96 value = ia_css_device_load_uint32(reg_addr);
97 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
98 "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);
99
100 return value;
101 }
102
103 /* end of DLI */
104
105 #endif /* defined(ISP2401) */
106
107 #endif /* __ISYS_IRQ_PRIVATE_H__ */
108