xref: /openbmc/qemu/hw/pci/pci_host.c (revision 93829009)
1 /*
2  * pci_host.c
3  *
4  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5  *                    VA Linux Systems Japan K.K.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11 
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16 
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/pci_host.h"
25 #include "hw/qdev-properties.h"
26 #include "qemu/module.h"
27 #include "hw/pci/pci_bus.h"
28 #include "migration/vmstate.h"
29 #include "trace.h"
30 
31 /* debug PCI */
32 //#define DEBUG_PCI
33 
34 #ifdef DEBUG_PCI
35 #define PCI_DPRINTF(fmt, ...) \
36 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
37 #else
38 #define PCI_DPRINTF(fmt, ...)
39 #endif
40 
41 /*
42  * PCI address
43  * bit 16 - 24: bus number
44  * bit  8 - 15: devfun number
45  * bit  0 -  7: offset in configuration space of a given pci device
46  */
47 
48 /* the helper function to get a PCIDevice* for a given pci address */
pci_dev_find_by_addr(PCIBus * bus,uint32_t addr)49 static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
50 {
51     uint8_t bus_num = addr >> 16;
52     uint8_t devfn = addr >> 8;
53 
54     return pci_find_device(bus, bus_num, devfn);
55 }
56 
pci_adjust_config_limit(PCIBus * bus,uint32_t * limit)57 static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit)
58 {
59     if ((*limit > PCI_CONFIG_SPACE_SIZE) &&
60         !pci_bus_allows_extended_config_space(bus)) {
61         *limit = PCI_CONFIG_SPACE_SIZE;
62     }
63 }
64 
is_pci_dev_ejected(PCIDevice * pci_dev)65 static bool is_pci_dev_ejected(PCIDevice *pci_dev)
66 {
67     /*
68      * device unplug was requested and the guest acked it,
69      * so we stop responding config accesses even if the
70      * device is not deleted (failover flow)
71      */
72     return pci_dev && pci_dev->partially_hotplugged &&
73            !pci_dev->qdev.pending_deleted_event;
74 }
75 
pci_host_config_write_common(PCIDevice * pci_dev,uint32_t addr,uint32_t limit,uint32_t val,uint32_t len)76 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
77                                   uint32_t limit, uint32_t val, uint32_t len)
78 {
79     pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
80     if (limit <= addr) {
81         return;
82     }
83 
84     assert(len <= 4);
85     /* non-zero functions are only exposed when function 0 is present,
86      * allowing direct removal of unexposed functions.
87      */
88     if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) ||
89         !pci_dev->has_power || is_pci_dev_ejected(pci_dev)) {
90         return;
91     }
92 
93     trace_pci_cfg_write(pci_dev->name, pci_dev_bus_num(pci_dev),
94                         PCI_SLOT(pci_dev->devfn),
95                         PCI_FUNC(pci_dev->devfn), addr, val);
96     pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
97 }
98 
pci_host_config_read_common(PCIDevice * pci_dev,uint32_t addr,uint32_t limit,uint32_t len)99 uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
100                                      uint32_t limit, uint32_t len)
101 {
102     uint32_t ret;
103 
104     pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
105     if (limit <= addr) {
106         return ~0x0;
107     }
108 
109     assert(len <= 4);
110     /* non-zero functions are only exposed when function 0 is present,
111      * allowing direct removal of unexposed functions.
112      */
113     if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) ||
114         !pci_dev->has_power || is_pci_dev_ejected(pci_dev)) {
115         return ~0x0;
116     }
117 
118     ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
119     trace_pci_cfg_read(pci_dev->name, pci_dev_bus_num(pci_dev),
120                        PCI_SLOT(pci_dev->devfn),
121                        PCI_FUNC(pci_dev->devfn), addr, ret);
122 
123     return ret;
124 }
125 
pci_data_write(PCIBus * s,uint32_t addr,uint32_t val,unsigned len)126 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len)
127 {
128     PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
129     uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
130 
131     if (!pci_dev) {
132         trace_pci_cfg_write("empty", extract32(addr, 16, 8),
133                             extract32(addr, 11, 5), extract32(addr, 8, 3),
134                             config_addr, val);
135         return;
136     }
137 
138     pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
139                                  val, len);
140 }
141 
pci_data_read(PCIBus * s,uint32_t addr,unsigned len)142 uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len)
143 {
144     PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
145     uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
146 
147     if (!pci_dev) {
148         trace_pci_cfg_read("empty", extract32(addr, 16, 8),
149                            extract32(addr, 11, 5), extract32(addr, 8, 3),
150                            config_addr, ~0x0);
151         return ~0x0;
152     }
153 
154     return pci_host_config_read_common(pci_dev, config_addr,
155                                        PCI_CONFIG_SPACE_SIZE, len);
156 }
157 
pci_host_config_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)158 static void pci_host_config_write(void *opaque, hwaddr addr,
159                                   uint64_t val, unsigned len)
160 {
161     PCIHostState *s = opaque;
162 
163     PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx64"\n",
164                 __func__, addr, len, val);
165     if (addr != 0 || len != 4) {
166         return;
167     }
168     s->config_reg = val;
169 }
170 
pci_host_config_read(void * opaque,hwaddr addr,unsigned len)171 static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
172                                      unsigned len)
173 {
174     PCIHostState *s = opaque;
175     uint32_t val = s->config_reg;
176 
177     PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx32"\n",
178                 __func__, addr, len, val);
179     return val;
180 }
181 
pci_host_data_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)182 static void pci_host_data_write(void *opaque, hwaddr addr,
183                                 uint64_t val, unsigned len)
184 {
185     PCIHostState *s = opaque;
186 
187     if (s->config_reg & (1u << 31))
188         pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
189 }
190 
pci_host_data_read(void * opaque,hwaddr addr,unsigned len)191 static uint64_t pci_host_data_read(void *opaque,
192                                    hwaddr addr, unsigned len)
193 {
194     PCIHostState *s = opaque;
195 
196     if (!(s->config_reg & (1U << 31))) {
197         return 0xffffffff;
198     }
199     return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
200 }
201 
202 const MemoryRegionOps pci_host_conf_le_ops = {
203     .read = pci_host_config_read,
204     .write = pci_host_config_write,
205     .endianness = DEVICE_LITTLE_ENDIAN,
206 };
207 
208 const MemoryRegionOps pci_host_conf_be_ops = {
209     .read = pci_host_config_read,
210     .write = pci_host_config_write,
211     .endianness = DEVICE_BIG_ENDIAN,
212 };
213 
214 const MemoryRegionOps pci_host_data_le_ops = {
215     .read = pci_host_data_read,
216     .write = pci_host_data_write,
217     .endianness = DEVICE_LITTLE_ENDIAN,
218 };
219 
220 const MemoryRegionOps pci_host_data_be_ops = {
221     .read = pci_host_data_read,
222     .write = pci_host_data_write,
223     .endianness = DEVICE_BIG_ENDIAN,
224 };
225 
pci_host_needed(void * opaque)226 static bool pci_host_needed(void *opaque)
227 {
228     PCIHostState *s = opaque;
229     return s->mig_enabled;
230 }
231 
232 const VMStateDescription vmstate_pcihost = {
233     .name = "PCIHost",
234     .needed = pci_host_needed,
235     .version_id = 1,
236     .minimum_version_id = 1,
237     .fields = (const VMStateField[]) {
238         VMSTATE_UINT32(config_reg, PCIHostState),
239         VMSTATE_END_OF_LIST()
240     }
241 };
242 
243 static Property pci_host_properties_common[] = {
244     DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState,
245                      mig_enabled, true),
246     DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, false),
247     DEFINE_PROP_END_OF_LIST(),
248 };
249 
pci_host_class_init(ObjectClass * klass,void * data)250 static void pci_host_class_init(ObjectClass *klass, void *data)
251 {
252     DeviceClass *dc = DEVICE_CLASS(klass);
253     device_class_set_props(dc, pci_host_properties_common);
254     dc->vmsd = &vmstate_pcihost;
255 }
256 
257 static const TypeInfo pci_host_type_info = {
258     .name = TYPE_PCI_HOST_BRIDGE,
259     .parent = TYPE_SYS_BUS_DEVICE,
260     .abstract = true,
261     .class_size = sizeof(PCIHostBridgeClass),
262     .instance_size = sizeof(PCIHostState),
263     .class_init = pci_host_class_init,
264 };
265 
pci_host_register_types(void)266 static void pci_host_register_types(void)
267 {
268     type_register_static(&pci_host_type_info);
269 }
270 
271 type_init(pci_host_register_types)
272