1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements dp specific link capability retrieval sequence. It is
28 * responsible for retrieving, parsing, overriding, deciding capability obtained
29 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
30 * usb and all other possible backend capabilities. Other components should
31 * include this header file in order to access link capability. Accessing link
32 * capability by dereferencing dc_link outside dp_link_capability is not a
33 * recommended method as it makes the component dependent on the underlying data
34 * structure used to represent link capability instead of function interfaces.
35 */
36
37 #include "link_dp_capability.h"
38 #include "link_ddc.h"
39 #include "link_dpcd.h"
40 #include "link_dp_dpia.h"
41 #include "link_dp_phy.h"
42 #include "link_edp_panel_control.h"
43 #include "link_dp_irq_handler.h"
44 #include "link/accessories/link_dp_trace.h"
45 #include "link/link_detection.h"
46 #include "link/link_validation.h"
47 #include "link_dp_training.h"
48 #include "atomfirmware.h"
49 #include "resource.h"
50 #include "link_enc_cfg.h"
51 #include "dc_dmub_srv.h"
52 #include "gpio_service_interface.h"
53
54 #define DC_LOGGER \
55 link->ctx->logger
56 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
57
58 #ifndef MAX
59 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
60 #endif
61 #ifndef MIN
62 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
63 #endif
64
65 struct dp_lt_fallback_entry {
66 enum dc_lane_count lane_count;
67 enum dc_link_rate link_rate;
68 };
69
70 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
71 /* This link training fallback array is ordered by
72 * link bandwidth from highest to lowest.
73 * DP specs makes it a normative policy to always
74 * choose the next highest link bandwidth during
75 * link training fallback.
76 */
77 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
78 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
79 {LANE_COUNT_TWO, LINK_RATE_UHBR20},
80 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
81 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
82 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
83 {LANE_COUNT_ONE, LINK_RATE_UHBR20},
84 {LANE_COUNT_TWO, LINK_RATE_UHBR10},
85 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
86 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
87 {LANE_COUNT_TWO, LINK_RATE_HIGH3},
88 {LANE_COUNT_ONE, LINK_RATE_UHBR10},
89 {LANE_COUNT_TWO, LINK_RATE_HIGH2},
90 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
91 {LANE_COUNT_ONE, LINK_RATE_HIGH3},
92 {LANE_COUNT_FOUR, LINK_RATE_LOW},
93 {LANE_COUNT_ONE, LINK_RATE_HIGH2},
94 {LANE_COUNT_TWO, LINK_RATE_HIGH},
95 {LANE_COUNT_TWO, LINK_RATE_LOW},
96 {LANE_COUNT_ONE, LINK_RATE_HIGH},
97 {LANE_COUNT_ONE, LINK_RATE_LOW},
98 };
99
100 static const struct dc_link_settings fail_safe_link_settings = {
101 .lane_count = LANE_COUNT_ONE,
102 .link_rate = LINK_RATE_LOW,
103 .link_spread = LINK_SPREAD_DISABLED,
104 };
105
is_dp_active_dongle(const struct dc_link * link)106 bool is_dp_active_dongle(const struct dc_link *link)
107 {
108 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
109 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
110 }
111
is_dp_branch_device(const struct dc_link * link)112 bool is_dp_branch_device(const struct dc_link *link)
113 {
114 return link->dpcd_caps.is_branch_dev;
115 }
116
translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)117 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
118 {
119 switch (bpc) {
120 case DOWN_STREAM_MAX_8BPC:
121 return 8;
122 case DOWN_STREAM_MAX_10BPC:
123 return 10;
124 case DOWN_STREAM_MAX_12BPC:
125 return 12;
126 case DOWN_STREAM_MAX_16BPC:
127 return 16;
128 default:
129 break;
130 }
131
132 return -1;
133 }
134
dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)135 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
136 {
137 switch (lttpr_repeater_count) {
138 case 0x80: // 1 lttpr repeater
139 return 1;
140 case 0x40: // 2 lttpr repeaters
141 return 2;
142 case 0x20: // 3 lttpr repeaters
143 return 3;
144 case 0x10: // 4 lttpr repeaters
145 return 4;
146 case 0x08: // 5 lttpr repeaters
147 return 5;
148 case 0x04: // 6 lttpr repeaters
149 return 6;
150 case 0x02: // 7 lttpr repeaters
151 return 7;
152 case 0x01: // 8 lttpr repeaters
153 return 8;
154 default:
155 break;
156 }
157 return 0; // invalid value
158 }
159
link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)160 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
161 {
162 switch (bw) {
163 case 0b001:
164 return 9000000;
165 case 0b010:
166 return 18000000;
167 case 0b011:
168 return 24000000;
169 case 0b100:
170 return 32000000;
171 case 0b101:
172 return 40000000;
173 case 0b110:
174 return 48000000;
175 }
176
177 return 0;
178 }
179
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)180 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
181 {
182 enum dc_link_rate link_rate;
183 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
184 switch (link_rate_in_khz) {
185 case 1620000:
186 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
187 break;
188 case 2160000:
189 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
190 break;
191 case 2430000:
192 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
193 break;
194 case 2700000:
195 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
196 break;
197 case 3240000:
198 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane
199 break;
200 case 4320000:
201 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
202 break;
203 case 5400000:
204 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane
205 break;
206 case 6750000:
207 link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane
208 break;
209 case 8100000:
210 link_rate = LINK_RATE_HIGH3; // Rate_9 (HBR3)- 8.10 Gbps/Lane
211 break;
212 default:
213 link_rate = LINK_RATE_UNKNOWN;
214 break;
215 }
216 return link_rate;
217 }
218
intersect_cable_id(union dp_cable_id * a,union dp_cable_id * b)219 static union dp_cable_id intersect_cable_id(
220 union dp_cable_id *a, union dp_cable_id *b)
221 {
222 union dp_cable_id out;
223
224 out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
225 b->bits.UHBR10_20_CAPABILITY);
226 out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
227 b->bits.UHBR13_5_CAPABILITY);
228 out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
229
230 return out;
231 }
232
233 /*
234 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
235 */
intersect_frl_link_bw_support(const uint32_t max_supported_frl_bw_in_kbps,const union hdmi_encoded_link_bw hdmi_encoded_link_bw)236 static uint32_t intersect_frl_link_bw_support(
237 const uint32_t max_supported_frl_bw_in_kbps,
238 const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
239 {
240 uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
241
242 // HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode)
243 if (hdmi_encoded_link_bw.bits.FRL_MODE) {
244 if (hdmi_encoded_link_bw.bits.BW_48Gbps)
245 supported_bw_in_kbps = 48000000;
246 else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
247 supported_bw_in_kbps = 40000000;
248 else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
249 supported_bw_in_kbps = 32000000;
250 else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
251 supported_bw_in_kbps = 24000000;
252 else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
253 supported_bw_in_kbps = 18000000;
254 else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
255 supported_bw_in_kbps = 9000000;
256 }
257
258 return supported_bw_in_kbps;
259 }
260
get_clock_source_id(struct dc_link * link)261 static enum clock_source_id get_clock_source_id(struct dc_link *link)
262 {
263 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
264 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
265
266 if (dp_cs != NULL) {
267 dp_cs_id = dp_cs->id;
268 } else {
269 /*
270 * dp clock source is not initialized for some reason.
271 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
272 */
273 ASSERT(dp_cs);
274 }
275
276 return dp_cs_id;
277 }
278
dp_wa_power_up_0010FA(struct dc_link * link,uint8_t * dpcd_data,int length)279 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
280 int length)
281 {
282 int retry = 0;
283
284 if (!link->dpcd_caps.dpcd_rev.raw) {
285 do {
286 dpcd_write_rx_power_ctrl(link, true);
287 core_link_read_dpcd(link, DP_DPCD_REV,
288 dpcd_data, length);
289 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
290 DP_DPCD_REV -
291 DP_DPCD_REV];
292 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
293 }
294
295 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
296 switch (link->dpcd_caps.branch_dev_id) {
297 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
298 * all internal circuits including AUX communication preventing
299 * reading DPCD table and EDID (spec violation).
300 * Encoder will skip DP RX power down on disable_output to
301 * keep receiver powered all the time.*/
302 case DP_BRANCH_DEVICE_ID_0010FA:
303 case DP_BRANCH_DEVICE_ID_0080E1:
304 case DP_BRANCH_DEVICE_ID_00E04C:
305 link->wa_flags.dp_keep_receiver_powered = true;
306 break;
307
308 /* TODO: May need work around for other dongles. */
309 default:
310 link->wa_flags.dp_keep_receiver_powered = false;
311 break;
312 }
313 } else
314 link->wa_flags.dp_keep_receiver_powered = false;
315 }
316
dp_is_fec_supported(const struct dc_link * link)317 bool dp_is_fec_supported(const struct dc_link *link)
318 {
319 /* TODO - use asic cap instead of link_enc->features
320 * we no longer know which link enc to use for this link before commit
321 */
322 struct link_encoder *link_enc = NULL;
323
324 link_enc = link_enc_cfg_get_link_enc(link);
325 ASSERT(link_enc);
326
327 return (dc_is_dp_signal(link->connector_signal) && link_enc &&
328 link_enc->features.fec_supported &&
329 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);
330 }
331
dp_should_enable_fec(const struct dc_link * link)332 bool dp_should_enable_fec(const struct dc_link *link)
333 {
334 bool force_disable = false;
335
336 if (link->fec_state == dc_link_fec_enabled)
337 force_disable = false;
338 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
339 link->local_sink &&
340 link->local_sink->edid_caps.panel_patch.disable_fec)
341 force_disable = true;
342 else if (link->connector_signal == SIGNAL_TYPE_EDP
343 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
344 dsc_support.DSC_SUPPORT == false
345 || link->panel_config.dsc.disable_dsc_edp
346 || !link->dc->caps.edp_dsc_support))
347 force_disable = true;
348
349 return !force_disable && dp_is_fec_supported(link);
350 }
351
dp_is_128b_132b_signal(struct pipe_ctx * pipe_ctx)352 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
353 {
354 /* If this assert is hit then we have a link encoder dynamic management issue */
355 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
356 return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
357 pipe_ctx->link_res.hpo_dp_link_enc &&
358 dc_is_dp_signal(pipe_ctx->stream->signal));
359 }
360
dp_is_lttpr_present(struct dc_link * link)361 bool dp_is_lttpr_present(struct dc_link *link)
362 {
363 return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
364 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
365 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
366 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
367 }
368
369 /* in DP compliance test, DPR-120 may have
370 * a random value in its MAX_LINK_BW dpcd field.
371 * We map it to the maximum supported link rate that
372 * is smaller than MAX_LINK_BW in this case.
373 */
get_link_rate_from_max_link_bw(uint8_t max_link_bw)374 static enum dc_link_rate get_link_rate_from_max_link_bw(
375 uint8_t max_link_bw)
376 {
377 enum dc_link_rate link_rate;
378
379 if (max_link_bw >= LINK_RATE_HIGH3) {
380 link_rate = LINK_RATE_HIGH3;
381 } else if (max_link_bw < LINK_RATE_HIGH3
382 && max_link_bw >= LINK_RATE_HIGH2) {
383 link_rate = LINK_RATE_HIGH2;
384 } else if (max_link_bw < LINK_RATE_HIGH2
385 && max_link_bw >= LINK_RATE_HIGH) {
386 link_rate = LINK_RATE_HIGH;
387 } else if (max_link_bw < LINK_RATE_HIGH
388 && max_link_bw >= LINK_RATE_LOW) {
389 link_rate = LINK_RATE_LOW;
390 } else {
391 link_rate = LINK_RATE_UNKNOWN;
392 }
393
394 return link_rate;
395 }
396
get_lttpr_max_link_rate(struct dc_link * link)397 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
398 {
399 enum dc_link_rate lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
400
401 if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
402 lttpr_max_link_rate = LINK_RATE_UHBR20;
403 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
404 lttpr_max_link_rate = LINK_RATE_UHBR13_5;
405 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
406 lttpr_max_link_rate = LINK_RATE_UHBR10;
407
408 return lttpr_max_link_rate;
409 }
410
get_cable_max_link_rate(struct dc_link * link)411 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
412 {
413 enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;
414
415 if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20)
416 cable_max_link_rate = LINK_RATE_UHBR20;
417 else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)
418 cable_max_link_rate = LINK_RATE_UHBR13_5;
419 else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10)
420 cable_max_link_rate = LINK_RATE_UHBR10;
421
422 return cable_max_link_rate;
423 }
424
reached_minimum_lane_count(enum dc_lane_count lane_count)425 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
426 {
427 return lane_count <= LANE_COUNT_ONE;
428 }
429
reached_minimum_link_rate(enum dc_link_rate link_rate)430 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
431 {
432 return link_rate <= LINK_RATE_LOW;
433 }
434
reduce_lane_count(enum dc_lane_count lane_count)435 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
436 {
437 switch (lane_count) {
438 case LANE_COUNT_FOUR:
439 return LANE_COUNT_TWO;
440 case LANE_COUNT_TWO:
441 return LANE_COUNT_ONE;
442 case LANE_COUNT_ONE:
443 return LANE_COUNT_UNKNOWN;
444 default:
445 return LANE_COUNT_UNKNOWN;
446 }
447 }
448
reduce_link_rate(const struct dc_link * link,enum dc_link_rate link_rate)449 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate)
450 {
451 // NEEDSWORK: provide some details about why this function never returns some of the
452 // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended.
453 //
454
455 switch (link_rate) {
456 case LINK_RATE_UHBR20:
457 return LINK_RATE_UHBR13_5;
458 case LINK_RATE_UHBR13_5:
459 return LINK_RATE_UHBR10;
460 case LINK_RATE_UHBR10:
461 return LINK_RATE_HIGH3;
462 case LINK_RATE_HIGH3:
463 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)
464 return LINK_RATE_RATE_8;
465 return LINK_RATE_HIGH2;
466 case LINK_RATE_RATE_8:
467 return LINK_RATE_HIGH2;
468 case LINK_RATE_HIGH2:
469 return LINK_RATE_HIGH;
470 case LINK_RATE_RATE_6:
471 case LINK_RATE_RBR2:
472 return LINK_RATE_HIGH;
473 case LINK_RATE_HIGH:
474 return LINK_RATE_LOW;
475 case LINK_RATE_RATE_3:
476 case LINK_RATE_RATE_2:
477 return LINK_RATE_LOW;
478 case LINK_RATE_LOW:
479 default:
480 return LINK_RATE_UNKNOWN;
481 }
482 }
483
increase_lane_count(enum dc_lane_count lane_count)484 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
485 {
486 switch (lane_count) {
487 case LANE_COUNT_ONE:
488 return LANE_COUNT_TWO;
489 case LANE_COUNT_TWO:
490 return LANE_COUNT_FOUR;
491 default:
492 return LANE_COUNT_UNKNOWN;
493 }
494 }
495
increase_link_rate(struct dc_link * link,enum dc_link_rate link_rate)496 static enum dc_link_rate increase_link_rate(struct dc_link *link,
497 enum dc_link_rate link_rate)
498 {
499 switch (link_rate) {
500 case LINK_RATE_LOW:
501 return LINK_RATE_HIGH;
502 case LINK_RATE_HIGH:
503 return LINK_RATE_HIGH2;
504 case LINK_RATE_HIGH2:
505 return LINK_RATE_HIGH3;
506 case LINK_RATE_HIGH3:
507 return LINK_RATE_UHBR10;
508 case LINK_RATE_UHBR10:
509 /* upto DP2.x specs UHBR13.5 is the only link rate that could be
510 * not supported by DPRX when higher link rate is supported.
511 * so we treat it as a special case for code simplicity. When we
512 * have new specs with more link rates like this, we should
513 * consider a more generic solution to handle discrete link
514 * rate capabilities.
515 */
516 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?
517 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20;
518 case LINK_RATE_UHBR13_5:
519 return LINK_RATE_UHBR20;
520 default:
521 return LINK_RATE_UNKNOWN;
522 }
523 }
524
decide_fallback_link_setting_max_bw_policy(struct dc_link * link,const struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)525 static bool decide_fallback_link_setting_max_bw_policy(
526 struct dc_link *link,
527 const struct dc_link_settings *max,
528 struct dc_link_settings *cur,
529 enum link_training_result training_result)
530 {
531 uint8_t cur_idx = 0, next_idx;
532 bool found = false;
533
534 if (training_result == LINK_TRAINING_ABORT)
535 return false;
536
537 while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
538 /* find current index */
539 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
540 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
541 break;
542 else
543 cur_idx++;
544
545 next_idx = cur_idx + 1;
546
547 while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
548 /* find next index */
549 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count ||
550 dp_lt_fallbacks[next_idx].link_rate > max->link_rate)
551 next_idx++;
552 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 &&
553 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)
554 /* upto DP2.x specs UHBR13.5 is the only link rate that
555 * could be not supported by DPRX when higher link rate
556 * is supported. so we treat it as a special case for
557 * code simplicity. When we have new specs with more
558 * link rates like this, we should consider a more
559 * generic solution to handle discrete link rate
560 * capabilities.
561 */
562 next_idx++;
563 else
564 break;
565
566 if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
567 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
568 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
569 found = true;
570 }
571
572 return found;
573 }
574
575 /*
576 * function: set link rate and lane count fallback based
577 * on current link setting and last link training result
578 * return value:
579 * true - link setting could be set
580 * false - has reached minimum setting
581 * and no further fallback could be done
582 */
decide_fallback_link_setting(struct dc_link * link,struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)583 bool decide_fallback_link_setting(
584 struct dc_link *link,
585 struct dc_link_settings *max,
586 struct dc_link_settings *cur,
587 enum link_training_result training_result)
588 {
589 if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING ||
590 link->dc->debug.force_dp2_lt_fallback_method)
591 return decide_fallback_link_setting_max_bw_policy(link, max,
592 cur, training_result);
593
594 switch (training_result) {
595 case LINK_TRAINING_CR_FAIL_LANE0:
596 case LINK_TRAINING_CR_FAIL_LANE1:
597 case LINK_TRAINING_CR_FAIL_LANE23:
598 case LINK_TRAINING_LQA_FAIL:
599 {
600 if (!reached_minimum_link_rate(cur->link_rate)) {
601 cur->link_rate = reduce_link_rate(link, cur->link_rate);
602 } else if (!reached_minimum_lane_count(cur->lane_count)) {
603 cur->link_rate = max->link_rate;
604 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
605 return false;
606 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
607 cur->lane_count = LANE_COUNT_ONE;
608 else if (training_result == LINK_TRAINING_CR_FAIL_LANE23)
609 cur->lane_count = LANE_COUNT_TWO;
610 else
611 cur->lane_count = reduce_lane_count(cur->lane_count);
612 } else {
613 return false;
614 }
615 break;
616 }
617 case LINK_TRAINING_EQ_FAIL_EQ:
618 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
619 {
620 if (!reached_minimum_lane_count(cur->lane_count)) {
621 cur->lane_count = reduce_lane_count(cur->lane_count);
622 } else if (!reached_minimum_link_rate(cur->link_rate)) {
623 cur->link_rate = reduce_link_rate(link, cur->link_rate);
624 /* Reduce max link rate to avoid potential infinite loop.
625 * Needed so that any subsequent CR_FAIL fallback can't
626 * re-set the link rate higher than the link rate from
627 * the latest EQ_FAIL fallback.
628 */
629 max->link_rate = cur->link_rate;
630 cur->lane_count = max->lane_count;
631 } else {
632 return false;
633 }
634 break;
635 }
636 case LINK_TRAINING_EQ_FAIL_CR:
637 {
638 if (!reached_minimum_link_rate(cur->link_rate)) {
639 cur->link_rate = reduce_link_rate(link, cur->link_rate);
640 /* Reduce max link rate to avoid potential infinite loop.
641 * Needed so that any subsequent CR_FAIL fallback can't
642 * re-set the link rate higher than the link rate from
643 * the latest EQ_FAIL fallback.
644 */
645 max->link_rate = cur->link_rate;
646 cur->lane_count = max->lane_count;
647 } else {
648 return false;
649 }
650 break;
651 }
652 default:
653 return false;
654 }
655 return true;
656 }
decide_dp_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)657 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
658 {
659 struct dc_link_settings initial_link_setting = {
660 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
661 struct dc_link_settings current_link_setting =
662 initial_link_setting;
663 uint32_t link_bw;
664
665 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
666 return false;
667
668 /* search for the minimum link setting that:
669 * 1. is supported according to the link training result
670 * 2. could support the b/w requested by the timing
671 */
672 while (current_link_setting.link_rate <=
673 link->verified_link_cap.link_rate) {
674 link_bw = dp_link_bandwidth_kbps(
675 link,
676 ¤t_link_setting);
677 if (req_bw <= link_bw) {
678 *link_setting = current_link_setting;
679 return true;
680 }
681
682 if (current_link_setting.lane_count <
683 link->verified_link_cap.lane_count) {
684 current_link_setting.lane_count =
685 increase_lane_count(
686 current_link_setting.lane_count);
687 } else {
688 current_link_setting.link_rate =
689 increase_link_rate(link,
690 current_link_setting.link_rate);
691 current_link_setting.lane_count =
692 initial_link_setting.lane_count;
693 }
694 }
695
696 return false;
697 }
698
edp_decide_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)699 bool edp_decide_link_settings(struct dc_link *link,
700 struct dc_link_settings *link_setting, uint32_t req_bw)
701 {
702 struct dc_link_settings initial_link_setting;
703 struct dc_link_settings current_link_setting;
704 uint32_t link_bw;
705
706 /*
707 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
708 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
709 */
710 if (!edp_is_ilr_optimization_enabled(link)) {
711 *link_setting = link->verified_link_cap;
712 return true;
713 }
714
715 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
716 initial_link_setting.lane_count = LANE_COUNT_ONE;
717 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
718 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
719 initial_link_setting.use_link_rate_set = true;
720 initial_link_setting.link_rate_set = 0;
721 current_link_setting = initial_link_setting;
722
723 /* search for the minimum link setting that:
724 * 1. is supported according to the link training result
725 * 2. could support the b/w requested by the timing
726 */
727 while (current_link_setting.link_rate <=
728 link->verified_link_cap.link_rate) {
729 link_bw = dp_link_bandwidth_kbps(
730 link,
731 ¤t_link_setting);
732 if (req_bw <= link_bw) {
733 *link_setting = current_link_setting;
734 return true;
735 }
736
737 if (current_link_setting.lane_count <
738 link->verified_link_cap.lane_count) {
739 current_link_setting.lane_count =
740 increase_lane_count(
741 current_link_setting.lane_count);
742 } else {
743 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
744 current_link_setting.link_rate_set++;
745 current_link_setting.link_rate =
746 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
747 current_link_setting.lane_count =
748 initial_link_setting.lane_count;
749 } else
750 break;
751 }
752 }
753 return false;
754 }
755
decide_edp_link_settings_with_dsc(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw,enum dc_link_rate max_link_rate)756 bool decide_edp_link_settings_with_dsc(struct dc_link *link,
757 struct dc_link_settings *link_setting,
758 uint32_t req_bw,
759 enum dc_link_rate max_link_rate)
760 {
761 struct dc_link_settings initial_link_setting;
762 struct dc_link_settings current_link_setting;
763 uint32_t link_bw;
764
765 unsigned int policy = 0;
766
767 policy = link->panel_config.dsc.force_dsc_edp_policy;
768 if (max_link_rate == LINK_RATE_UNKNOWN)
769 max_link_rate = link->verified_link_cap.link_rate;
770 /*
771 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
772 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
773 */
774 if (!edp_is_ilr_optimization_enabled(link)) {
775 /* for DSC enabled case, we search for minimum lane count */
776 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
777 initial_link_setting.lane_count = LANE_COUNT_ONE;
778 initial_link_setting.link_rate = LINK_RATE_LOW;
779 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
780 initial_link_setting.use_link_rate_set = false;
781 initial_link_setting.link_rate_set = 0;
782 current_link_setting = initial_link_setting;
783 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
784 return false;
785
786 /* search for the minimum link setting that:
787 * 1. is supported according to the link training result
788 * 2. could support the b/w requested by the timing
789 */
790 while (current_link_setting.link_rate <=
791 max_link_rate) {
792 link_bw = dp_link_bandwidth_kbps(
793 link,
794 ¤t_link_setting);
795 if (req_bw <= link_bw) {
796 *link_setting = current_link_setting;
797 return true;
798 }
799 if (policy) {
800 /* minimize lane */
801 if (current_link_setting.link_rate < max_link_rate) {
802 current_link_setting.link_rate =
803 increase_link_rate(link,
804 current_link_setting.link_rate);
805 } else {
806 if (current_link_setting.lane_count <
807 link->verified_link_cap.lane_count) {
808 current_link_setting.lane_count =
809 increase_lane_count(
810 current_link_setting.lane_count);
811 current_link_setting.link_rate = initial_link_setting.link_rate;
812 } else
813 break;
814 }
815 } else {
816 /* minimize link rate */
817 if (current_link_setting.lane_count <
818 link->verified_link_cap.lane_count) {
819 current_link_setting.lane_count =
820 increase_lane_count(
821 current_link_setting.lane_count);
822 } else {
823 current_link_setting.link_rate =
824 increase_link_rate(link,
825 current_link_setting.link_rate);
826 current_link_setting.lane_count =
827 initial_link_setting.lane_count;
828 }
829 }
830 }
831 return false;
832 }
833
834 /* if optimize edp link is supported */
835 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
836 initial_link_setting.lane_count = LANE_COUNT_ONE;
837 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
838 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
839 initial_link_setting.use_link_rate_set = true;
840 initial_link_setting.link_rate_set = 0;
841 current_link_setting = initial_link_setting;
842
843 /* search for the minimum link setting that:
844 * 1. is supported according to the link training result
845 * 2. could support the b/w requested by the timing
846 */
847 while (current_link_setting.link_rate <=
848 max_link_rate) {
849 link_bw = dp_link_bandwidth_kbps(
850 link,
851 ¤t_link_setting);
852 if (req_bw <= link_bw) {
853 *link_setting = current_link_setting;
854 return true;
855 }
856 if (policy) {
857 /* minimize lane */
858 if (current_link_setting.link_rate_set <
859 link->dpcd_caps.edp_supported_link_rates_count
860 && current_link_setting.link_rate < max_link_rate) {
861 current_link_setting.link_rate_set++;
862 current_link_setting.link_rate =
863 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
864 } else {
865 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
866 current_link_setting.lane_count =
867 increase_lane_count(
868 current_link_setting.lane_count);
869 current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
870 current_link_setting.link_rate =
871 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
872 } else
873 break;
874 }
875 } else {
876 /* minimize link rate */
877 if (current_link_setting.lane_count <
878 link->verified_link_cap.lane_count) {
879 current_link_setting.lane_count =
880 increase_lane_count(
881 current_link_setting.lane_count);
882 } else {
883 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
884 current_link_setting.link_rate_set++;
885 current_link_setting.link_rate =
886 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
887 current_link_setting.lane_count =
888 initial_link_setting.lane_count;
889 } else
890 break;
891 }
892 }
893 }
894 return false;
895 }
896
decide_mst_link_settings(const struct dc_link * link,struct dc_link_settings * link_setting)897 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
898 {
899 *link_setting = link->verified_link_cap;
900 return true;
901 }
902
link_decide_link_settings(struct dc_stream_state * stream,struct dc_link_settings * link_setting)903 bool link_decide_link_settings(struct dc_stream_state *stream,
904 struct dc_link_settings *link_setting)
905 {
906 struct dc_link *link = stream->link;
907 uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
908
909 memset(link_setting, 0, sizeof(*link_setting));
910
911 /* if preferred is specified through AMDDP, use it, if it's enough
912 * to drive the mode
913 */
914 if (link->preferred_link_setting.lane_count !=
915 LANE_COUNT_UNKNOWN &&
916 link->preferred_link_setting.link_rate !=
917 LINK_RATE_UNKNOWN) {
918 *link_setting = link->preferred_link_setting;
919 return true;
920 }
921
922 /* MST doesn't perform link training for now
923 * TODO: add MST specific link training routine
924 */
925 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
926 decide_mst_link_settings(link, link_setting);
927 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
928 /* enable edp link optimization for DSC eDP case */
929 if (stream->timing.flags.DSC) {
930 enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
931
932 if (link->panel_config.dsc.force_dsc_edp_policy) {
933 /* calculate link max link rate cap*/
934 struct dc_link_settings tmp_link_setting;
935 struct dc_crtc_timing tmp_timing = stream->timing;
936 uint32_t orig_req_bw;
937
938 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
939 tmp_timing.flags.DSC = 0;
940 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing,
941 dc_link_get_highest_encoding_format(link));
942 edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw);
943 max_link_rate = tmp_link_setting.link_rate;
944 }
945 decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate);
946 } else {
947 edp_decide_link_settings(link, link_setting, req_bw);
948 }
949 } else {
950 decide_dp_link_settings(link, link_setting, req_bw);
951 }
952
953 return link_setting->lane_count != LANE_COUNT_UNKNOWN &&
954 link_setting->link_rate != LINK_RATE_UNKNOWN;
955 }
956
link_dp_get_encoding_format(const struct dc_link_settings * link_settings)957 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
958 {
959 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
960 (link_settings->link_rate <= LINK_RATE_HIGH3))
961 return DP_8b_10b_ENCODING;
962 else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
963 (link_settings->link_rate <= LINK_RATE_UHBR20))
964 return DP_128b_132b_ENCODING;
965 return DP_UNKNOWN_ENCODING;
966 }
967
mst_decide_link_encoding_format(const struct dc_link * link)968 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link)
969 {
970 struct dc_link_settings link_settings = {0};
971
972 if (!dc_is_dp_signal(link->connector_signal))
973 return DP_UNKNOWN_ENCODING;
974
975 if (link->preferred_link_setting.lane_count !=
976 LANE_COUNT_UNKNOWN &&
977 link->preferred_link_setting.link_rate !=
978 LINK_RATE_UNKNOWN) {
979 link_settings = link->preferred_link_setting;
980 } else {
981 decide_mst_link_settings(link, &link_settings);
982 }
983
984 return link_dp_get_encoding_format(&link_settings);
985 }
986
read_dp_device_vendor_id(struct dc_link * link)987 static void read_dp_device_vendor_id(struct dc_link *link)
988 {
989 struct dp_device_vendor_id dp_id;
990
991 /* read IEEE branch device id */
992 core_link_read_dpcd(
993 link,
994 DP_BRANCH_OUI,
995 (uint8_t *)&dp_id,
996 sizeof(dp_id));
997
998 link->dpcd_caps.branch_dev_id =
999 (dp_id.ieee_oui[0] << 16) +
1000 (dp_id.ieee_oui[1] << 8) +
1001 dp_id.ieee_oui[2];
1002
1003 memmove(
1004 link->dpcd_caps.branch_dev_name,
1005 dp_id.ieee_device_id,
1006 sizeof(dp_id.ieee_device_id));
1007 }
1008
wake_up_aux_channel(struct dc_link * link)1009 static enum dc_status wake_up_aux_channel(struct dc_link *link)
1010 {
1011 enum dc_status status = DC_ERROR_UNEXPECTED;
1012 uint32_t aux_channel_retry_cnt = 0;
1013 uint8_t dpcd_power_state = '\0';
1014
1015 while (status != DC_OK && aux_channel_retry_cnt < 10) {
1016 status = core_link_read_dpcd(link, DP_SET_POWER,
1017 &dpcd_power_state, sizeof(dpcd_power_state));
1018
1019 /* Delay 1 ms if AUX CH is in power down state. Based on spec
1020 * section 2.3.1.2, if AUX CH may be powered down due to
1021 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
1022 * signal and may need up to 1 ms before being able to reply.
1023 */
1024 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
1025 fsleep(1000);
1026 aux_channel_retry_cnt++;
1027 }
1028 }
1029
1030 if (status != DC_OK) {
1031 dpcd_power_state = DP_SET_POWER_D0;
1032 status = core_link_write_dpcd(
1033 link,
1034 DP_SET_POWER,
1035 &dpcd_power_state,
1036 sizeof(dpcd_power_state));
1037
1038 dpcd_power_state = DP_SET_POWER_D3;
1039 status = core_link_write_dpcd(
1040 link,
1041 DP_SET_POWER,
1042 &dpcd_power_state,
1043 sizeof(dpcd_power_state));
1044 DC_LOG_DC("%s: Failed to power up sink\n", __func__);
1045 return DC_ERROR_UNEXPECTED;
1046 }
1047
1048 return DC_OK;
1049 }
1050
get_active_converter_info(uint8_t data,struct dc_link * link)1051 static void get_active_converter_info(
1052 uint8_t data, struct dc_link *link)
1053 {
1054 union dp_downstream_port_present ds_port = { .byte = data };
1055 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
1056
1057 /* decode converter info*/
1058 if (!ds_port.fields.PORT_PRESENT) {
1059 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1060 set_dongle_type(link->ddc,
1061 link->dpcd_caps.dongle_type);
1062 link->dpcd_caps.is_branch_dev = false;
1063 return;
1064 }
1065
1066 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
1067 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
1068
1069 switch (ds_port.fields.PORT_TYPE) {
1070 case DOWNSTREAM_VGA:
1071 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
1072 break;
1073 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
1074 /* At this point we don't know is it DVI or HDMI or DP++,
1075 * assume DVI.*/
1076 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
1077 break;
1078 default:
1079 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1080 break;
1081 }
1082
1083 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
1084 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
1085 union dwnstream_port_caps_byte0 *port_caps =
1086 (union dwnstream_port_caps_byte0 *)det_caps;
1087 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
1088 det_caps, sizeof(det_caps)) == DC_OK) {
1089
1090 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
1091 /*Handle DP case as DONGLE_NONE*/
1092 case DOWN_STREAM_DETAILED_DP:
1093 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1094 break;
1095 case DOWN_STREAM_DETAILED_VGA:
1096 link->dpcd_caps.dongle_type =
1097 DISPLAY_DONGLE_DP_VGA_CONVERTER;
1098 break;
1099 case DOWN_STREAM_DETAILED_DVI:
1100 link->dpcd_caps.dongle_type =
1101 DISPLAY_DONGLE_DP_DVI_CONVERTER;
1102 break;
1103 case DOWN_STREAM_DETAILED_HDMI:
1104 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
1105 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
1106 link->dpcd_caps.dongle_type =
1107 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
1108
1109 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
1110 if (ds_port.fields.DETAILED_CAPS) {
1111
1112 union dwnstream_port_caps_byte3_hdmi
1113 hdmi_caps = {.raw = det_caps[3] };
1114 union dwnstream_port_caps_byte2
1115 hdmi_color_caps = {.raw = det_caps[2] };
1116 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
1117 det_caps[1] * 2500;
1118
1119 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
1120 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
1121 /*YCBCR capability only for HDMI case*/
1122 if (port_caps->bits.DWN_STRM_PORTX_TYPE
1123 == DOWN_STREAM_DETAILED_HDMI) {
1124 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
1125 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
1126 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
1127 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
1128 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
1129 hdmi_caps.bits.YCrCr422_CONVERSION;
1130 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
1131 hdmi_caps.bits.YCrCr420_CONVERSION;
1132 }
1133
1134 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
1135 translate_dpcd_max_bpc(
1136 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
1137
1138 if (link->dc->caps.dp_hdmi21_pcon_support) {
1139 union hdmi_encoded_link_bw hdmi_encoded_link_bw;
1140
1141 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
1142 link_bw_kbps_from_raw_frl_link_rate_data(
1143 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1144
1145 // Intersect reported max link bw support with the supported link rate post FRL link training
1146 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
1147 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
1148 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
1149 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
1150 hdmi_encoded_link_bw);
1151 }
1152
1153 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
1154 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1155 }
1156
1157 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
1158 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1159 }
1160
1161 break;
1162 }
1163 }
1164 }
1165
1166 set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
1167
1168 {
1169 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1170
1171 core_link_read_dpcd(
1172 link,
1173 DP_BRANCH_REVISION_START,
1174 (uint8_t *)&dp_hw_fw_revision,
1175 sizeof(dp_hw_fw_revision));
1176
1177 link->dpcd_caps.branch_hw_revision =
1178 dp_hw_fw_revision.ieee_hw_rev;
1179
1180 memmove(
1181 link->dpcd_caps.branch_fw_revision,
1182 dp_hw_fw_revision.ieee_fw_rev,
1183 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1184 }
1185 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
1186 link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1187 union dp_dfp_cap_ext dfp_cap_ext;
1188 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
1189 core_link_read_dpcd(
1190 link,
1191 DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
1192 dfp_cap_ext.raw,
1193 sizeof(dfp_cap_ext.raw));
1194 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
1195 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
1196 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
1197 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
1198 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
1199 dfp_cap_ext.fields.max_video_h_active_width[0] +
1200 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
1201 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
1202 dfp_cap_ext.fields.max_video_v_active_height[0] +
1203 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
1204 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
1205 dfp_cap_ext.fields.encoding_format_caps;
1206 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
1207 dfp_cap_ext.fields.rgb_color_depth_caps;
1208 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
1209 dfp_cap_ext.fields.ycbcr444_color_depth_caps;
1210 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
1211 dfp_cap_ext.fields.ycbcr422_color_depth_caps;
1212 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
1213 dfp_cap_ext.fields.ycbcr420_color_depth_caps;
1214 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
1215 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
1216 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
1217 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
1218 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
1219 }
1220 }
1221
apply_usbc_combo_phy_reset_wa(struct dc_link * link,struct dc_link_settings * link_settings)1222 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
1223 struct dc_link_settings *link_settings)
1224 {
1225 /* Temporary Renoir-specific workaround PHY will sometimes be in bad
1226 * state on hotplugging display from certain USB-C dongle, so add extra
1227 * cycle of enabling and disabling the PHY before first link training.
1228 */
1229 struct link_resource link_res = {0};
1230 enum clock_source_id dp_cs_id = get_clock_source_id(link);
1231
1232 dp_enable_link_phy(link, &link_res, link->connector_signal,
1233 dp_cs_id, link_settings);
1234 dp_disable_link_phy(link, &link_res, link->connector_signal);
1235 }
1236
dp_overwrite_extended_receiver_cap(struct dc_link * link)1237 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
1238 {
1239 uint8_t dpcd_data[16];
1240 uint32_t read_dpcd_retry_cnt = 3;
1241 enum dc_status status = DC_ERROR_UNEXPECTED;
1242 union dp_downstream_port_present ds_port = { 0 };
1243 union down_stream_port_count down_strm_port_count;
1244 union edp_configuration_cap edp_config_cap;
1245
1246 int i;
1247
1248 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1249 status = core_link_read_dpcd(
1250 link,
1251 DP_DPCD_REV,
1252 dpcd_data,
1253 sizeof(dpcd_data));
1254 if (status == DC_OK)
1255 break;
1256 }
1257
1258 link->dpcd_caps.dpcd_rev.raw =
1259 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1260
1261 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1262 return false;
1263
1264 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1265 DP_DPCD_REV];
1266
1267 get_active_converter_info(ds_port.byte, link);
1268
1269 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1270 DP_DPCD_REV];
1271
1272 link->dpcd_caps.allow_invalid_MSA_timing_param =
1273 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1274
1275 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1276 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1277
1278 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1279 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1280
1281 link->reported_link_cap.lane_count =
1282 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1283 link->reported_link_cap.link_rate = dpcd_data[
1284 DP_MAX_LINK_RATE - DP_DPCD_REV];
1285 link->reported_link_cap.link_spread =
1286 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1287 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1288
1289 edp_config_cap.raw = dpcd_data[
1290 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1291 link->dpcd_caps.panel_mode_edp =
1292 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1293 link->dpcd_caps.dpcd_display_control_capable =
1294 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1295
1296 return true;
1297 }
1298
dpcd_set_source_specific_data(struct dc_link * link)1299 void dpcd_set_source_specific_data(struct dc_link *link)
1300 {
1301 if (!link->dc->vendor_signature.is_valid) {
1302 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
1303 struct dpcd_amd_signature amd_signature = {0};
1304 struct dpcd_amd_device_id amd_device_id = {0};
1305
1306 amd_device_id.device_id_byte1 =
1307 (uint8_t)(link->ctx->asic_id.chip_id);
1308 amd_device_id.device_id_byte2 =
1309 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
1310 amd_device_id.dce_version =
1311 (uint8_t)(link->ctx->dce_version);
1312 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
1313 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
1314
1315 core_link_read_dpcd(link, DP_SOURCE_OUI,
1316 (uint8_t *)(&amd_signature),
1317 sizeof(amd_signature));
1318
1319 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
1320 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
1321 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
1322
1323 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
1324 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
1325 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
1326
1327 core_link_write_dpcd(link, DP_SOURCE_OUI,
1328 (uint8_t *)(&amd_signature),
1329 sizeof(amd_signature));
1330 }
1331
1332 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
1333 (uint8_t *)(&amd_device_id),
1334 sizeof(amd_device_id));
1335
1336 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
1337 link->dc->caps.min_horizontal_blanking_period != 0) {
1338
1339 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
1340
1341 result_write_min_hblank = core_link_write_dpcd(link,
1342 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
1343 sizeof(hblank_size));
1344 }
1345 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
1346 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
1347 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
1348 result_write_min_hblank,
1349 link->link_index,
1350 link->ctx->dce_version,
1351 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
1352 link->dc->caps.min_horizontal_blanking_period,
1353 link->dpcd_caps.branch_dev_id,
1354 link->dpcd_caps.branch_dev_name[0],
1355 link->dpcd_caps.branch_dev_name[1],
1356 link->dpcd_caps.branch_dev_name[2],
1357 link->dpcd_caps.branch_dev_name[3],
1358 link->dpcd_caps.branch_dev_name[4],
1359 link->dpcd_caps.branch_dev_name[5]);
1360 } else {
1361 core_link_write_dpcd(link, DP_SOURCE_OUI,
1362 link->dc->vendor_signature.data.raw,
1363 sizeof(link->dc->vendor_signature.data.raw));
1364 }
1365 }
1366
dpcd_write_cable_id_to_dprx(struct dc_link * link)1367 void dpcd_write_cable_id_to_dprx(struct dc_link *link)
1368 {
1369 if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
1370 link->dpcd_caps.cable_id.raw == 0 ||
1371 link->dprx_states.cable_id_written)
1372 return;
1373
1374 core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
1375 &link->dpcd_caps.cable_id.raw,
1376 sizeof(link->dpcd_caps.cable_id.raw));
1377
1378 link->dprx_states.cable_id_written = 1;
1379 }
1380
get_usbc_cable_id(struct dc_link * link,union dp_cable_id * cable_id)1381 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
1382 {
1383 union dmub_rb_cmd cmd;
1384
1385 if (!link->ctx->dmub_srv ||
1386 link->ep_type != DISPLAY_ENDPOINT_PHY ||
1387 link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
1388 return false;
1389
1390 memset(&cmd, 0, sizeof(cmd));
1391 cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
1392 cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
1393 cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
1394 link->dc, link->link_enc->transmitter);
1395 if (dm_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
1396 cmd.cable_id.header.ret_status == 1) {
1397 cable_id->raw = cmd.cable_id.data.output_raw;
1398 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw);
1399 }
1400 return cmd.cable_id.header.ret_status == 1;
1401 }
1402
retrieve_cable_id(struct dc_link * link)1403 static void retrieve_cable_id(struct dc_link *link)
1404 {
1405 union dp_cable_id usbc_cable_id;
1406
1407 link->dpcd_caps.cable_id.raw = 0;
1408 core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
1409 &link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
1410
1411 if (get_usbc_cable_id(link, &usbc_cable_id))
1412 link->dpcd_caps.cable_id = intersect_cable_id(
1413 &link->dpcd_caps.cable_id, &usbc_cable_id);
1414 }
1415
read_is_mst_supported(struct dc_link * link)1416 bool read_is_mst_supported(struct dc_link *link)
1417 {
1418 bool mst = false;
1419 enum dc_status st = DC_OK;
1420 union dpcd_rev rev;
1421 union mstm_cap cap;
1422
1423 if (link->preferred_training_settings.mst_enable &&
1424 *link->preferred_training_settings.mst_enable == false) {
1425 return false;
1426 }
1427
1428 rev.raw = 0;
1429 cap.raw = 0;
1430
1431 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
1432 sizeof(rev));
1433
1434 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
1435
1436 st = core_link_read_dpcd(link, DP_MSTM_CAP,
1437 &cap.raw, sizeof(cap));
1438 if (st == DC_OK && cap.bits.MST_CAP == 1)
1439 mst = true;
1440 }
1441 return mst;
1442
1443 }
1444
1445 /* Read additional sink caps defined in source specific DPCD area
1446 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
1447 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
1448 */
dpcd_read_sink_ext_caps(struct dc_link * link)1449 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
1450 {
1451 uint8_t dpcd_data = 0;
1452 uint8_t edp_general_cap2 = 0;
1453
1454 if (!link)
1455 return false;
1456
1457 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
1458 return false;
1459
1460 link->dpcd_sink_ext_caps.raw = dpcd_data;
1461
1462 if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK)
1463 return false;
1464
1465 link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
1466
1467 return true;
1468 }
1469
dp_retrieve_lttpr_cap(struct dc_link * link)1470 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
1471 {
1472 uint8_t lttpr_dpcd_data[8];
1473 enum dc_status status;
1474 bool is_lttpr_present;
1475
1476 /* Logic to determine LTTPR support*/
1477 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
1478
1479 if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)
1480 return DC_NOT_SUPPORTED;
1481
1482 /* By reading LTTPR capability, RX assumes that we will enable
1483 * LTTPR extended aux timeout if LTTPR is present.
1484 */
1485 status = core_link_read_dpcd(
1486 link,
1487 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
1488 lttpr_dpcd_data,
1489 sizeof(lttpr_dpcd_data));
1490
1491 link->dpcd_caps.lttpr_caps.revision.raw =
1492 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
1493 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1494
1495 link->dpcd_caps.lttpr_caps.max_link_rate =
1496 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
1497 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1498
1499 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
1500 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
1501 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1502
1503 link->dpcd_caps.lttpr_caps.max_lane_count =
1504 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
1505 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1506
1507 link->dpcd_caps.lttpr_caps.mode =
1508 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
1509 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1510
1511 link->dpcd_caps.lttpr_caps.max_ext_timeout =
1512 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
1513 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1514 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
1515 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
1516 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1517
1518 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
1519 lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
1520 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1521
1522 /* If this chip cap is set, at least one retimer must exist in the chain
1523 * Override count to 1 if we receive a known bad count (0 or an invalid value) */
1524 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1525 (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
1526 ASSERT(0);
1527 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1528 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1529 }
1530
1531 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
1532 is_lttpr_present = dp_is_lttpr_present(link);
1533
1534 if (is_lttpr_present)
1535 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1536
1537 DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
1538 return status;
1539 }
1540
retrieve_link_cap(struct dc_link * link)1541 static bool retrieve_link_cap(struct dc_link *link)
1542 {
1543 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
1544 * which means size 16 will be good for both of those DPCD register block reads
1545 */
1546 uint8_t dpcd_data[16];
1547 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
1548 */
1549 uint8_t dpcd_dprx_data = '\0';
1550
1551 struct dp_device_vendor_id sink_id;
1552 union down_stream_port_count down_strm_port_count;
1553 union edp_configuration_cap edp_config_cap;
1554 union dp_downstream_port_present ds_port = { 0 };
1555 enum dc_status status = DC_ERROR_UNEXPECTED;
1556 uint32_t read_dpcd_retry_cnt = 3;
1557 int i;
1558 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1559 const uint32_t post_oui_delay = 30; // 30ms
1560 bool is_fec_supported = false;
1561 bool is_dsc_basic_supported = false;
1562 bool is_dsc_passthrough_supported = false;
1563
1564 memset(dpcd_data, '\0', sizeof(dpcd_data));
1565 memset(&down_strm_port_count,
1566 '\0', sizeof(union down_stream_port_count));
1567 memset(&edp_config_cap, '\0',
1568 sizeof(union edp_configuration_cap));
1569
1570 /* if extended timeout is supported in hardware,
1571 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
1572 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
1573 */
1574 try_to_configure_aux_timeout(link->ddc,
1575 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
1576
1577 status = dp_retrieve_lttpr_cap(link);
1578
1579 if (status != DC_OK) {
1580 status = wake_up_aux_channel(link);
1581 if (status == DC_OK)
1582 dp_retrieve_lttpr_cap(link);
1583 else
1584 return false;
1585 }
1586
1587 if (dp_is_lttpr_present(link))
1588 configure_lttpr_mode_transparent(link);
1589
1590 /* Read DP tunneling information. */
1591 status = dpcd_get_tunneling_device_data(link);
1592
1593 dpcd_set_source_specific_data(link);
1594 /* Sink may need to configure internals based on vendor, so allow some
1595 * time before proceeding with possibly vendor specific transactions
1596 */
1597 msleep(post_oui_delay);
1598
1599 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1600 status = core_link_read_dpcd(
1601 link,
1602 DP_DPCD_REV,
1603 dpcd_data,
1604 sizeof(dpcd_data));
1605 if (status == DC_OK)
1606 break;
1607 }
1608
1609
1610 if (status != DC_OK) {
1611 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
1612 return false;
1613 }
1614
1615 if (!dp_is_lttpr_present(link))
1616 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
1617
1618
1619 {
1620 union training_aux_rd_interval aux_rd_interval;
1621
1622 aux_rd_interval.raw =
1623 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
1624
1625 link->dpcd_caps.ext_receiver_cap_field_present =
1626 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
1627
1628 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
1629 uint8_t ext_cap_data[16];
1630
1631 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
1632 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1633 status = core_link_read_dpcd(
1634 link,
1635 DP_DP13_DPCD_REV,
1636 ext_cap_data,
1637 sizeof(ext_cap_data));
1638 if (status == DC_OK) {
1639 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
1640 break;
1641 }
1642 }
1643 if (status != DC_OK)
1644 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
1645 }
1646 }
1647
1648 link->dpcd_caps.dpcd_rev.raw =
1649 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1650
1651 if (link->dpcd_caps.ext_receiver_cap_field_present) {
1652 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1653 status = core_link_read_dpcd(
1654 link,
1655 DP_DPRX_FEATURE_ENUMERATION_LIST,
1656 &dpcd_dprx_data,
1657 sizeof(dpcd_dprx_data));
1658 if (status == DC_OK)
1659 break;
1660 }
1661
1662 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
1663
1664 if (status != DC_OK)
1665 dm_error("%s: Read DPRX caps data failed.\n", __func__);
1666
1667 /* AdaptiveSyncCapability */
1668 dpcd_dprx_data = 0;
1669 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1670 status = core_link_read_dpcd(
1671 link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
1672 &dpcd_dprx_data, sizeof(dpcd_dprx_data));
1673 if (status == DC_OK)
1674 break;
1675 }
1676
1677 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;
1678
1679 if (status != DC_OK)
1680 dm_error("%s: Read DPRX caps data failed. Addr:%#x\n",
1681 __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);
1682 }
1683
1684 else {
1685 link->dpcd_caps.dprx_feature.raw = 0;
1686 }
1687
1688
1689 /* Error condition checking...
1690 * It is impossible for Sink to report Max Lane Count = 0.
1691 * It is possible for Sink to report Max Link Rate = 0, if it is
1692 * an eDP device that is reporting specialized link rates in the
1693 * SUPPORTED_LINK_RATE table.
1694 */
1695 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1696 return false;
1697
1698 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1699 DP_DPCD_REV];
1700
1701 read_dp_device_vendor_id(link);
1702
1703 /* TODO - decouple raw mst capability from policy decision */
1704 link->dpcd_caps.is_mst_capable = read_is_mst_supported(link);
1705 DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable));
1706
1707 get_active_converter_info(ds_port.byte, link);
1708
1709 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
1710
1711 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1712 DP_DPCD_REV];
1713
1714 link->dpcd_caps.allow_invalid_MSA_timing_param =
1715 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1716
1717 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1718 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1719
1720 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1721 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1722
1723 link->reported_link_cap.lane_count =
1724 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1725 link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw(
1726 dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]);
1727 link->reported_link_cap.link_spread =
1728 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1729 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1730
1731 edp_config_cap.raw = dpcd_data[
1732 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1733 link->dpcd_caps.panel_mode_edp =
1734 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1735 link->dpcd_caps.dpcd_display_control_capable =
1736 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1737 link->dpcd_caps.channel_coding_cap.raw =
1738 dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
1739 link->test_pattern_enabled = false;
1740 link->compliance_test_state.raw = 0;
1741
1742 /* read sink count */
1743 core_link_read_dpcd(link,
1744 DP_SINK_COUNT,
1745 &link->dpcd_caps.sink_count.raw,
1746 sizeof(link->dpcd_caps.sink_count.raw));
1747
1748 /* read sink ieee oui */
1749 core_link_read_dpcd(link,
1750 DP_SINK_OUI,
1751 (uint8_t *)(&sink_id),
1752 sizeof(sink_id));
1753
1754 link->dpcd_caps.sink_dev_id =
1755 (sink_id.ieee_oui[0] << 16) +
1756 (sink_id.ieee_oui[1] << 8) +
1757 (sink_id.ieee_oui[2]);
1758
1759 memmove(
1760 link->dpcd_caps.sink_dev_id_str,
1761 sink_id.ieee_device_id,
1762 sizeof(sink_id.ieee_device_id));
1763
1764 core_link_read_dpcd(
1765 link,
1766 DP_SINK_HW_REVISION_START,
1767 (uint8_t *)&dp_hw_fw_revision,
1768 sizeof(dp_hw_fw_revision));
1769
1770 link->dpcd_caps.sink_hw_revision =
1771 dp_hw_fw_revision.ieee_hw_rev;
1772
1773 memmove(
1774 link->dpcd_caps.sink_fw_revision,
1775 dp_hw_fw_revision.ieee_fw_rev,
1776 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1777
1778 /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */
1779 {
1780 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
1781 uint8_t fwrev_mbp_2018[] = { 7, 4 };
1782 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
1783
1784 /* We also check for the firmware revision as 16,1 models have an
1785 * identical device id and are incorrectly quirked otherwise.
1786 */
1787 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
1788 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
1789 sizeof(str_mbp_2018)) &&
1790 (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
1791 sizeof(fwrev_mbp_2018)) ||
1792 !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega,
1793 sizeof(fwrev_mbp_2018_vega)))) {
1794 link->reported_link_cap.link_rate = LINK_RATE_RBR2;
1795 }
1796 }
1797
1798 memset(&link->dpcd_caps.dsc_caps, '\0',
1799 sizeof(link->dpcd_caps.dsc_caps));
1800 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1801 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
1802 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
1803 status = core_link_read_dpcd(
1804 link,
1805 DP_FEC_CAPABILITY,
1806 &link->dpcd_caps.fec_cap.raw,
1807 sizeof(link->dpcd_caps.fec_cap.raw));
1808 status = core_link_read_dpcd(
1809 link,
1810 DP_DSC_SUPPORT,
1811 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
1812 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
1813 if (status == DC_OK) {
1814 is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE;
1815 is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT;
1816 is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT;
1817 DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__,
1818 str_yes_no(is_fec_supported));
1819 DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__,
1820 str_yes_no(is_dsc_basic_supported));
1821 DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__,
1822 str_yes_no(is_dsc_passthrough_supported));
1823 }
1824 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1825 status = core_link_read_dpcd(
1826 link,
1827 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
1828 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
1829 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
1830 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
1831 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
1832 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
1833 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
1834 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
1835 DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
1836 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
1837 }
1838
1839 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
1840 * only if required.
1841 */
1842 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1843 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&
1844 link->dpcd_caps.is_branch_dev &&
1845 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
1846 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
1847 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
1848 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
1849 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
1850 * Clear FEC and DSC capabilities as a work around if that is not the case.
1851 */
1852 link->wa_flags.dpia_forced_tbt3_mode = true;
1853 memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
1854 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1855 DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
1856 } else
1857 link->wa_flags.dpia_forced_tbt3_mode = false;
1858 }
1859
1860 if (!dpcd_read_sink_ext_caps(link))
1861 link->dpcd_sink_ext_caps.raw = 0;
1862
1863 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
1864 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
1865
1866 core_link_read_dpcd(link,
1867 DP_128B132B_SUPPORTED_LINK_RATES,
1868 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
1869 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
1870 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
1871 link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
1872 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
1873 link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
1874 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
1875 link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
1876 else
1877 dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
1878 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
1879 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
1880 link->reported_link_cap.link_rate / 100,
1881 link->reported_link_cap.link_rate % 100);
1882
1883 core_link_read_dpcd(link,
1884 DP_SINK_VIDEO_FALLBACK_FORMATS,
1885 &link->dpcd_caps.fallback_formats.raw,
1886 sizeof(link->dpcd_caps.fallback_formats.raw));
1887 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
1888 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
1889 DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
1890 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
1891 DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
1892 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
1893 DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
1894 if (link->dpcd_caps.fallback_formats.raw == 0) {
1895 DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
1896 link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
1897 }
1898
1899 core_link_read_dpcd(link,
1900 DP_FEC_CAPABILITY_1,
1901 &link->dpcd_caps.fec_cap1.raw,
1902 sizeof(link->dpcd_caps.fec_cap1.raw));
1903 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
1904 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
1905 DC_LOG_DP2("\tFEC aggregated error counters are supported");
1906 }
1907
1908 retrieve_cable_id(link);
1909 dpcd_write_cable_id_to_dprx(link);
1910
1911 /* Connectivity log: detection */
1912 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
1913
1914 return true;
1915 }
1916
detect_dp_sink_caps(struct dc_link * link)1917 bool detect_dp_sink_caps(struct dc_link *link)
1918 {
1919 return retrieve_link_cap(link);
1920 }
1921
detect_edp_sink_caps(struct dc_link * link)1922 void detect_edp_sink_caps(struct dc_link *link)
1923 {
1924 uint8_t supported_link_rates[16];
1925 uint32_t entry;
1926 uint32_t link_rate_in_khz;
1927 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
1928 uint8_t backlight_adj_cap;
1929 uint8_t general_edp_cap;
1930
1931 retrieve_link_cap(link);
1932 link->dpcd_caps.edp_supported_link_rates_count = 0;
1933 memset(supported_link_rates, 0, sizeof(supported_link_rates));
1934
1935 /*
1936 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
1937 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
1938 */
1939 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) {
1940 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
1941 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
1942 supported_link_rates, sizeof(supported_link_rates));
1943
1944 for (entry = 0; entry < 16; entry += 2) {
1945 // DPCD register reports per-lane link rate = 16-bit link rate capability
1946 // value X 200 kHz. Need multiplier to find link rate in kHz.
1947 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
1948 supported_link_rates[entry]) * 200;
1949
1950 DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__,
1951 entry / 2, link_rate_in_khz);
1952
1953 if (link_rate_in_khz != 0) {
1954 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
1955 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
1956 link->dpcd_caps.edp_supported_link_rates_count++;
1957 }
1958 }
1959 }
1960
1961 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
1962 &backlight_adj_cap, sizeof(backlight_adj_cap));
1963
1964 link->dpcd_caps.dynamic_backlight_capable_edp =
1965 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
1966
1967 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
1968 &general_edp_cap, sizeof(general_edp_cap));
1969
1970 link->dpcd_caps.set_power_state_capable_edp =
1971 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
1972
1973 set_default_brightness_aux(link);
1974
1975 core_link_read_dpcd(link, DP_EDP_DPCD_REV,
1976 &link->dpcd_caps.edp_rev,
1977 sizeof(link->dpcd_caps.edp_rev));
1978 /*
1979 * PSR is only valid for eDP v1.3 or higher.
1980 */
1981 if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
1982 core_link_read_dpcd(link, DP_PSR_SUPPORT,
1983 &link->dpcd_caps.psr_info.psr_version,
1984 sizeof(link->dpcd_caps.psr_info.psr_version));
1985 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
1986 core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
1987 &link->dpcd_caps.psr_info.force_psrsu_cap,
1988 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
1989 core_link_read_dpcd(link, DP_PSR_CAPS,
1990 &link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
1991 sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
1992 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
1993 core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
1994 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
1995 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
1996 }
1997 }
1998
1999 /*
2000 * ALPM is only valid for eDP v1.4 or higher.
2001 */
2002 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2003 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
2004 &link->dpcd_caps.alpm_caps.raw,
2005 sizeof(link->dpcd_caps.alpm_caps.raw));
2006
2007 /*
2008 * Read REPLAY info
2009 */
2010 core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE,
2011 &link->dpcd_caps.pr_info.pixel_deviation_per_line,
2012 sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line));
2013 core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,
2014 &link->dpcd_caps.pr_info.max_deviation_line,
2015 sizeof(link->dpcd_caps.pr_info.max_deviation_line));
2016 }
2017
dp_get_max_link_enc_cap(const struct dc_link * link,struct dc_link_settings * max_link_enc_cap)2018 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2019 {
2020 struct link_encoder *link_enc = NULL;
2021
2022 if (!max_link_enc_cap) {
2023 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2024 return false;
2025 }
2026
2027 link_enc = link_enc_cfg_get_link_enc(link);
2028 ASSERT(link_enc);
2029
2030 if (link_enc && link_enc->funcs->get_max_link_cap) {
2031 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
2032 return true;
2033 }
2034
2035 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2036 max_link_enc_cap->lane_count = 1;
2037 max_link_enc_cap->link_rate = 6;
2038 return false;
2039 }
2040
dp_get_verified_link_cap(const struct dc_link * link)2041 const struct dc_link_settings *dp_get_verified_link_cap(
2042 const struct dc_link *link)
2043 {
2044 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
2045 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
2046 return &link->preferred_link_setting;
2047 return &link->verified_link_cap;
2048 }
2049
dp_get_max_link_cap(struct dc_link * link)2050 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
2051 {
2052 struct dc_link_settings max_link_cap = {0};
2053 enum dc_link_rate lttpr_max_link_rate;
2054 enum dc_link_rate cable_max_link_rate;
2055 struct link_encoder *link_enc = NULL;
2056
2057
2058 link_enc = link_enc_cfg_get_link_enc(link);
2059 ASSERT(link_enc);
2060
2061 /* get max link encoder capability */
2062 if (link_enc)
2063 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2064
2065 /* Lower link settings based on sink's link cap */
2066 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2067 max_link_cap.lane_count =
2068 link->reported_link_cap.lane_count;
2069 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2070 max_link_cap.link_rate =
2071 link->reported_link_cap.link_rate;
2072 if (link->reported_link_cap.link_spread <
2073 max_link_cap.link_spread)
2074 max_link_cap.link_spread =
2075 link->reported_link_cap.link_spread;
2076
2077 /* Lower link settings based on cable attributes
2078 * Cable ID is a DP2 feature to identify max certified link rate that
2079 * a cable can carry. The cable identification method requires both
2080 * cable and display hardware support. Since the specs comes late, it is
2081 * anticipated that the first round of DP2 cables and displays may not
2082 * be fully compatible to reliably return cable ID data. Therefore the
2083 * decision of our cable id policy is that if the cable can return non
2084 * zero cable id data, we will take cable's link rate capability into
2085 * account. However if we get zero data, the cable link rate capability
2086 * is considered inconclusive. In this case, we will not take cable's
2087 * capability into account to avoid of over limiting hardware capability
2088 * from users. The max overall link rate capability is still determined
2089 * after actual dp pre-training. Cable id is considered as an auxiliary
2090 * method of determining max link bandwidth capability.
2091 */
2092 cable_max_link_rate = get_cable_max_link_rate(link);
2093
2094 if (!link->dc->debug.ignore_cable_id &&
2095 cable_max_link_rate != LINK_RATE_UNKNOWN &&
2096 cable_max_link_rate < max_link_cap.link_rate)
2097 max_link_cap.link_rate = cable_max_link_rate;
2098
2099 /* account for lttpr repeaters cap
2100 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2101 */
2102 if (dp_is_lttpr_present(link)) {
2103 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2104 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2105 lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2106
2107 if (lttpr_max_link_rate < max_link_cap.link_rate)
2108 max_link_cap.link_rate = lttpr_max_link_rate;
2109
2110 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2111 __func__,
2112 max_link_cap.lane_count,
2113 max_link_cap.link_rate);
2114 }
2115
2116 if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING &&
2117 link->dc->debug.disable_uhbr)
2118 max_link_cap.link_rate = LINK_RATE_HIGH3;
2119
2120 return max_link_cap;
2121 }
2122
dp_verify_link_cap(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int * fail_count)2123 static bool dp_verify_link_cap(
2124 struct dc_link *link,
2125 struct dc_link_settings *known_limit_link_setting,
2126 int *fail_count)
2127 {
2128 struct dc_link_settings cur_link_settings = {0};
2129 struct dc_link_settings max_link_settings = *known_limit_link_setting;
2130 bool success = false;
2131 bool skip_video_pattern;
2132 enum clock_source_id dp_cs_id = get_clock_source_id(link);
2133 enum link_training_result status = LINK_TRAINING_SUCCESS;
2134 union hpd_irq_data irq_data;
2135 struct link_resource link_res;
2136
2137 memset(&irq_data, 0, sizeof(irq_data));
2138 cur_link_settings = max_link_settings;
2139
2140 /* Grant extended timeout request */
2141 if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2142 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2143
2144 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2145 }
2146
2147 do {
2148 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings))
2149 continue;
2150
2151 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW;
2152 dp_enable_link_phy(
2153 link,
2154 &link_res,
2155 link->connector_signal,
2156 dp_cs_id,
2157 &cur_link_settings);
2158
2159 status = dp_perform_link_training(
2160 link,
2161 &link_res,
2162 &cur_link_settings,
2163 skip_video_pattern);
2164
2165 if (status == LINK_TRAINING_SUCCESS) {
2166 success = true;
2167 fsleep(1000);
2168 if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK &&
2169 dp_parse_link_loss_status(
2170 link,
2171 &irq_data))
2172 (*fail_count)++;
2173 } else if (status == LINK_TRAINING_LINK_LOSS) {
2174 success = true;
2175 (*fail_count)++;
2176 } else {
2177 (*fail_count)++;
2178 }
2179 dp_trace_lt_total_count_increment(link, true);
2180 dp_trace_lt_result_update(link, status, true);
2181 dp_disable_link_phy(link, &link_res, link->connector_signal);
2182 } while (!success && decide_fallback_link_setting(link,
2183 &max_link_settings, &cur_link_settings, status));
2184
2185 link->verified_link_cap = success ?
2186 cur_link_settings : fail_safe_link_settings;
2187 return success;
2188 }
2189
dp_verify_link_cap_with_retries(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int attempts)2190 bool dp_verify_link_cap_with_retries(
2191 struct dc_link *link,
2192 struct dc_link_settings *known_limit_link_setting,
2193 int attempts)
2194 {
2195 int i = 0;
2196 bool success = false;
2197 int fail_count = 0;
2198 struct dc_link_settings last_verified_link_cap = fail_safe_link_settings;
2199
2200 dp_trace_detect_lt_init(link);
2201
2202 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
2203 link->dc->debug.usbc_combo_phy_reset_wa)
2204 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);
2205
2206 dp_trace_set_lt_start_timestamp(link, false);
2207 for (i = 0; i < attempts; i++) {
2208 enum dc_connection_type type = dc_connection_none;
2209
2210 memset(&link->verified_link_cap, 0,
2211 sizeof(struct dc_link_settings));
2212 if (!link_detect_connection_type(link, &type) || type == dc_connection_none) {
2213 link->verified_link_cap = fail_safe_link_settings;
2214 break;
2215 } else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {
2216 last_verified_link_cap = link->verified_link_cap;
2217 if (fail_count == 0) {
2218 success = true;
2219 break;
2220 }
2221 } else {
2222 link->verified_link_cap = last_verified_link_cap;
2223 }
2224 fsleep(10 * 1000);
2225 }
2226
2227 dp_trace_lt_fail_count_update(link, fail_count, true);
2228 dp_trace_set_lt_end_timestamp(link, true);
2229
2230 return success;
2231 }
2232
2233 /*
2234 * Check if there is a native DP or passive DP-HDMI dongle connected
2235 */
dp_is_sink_present(struct dc_link * link)2236 bool dp_is_sink_present(struct dc_link *link)
2237 {
2238 enum gpio_result gpio_result;
2239 uint32_t clock_pin = 0;
2240 uint8_t retry = 0;
2241 struct ddc *ddc;
2242
2243 enum connector_id connector_id =
2244 dal_graphics_object_id_get_connector_id(link->link_id);
2245
2246 bool present =
2247 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
2248 (connector_id == CONNECTOR_ID_EDP) ||
2249 (connector_id == CONNECTOR_ID_USBC));
2250
2251 ddc = get_ddc_pin(link->ddc);
2252
2253 if (!ddc) {
2254 BREAK_TO_DEBUGGER();
2255 return present;
2256 }
2257
2258 /* Open GPIO and set it to I2C mode */
2259 /* Note: this GpioMode_Input will be converted
2260 * to GpioConfigType_I2cAuxDualMode in GPIO component,
2261 * which indicates we need additional delay
2262 */
2263
2264 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
2265 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
2266 dal_ddc_close(ddc);
2267
2268 return present;
2269 }
2270
2271 /*
2272 * Read GPIO: DP sink is present if both clock and data pins are zero
2273 *
2274 * [W/A] plug-unplug DP cable, sometimes customer board has
2275 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
2276 * then monitor can't br light up. Add retry 3 times
2277 * But in real passive dongle, it need additional 3ms to detect
2278 */
2279 do {
2280 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
2281 ASSERT(gpio_result == GPIO_RESULT_OK);
2282 if (clock_pin)
2283 fsleep(1000);
2284 else
2285 break;
2286 } while (retry++ < 3);
2287
2288 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
2289
2290 dal_ddc_close(ddc);
2291
2292 return present;
2293 }
2294