1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/types.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 
12 #include "rvu.h"
13 #include "cgx.h"
14 #include "lmac_common.h"
15 #include "rvu_reg.h"
16 #include "rvu_trace.h"
17 #include "rvu_npc_hash.h"
18 
19 struct cgx_evq_entry {
20 	struct list_head evq_node;
21 	struct cgx_link_event link_event;
22 };
23 
24 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
25 static struct _req_type __maybe_unused					\
26 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid)		\
27 {									\
28 	struct _req_type *req;						\
29 									\
30 	req = (struct _req_type *)otx2_mbox_alloc_msg_rsp(		\
31 		&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
32 		sizeof(struct _rsp_type));				\
33 	if (!req)							\
34 		return NULL;						\
35 	req->hdr.sig = OTX2_MBOX_REQ_SIG;				\
36 	req->hdr.id = _id;						\
37 	trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req));		\
38 	return req;							\
39 }
40 
41 MBOX_UP_CGX_MESSAGES
42 #undef M
43 
is_mac_feature_supported(struct rvu * rvu,int pf,int feature)44 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)
45 {
46 	u8 cgx_id, lmac_id;
47 	void *cgxd;
48 
49 	if (!is_pf_cgxmapped(rvu, pf))
50 		return 0;
51 
52 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
53 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
54 
55 	return  (cgx_features_get(cgxd) & feature);
56 }
57 
58 #define CGX_OFFSET(x)			((x) * rvu->hw->lmac_per_cgx)
59 /* Returns bitmap of mapped PFs */
cgxlmac_to_pfmap(struct rvu * rvu,u8 cgx_id,u8 lmac_id)60 static u64 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)
61 {
62 	return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];
63 }
64 
cgxlmac_to_pf(struct rvu * rvu,int cgx_id,int lmac_id)65 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)
66 {
67 	unsigned long pfmap;
68 
69 	pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);
70 
71 	/* Assumes only one pf mapped to a cgx lmac port */
72 	if (!pfmap)
73 		return -ENODEV;
74 	else
75 		return find_first_bit(&pfmap,
76 				      rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx);
77 }
78 
cgxlmac_id_to_bmap(u8 cgx_id,u8 lmac_id)79 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
80 {
81 	return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
82 }
83 
rvu_cgx_pdata(u8 cgx_id,struct rvu * rvu)84 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
85 {
86 	if (cgx_id >= rvu->cgx_cnt_max)
87 		return NULL;
88 
89 	return rvu->cgx_idmap[cgx_id];
90 }
91 
92 /* Return first enabled CGX instance if none are enabled then return NULL */
rvu_first_cgx_pdata(struct rvu * rvu)93 void *rvu_first_cgx_pdata(struct rvu *rvu)
94 {
95 	int first_enabled_cgx = 0;
96 	void *cgxd = NULL;
97 
98 	for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {
99 		cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);
100 		if (cgxd)
101 			break;
102 	}
103 
104 	return cgxd;
105 }
106 
107 /* Based on P2X connectivity find mapped NIX block for a PF */
rvu_map_cgx_nix_block(struct rvu * rvu,int pf,int cgx_id,int lmac_id)108 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,
109 				  int cgx_id, int lmac_id)
110 {
111 	struct rvu_pfvf *pfvf = &rvu->pf[pf];
112 	u8 p2x;
113 
114 	p2x = cgx_lmac_get_p2x(cgx_id, lmac_id);
115 	/* Firmware sets P2X_SELECT as either NIX0 or NIX1 */
116 	pfvf->nix_blkaddr = BLKADDR_NIX0;
117 	if (is_rvu_supports_nix1(rvu) && p2x == CMR_P2X_SEL_NIX1)
118 		pfvf->nix_blkaddr = BLKADDR_NIX1;
119 }
120 
rvu_map_cgx_lmac_pf(struct rvu * rvu)121 static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
122 {
123 	struct npc_pkind *pkind = &rvu->hw->pkind;
124 	int cgx_cnt_max = rvu->cgx_cnt_max;
125 	int pf = PF_CGXMAP_BASE;
126 	unsigned long lmac_bmap;
127 	int size, free_pkind;
128 	int cgx, lmac, iter;
129 	int numvfs, hwvfs;
130 
131 	if (!cgx_cnt_max)
132 		return 0;
133 
134 	if (cgx_cnt_max > 0xF || rvu->hw->lmac_per_cgx > 0xF)
135 		return -EINVAL;
136 
137 	/* Alloc map table
138 	 * An additional entry is required since PF id starts from 1 and
139 	 * hence entry at offset 0 is invalid.
140 	 */
141 	size = (cgx_cnt_max * rvu->hw->lmac_per_cgx + 1) * sizeof(u8);
142 	rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);
143 	if (!rvu->pf2cgxlmac_map)
144 		return -ENOMEM;
145 
146 	/* Initialize all entries with an invalid cgx and lmac id */
147 	memset(rvu->pf2cgxlmac_map, 0xFF, size);
148 
149 	/* Reverse map table */
150 	rvu->cgxlmac2pf_map =
151 		devm_kzalloc(rvu->dev,
152 			     cgx_cnt_max * rvu->hw->lmac_per_cgx * sizeof(u64),
153 			     GFP_KERNEL);
154 	if (!rvu->cgxlmac2pf_map)
155 		return -ENOMEM;
156 
157 	rvu->cgx_mapped_pfs = 0;
158 	for (cgx = 0; cgx < cgx_cnt_max; cgx++) {
159 		if (!rvu_cgx_pdata(cgx, rvu))
160 			continue;
161 		lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));
162 		for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) {
163 			if (iter >= MAX_LMAC_COUNT)
164 				continue;
165 			lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),
166 					      iter);
167 			rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
168 			rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
169 			free_pkind = rvu_alloc_rsrc(&pkind->rsrc);
170 			pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
171 			rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);
172 			rvu->cgx_mapped_pfs++;
173 			rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);
174 			rvu->cgx_mapped_vfs += numvfs;
175 			pf++;
176 		}
177 	}
178 	return 0;
179 }
180 
rvu_cgx_send_link_info(int cgx_id,int lmac_id,struct rvu * rvu)181 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu)
182 {
183 	struct cgx_evq_entry *qentry;
184 	unsigned long flags;
185 	int err;
186 
187 	qentry = kmalloc(sizeof(*qentry), GFP_KERNEL);
188 	if (!qentry)
189 		return -ENOMEM;
190 
191 	/* Lock the event queue before we read the local link status */
192 	spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
193 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
194 				&qentry->link_event.link_uinfo);
195 	qentry->link_event.cgx_id = cgx_id;
196 	qentry->link_event.lmac_id = lmac_id;
197 	if (err) {
198 		kfree(qentry);
199 		goto skip_add;
200 	}
201 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
202 skip_add:
203 	spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
204 
205 	/* start worker to process the events */
206 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
207 
208 	return 0;
209 }
210 
211 /* This is called from interrupt context and is expected to be atomic */
cgx_lmac_postevent(struct cgx_link_event * event,void * data)212 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data)
213 {
214 	struct cgx_evq_entry *qentry;
215 	struct rvu *rvu = data;
216 
217 	/* post event to the event queue */
218 	qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC);
219 	if (!qentry)
220 		return -ENOMEM;
221 	qentry->link_event = *event;
222 	spin_lock(&rvu->cgx_evq_lock);
223 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
224 	spin_unlock(&rvu->cgx_evq_lock);
225 
226 	/* start worker to process the events */
227 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
228 
229 	return 0;
230 }
231 
cgx_notify_pfs(struct cgx_link_event * event,struct rvu * rvu)232 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)
233 {
234 	struct cgx_link_user_info *linfo;
235 	struct cgx_link_info_msg *msg;
236 	unsigned long pfmap;
237 	int pfid;
238 
239 	linfo = &event->link_uinfo;
240 	pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);
241 	if (!pfmap) {
242 		dev_err(rvu->dev, "CGX port%d:%d not mapped with PF\n",
243 			event->cgx_id, event->lmac_id);
244 		return;
245 	}
246 
247 	do {
248 		pfid = find_first_bit(&pfmap,
249 				      rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx);
250 		clear_bit(pfid, &pfmap);
251 
252 		/* check if notification is enabled */
253 		if (!test_bit(pfid, &rvu->pf_notify_bmap)) {
254 			dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n",
255 				 event->cgx_id, event->lmac_id,
256 				 linfo->link_up ? "UP" : "DOWN");
257 			continue;
258 		}
259 
260 		mutex_lock(&rvu->mbox_lock);
261 
262 		/* Send mbox message to PF */
263 		msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);
264 		if (!msg) {
265 			mutex_unlock(&rvu->mbox_lock);
266 			continue;
267 		}
268 
269 		msg->link_info = *linfo;
270 
271 		otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pfid);
272 
273 		otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pfid);
274 
275 		mutex_unlock(&rvu->mbox_lock);
276 	} while (pfmap);
277 }
278 
cgx_evhandler_task(struct work_struct * work)279 static void cgx_evhandler_task(struct work_struct *work)
280 {
281 	struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work);
282 	struct cgx_evq_entry *qentry;
283 	struct cgx_link_event *event;
284 	unsigned long flags;
285 
286 	do {
287 		/* Dequeue an event */
288 		spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
289 		qentry = list_first_entry_or_null(&rvu->cgx_evq_head,
290 						  struct cgx_evq_entry,
291 						  evq_node);
292 		if (qentry)
293 			list_del(&qentry->evq_node);
294 		spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
295 		if (!qentry)
296 			break; /* nothing more to process */
297 
298 		event = &qentry->link_event;
299 
300 		/* process event */
301 		cgx_notify_pfs(event, rvu);
302 		kfree(qentry);
303 	} while (1);
304 }
305 
cgx_lmac_event_handler_init(struct rvu * rvu)306 static int cgx_lmac_event_handler_init(struct rvu *rvu)
307 {
308 	unsigned long lmac_bmap;
309 	struct cgx_event_cb cb;
310 	int cgx, lmac, err;
311 	void *cgxd;
312 
313 	spin_lock_init(&rvu->cgx_evq_lock);
314 	INIT_LIST_HEAD(&rvu->cgx_evq_head);
315 	INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task);
316 	rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);
317 	if (!rvu->cgx_evh_wq) {
318 		dev_err(rvu->dev, "alloc workqueue failed");
319 		return -ENOMEM;
320 	}
321 
322 	cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */
323 	cb.data = rvu;
324 
325 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
326 		cgxd = rvu_cgx_pdata(cgx, rvu);
327 		if (!cgxd)
328 			continue;
329 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
330 		for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx) {
331 			err = cgx_lmac_evh_register(&cb, cgxd, lmac);
332 			if (err)
333 				dev_err(rvu->dev,
334 					"%d:%d handler register failed\n",
335 					cgx, lmac);
336 		}
337 	}
338 
339 	return 0;
340 }
341 
rvu_cgx_wq_destroy(struct rvu * rvu)342 static void rvu_cgx_wq_destroy(struct rvu *rvu)
343 {
344 	if (rvu->cgx_evh_wq) {
345 		destroy_workqueue(rvu->cgx_evh_wq);
346 		rvu->cgx_evh_wq = NULL;
347 	}
348 }
349 
rvu_cgx_init(struct rvu * rvu)350 int rvu_cgx_init(struct rvu *rvu)
351 {
352 	int cgx, err;
353 	void *cgxd;
354 
355 	/* CGX port id starts from 0 and are not necessarily contiguous
356 	 * Hence we allocate resources based on the maximum port id value.
357 	 */
358 	rvu->cgx_cnt_max = cgx_get_cgxcnt_max();
359 	if (!rvu->cgx_cnt_max) {
360 		dev_info(rvu->dev, "No CGX devices found!\n");
361 		return 0;
362 	}
363 
364 	rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max *
365 				      sizeof(void *), GFP_KERNEL);
366 	if (!rvu->cgx_idmap)
367 		return -ENOMEM;
368 
369 	/* Initialize the cgxdata table */
370 	for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++)
371 		rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);
372 
373 	/* Map CGX LMAC interfaces to RVU PFs */
374 	err = rvu_map_cgx_lmac_pf(rvu);
375 	if (err)
376 		return err;
377 
378 	/* Register for CGX events */
379 	err = cgx_lmac_event_handler_init(rvu);
380 	if (err)
381 		return err;
382 
383 	mutex_init(&rvu->cgx_cfg_lock);
384 
385 	/* Ensure event handler registration is completed, before
386 	 * we turn on the links
387 	 */
388 	mb();
389 
390 	/* Do link up for all CGX ports */
391 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
392 		cgxd = rvu_cgx_pdata(cgx, rvu);
393 		if (!cgxd)
394 			continue;
395 		err = cgx_lmac_linkup_start(cgxd);
396 		if (err)
397 			dev_err(rvu->dev,
398 				"Link up process failed to start on cgx %d\n",
399 				cgx);
400 	}
401 
402 	return 0;
403 }
404 
rvu_cgx_exit(struct rvu * rvu)405 int rvu_cgx_exit(struct rvu *rvu)
406 {
407 	unsigned long lmac_bmap;
408 	int cgx, lmac;
409 	void *cgxd;
410 
411 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
412 		cgxd = rvu_cgx_pdata(cgx, rvu);
413 		if (!cgxd)
414 			continue;
415 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
416 		for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx)
417 			cgx_lmac_evh_unregister(cgxd, lmac);
418 	}
419 
420 	/* Ensure event handler unregister is completed */
421 	mb();
422 
423 	rvu_cgx_wq_destroy(rvu);
424 	return 0;
425 }
426 
427 /* Most of the CGX configuration is restricted to the mapped PF only,
428  * VF's of mapped PF and other PFs are not allowed. This fn() checks
429  * whether a PFFUNC is permitted to do the config or not.
430  */
is_cgx_config_permitted(struct rvu * rvu,u16 pcifunc)431 inline bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc)
432 {
433 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
434 	    !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
435 		return false;
436 	return true;
437 }
438 
rvu_cgx_enadis_rx_bp(struct rvu * rvu,int pf,bool enable)439 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable)
440 {
441 	struct mac_ops *mac_ops;
442 	u8 cgx_id, lmac_id;
443 	void *cgxd;
444 
445 	if (!is_pf_cgxmapped(rvu, pf))
446 		return;
447 
448 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
449 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
450 
451 	mac_ops = get_mac_ops(cgxd);
452 	/* Set / clear CTL_BCK to control pause frame forwarding to NIX */
453 	if (enable)
454 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true);
455 	else
456 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false);
457 }
458 
rvu_cgx_config_rxtx(struct rvu * rvu,u16 pcifunc,bool start)459 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)
460 {
461 	int pf = rvu_get_pf(pcifunc);
462 	struct mac_ops *mac_ops;
463 	u8 cgx_id, lmac_id;
464 	void *cgxd;
465 
466 	if (!is_cgx_config_permitted(rvu, pcifunc))
467 		return LMAC_AF_ERR_PERM_DENIED;
468 
469 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
470 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
471 	mac_ops = get_mac_ops(cgxd);
472 
473 	return mac_ops->mac_rx_tx_enable(cgxd, lmac_id, start);
474 }
475 
rvu_cgx_tx_enable(struct rvu * rvu,u16 pcifunc,bool enable)476 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable)
477 {
478 	int pf = rvu_get_pf(pcifunc);
479 	struct mac_ops *mac_ops;
480 	u8 cgx_id, lmac_id;
481 	void *cgxd;
482 
483 	if (!is_cgx_config_permitted(rvu, pcifunc))
484 		return LMAC_AF_ERR_PERM_DENIED;
485 
486 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
487 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
488 	mac_ops = get_mac_ops(cgxd);
489 
490 	return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);
491 }
492 
rvu_cgx_config_tx(void * cgxd,int lmac_id,bool enable)493 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable)
494 {
495 	struct mac_ops *mac_ops;
496 
497 	mac_ops = get_mac_ops(cgxd);
498 	return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);
499 }
500 
rvu_cgx_disable_dmac_entries(struct rvu * rvu,u16 pcifunc)501 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc)
502 {
503 	int pf = rvu_get_pf(pcifunc);
504 	int i = 0, lmac_count = 0;
505 	struct mac_ops *mac_ops;
506 	u8 max_dmac_filters;
507 	u8 cgx_id, lmac_id;
508 	void *cgx_dev;
509 
510 	if (!is_cgx_config_permitted(rvu, pcifunc))
511 		return;
512 
513 	if (rvu_npc_exact_has_match_table(rvu)) {
514 		rvu_npc_exact_reset(rvu, pcifunc);
515 		return;
516 	}
517 
518 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
519 	cgx_dev = cgx_get_pdata(cgx_id);
520 	lmac_count = cgx_get_lmac_cnt(cgx_dev);
521 
522 	mac_ops = get_mac_ops(cgx_dev);
523 	if (!mac_ops)
524 		return;
525 
526 	max_dmac_filters = mac_ops->dmac_filter_count / lmac_count;
527 
528 	for (i = 0; i < max_dmac_filters; i++)
529 		cgx_lmac_addr_del(cgx_id, lmac_id, i);
530 
531 	/* As cgx_lmac_addr_del does not clear entry for index 0
532 	 * so it needs to be done explicitly
533 	 */
534 	cgx_lmac_addr_reset(cgx_id, lmac_id);
535 }
536 
rvu_mbox_handler_cgx_start_rxtx(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)537 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,
538 				    struct msg_rsp *rsp)
539 {
540 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true);
541 	return 0;
542 }
543 
rvu_mbox_handler_cgx_stop_rxtx(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)544 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,
545 				   struct msg_rsp *rsp)
546 {
547 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);
548 	return 0;
549 }
550 
rvu_lmac_get_stats(struct rvu * rvu,struct msg_req * req,void * rsp)551 static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req,
552 			      void *rsp)
553 {
554 	int pf = rvu_get_pf(req->hdr.pcifunc);
555 	struct mac_ops *mac_ops;
556 	int stat = 0, err = 0;
557 	u64 tx_stat, rx_stat;
558 	u8 cgx_idx, lmac;
559 	void *cgxd;
560 
561 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
562 		return LMAC_AF_ERR_PERM_DENIED;
563 
564 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
565 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
566 	mac_ops = get_mac_ops(cgxd);
567 
568 	/* Rx stats */
569 	while (stat < mac_ops->rx_stats_cnt) {
570 		err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat);
571 		if (err)
572 			return err;
573 		if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT)
574 			((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
575 		else
576 			((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
577 		stat++;
578 	}
579 
580 	/* Tx stats */
581 	stat = 0;
582 	while (stat < mac_ops->tx_stats_cnt) {
583 		err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat);
584 		if (err)
585 			return err;
586 		if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT)
587 			((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
588 		else
589 			((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
590 		stat++;
591 	}
592 	return 0;
593 }
594 
rvu_mbox_handler_cgx_stats(struct rvu * rvu,struct msg_req * req,struct cgx_stats_rsp * rsp)595 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,
596 			       struct cgx_stats_rsp *rsp)
597 {
598 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
599 }
600 
rvu_mbox_handler_rpm_stats(struct rvu * rvu,struct msg_req * req,struct rpm_stats_rsp * rsp)601 int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req,
602 			       struct rpm_stats_rsp *rsp)
603 {
604 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
605 }
606 
rvu_mbox_handler_cgx_fec_stats(struct rvu * rvu,struct msg_req * req,struct cgx_fec_stats_rsp * rsp)607 int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu,
608 				   struct msg_req *req,
609 				   struct cgx_fec_stats_rsp *rsp)
610 {
611 	int pf = rvu_get_pf(req->hdr.pcifunc);
612 	struct mac_ops *mac_ops;
613 	u8 cgx_idx, lmac;
614 	void *cgxd;
615 
616 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
617 		return LMAC_AF_ERR_PERM_DENIED;
618 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
619 
620 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
621 	mac_ops = get_mac_ops(cgxd);
622 	return  mac_ops->get_fec_stats(cgxd, lmac, rsp);
623 }
624 
rvu_mbox_handler_cgx_mac_addr_set(struct rvu * rvu,struct cgx_mac_addr_set_or_get * req,struct cgx_mac_addr_set_or_get * rsp)625 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,
626 				      struct cgx_mac_addr_set_or_get *req,
627 				      struct cgx_mac_addr_set_or_get *rsp)
628 {
629 	int pf = rvu_get_pf(req->hdr.pcifunc);
630 	u8 cgx_id, lmac_id;
631 
632 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
633 		return -EPERM;
634 
635 	if (rvu_npc_exact_has_match_table(rvu))
636 		return rvu_npc_exact_mac_addr_set(rvu, req, rsp);
637 
638 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
639 
640 	cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);
641 
642 	return 0;
643 }
644 
rvu_mbox_handler_cgx_mac_addr_add(struct rvu * rvu,struct cgx_mac_addr_add_req * req,struct cgx_mac_addr_add_rsp * rsp)645 int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu,
646 				      struct cgx_mac_addr_add_req *req,
647 				      struct cgx_mac_addr_add_rsp *rsp)
648 {
649 	int pf = rvu_get_pf(req->hdr.pcifunc);
650 	u8 cgx_id, lmac_id;
651 	int rc = 0;
652 
653 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
654 		return -EPERM;
655 
656 	if (rvu_npc_exact_has_match_table(rvu))
657 		return rvu_npc_exact_mac_addr_add(rvu, req, rsp);
658 
659 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
660 	rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr);
661 	if (rc >= 0) {
662 		rsp->index = rc;
663 		return 0;
664 	}
665 
666 	return rc;
667 }
668 
rvu_mbox_handler_cgx_mac_addr_del(struct rvu * rvu,struct cgx_mac_addr_del_req * req,struct msg_rsp * rsp)669 int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu,
670 				      struct cgx_mac_addr_del_req *req,
671 				      struct msg_rsp *rsp)
672 {
673 	int pf = rvu_get_pf(req->hdr.pcifunc);
674 	u8 cgx_id, lmac_id;
675 
676 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
677 		return -EPERM;
678 
679 	if (rvu_npc_exact_has_match_table(rvu))
680 		return rvu_npc_exact_mac_addr_del(rvu, req, rsp);
681 
682 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
683 	return cgx_lmac_addr_del(cgx_id, lmac_id, req->index);
684 }
685 
rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu * rvu,struct msg_req * req,struct cgx_max_dmac_entries_get_rsp * rsp)686 int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu,
687 					     struct msg_req *req,
688 					     struct cgx_max_dmac_entries_get_rsp
689 					     *rsp)
690 {
691 	int pf = rvu_get_pf(req->hdr.pcifunc);
692 	u8 cgx_id, lmac_id;
693 
694 	/* If msg is received from PFs(which are not mapped to CGX LMACs)
695 	 * or VF then no entries are allocated for DMAC filters at CGX level.
696 	 * So returning zero.
697 	 */
698 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) {
699 		rsp->max_dmac_filters = 0;
700 		return 0;
701 	}
702 
703 	if (rvu_npc_exact_has_match_table(rvu)) {
704 		rsp->max_dmac_filters = rvu_npc_exact_get_max_entries(rvu);
705 		return 0;
706 	}
707 
708 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
709 	rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id);
710 	return 0;
711 }
712 
rvu_mbox_handler_cgx_mac_addr_get(struct rvu * rvu,struct cgx_mac_addr_set_or_get * req,struct cgx_mac_addr_set_or_get * rsp)713 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,
714 				      struct cgx_mac_addr_set_or_get *req,
715 				      struct cgx_mac_addr_set_or_get *rsp)
716 {
717 	int pf = rvu_get_pf(req->hdr.pcifunc);
718 	u8 cgx_id, lmac_id;
719 	int rc = 0;
720 	u64 cfg;
721 
722 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
723 		return -EPERM;
724 
725 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
726 
727 	rsp->hdr.rc = rc;
728 	cfg = cgx_lmac_addr_get(cgx_id, lmac_id);
729 	/* copy 48 bit mac address to req->mac_addr */
730 	u64_to_ether_addr(cfg, rsp->mac_addr);
731 	return 0;
732 }
733 
rvu_mbox_handler_cgx_promisc_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)734 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,
735 					struct msg_rsp *rsp)
736 {
737 	u16 pcifunc = req->hdr.pcifunc;
738 	int pf = rvu_get_pf(pcifunc);
739 	u8 cgx_id, lmac_id;
740 
741 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
742 		return -EPERM;
743 
744 	/* Disable drop on non hit rule */
745 	if (rvu_npc_exact_has_match_table(rvu))
746 		return rvu_npc_exact_promisc_enable(rvu, req->hdr.pcifunc);
747 
748 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
749 
750 	cgx_lmac_promisc_config(cgx_id, lmac_id, true);
751 	return 0;
752 }
753 
rvu_mbox_handler_cgx_promisc_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)754 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,
755 					 struct msg_rsp *rsp)
756 {
757 	int pf = rvu_get_pf(req->hdr.pcifunc);
758 	u8 cgx_id, lmac_id;
759 
760 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
761 		return -EPERM;
762 
763 	/* Disable drop on non hit rule */
764 	if (rvu_npc_exact_has_match_table(rvu))
765 		return rvu_npc_exact_promisc_disable(rvu, req->hdr.pcifunc);
766 
767 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
768 
769 	cgx_lmac_promisc_config(cgx_id, lmac_id, false);
770 	return 0;
771 }
772 
rvu_cgx_ptp_rx_cfg(struct rvu * rvu,u16 pcifunc,bool enable)773 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
774 {
775 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
776 	int pf = rvu_get_pf(pcifunc);
777 	struct mac_ops *mac_ops;
778 	u8 cgx_id, lmac_id;
779 	void *cgxd;
780 
781 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))
782 		return 0;
783 
784 	/* This msg is expected only from PFs that are mapped to CGX LMACs,
785 	 * if received from other PF/VF simply ACK, nothing to do.
786 	 */
787 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
788 	    !is_pf_cgxmapped(rvu, pf))
789 		return -ENODEV;
790 
791 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
792 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
793 
794 	mac_ops = get_mac_ops(cgxd);
795 	mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, enable);
796 	/* If PTP is enabled then inform NPC that packets to be
797 	 * parsed by this PF will have their data shifted by 8 bytes
798 	 * and if PTP is disabled then no shift is required
799 	 */
800 	if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable))
801 		return -EINVAL;
802 	/* This flag is required to clean up CGX conf if app gets killed */
803 	pfvf->hw_rx_tstamp_en = enable;
804 
805 	/* Inform MCS about 8B RX header */
806 	rvu_mcs_ptp_cfg(rvu, cgx_id, lmac_id, enable);
807 	return 0;
808 }
809 
rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)810 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req,
811 				       struct msg_rsp *rsp)
812 {
813 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(req->hdr.pcifunc)))
814 		return -EPERM;
815 
816 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true);
817 }
818 
rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)819 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req,
820 					struct msg_rsp *rsp)
821 {
822 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false);
823 }
824 
rvu_cgx_config_linkevents(struct rvu * rvu,u16 pcifunc,bool en)825 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en)
826 {
827 	int pf = rvu_get_pf(pcifunc);
828 	u8 cgx_id, lmac_id;
829 
830 	if (!is_cgx_config_permitted(rvu, pcifunc))
831 		return -EPERM;
832 
833 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
834 
835 	if (en) {
836 		set_bit(pf, &rvu->pf_notify_bmap);
837 		/* Send the current link status to PF */
838 		rvu_cgx_send_link_info(cgx_id, lmac_id, rvu);
839 	} else {
840 		clear_bit(pf, &rvu->pf_notify_bmap);
841 	}
842 
843 	return 0;
844 }
845 
rvu_mbox_handler_cgx_start_linkevents(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)846 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,
847 					  struct msg_rsp *rsp)
848 {
849 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true);
850 	return 0;
851 }
852 
rvu_mbox_handler_cgx_stop_linkevents(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)853 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,
854 					 struct msg_rsp *rsp)
855 {
856 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false);
857 	return 0;
858 }
859 
rvu_mbox_handler_cgx_get_linkinfo(struct rvu * rvu,struct msg_req * req,struct cgx_link_info_msg * rsp)860 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,
861 				      struct cgx_link_info_msg *rsp)
862 {
863 	u8 cgx_id, lmac_id;
864 	int pf, err;
865 
866 	pf = rvu_get_pf(req->hdr.pcifunc);
867 
868 	if (!is_pf_cgxmapped(rvu, pf))
869 		return -ENODEV;
870 
871 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
872 
873 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
874 				&rsp->link_info);
875 	return err;
876 }
877 
rvu_mbox_handler_cgx_features_get(struct rvu * rvu,struct msg_req * req,struct cgx_features_info_msg * rsp)878 int rvu_mbox_handler_cgx_features_get(struct rvu *rvu,
879 				      struct msg_req *req,
880 				      struct cgx_features_info_msg *rsp)
881 {
882 	int pf = rvu_get_pf(req->hdr.pcifunc);
883 	u8 cgx_idx, lmac;
884 	void *cgxd;
885 
886 	if (!is_pf_cgxmapped(rvu, pf))
887 		return 0;
888 
889 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
890 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
891 	rsp->lmac_features = cgx_features_get(cgxd);
892 
893 	return 0;
894 }
895 
rvu_cgx_get_fifolen(struct rvu * rvu)896 u32 rvu_cgx_get_fifolen(struct rvu *rvu)
897 {
898 	struct mac_ops *mac_ops;
899 	u32 fifo_len;
900 
901 	mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu));
902 	fifo_len = mac_ops ? mac_ops->fifo_len : 0;
903 
904 	return fifo_len;
905 }
906 
rvu_cgx_get_lmac_fifolen(struct rvu * rvu,int cgx,int lmac)907 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac)
908 {
909 	struct mac_ops *mac_ops;
910 	void *cgxd;
911 
912 	cgxd = rvu_cgx_pdata(cgx, rvu);
913 	if (!cgxd)
914 		return 0;
915 
916 	mac_ops = get_mac_ops(cgxd);
917 	if (!mac_ops->lmac_fifo_len)
918 		return 0;
919 
920 	return mac_ops->lmac_fifo_len(cgxd, lmac);
921 }
922 
rvu_cgx_config_intlbk(struct rvu * rvu,u16 pcifunc,bool en)923 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en)
924 {
925 	int pf = rvu_get_pf(pcifunc);
926 	struct mac_ops *mac_ops;
927 	u8 cgx_id, lmac_id;
928 
929 	if (!is_cgx_config_permitted(rvu, pcifunc))
930 		return -EPERM;
931 
932 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
933 	mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));
934 
935 	return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),
936 					  lmac_id, en);
937 }
938 
rvu_mbox_handler_cgx_intlbk_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)939 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,
940 				       struct msg_rsp *rsp)
941 {
942 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true);
943 	return 0;
944 }
945 
rvu_mbox_handler_cgx_intlbk_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)946 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,
947 					struct msg_rsp *rsp)
948 {
949 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false);
950 	return 0;
951 }
952 
rvu_cgx_cfg_pause_frm(struct rvu * rvu,u16 pcifunc,u8 tx_pause,u8 rx_pause)953 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause)
954 {
955 	int pf = rvu_get_pf(pcifunc);
956 	u8 rx_pfc = 0, tx_pfc = 0;
957 	struct mac_ops *mac_ops;
958 	u8 cgx_id, lmac_id;
959 	void *cgxd;
960 
961 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC))
962 		return 0;
963 
964 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
965 	 * if received from other PF/VF simply ACK, nothing to do.
966 	 */
967 	if (!is_pf_cgxmapped(rvu, pf))
968 		return LMAC_AF_ERR_PF_NOT_MAPPED;
969 
970 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
971 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
972 	mac_ops = get_mac_ops(cgxd);
973 
974 	mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &tx_pfc, &rx_pfc);
975 	if (tx_pfc || rx_pfc) {
976 		dev_warn(rvu->dev,
977 			 "Can not configure 802.3X flow control as PFC frames are enabled");
978 		return LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED;
979 	}
980 
981 	mutex_lock(&rvu->rsrc_lock);
982 	if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause,
983 			       pcifunc & RVU_PFVF_FUNC_MASK)) {
984 		mutex_unlock(&rvu->rsrc_lock);
985 		return LMAC_AF_ERR_PERM_DENIED;
986 	}
987 	mutex_unlock(&rvu->rsrc_lock);
988 
989 	return mac_ops->mac_enadis_pause_frm(cgxd, lmac_id, tx_pause, rx_pause);
990 }
991 
rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu * rvu,struct cgx_pause_frm_cfg * req,struct cgx_pause_frm_cfg * rsp)992 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu,
993 				       struct cgx_pause_frm_cfg *req,
994 				       struct cgx_pause_frm_cfg *rsp)
995 {
996 	int pf = rvu_get_pf(req->hdr.pcifunc);
997 	struct mac_ops *mac_ops;
998 	u8 cgx_id, lmac_id;
999 	int err = 0;
1000 	void *cgxd;
1001 
1002 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
1003 	 * if received from other PF/VF simply ACK, nothing to do.
1004 	 */
1005 	if (!is_pf_cgxmapped(rvu, pf))
1006 		return -ENODEV;
1007 
1008 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1009 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
1010 	mac_ops = get_mac_ops(cgxd);
1011 
1012 	if (req->set)
1013 		err = rvu_cgx_cfg_pause_frm(rvu, req->hdr.pcifunc, req->tx_pause, req->rx_pause);
1014 	else
1015 		mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause);
1016 
1017 	return err;
1018 }
1019 
rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)1020 int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req,
1021 					   struct msg_rsp *rsp)
1022 {
1023 	int pf = rvu_get_pf(req->hdr.pcifunc);
1024 	u8 cgx_id, lmac_id;
1025 
1026 	if (!is_pf_cgxmapped(rvu, pf))
1027 		return LMAC_AF_ERR_PF_NOT_MAPPED;
1028 
1029 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1030 	return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id);
1031 }
1032 
1033 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those
1034  * from its VFs as well. ie. NIX rx/tx counters at the CGX port level
1035  */
rvu_cgx_nix_cuml_stats(struct rvu * rvu,void * cgxd,int lmac_id,int index,int rxtxflag,u64 * stat)1036 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id,
1037 			   int index, int rxtxflag, u64 *stat)
1038 {
1039 	struct rvu_block *block;
1040 	int blkaddr;
1041 	u16 pcifunc;
1042 	int pf, lf;
1043 
1044 	*stat = 0;
1045 
1046 	if (!cgxd || !rvu)
1047 		return -EINVAL;
1048 
1049 	pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);
1050 	if (pf < 0)
1051 		return pf;
1052 
1053 	/* Assumes LF of a PF and all of its VF belongs to the same
1054 	 * NIX block
1055 	 */
1056 	pcifunc = pf << RVU_PFVF_PF_SHIFT;
1057 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1058 	if (blkaddr < 0)
1059 		return 0;
1060 	block = &rvu->hw->block[blkaddr];
1061 
1062 	for (lf = 0; lf < block->lf.max; lf++) {
1063 		/* Check if a lf is attached to this PF or one of its VFs */
1064 		if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc &
1065 			 ~RVU_PFVF_FUNC_MASK)))
1066 			continue;
1067 		if (rxtxflag == NIX_STATS_RX)
1068 			*stat += rvu_read64(rvu, blkaddr,
1069 					    NIX_AF_LFX_RX_STATX(lf, index));
1070 		else
1071 			*stat += rvu_read64(rvu, blkaddr,
1072 					    NIX_AF_LFX_TX_STATX(lf, index));
1073 	}
1074 
1075 	return 0;
1076 }
1077 
rvu_cgx_start_stop_io(struct rvu * rvu,u16 pcifunc,bool start)1078 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start)
1079 {
1080 	struct rvu_pfvf *parent_pf, *pfvf;
1081 	int cgx_users, err = 0;
1082 
1083 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
1084 		return 0;
1085 
1086 	parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
1087 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1088 
1089 	mutex_lock(&rvu->cgx_cfg_lock);
1090 
1091 	if (start && pfvf->cgx_in_use)
1092 		goto exit;  /* CGX is already started hence nothing to do */
1093 	if (!start && !pfvf->cgx_in_use)
1094 		goto exit; /* CGX is already stopped hence nothing to do */
1095 
1096 	if (start) {
1097 		cgx_users = parent_pf->cgx_users;
1098 		parent_pf->cgx_users++;
1099 	} else {
1100 		parent_pf->cgx_users--;
1101 		cgx_users = parent_pf->cgx_users;
1102 	}
1103 
1104 	/* Start CGX when first of all NIXLFs is started.
1105 	 * Stop CGX when last of all NIXLFs is stopped.
1106 	 */
1107 	if (!cgx_users) {
1108 		err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK,
1109 					  start);
1110 		if (err) {
1111 			dev_err(rvu->dev, "Unable to %s CGX\n",
1112 				start ? "start" : "stop");
1113 			/* Revert the usage count in case of error */
1114 			parent_pf->cgx_users = start ? parent_pf->cgx_users  - 1
1115 					       : parent_pf->cgx_users  + 1;
1116 			goto exit;
1117 		}
1118 	}
1119 	pfvf->cgx_in_use = start;
1120 exit:
1121 	mutex_unlock(&rvu->cgx_cfg_lock);
1122 	return err;
1123 }
1124 
rvu_mbox_handler_cgx_set_fec_param(struct rvu * rvu,struct fec_mode * req,struct fec_mode * rsp)1125 int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu,
1126 				       struct fec_mode *req,
1127 				       struct fec_mode *rsp)
1128 {
1129 	int pf = rvu_get_pf(req->hdr.pcifunc);
1130 	u8 cgx_id, lmac_id;
1131 
1132 	if (!is_pf_cgxmapped(rvu, pf))
1133 		return -EPERM;
1134 
1135 	if (req->fec == OTX2_FEC_OFF)
1136 		req->fec = OTX2_FEC_NONE;
1137 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1138 	rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id);
1139 	return 0;
1140 }
1141 
rvu_mbox_handler_cgx_get_aux_link_info(struct rvu * rvu,struct msg_req * req,struct cgx_fw_data * rsp)1142 int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req,
1143 					   struct cgx_fw_data *rsp)
1144 {
1145 	int pf = rvu_get_pf(req->hdr.pcifunc);
1146 	u8 cgx_id, lmac_id;
1147 
1148 	if (!rvu->fwdata)
1149 		return LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED;
1150 
1151 	if (!is_pf_cgxmapped(rvu, pf))
1152 		return -EPERM;
1153 
1154 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1155 
1156 	if (rvu->hw->lmac_per_cgx == CGX_LMACS_USX)
1157 		memcpy(&rsp->fwdata,
1158 		       &rvu->fwdata->cgx_fw_data_usx[cgx_id][lmac_id],
1159 		       sizeof(struct cgx_lmac_fwdata_s));
1160 	else
1161 		memcpy(&rsp->fwdata,
1162 		       &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id],
1163 		       sizeof(struct cgx_lmac_fwdata_s));
1164 
1165 	return 0;
1166 }
1167 
rvu_mbox_handler_cgx_set_link_mode(struct rvu * rvu,struct cgx_set_link_mode_req * req,struct cgx_set_link_mode_rsp * rsp)1168 int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
1169 				       struct cgx_set_link_mode_req *req,
1170 				       struct cgx_set_link_mode_rsp *rsp)
1171 {
1172 	int pf = rvu_get_pf(req->hdr.pcifunc);
1173 	u8 cgx_idx, lmac;
1174 	void *cgxd;
1175 
1176 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1177 		return -EPERM;
1178 
1179 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
1180 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
1181 	rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);
1182 	return 0;
1183 }
1184 
rvu_mbox_handler_cgx_mac_addr_reset(struct rvu * rvu,struct cgx_mac_addr_reset_req * req,struct msg_rsp * rsp)1185 int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct cgx_mac_addr_reset_req *req,
1186 					struct msg_rsp *rsp)
1187 {
1188 	int pf = rvu_get_pf(req->hdr.pcifunc);
1189 	u8 cgx_id, lmac_id;
1190 
1191 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1192 		return LMAC_AF_ERR_PERM_DENIED;
1193 
1194 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1195 
1196 	if (rvu_npc_exact_has_match_table(rvu))
1197 		return rvu_npc_exact_mac_addr_reset(rvu, req, rsp);
1198 
1199 	return cgx_lmac_addr_reset(cgx_id, lmac_id);
1200 }
1201 
rvu_mbox_handler_cgx_mac_addr_update(struct rvu * rvu,struct cgx_mac_addr_update_req * req,struct cgx_mac_addr_update_rsp * rsp)1202 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,
1203 					 struct cgx_mac_addr_update_req *req,
1204 					 struct cgx_mac_addr_update_rsp *rsp)
1205 {
1206 	int pf = rvu_get_pf(req->hdr.pcifunc);
1207 	u8 cgx_id, lmac_id;
1208 
1209 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1210 		return LMAC_AF_ERR_PERM_DENIED;
1211 
1212 	if (rvu_npc_exact_has_match_table(rvu))
1213 		return rvu_npc_exact_mac_addr_update(rvu, req, rsp);
1214 
1215 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1216 	return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index);
1217 }
1218 
rvu_cgx_prio_flow_ctrl_cfg(struct rvu * rvu,u16 pcifunc,u8 tx_pause,u8 rx_pause,u16 pfc_en)1219 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause,
1220 			       u8 rx_pause, u16 pfc_en)
1221 {
1222 	int pf = rvu_get_pf(pcifunc);
1223 	u8 rx_8023 = 0, tx_8023 = 0;
1224 	struct mac_ops *mac_ops;
1225 	u8 cgx_id, lmac_id;
1226 	void *cgxd;
1227 
1228 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
1229 	 * if received from other PF/VF simply ACK, nothing to do.
1230 	 */
1231 	if (!is_pf_cgxmapped(rvu, pf))
1232 		return -ENODEV;
1233 
1234 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1235 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
1236 	mac_ops = get_mac_ops(cgxd);
1237 
1238 	mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &tx_8023, &rx_8023);
1239 	if (tx_8023 || rx_8023) {
1240 		dev_warn(rvu->dev,
1241 			 "Can not configure PFC as 802.3X pause frames are enabled");
1242 		return LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED;
1243 	}
1244 
1245 	mutex_lock(&rvu->rsrc_lock);
1246 	if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause,
1247 			       pcifunc & RVU_PFVF_FUNC_MASK)) {
1248 		mutex_unlock(&rvu->rsrc_lock);
1249 		return LMAC_AF_ERR_PERM_DENIED;
1250 	}
1251 	mutex_unlock(&rvu->rsrc_lock);
1252 
1253 	return mac_ops->pfc_config(cgxd, lmac_id, tx_pause, rx_pause, pfc_en);
1254 }
1255 
rvu_mbox_handler_cgx_prio_flow_ctrl_cfg(struct rvu * rvu,struct cgx_pfc_cfg * req,struct cgx_pfc_rsp * rsp)1256 int rvu_mbox_handler_cgx_prio_flow_ctrl_cfg(struct rvu *rvu,
1257 					    struct cgx_pfc_cfg *req,
1258 					    struct cgx_pfc_rsp *rsp)
1259 {
1260 	int pf = rvu_get_pf(req->hdr.pcifunc);
1261 	struct mac_ops *mac_ops;
1262 	u8 cgx_id, lmac_id;
1263 	void *cgxd;
1264 	int err;
1265 
1266 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
1267 	 * if received from other PF/VF simply ACK, nothing to do.
1268 	 */
1269 	if (!is_pf_cgxmapped(rvu, pf))
1270 		return -ENODEV;
1271 
1272 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1273 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
1274 	mac_ops = get_mac_ops(cgxd);
1275 
1276 	err = rvu_cgx_prio_flow_ctrl_cfg(rvu, req->hdr.pcifunc, req->tx_pause,
1277 					 req->rx_pause, req->pfc_en);
1278 
1279 	mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause);
1280 	return err;
1281 }
1282 
rvu_mac_reset(struct rvu * rvu,u16 pcifunc)1283 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc)
1284 {
1285 	int pf = rvu_get_pf(pcifunc);
1286 	struct mac_ops *mac_ops;
1287 	struct cgx *cgxd;
1288 	u8 cgx, lmac;
1289 
1290 	if (!is_pf_cgxmapped(rvu, pf))
1291 		return;
1292 
1293 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac);
1294 	cgxd = rvu_cgx_pdata(cgx, rvu);
1295 	mac_ops = get_mac_ops(cgxd);
1296 
1297 	if (mac_ops->mac_reset(cgxd, lmac, !is_vf(pcifunc)))
1298 		dev_err(rvu->dev, "Failed to reset MAC\n");
1299 }
1300