1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*****************************************************************************
3  *                                                                           *
4  * File: common.h                                                            *
5  * $Revision: 1.21 $                                                         *
6  * $Date: 2005/06/22 00:43:25 $                                              *
7  * Description:                                                              *
8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
9  *                                                                           *
10  *                                                                           *
11  * http://www.chelsio.com                                                    *
12  *                                                                           *
13  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
14  * All rights reserved.                                                      *
15  *                                                                           *
16  * Maintainers: maintainers@chelsio.com                                      *
17  *                                                                           *
18  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
19  *          Tina Yang               <tainay@chelsio.com>                     *
20  *          Felix Marti             <felix@chelsio.com>                      *
21  *          Scott Bardone           <sbardone@chelsio.com>                   *
22  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
23  *          Frank DiMambro          <frank@chelsio.com>                      *
24  *                                                                           *
25  * History:                                                                  *
26  *                                                                           *
27  ****************************************************************************/
28 
29 #define pr_fmt(fmt) "cxgb: " fmt
30 
31 #ifndef _CXGB_COMMON_H_
32 #define _CXGB_COMMON_H_
33 
34 #include <linux/module.h>
35 #include <linux/netdevice.h>
36 #include <linux/types.h>
37 #include <linux/delay.h>
38 #include <linux/pci.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/mdio.h>
42 #include <linux/crc32.h>
43 #include <linux/slab.h>
44 #include <asm/io.h>
45 #include <linux/pci_ids.h>
46 
47 #define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
48 #define DRV_NAME "cxgb"
49 
50 #define CH_DEVICE(devid, ssid, idx) \
51 	{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
52 
53 #define SUPPORTED_PAUSE       (1 << 13)
54 #define SUPPORTED_LOOPBACK    (1 << 15)
55 
56 #define ADVERTISED_PAUSE      (1 << 13)
57 #define ADVERTISED_ASYM_PAUSE (1 << 14)
58 
59 typedef struct adapter adapter_t;
60 
61 struct t1_rx_mode {
62        struct net_device *dev;
63 };
64 
65 #define t1_rx_mode_promisc(rm)	(rm->dev->flags & IFF_PROMISC)
66 #define t1_rx_mode_allmulti(rm)	(rm->dev->flags & IFF_ALLMULTI)
67 #define t1_rx_mode_mc_cnt(rm)	(netdev_mc_count(rm->dev))
68 #define t1_get_netdev(rm)	(rm->dev)
69 
70 #define	MAX_NPORTS 4
71 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
72 #define NMTUS      8
73 #define TCB_SIZE   128
74 
75 #define SPEED_INVALID 0xffff
76 #define DUPLEX_INVALID 0xff
77 
78 /* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
79 #define PM3393_MAX_FRAME_SIZE 9600
80 
81 #define VSC7326_MAX_MTU 9600
82 
83 enum {
84 	CHBT_BOARD_N110,
85 	CHBT_BOARD_N210,
86 	CHBT_BOARD_7500,
87 	CHBT_BOARD_8000,
88 	CHBT_BOARD_CHT101,
89 	CHBT_BOARD_CHT110,
90 	CHBT_BOARD_CHT210,
91 	CHBT_BOARD_CHT204,
92 	CHBT_BOARD_CHT204V,
93 	CHBT_BOARD_CHT204E,
94 	CHBT_BOARD_CHN204,
95 	CHBT_BOARD_COUGAR,
96 	CHBT_BOARD_6800,
97 	CHBT_BOARD_SIMUL,
98 };
99 
100 enum {
101 	CHBT_TERM_FPGA,
102 	CHBT_TERM_T1,
103 	CHBT_TERM_T2,
104 	CHBT_TERM_T3
105 };
106 
107 enum {
108 	CHBT_MAC_CHELSIO_A,
109 	CHBT_MAC_IXF1010,
110 	CHBT_MAC_PM3393,
111 	CHBT_MAC_VSC7321,
112 	CHBT_MAC_DUMMY
113 };
114 
115 enum {
116 	CHBT_PHY_88E1041,
117 	CHBT_PHY_88E1111,
118 	CHBT_PHY_88X2010,
119 	CHBT_PHY_XPAK,
120 	CHBT_PHY_MY3126,
121 	CHBT_PHY_8244,
122 	CHBT_PHY_DUMMY
123 };
124 
125 enum {
126 	PAUSE_RX      = 1 << 0,
127 	PAUSE_TX      = 1 << 1,
128 	PAUSE_AUTONEG = 1 << 2
129 };
130 
131 /* Revisions of T1 chip */
132 enum {
133 	TERM_T1A   = 0,
134 	TERM_T1B   = 1,
135 	TERM_T2    = 3
136 };
137 
138 struct sge_params {
139 	unsigned int cmdQ_size[2];
140 	unsigned int freelQ_size[2];
141 	unsigned int large_buf_capacity;
142 	unsigned int rx_coalesce_usecs;
143 	unsigned int last_rx_coalesce_raw;
144 	unsigned int default_rx_coalesce_usecs;
145 	unsigned int sample_interval_usecs;
146 	unsigned int coalesce_enable;
147 	unsigned int polling;
148 };
149 
150 struct chelsio_pci_params {
151 	unsigned short speed;
152 	unsigned char  width;
153 	unsigned char  is_pcix;
154 };
155 
156 struct tp_params {
157 	unsigned int pm_size;
158 	unsigned int cm_size;
159 	unsigned int pm_rx_base;
160 	unsigned int pm_tx_base;
161 	unsigned int pm_rx_pg_size;
162 	unsigned int pm_tx_pg_size;
163 	unsigned int pm_rx_num_pgs;
164 	unsigned int pm_tx_num_pgs;
165 	unsigned int rx_coalescing_size;
166 	unsigned int use_5tuple_mode;
167 };
168 
169 struct mc5_params {
170 	unsigned int mode;       /* selects MC5 width */
171 	unsigned int nservers;   /* size of server region */
172 	unsigned int nroutes;    /* size of routing region */
173 };
174 
175 /* Default MC5 region sizes */
176 #define DEFAULT_SERVER_REGION_LEN 256
177 #define DEFAULT_RT_REGION_LEN 1024
178 
179 struct adapter_params {
180 	struct sge_params sge;
181 	struct mc5_params mc5;
182 	struct tp_params  tp;
183 	struct chelsio_pci_params pci;
184 
185 	const struct board_info *brd_info;
186 
187 	unsigned short mtus[NMTUS];
188 	unsigned int   nports;          /* # of ethernet ports */
189 	unsigned int   stats_update_period;
190 	unsigned short chip_revision;
191 	unsigned char  chip_version;
192 	unsigned char  is_asic;
193 	unsigned char  has_msi;
194 };
195 
196 struct link_config {
197 	unsigned int   supported;        /* link capabilities */
198 	unsigned int   advertising;      /* advertised capabilities */
199 	unsigned short requested_speed;  /* speed user has requested */
200 	unsigned short speed;            /* actual link speed */
201 	unsigned char  requested_duplex; /* duplex user has requested */
202 	unsigned char  duplex;           /* actual link duplex */
203 	unsigned char  requested_fc;     /* flow control user has requested */
204 	unsigned char  fc;               /* actual link flow control */
205 	unsigned char  autoneg;          /* autonegotiating? */
206 };
207 
208 struct cmac;
209 struct cphy;
210 
211 struct port_info {
212 	struct net_device *dev;
213 	struct cmac *mac;
214 	struct cphy *phy;
215 	struct link_config link_config;
216 };
217 
218 struct sge;
219 struct peespi;
220 
221 struct adapter {
222 	u8 __iomem *regs;
223 	struct pci_dev *pdev;
224 	unsigned long registered_device_map;
225 	unsigned long open_device_map;
226 	unsigned long flags;
227 
228 	const char *name;
229 	int msg_enable;
230 	u32 mmio_len;
231 
232 	struct adapter_params params;
233 
234 	/* Terminator modules. */
235 	struct sge    *sge;
236 	struct peespi *espi;
237 	struct petp   *tp;
238 
239 	struct napi_struct napi;
240 	struct port_info port[MAX_NPORTS];
241 	struct delayed_work stats_update_task;
242 	struct timer_list stats_update_timer;
243 
244 	spinlock_t tpi_lock;
245 	spinlock_t work_lock;
246 	spinlock_t mac_lock;
247 
248 	/* guards async operations */
249 	spinlock_t async_lock ____cacheline_aligned;
250 	u32 pending_thread_intr;
251 	u32 slow_intr_mask;
252 	int t1powersave;
253 };
254 
255 enum {                                           /* adapter flags */
256 	FULL_INIT_DONE        = 1 << 0,
257 };
258 
259 struct mdio_ops;
260 struct gmac;
261 struct gphy;
262 
263 struct board_info {
264 	unsigned char           board;
265 	unsigned char           port_number;
266 	unsigned long           caps;
267 	unsigned char           chip_term;
268 	unsigned char           chip_mac;
269 	unsigned char           chip_phy;
270 	unsigned int            clock_core;
271 	unsigned int            clock_mc3;
272 	unsigned int            clock_mc4;
273 	unsigned int            espi_nports;
274 	unsigned int            clock_elmer0;
275 	unsigned char           mdio_mdien;
276 	unsigned char           mdio_mdiinv;
277 	unsigned char           mdio_mdc;
278 	unsigned char           mdio_phybaseaddr;
279 	const struct gmac      *gmac;
280 	const struct gphy      *gphy;
281 	const struct mdio_ops  *mdio_ops;
282 	const char             *desc;
283 };
284 
t1_is_asic(const adapter_t * adapter)285 static inline int t1_is_asic(const adapter_t *adapter)
286 {
287 	return adapter->params.is_asic;
288 }
289 
290 extern const struct pci_device_id t1_pci_tbl[];
291 
adapter_matches_type(const adapter_t * adapter,int version,int revision)292 static inline int adapter_matches_type(const adapter_t *adapter,
293 				       int version, int revision)
294 {
295 	return adapter->params.chip_version == version &&
296 	       adapter->params.chip_revision == revision;
297 }
298 
299 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
300 #define is_T2(adap)     adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
301 
302 /* Returns true if an adapter supports VLAN acceleration and TSO */
vlan_tso_capable(const adapter_t * adapter)303 static inline int vlan_tso_capable(const adapter_t *adapter)
304 {
305 	return !t1_is_T1B(adapter);
306 }
307 
308 #define for_each_port(adapter, iter) \
309 	for (iter = 0; iter < (adapter)->params.nports; ++iter)
310 
311 #define board_info(adapter) ((adapter)->params.brd_info)
312 #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
313 
core_ticks_per_usec(const adapter_t * adap)314 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
315 {
316 	return board_info(adap)->clock_core / 1000000;
317 }
318 
319 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
320 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
321 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
322 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
323 
324 void t1_interrupts_enable(adapter_t *adapter);
325 void t1_interrupts_disable(adapter_t *adapter);
326 void t1_interrupts_clear(adapter_t *adapter);
327 int t1_elmer0_ext_intr_handler(adapter_t *adapter);
328 irqreturn_t t1_slow_intr_handler(adapter_t *adapter);
329 
330 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
331 const struct board_info *t1_get_board_info(unsigned int board_id);
332 const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
333 						    unsigned short ssid);
334 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
335 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
336 		     struct adapter_params *p);
337 int t1_init_hw_modules(adapter_t *adapter);
338 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
339 void t1_free_sw_modules(adapter_t *adapter);
340 void t1_link_changed(adapter_t *adapter, int port_id);
341 void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
342 			    int speed, int duplex, int pause);
343 #endif /* _CXGB_COMMON_H_ */
344