1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include <linux/slab.h>
27 
28 #include "dm_services.h"
29 
30 #include "include/logger_interface.h"
31 
32 #include "../dce110/irq_service_dce110.h"
33 
34 #include "dcn/dcn_2_0_0_offset.h"
35 #include "dcn/dcn_2_0_0_sh_mask.h"
36 #include "navi10_ip_offset.h"
37 
38 
39 #include "irq_service_dcn20.h"
40 
41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
42 
to_dal_irq_source_dcn20(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)43 static enum dc_irq_source to_dal_irq_source_dcn20(
44 		struct irq_service *irq_service,
45 		uint32_t src_id,
46 		uint32_t ext_id)
47 {
48 	switch (src_id) {
49 	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
50 		return DC_IRQ_SOURCE_VBLANK1;
51 	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
52 		return DC_IRQ_SOURCE_VBLANK2;
53 	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
54 		return DC_IRQ_SOURCE_VBLANK3;
55 	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
56 		return DC_IRQ_SOURCE_VBLANK4;
57 	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
58 		return DC_IRQ_SOURCE_VBLANK5;
59 	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
60 		return DC_IRQ_SOURCE_VBLANK6;
61 	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
62 		return DC_IRQ_SOURCE_DC1_VLINE0;
63 	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
64 		return DC_IRQ_SOURCE_DC2_VLINE0;
65 	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
66 		return DC_IRQ_SOURCE_DC3_VLINE0;
67 	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
68 		return DC_IRQ_SOURCE_DC4_VLINE0;
69 	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
70 		return DC_IRQ_SOURCE_DC5_VLINE0;
71 	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
72 		return DC_IRQ_SOURCE_DC6_VLINE0;
73 	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
74 		return DC_IRQ_SOURCE_PFLIP1;
75 	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
76 		return DC_IRQ_SOURCE_PFLIP2;
77 	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
78 		return DC_IRQ_SOURCE_PFLIP3;
79 	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
80 		return DC_IRQ_SOURCE_PFLIP4;
81 	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
82 		return DC_IRQ_SOURCE_PFLIP5;
83 	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
84 		return DC_IRQ_SOURCE_PFLIP6;
85 	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
86 		return DC_IRQ_SOURCE_VUPDATE1;
87 	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 		return DC_IRQ_SOURCE_VUPDATE2;
89 	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 		return DC_IRQ_SOURCE_VUPDATE3;
91 	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
92 		return DC_IRQ_SOURCE_VUPDATE4;
93 	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
94 		return DC_IRQ_SOURCE_VUPDATE5;
95 	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
96 		return DC_IRQ_SOURCE_VUPDATE6;
97 
98 	case DCN_1_0__SRCID__DC_HPD1_INT:
99 		/* generic src_id for all HPD and HPDRX interrupts */
100 		switch (ext_id) {
101 		case DCN_1_0__CTXID__DC_HPD1_INT:
102 			return DC_IRQ_SOURCE_HPD1;
103 		case DCN_1_0__CTXID__DC_HPD2_INT:
104 			return DC_IRQ_SOURCE_HPD2;
105 		case DCN_1_0__CTXID__DC_HPD3_INT:
106 			return DC_IRQ_SOURCE_HPD3;
107 		case DCN_1_0__CTXID__DC_HPD4_INT:
108 			return DC_IRQ_SOURCE_HPD4;
109 		case DCN_1_0__CTXID__DC_HPD5_INT:
110 			return DC_IRQ_SOURCE_HPD5;
111 		case DCN_1_0__CTXID__DC_HPD6_INT:
112 			return DC_IRQ_SOURCE_HPD6;
113 		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
114 			return DC_IRQ_SOURCE_HPD1RX;
115 		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
116 			return DC_IRQ_SOURCE_HPD2RX;
117 		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
118 			return DC_IRQ_SOURCE_HPD3RX;
119 		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
120 			return DC_IRQ_SOURCE_HPD4RX;
121 		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
122 			return DC_IRQ_SOURCE_HPD5RX;
123 		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
124 			return DC_IRQ_SOURCE_HPD6RX;
125 		default:
126 			return DC_IRQ_SOURCE_INVALID;
127 		}
128 		break;
129 
130 	default:
131 		return DC_IRQ_SOURCE_INVALID;
132 	}
133 }
134 
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)135 static bool hpd_ack(
136 	struct irq_service *irq_service,
137 	const struct irq_source_info *info)
138 {
139 	uint32_t addr = info->status_reg;
140 	uint32_t value = dm_read_reg(irq_service->ctx, addr);
141 	uint32_t current_status =
142 		get_reg_field_value(
143 			value,
144 			HPD0_DC_HPD_INT_STATUS,
145 			DC_HPD_SENSE_DELAYED);
146 
147 	dal_irq_service_ack_generic(irq_service, info);
148 
149 	value = dm_read_reg(irq_service->ctx, info->enable_reg);
150 
151 	set_reg_field_value(
152 		value,
153 		current_status ? 0 : 1,
154 		HPD0_DC_HPD_INT_CONTROL,
155 		DC_HPD_INT_POLARITY);
156 
157 	dm_write_reg(irq_service->ctx, info->enable_reg, value);
158 
159 	return true;
160 }
161 
162 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
163 	.set = NULL,
164 	.ack = hpd_ack
165 };
166 
167 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
168 	.set = NULL,
169 	.ack = NULL
170 };
171 
172 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
173 	.set = NULL,
174 	.ack = NULL
175 };
176 
177 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
178 	.set = NULL,
179 	.ack = NULL
180 };
181 
182 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
183 	.set = NULL,
184 	.ack = NULL
185 };
186 
187 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
188 	.set = NULL,
189 	.ack = NULL
190 };
191 
192 #undef BASE_INNER
193 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
194 
195 /* compile time expand base address. */
196 #define BASE(seg) \
197 	BASE_INNER(seg)
198 
199 
200 #define SRI(reg_name, block, id)\
201 	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
202 			mm ## block ## id ## _ ## reg_name
203 
204 
205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
206 	.enable_reg = SRI(reg1, block, reg_num),\
207 	.enable_mask = \
208 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 	.enable_value = {\
210 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
211 		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
212 	},\
213 	.ack_reg = SRI(reg2, block, reg_num),\
214 	.ack_mask = \
215 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
216 	.ack_value = \
217 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
218 
219 
220 
221 #define hpd_int_entry(reg_num)\
222 	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
223 		IRQ_REG_ENTRY(HPD, reg_num,\
224 			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
225 			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
226 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
227 		.funcs = &hpd_irq_info_funcs\
228 	}
229 
230 #define hpd_rx_int_entry(reg_num)\
231 	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
232 		IRQ_REG_ENTRY(HPD, reg_num,\
233 			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
234 			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
235 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
236 		.funcs = &hpd_rx_irq_info_funcs\
237 	}
238 #define pflip_int_entry(reg_num)\
239 	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
240 		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
241 			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
242 			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
243 		.funcs = &pflip_irq_info_funcs\
244 	}
245 
246 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
247  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
248  */
249 #define vupdate_no_lock_int_entry(reg_num)\
250 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
251 		IRQ_REG_ENTRY(OTG, reg_num,\
252 			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
253 			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
254 		.funcs = &vupdate_no_lock_irq_info_funcs\
255 	}
256 
257 #define vblank_int_entry(reg_num)\
258 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
259 		IRQ_REG_ENTRY(OTG, reg_num,\
260 			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
261 			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
262 		.funcs = &vblank_irq_info_funcs\
263 	}
264 
265 #define vline0_int_entry(reg_num)\
266 	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
267 		IRQ_REG_ENTRY(OTG, reg_num,\
268 			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
269 			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
270 		.funcs = &vline0_irq_info_funcs\
271 	}
272 
273 #define dummy_irq_entry() \
274 	{\
275 		.funcs = &dummy_irq_info_funcs\
276 	}
277 
278 #define i2c_int_entry(reg_num) \
279 	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
280 
281 #define dp_sink_int_entry(reg_num) \
282 	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
283 
284 #define gpio_pad_int_entry(reg_num) \
285 	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
286 
287 #define dc_underflow_int_entry(reg_num) \
288 	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
289 
290 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
291 	.set = dal_irq_service_dummy_set,
292 	.ack = dal_irq_service_dummy_ack
293 };
294 
295 static const struct irq_source_info
296 irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
297 	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
298 	hpd_int_entry(0),
299 	hpd_int_entry(1),
300 	hpd_int_entry(2),
301 	hpd_int_entry(3),
302 	hpd_int_entry(4),
303 	hpd_int_entry(5),
304 	hpd_rx_int_entry(0),
305 	hpd_rx_int_entry(1),
306 	hpd_rx_int_entry(2),
307 	hpd_rx_int_entry(3),
308 	hpd_rx_int_entry(4),
309 	hpd_rx_int_entry(5),
310 	i2c_int_entry(1),
311 	i2c_int_entry(2),
312 	i2c_int_entry(3),
313 	i2c_int_entry(4),
314 	i2c_int_entry(5),
315 	i2c_int_entry(6),
316 	dp_sink_int_entry(1),
317 	dp_sink_int_entry(2),
318 	dp_sink_int_entry(3),
319 	dp_sink_int_entry(4),
320 	dp_sink_int_entry(5),
321 	dp_sink_int_entry(6),
322 	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
323 	pflip_int_entry(0),
324 	pflip_int_entry(1),
325 	pflip_int_entry(2),
326 	pflip_int_entry(3),
327 	pflip_int_entry(4),
328 	pflip_int_entry(5),
329 	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
330 	gpio_pad_int_entry(0),
331 	gpio_pad_int_entry(1),
332 	gpio_pad_int_entry(2),
333 	gpio_pad_int_entry(3),
334 	gpio_pad_int_entry(4),
335 	gpio_pad_int_entry(5),
336 	gpio_pad_int_entry(6),
337 	gpio_pad_int_entry(7),
338 	gpio_pad_int_entry(8),
339 	gpio_pad_int_entry(9),
340 	gpio_pad_int_entry(10),
341 	gpio_pad_int_entry(11),
342 	gpio_pad_int_entry(12),
343 	gpio_pad_int_entry(13),
344 	gpio_pad_int_entry(14),
345 	gpio_pad_int_entry(15),
346 	gpio_pad_int_entry(16),
347 	gpio_pad_int_entry(17),
348 	gpio_pad_int_entry(18),
349 	gpio_pad_int_entry(19),
350 	gpio_pad_int_entry(20),
351 	gpio_pad_int_entry(21),
352 	gpio_pad_int_entry(22),
353 	gpio_pad_int_entry(23),
354 	gpio_pad_int_entry(24),
355 	gpio_pad_int_entry(25),
356 	gpio_pad_int_entry(26),
357 	gpio_pad_int_entry(27),
358 	gpio_pad_int_entry(28),
359 	gpio_pad_int_entry(29),
360 	gpio_pad_int_entry(30),
361 	dc_underflow_int_entry(1),
362 	dc_underflow_int_entry(2),
363 	dc_underflow_int_entry(3),
364 	dc_underflow_int_entry(4),
365 	dc_underflow_int_entry(5),
366 	dc_underflow_int_entry(6),
367 	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
368 	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
369 	vupdate_no_lock_int_entry(0),
370 	vupdate_no_lock_int_entry(1),
371 	vupdate_no_lock_int_entry(2),
372 	vupdate_no_lock_int_entry(3),
373 	vupdate_no_lock_int_entry(4),
374 	vupdate_no_lock_int_entry(5),
375 	vblank_int_entry(0),
376 	vblank_int_entry(1),
377 	vblank_int_entry(2),
378 	vblank_int_entry(3),
379 	vblank_int_entry(4),
380 	vblank_int_entry(5),
381 	vline0_int_entry(0),
382 	vline0_int_entry(1),
383 	vline0_int_entry(2),
384 	vline0_int_entry(3),
385 	vline0_int_entry(4),
386 	vline0_int_entry(5),
387 };
388 
389 static const struct irq_service_funcs irq_service_funcs_dcn20 = {
390 		.to_dal_irq_source = to_dal_irq_source_dcn20
391 };
392 
dcn20_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)393 static void dcn20_irq_construct(
394 	struct irq_service *irq_service,
395 	struct irq_service_init_data *init_data)
396 {
397 	dal_irq_service_construct(irq_service, init_data);
398 
399 	irq_service->info = irq_source_info_dcn20;
400 	irq_service->funcs = &irq_service_funcs_dcn20;
401 }
402 
dal_irq_service_dcn20_create(struct irq_service_init_data * init_data)403 struct irq_service *dal_irq_service_dcn20_create(
404 	struct irq_service_init_data *init_data)
405 {
406 	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
407 						  GFP_KERNEL);
408 
409 	if (!irq_service)
410 		return NULL;
411 
412 	dcn20_irq_construct(irq_service, init_data);
413 	return irq_service;
414 }
415