xref: /openbmc/linux/drivers/tty/serial/sc16is7xx.c (revision 11244a43)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4  * Author: Jon Ringle <jringle@gridpoint.com>
5  *
6  *  Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
7  */
8 
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/sched.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/spi/spi.h>
27 #include <linux/uaccess.h>
28 #include <linux/units.h>
29 
30 #define SC16IS7XX_NAME			"sc16is7xx"
31 #define SC16IS7XX_MAX_DEVS		8
32 
33 /* SC16IS7XX register definitions */
34 #define SC16IS7XX_RHR_REG		(0x00) /* RX FIFO */
35 #define SC16IS7XX_THR_REG		(0x00) /* TX FIFO */
36 #define SC16IS7XX_IER_REG		(0x01) /* Interrupt enable */
37 #define SC16IS7XX_IIR_REG		(0x02) /* Interrupt Identification */
38 #define SC16IS7XX_FCR_REG		(0x02) /* FIFO control */
39 #define SC16IS7XX_LCR_REG		(0x03) /* Line Control */
40 #define SC16IS7XX_MCR_REG		(0x04) /* Modem Control */
41 #define SC16IS7XX_LSR_REG		(0x05) /* Line Status */
42 #define SC16IS7XX_MSR_REG		(0x06) /* Modem Status */
43 #define SC16IS7XX_SPR_REG		(0x07) /* Scratch Pad */
44 #define SC16IS7XX_TXLVL_REG		(0x08) /* TX FIFO level */
45 #define SC16IS7XX_RXLVL_REG		(0x09) /* RX FIFO level */
46 #define SC16IS7XX_IODIR_REG		(0x0a) /* I/O Direction
47 						* - only on 75x/76x
48 						*/
49 #define SC16IS7XX_IOSTATE_REG		(0x0b) /* I/O State
50 						* - only on 75x/76x
51 						*/
52 #define SC16IS7XX_IOINTENA_REG		(0x0c) /* I/O Interrupt Enable
53 						* - only on 75x/76x
54 						*/
55 #define SC16IS7XX_IOCONTROL_REG		(0x0e) /* I/O Control
56 						* - only on 75x/76x
57 						*/
58 #define SC16IS7XX_EFCR_REG		(0x0f) /* Extra Features Control */
59 
60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61 #define SC16IS7XX_TCR_REG		(0x06) /* Transmit control */
62 #define SC16IS7XX_TLR_REG		(0x07) /* Trigger level */
63 
64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65 #define SC16IS7XX_DLL_REG		(0x00) /* Divisor Latch Low */
66 #define SC16IS7XX_DLH_REG		(0x01) /* Divisor Latch High */
67 
68 /* Enhanced Register set: Only if (LCR == 0xBF) */
69 #define SC16IS7XX_EFR_REG		(0x02) /* Enhanced Features */
70 #define SC16IS7XX_XON1_REG		(0x04) /* Xon1 word */
71 #define SC16IS7XX_XON2_REG		(0x05) /* Xon2 word */
72 #define SC16IS7XX_XOFF1_REG		(0x06) /* Xoff1 word */
73 #define SC16IS7XX_XOFF2_REG		(0x07) /* Xoff2 word */
74 
75 /* IER register bits */
76 #define SC16IS7XX_IER_RDI_BIT		(1 << 0) /* Enable RX data interrupt */
77 #define SC16IS7XX_IER_THRI_BIT		(1 << 1) /* Enable TX holding register
78 						  * interrupt */
79 #define SC16IS7XX_IER_RLSI_BIT		(1 << 2) /* Enable RX line status
80 						  * interrupt */
81 #define SC16IS7XX_IER_MSI_BIT		(1 << 3) /* Enable Modem status
82 						  * interrupt */
83 
84 /* IER register bits - write only if (EFR[4] == 1) */
85 #define SC16IS7XX_IER_SLEEP_BIT		(1 << 4) /* Enable Sleep mode */
86 #define SC16IS7XX_IER_XOFFI_BIT		(1 << 5) /* Enable Xoff interrupt */
87 #define SC16IS7XX_IER_RTSI_BIT		(1 << 6) /* Enable nRTS interrupt */
88 #define SC16IS7XX_IER_CTSI_BIT		(1 << 7) /* Enable nCTS interrupt */
89 
90 /* FCR register bits */
91 #define SC16IS7XX_FCR_FIFO_BIT		(1 << 0) /* Enable FIFO */
92 #define SC16IS7XX_FCR_RXRESET_BIT	(1 << 1) /* Reset RX FIFO */
93 #define SC16IS7XX_FCR_TXRESET_BIT	(1 << 2) /* Reset TX FIFO */
94 #define SC16IS7XX_FCR_RXLVLL_BIT	(1 << 6) /* RX Trigger level LSB */
95 #define SC16IS7XX_FCR_RXLVLH_BIT	(1 << 7) /* RX Trigger level MSB */
96 
97 /* FCR register bits - write only if (EFR[4] == 1) */
98 #define SC16IS7XX_FCR_TXLVLL_BIT	(1 << 4) /* TX Trigger level LSB */
99 #define SC16IS7XX_FCR_TXLVLH_BIT	(1 << 5) /* TX Trigger level MSB */
100 
101 /* IIR register bits */
102 #define SC16IS7XX_IIR_NO_INT_BIT	(1 << 0) /* No interrupts pending */
103 #define SC16IS7XX_IIR_ID_MASK		0x3e     /* Mask for the interrupt ID */
104 #define SC16IS7XX_IIR_THRI_SRC		0x02     /* TX holding register empty */
105 #define SC16IS7XX_IIR_RDI_SRC		0x04     /* RX data interrupt */
106 #define SC16IS7XX_IIR_RLSE_SRC		0x06     /* RX line status error */
107 #define SC16IS7XX_IIR_RTOI_SRC		0x0c     /* RX time-out interrupt */
108 #define SC16IS7XX_IIR_MSI_SRC		0x00     /* Modem status interrupt
109 						  * - only on 75x/76x
110 						  */
111 #define SC16IS7XX_IIR_INPIN_SRC		0x30     /* Input pin change of state
112 						  * - only on 75x/76x
113 						  */
114 #define SC16IS7XX_IIR_XOFFI_SRC		0x10     /* Received Xoff */
115 #define SC16IS7XX_IIR_CTSRTS_SRC	0x20     /* nCTS,nRTS change of state
116 						  * from active (LOW)
117 						  * to inactive (HIGH)
118 						  */
119 /* LCR register bits */
120 #define SC16IS7XX_LCR_LENGTH0_BIT	(1 << 0) /* Word length bit 0 */
121 #define SC16IS7XX_LCR_LENGTH1_BIT	(1 << 1) /* Word length bit 1
122 						  *
123 						  * Word length bits table:
124 						  * 00 -> 5 bit words
125 						  * 01 -> 6 bit words
126 						  * 10 -> 7 bit words
127 						  * 11 -> 8 bit words
128 						  */
129 #define SC16IS7XX_LCR_STOPLEN_BIT	(1 << 2) /* STOP length bit
130 						  *
131 						  * STOP length bit table:
132 						  * 0 -> 1 stop bit
133 						  * 1 -> 1-1.5 stop bits if
134 						  *      word length is 5,
135 						  *      2 stop bits otherwise
136 						  */
137 #define SC16IS7XX_LCR_PARITY_BIT	(1 << 3) /* Parity bit enable */
138 #define SC16IS7XX_LCR_EVENPARITY_BIT	(1 << 4) /* Even parity bit enable */
139 #define SC16IS7XX_LCR_FORCEPARITY_BIT	(1 << 5) /* 9-bit multidrop parity */
140 #define SC16IS7XX_LCR_TXBREAK_BIT	(1 << 6) /* TX break enable */
141 #define SC16IS7XX_LCR_DLAB_BIT		(1 << 7) /* Divisor Latch enable */
142 #define SC16IS7XX_LCR_WORD_LEN_5	(0x00)
143 #define SC16IS7XX_LCR_WORD_LEN_6	(0x01)
144 #define SC16IS7XX_LCR_WORD_LEN_7	(0x02)
145 #define SC16IS7XX_LCR_WORD_LEN_8	(0x03)
146 #define SC16IS7XX_LCR_CONF_MODE_A	SC16IS7XX_LCR_DLAB_BIT /* Special
147 								* reg set */
148 #define SC16IS7XX_LCR_CONF_MODE_B	0xBF                   /* Enhanced
149 								* reg set */
150 
151 /* MCR register bits */
152 #define SC16IS7XX_MCR_DTR_BIT		(1 << 0) /* DTR complement
153 						  * - only on 75x/76x
154 						  */
155 #define SC16IS7XX_MCR_RTS_BIT		(1 << 1) /* RTS complement */
156 #define SC16IS7XX_MCR_TCRTLR_BIT	(1 << 2) /* TCR/TLR register enable */
157 #define SC16IS7XX_MCR_LOOP_BIT		(1 << 4) /* Enable loopback test mode */
158 #define SC16IS7XX_MCR_XONANY_BIT	(1 << 5) /* Enable Xon Any
159 						  * - write enabled
160 						  * if (EFR[4] == 1)
161 						  */
162 #define SC16IS7XX_MCR_IRDA_BIT		(1 << 6) /* Enable IrDA mode
163 						  * - write enabled
164 						  * if (EFR[4] == 1)
165 						  */
166 #define SC16IS7XX_MCR_CLKSEL_BIT	(1 << 7) /* Divide clock by 4
167 						  * - write enabled
168 						  * if (EFR[4] == 1)
169 						  */
170 
171 /* LSR register bits */
172 #define SC16IS7XX_LSR_DR_BIT		(1 << 0) /* Receiver data ready */
173 #define SC16IS7XX_LSR_OE_BIT		(1 << 1) /* Overrun Error */
174 #define SC16IS7XX_LSR_PE_BIT		(1 << 2) /* Parity Error */
175 #define SC16IS7XX_LSR_FE_BIT		(1 << 3) /* Frame Error */
176 #define SC16IS7XX_LSR_BI_BIT		(1 << 4) /* Break Interrupt */
177 #define SC16IS7XX_LSR_BRK_ERROR_MASK	0x1E     /* BI, FE, PE, OE bits */
178 #define SC16IS7XX_LSR_THRE_BIT		(1 << 5) /* TX holding register empty */
179 #define SC16IS7XX_LSR_TEMT_BIT		(1 << 6) /* Transmitter empty */
180 #define SC16IS7XX_LSR_FIFOE_BIT		(1 << 7) /* Fifo Error */
181 
182 /* MSR register bits */
183 #define SC16IS7XX_MSR_DCTS_BIT		(1 << 0) /* Delta CTS Clear To Send */
184 #define SC16IS7XX_MSR_DDSR_BIT		(1 << 1) /* Delta DSR Data Set Ready
185 						  * or (IO4)
186 						  * - only on 75x/76x
187 						  */
188 #define SC16IS7XX_MSR_DRI_BIT		(1 << 2) /* Delta RI Ring Indicator
189 						  * or (IO7)
190 						  * - only on 75x/76x
191 						  */
192 #define SC16IS7XX_MSR_DCD_BIT		(1 << 3) /* Delta CD Carrier Detect
193 						  * or (IO6)
194 						  * - only on 75x/76x
195 						  */
196 #define SC16IS7XX_MSR_CTS_BIT		(1 << 4) /* CTS */
197 #define SC16IS7XX_MSR_DSR_BIT		(1 << 5) /* DSR (IO4)
198 						  * - only on 75x/76x
199 						  */
200 #define SC16IS7XX_MSR_RI_BIT		(1 << 6) /* RI (IO7)
201 						  * - only on 75x/76x
202 						  */
203 #define SC16IS7XX_MSR_CD_BIT		(1 << 7) /* CD (IO6)
204 						  * - only on 75x/76x
205 						  */
206 #define SC16IS7XX_MSR_DELTA_MASK	0x0F     /* Any of the delta bits! */
207 
208 /*
209  * TCR register bits
210  * TCR trigger levels are available from 0 to 60 characters with a granularity
211  * of four.
212  * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213  * no built-in hardware check to make sure this condition is met. Also, the TCR
214  * must be programmed with this condition before auto RTS or software flow
215  * control is enabled to avoid spurious operation of the device.
216  */
217 #define SC16IS7XX_TCR_RX_HALT(words)	((((words) / 4) & 0x0f) << 0)
218 #define SC16IS7XX_TCR_RX_RESUME(words)	((((words) / 4) & 0x0f) << 4)
219 
220 /*
221  * TLR register bits
222  * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223  * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224  * trigger levels. Trigger levels from 4 characters to 60 characters are
225  * available with a granularity of four.
226  *
227  * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228  * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229  * the trigger level defined in FCR is discarded. This applies to both transmit
230  * FIFO and receive FIFO trigger level setting.
231  *
232  * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233  * default state, that is, '00'.
234  */
235 #define SC16IS7XX_TLR_TX_TRIGGER(words)	((((words) / 4) & 0x0f) << 0)
236 #define SC16IS7XX_TLR_RX_TRIGGER(words)	((((words) / 4) & 0x0f) << 4)
237 
238 /* IOControl register bits (Only 750/760) */
239 #define SC16IS7XX_IOCONTROL_LATCH_BIT	(1 << 0) /* Enable input latching */
240 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT	(1 << 1) /* Enable GPIO[7:4] as modem A pins */
241 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT	(1 << 2) /* Enable GPIO[3:0] as modem B pins */
242 #define SC16IS7XX_IOCONTROL_SRESET_BIT	(1 << 3) /* Software Reset */
243 
244 /* EFCR register bits */
245 #define SC16IS7XX_EFCR_9BIT_MODE_BIT	(1 << 0) /* Enable 9-bit or Multidrop
246 						  * mode (RS485) */
247 #define SC16IS7XX_EFCR_RXDISABLE_BIT	(1 << 1) /* Disable receiver */
248 #define SC16IS7XX_EFCR_TXDISABLE_BIT	(1 << 2) /* Disable transmitter */
249 #define SC16IS7XX_EFCR_AUTO_RS485_BIT	(1 << 4) /* Auto RS485 RTS direction */
250 #define SC16IS7XX_EFCR_RTS_INVERT_BIT	(1 << 5) /* RTS output inversion */
251 #define SC16IS7XX_EFCR_IRDA_MODE_BIT	(1 << 7) /* IrDA mode
252 						  * 0 = rate upto 115.2 kbit/s
253 						  *   - Only 750/760
254 						  * 1 = rate upto 1.152 Mbit/s
255 						  *   - Only 760
256 						  */
257 
258 /* EFR register bits */
259 #define SC16IS7XX_EFR_AUTORTS_BIT	(1 << 6) /* Auto RTS flow ctrl enable */
260 #define SC16IS7XX_EFR_AUTOCTS_BIT	(1 << 7) /* Auto CTS flow ctrl enable */
261 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT	(1 << 5) /* Enable Xoff2 detection */
262 #define SC16IS7XX_EFR_ENABLE_BIT	(1 << 4) /* Enable enhanced functions
263 						  * and writing to IER[7:4],
264 						  * FCR[5:4], MCR[7:5]
265 						  */
266 #define SC16IS7XX_EFR_SWFLOW3_BIT	(1 << 3) /* SWFLOW bit 3 */
267 #define SC16IS7XX_EFR_SWFLOW2_BIT	(1 << 2) /* SWFLOW bit 2
268 						  *
269 						  * SWFLOW bits 3 & 2 table:
270 						  * 00 -> no transmitter flow
271 						  *       control
272 						  * 01 -> transmitter generates
273 						  *       XON2 and XOFF2
274 						  * 10 -> transmitter generates
275 						  *       XON1 and XOFF1
276 						  * 11 -> transmitter generates
277 						  *       XON1, XON2, XOFF1 and
278 						  *       XOFF2
279 						  */
280 #define SC16IS7XX_EFR_SWFLOW1_BIT	(1 << 1) /* SWFLOW bit 2 */
281 #define SC16IS7XX_EFR_SWFLOW0_BIT	(1 << 0) /* SWFLOW bit 3
282 						  *
283 						  * SWFLOW bits 3 & 2 table:
284 						  * 00 -> no received flow
285 						  *       control
286 						  * 01 -> receiver compares
287 						  *       XON2 and XOFF2
288 						  * 10 -> receiver compares
289 						  *       XON1 and XOFF1
290 						  * 11 -> receiver compares
291 						  *       XON1, XON2, XOFF1 and
292 						  *       XOFF2
293 						  */
294 #define SC16IS7XX_EFR_FLOWCTRL_BITS	(SC16IS7XX_EFR_AUTORTS_BIT | \
295 					SC16IS7XX_EFR_AUTOCTS_BIT | \
296 					SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
297 					SC16IS7XX_EFR_SWFLOW3_BIT | \
298 					SC16IS7XX_EFR_SWFLOW2_BIT | \
299 					SC16IS7XX_EFR_SWFLOW1_BIT | \
300 					SC16IS7XX_EFR_SWFLOW0_BIT)
301 
302 
303 /* Misc definitions */
304 #define SC16IS7XX_SPI_READ_BIT		BIT(7)
305 #define SC16IS7XX_FIFO_SIZE		(64)
306 #define SC16IS7XX_GPIOS_PER_BANK	4
307 
308 struct sc16is7xx_devtype {
309 	char	name[10];
310 	int	nr_gpio;
311 	int	nr_uart;
312 };
313 
314 #define SC16IS7XX_RECONF_MD		(1 << 0)
315 #define SC16IS7XX_RECONF_IER		(1 << 1)
316 #define SC16IS7XX_RECONF_RS485		(1 << 2)
317 
318 struct sc16is7xx_one_config {
319 	unsigned int			flags;
320 	u8				ier_mask;
321 	u8				ier_val;
322 };
323 
324 struct sc16is7xx_one {
325 	struct uart_port		port;
326 	struct regmap			*regmap;
327 	struct mutex			efr_lock; /* EFR registers access */
328 	struct kthread_work		tx_work;
329 	struct kthread_work		reg_work;
330 	struct kthread_delayed_work	ms_work;
331 	struct sc16is7xx_one_config	config;
332 	bool				irda_mode;
333 	unsigned int			old_mctrl;
334 };
335 
336 struct sc16is7xx_port {
337 	const struct sc16is7xx_devtype	*devtype;
338 	struct clk			*clk;
339 #ifdef CONFIG_GPIOLIB
340 	struct gpio_chip		gpio;
341 	unsigned long			gpio_valid_mask;
342 #endif
343 	u8				mctrl_mask;
344 	unsigned char			buf[SC16IS7XX_FIFO_SIZE];
345 	struct kthread_worker		kworker;
346 	struct task_struct		*kworker_task;
347 	struct sc16is7xx_one		p[];
348 };
349 
350 static unsigned long sc16is7xx_lines;
351 
352 static struct uart_driver sc16is7xx_uart = {
353 	.owner		= THIS_MODULE,
354 	.dev_name	= "ttySC",
355 	.nr		= SC16IS7XX_MAX_DEVS,
356 };
357 
358 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit);
359 static void sc16is7xx_stop_tx(struct uart_port *port);
360 
361 #define to_sc16is7xx_port(p,e)	((container_of((p), struct sc16is7xx_port, e)))
362 #define to_sc16is7xx_one(p,e)	((container_of((p), struct sc16is7xx_one, e)))
363 
sc16is7xx_port_read(struct uart_port * port,u8 reg)364 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
365 {
366 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
367 	unsigned int val = 0;
368 
369 	regmap_read(one->regmap, reg, &val);
370 
371 	return val;
372 }
373 
sc16is7xx_port_write(struct uart_port * port,u8 reg,u8 val)374 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
375 {
376 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
377 
378 	regmap_write(one->regmap, reg, val);
379 }
380 
sc16is7xx_fifo_read(struct uart_port * port,unsigned int rxlen)381 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
382 {
383 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
384 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
385 
386 	regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, s->buf, rxlen);
387 }
388 
sc16is7xx_fifo_write(struct uart_port * port,u8 to_send)389 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
390 {
391 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
392 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
393 
394 	/*
395 	 * Don't send zero-length data, at least on SPI it confuses the chip
396 	 * delivering wrong TXLVL data.
397 	 */
398 	if (unlikely(!to_send))
399 		return;
400 
401 	regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
402 }
403 
sc16is7xx_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)404 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
405 				  u8 mask, u8 val)
406 {
407 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
408 
409 	regmap_update_bits(one->regmap, reg, mask, val);
410 }
411 
sc16is7xx_power(struct uart_port * port,int on)412 static void sc16is7xx_power(struct uart_port *port, int on)
413 {
414 	sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
415 			      SC16IS7XX_IER_SLEEP_BIT,
416 			      on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
417 }
418 
419 static const struct sc16is7xx_devtype sc16is74x_devtype = {
420 	.name		= "SC16IS74X",
421 	.nr_gpio	= 0,
422 	.nr_uart	= 1,
423 };
424 
425 static const struct sc16is7xx_devtype sc16is750_devtype = {
426 	.name		= "SC16IS750",
427 	.nr_gpio	= 8,
428 	.nr_uart	= 1,
429 };
430 
431 static const struct sc16is7xx_devtype sc16is752_devtype = {
432 	.name		= "SC16IS752",
433 	.nr_gpio	= 8,
434 	.nr_uart	= 2,
435 };
436 
437 static const struct sc16is7xx_devtype sc16is760_devtype = {
438 	.name		= "SC16IS760",
439 	.nr_gpio	= 8,
440 	.nr_uart	= 1,
441 };
442 
443 static const struct sc16is7xx_devtype sc16is762_devtype = {
444 	.name		= "SC16IS762",
445 	.nr_gpio	= 8,
446 	.nr_uart	= 2,
447 };
448 
sc16is7xx_regmap_volatile(struct device * dev,unsigned int reg)449 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
450 {
451 	switch (reg) {
452 	case SC16IS7XX_RHR_REG:
453 	case SC16IS7XX_IIR_REG:
454 	case SC16IS7XX_LSR_REG:
455 	case SC16IS7XX_MSR_REG:
456 	case SC16IS7XX_TXLVL_REG:
457 	case SC16IS7XX_RXLVL_REG:
458 	case SC16IS7XX_IOSTATE_REG:
459 	case SC16IS7XX_IOCONTROL_REG:
460 		return true;
461 	default:
462 		break;
463 	}
464 
465 	return false;
466 }
467 
sc16is7xx_regmap_precious(struct device * dev,unsigned int reg)468 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
469 {
470 	switch (reg) {
471 	case SC16IS7XX_RHR_REG:
472 		return true;
473 	default:
474 		break;
475 	}
476 
477 	return false;
478 }
479 
sc16is7xx_regmap_noinc(struct device * dev,unsigned int reg)480 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
481 {
482 	return reg == SC16IS7XX_RHR_REG;
483 }
484 
485 /*
486  * Configure programmable baud rate generator (divisor) according to the
487  * desired baud rate.
488  *
489  * From the datasheet, the divisor is computed according to:
490  *
491  *              XTAL1 input frequency
492  *             -----------------------
493  *                    prescaler
494  * divisor = ---------------------------
495  *            baud-rate x sampling-rate
496  */
sc16is7xx_set_baud(struct uart_port * port,int baud)497 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
498 {
499 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
500 	u8 lcr;
501 	unsigned int prescaler = 1;
502 	unsigned long clk = port->uartclk, div = clk / 16 / baud;
503 
504 	if (div >= BIT(16)) {
505 		prescaler = 4;
506 		div /= prescaler;
507 	}
508 
509 	/* In an amazing feat of design, the Enhanced Features Register shares
510 	 * the address of the Interrupt Identification Register, and is
511 	 * switched in by writing a magic value (0xbf) to the Line Control
512 	 * Register. Any interrupt firing during this time will see the EFR
513 	 * where it expects the IIR to be, leading to "Unexpected interrupt"
514 	 * messages.
515 	 *
516 	 * Prevent this possibility by claiming a mutex while accessing the
517 	 * EFR, and claiming the same mutex from within the interrupt handler.
518 	 * This is similar to disabling the interrupt, but that doesn't work
519 	 * because the bulk of the interrupt processing is run as a workqueue
520 	 * job in thread context.
521 	 */
522 	mutex_lock(&one->efr_lock);
523 
524 	lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
525 
526 	/* Open the LCR divisors for configuration */
527 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
528 			     SC16IS7XX_LCR_CONF_MODE_B);
529 
530 	/* Enable enhanced features */
531 	regcache_cache_bypass(one->regmap, true);
532 	sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
533 			      SC16IS7XX_EFR_ENABLE_BIT,
534 			      SC16IS7XX_EFR_ENABLE_BIT);
535 
536 	regcache_cache_bypass(one->regmap, false);
537 
538 	/* Put LCR back to the normal mode */
539 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
540 
541 	mutex_unlock(&one->efr_lock);
542 
543 	/* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
544 	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
545 			      SC16IS7XX_MCR_CLKSEL_BIT,
546 			      prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
547 
548 	/* Open the LCR divisors for configuration */
549 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
550 			     SC16IS7XX_LCR_CONF_MODE_A);
551 
552 	/* Write the new divisor */
553 	regcache_cache_bypass(one->regmap, true);
554 	sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
555 	sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
556 	regcache_cache_bypass(one->regmap, false);
557 
558 	/* Put LCR back to the normal mode */
559 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
560 
561 	return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
562 }
563 
sc16is7xx_handle_rx(struct uart_port * port,unsigned int rxlen,unsigned int iir)564 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
565 				unsigned int iir)
566 {
567 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
568 	unsigned int lsr = 0, bytes_read, i;
569 	bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
570 	u8 ch, flag;
571 
572 	if (unlikely(rxlen >= sizeof(s->buf))) {
573 		dev_warn_ratelimited(port->dev,
574 				     "ttySC%i: Possible RX FIFO overrun: %d\n",
575 				     port->line, rxlen);
576 		port->icount.buf_overrun++;
577 		/* Ensure sanity of RX level */
578 		rxlen = sizeof(s->buf);
579 	}
580 
581 	while (rxlen) {
582 		/* Only read lsr if there are possible errors in FIFO */
583 		if (read_lsr) {
584 			lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
585 			if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
586 				read_lsr = false; /* No errors left in FIFO */
587 		} else
588 			lsr = 0;
589 
590 		if (read_lsr) {
591 			s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
592 			bytes_read = 1;
593 		} else {
594 			sc16is7xx_fifo_read(port, rxlen);
595 			bytes_read = rxlen;
596 		}
597 
598 		lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
599 
600 		port->icount.rx++;
601 		flag = TTY_NORMAL;
602 
603 		if (unlikely(lsr)) {
604 			if (lsr & SC16IS7XX_LSR_BI_BIT) {
605 				port->icount.brk++;
606 				if (uart_handle_break(port))
607 					continue;
608 			} else if (lsr & SC16IS7XX_LSR_PE_BIT)
609 				port->icount.parity++;
610 			else if (lsr & SC16IS7XX_LSR_FE_BIT)
611 				port->icount.frame++;
612 			else if (lsr & SC16IS7XX_LSR_OE_BIT)
613 				port->icount.overrun++;
614 
615 			lsr &= port->read_status_mask;
616 			if (lsr & SC16IS7XX_LSR_BI_BIT)
617 				flag = TTY_BREAK;
618 			else if (lsr & SC16IS7XX_LSR_PE_BIT)
619 				flag = TTY_PARITY;
620 			else if (lsr & SC16IS7XX_LSR_FE_BIT)
621 				flag = TTY_FRAME;
622 			else if (lsr & SC16IS7XX_LSR_OE_BIT)
623 				flag = TTY_OVERRUN;
624 		}
625 
626 		for (i = 0; i < bytes_read; ++i) {
627 			ch = s->buf[i];
628 			if (uart_handle_sysrq_char(port, ch))
629 				continue;
630 
631 			if (lsr & port->ignore_status_mask)
632 				continue;
633 
634 			uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
635 					 flag);
636 		}
637 		rxlen -= bytes_read;
638 	}
639 
640 	tty_flip_buffer_push(&port->state->port);
641 }
642 
sc16is7xx_handle_tx(struct uart_port * port)643 static void sc16is7xx_handle_tx(struct uart_port *port)
644 {
645 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
646 	struct circ_buf *xmit = &port->state->xmit;
647 	unsigned int txlen, to_send, i;
648 	unsigned long flags;
649 
650 	if (unlikely(port->x_char)) {
651 		sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
652 		port->icount.tx++;
653 		port->x_char = 0;
654 		return;
655 	}
656 
657 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
658 		uart_port_lock_irqsave(port, &flags);
659 		sc16is7xx_stop_tx(port);
660 		uart_port_unlock_irqrestore(port, flags);
661 		return;
662 	}
663 
664 	/* Get length of data pending in circular buffer */
665 	to_send = uart_circ_chars_pending(xmit);
666 	if (likely(to_send)) {
667 		/* Limit to size of TX FIFO */
668 		txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
669 		if (txlen > SC16IS7XX_FIFO_SIZE) {
670 			dev_err_ratelimited(port->dev,
671 				"chip reports %d free bytes in TX fifo, but it only has %d",
672 				txlen, SC16IS7XX_FIFO_SIZE);
673 			txlen = 0;
674 		}
675 		to_send = (to_send > txlen) ? txlen : to_send;
676 
677 		/* Convert to linear buffer */
678 		for (i = 0; i < to_send; ++i) {
679 			s->buf[i] = xmit->buf[xmit->tail];
680 			uart_xmit_advance(port, 1);
681 		}
682 
683 		sc16is7xx_fifo_write(port, to_send);
684 	}
685 
686 	uart_port_lock_irqsave(port, &flags);
687 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
688 		uart_write_wakeup(port);
689 
690 	if (uart_circ_empty(xmit))
691 		sc16is7xx_stop_tx(port);
692 	else
693 		sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
694 	uart_port_unlock_irqrestore(port, flags);
695 }
696 
sc16is7xx_get_hwmctrl(struct uart_port * port)697 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
698 {
699 	u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
700 	unsigned int mctrl = 0;
701 
702 	mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
703 	mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
704 	mctrl |= (msr & SC16IS7XX_MSR_CD_BIT)  ? TIOCM_CAR : 0;
705 	mctrl |= (msr & SC16IS7XX_MSR_RI_BIT)  ? TIOCM_RNG : 0;
706 	return mctrl;
707 }
708 
sc16is7xx_update_mlines(struct sc16is7xx_one * one)709 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
710 {
711 	struct uart_port *port = &one->port;
712 	unsigned long flags;
713 	unsigned int status, changed;
714 
715 	lockdep_assert_held_once(&one->efr_lock);
716 
717 	status = sc16is7xx_get_hwmctrl(port);
718 	changed = status ^ one->old_mctrl;
719 
720 	if (changed == 0)
721 		return;
722 
723 	one->old_mctrl = status;
724 
725 	uart_port_lock_irqsave(port, &flags);
726 	if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
727 		port->icount.rng++;
728 	if (changed & TIOCM_DSR)
729 		port->icount.dsr++;
730 	if (changed & TIOCM_CAR)
731 		uart_handle_dcd_change(port, status & TIOCM_CAR);
732 	if (changed & TIOCM_CTS)
733 		uart_handle_cts_change(port, status & TIOCM_CTS);
734 
735 	wake_up_interruptible(&port->state->port.delta_msr_wait);
736 	uart_port_unlock_irqrestore(port, flags);
737 }
738 
sc16is7xx_port_irq(struct sc16is7xx_port * s,int portno)739 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
740 {
741 	bool rc = true;
742 	unsigned int iir, rxlen;
743 	struct uart_port *port = &s->p[portno].port;
744 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
745 
746 	mutex_lock(&one->efr_lock);
747 
748 	iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
749 	if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
750 		rc = false;
751 		goto out_port_irq;
752 	}
753 
754 	iir &= SC16IS7XX_IIR_ID_MASK;
755 
756 	switch (iir) {
757 	case SC16IS7XX_IIR_RDI_SRC:
758 	case SC16IS7XX_IIR_RLSE_SRC:
759 	case SC16IS7XX_IIR_RTOI_SRC:
760 	case SC16IS7XX_IIR_XOFFI_SRC:
761 		rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
762 
763 		/*
764 		 * There is a silicon bug that makes the chip report a
765 		 * time-out interrupt but no data in the FIFO. This is
766 		 * described in errata section 18.1.4.
767 		 *
768 		 * When this happens, read one byte from the FIFO to
769 		 * clear the interrupt.
770 		 */
771 		if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
772 			rxlen = 1;
773 
774 		if (rxlen)
775 			sc16is7xx_handle_rx(port, rxlen, iir);
776 		break;
777 		/* CTSRTS interrupt comes only when CTS goes inactive */
778 	case SC16IS7XX_IIR_CTSRTS_SRC:
779 	case SC16IS7XX_IIR_MSI_SRC:
780 		sc16is7xx_update_mlines(one);
781 		break;
782 	case SC16IS7XX_IIR_THRI_SRC:
783 		sc16is7xx_handle_tx(port);
784 		break;
785 	default:
786 		dev_err_ratelimited(port->dev,
787 				    "ttySC%i: Unexpected interrupt: %x",
788 				    port->line, iir);
789 		break;
790 	}
791 
792 out_port_irq:
793 	mutex_unlock(&one->efr_lock);
794 
795 	return rc;
796 }
797 
sc16is7xx_irq(int irq,void * dev_id)798 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
799 {
800 	bool keep_polling;
801 
802 	struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
803 
804 	do {
805 		int i;
806 
807 		keep_polling = false;
808 
809 		for (i = 0; i < s->devtype->nr_uart; ++i)
810 			keep_polling |= sc16is7xx_port_irq(s, i);
811 	} while (keep_polling);
812 
813 	return IRQ_HANDLED;
814 }
815 
sc16is7xx_tx_proc(struct kthread_work * ws)816 static void sc16is7xx_tx_proc(struct kthread_work *ws)
817 {
818 	struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
819 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
820 
821 	if ((port->rs485.flags & SER_RS485_ENABLED) &&
822 	    (port->rs485.delay_rts_before_send > 0))
823 		msleep(port->rs485.delay_rts_before_send);
824 
825 	mutex_lock(&one->efr_lock);
826 	sc16is7xx_handle_tx(port);
827 	mutex_unlock(&one->efr_lock);
828 }
829 
sc16is7xx_reconf_rs485(struct uart_port * port)830 static void sc16is7xx_reconf_rs485(struct uart_port *port)
831 {
832 	const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
833 			 SC16IS7XX_EFCR_RTS_INVERT_BIT;
834 	u32 efcr = 0;
835 	struct serial_rs485 *rs485 = &port->rs485;
836 	unsigned long irqflags;
837 
838 	uart_port_lock_irqsave(port, &irqflags);
839 	if (rs485->flags & SER_RS485_ENABLED) {
840 		efcr |=	SC16IS7XX_EFCR_AUTO_RS485_BIT;
841 
842 		if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
843 			efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
844 	}
845 	uart_port_unlock_irqrestore(port, irqflags);
846 
847 	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
848 }
849 
sc16is7xx_reg_proc(struct kthread_work * ws)850 static void sc16is7xx_reg_proc(struct kthread_work *ws)
851 {
852 	struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
853 	struct sc16is7xx_one_config config;
854 	unsigned long irqflags;
855 
856 	uart_port_lock_irqsave(&one->port, &irqflags);
857 	config = one->config;
858 	memset(&one->config, 0, sizeof(one->config));
859 	uart_port_unlock_irqrestore(&one->port, irqflags);
860 
861 	if (config.flags & SC16IS7XX_RECONF_MD) {
862 		u8 mcr = 0;
863 
864 		/* Device ignores RTS setting when hardware flow is enabled */
865 		if (one->port.mctrl & TIOCM_RTS)
866 			mcr |= SC16IS7XX_MCR_RTS_BIT;
867 
868 		if (one->port.mctrl & TIOCM_DTR)
869 			mcr |= SC16IS7XX_MCR_DTR_BIT;
870 
871 		if (one->port.mctrl & TIOCM_LOOP)
872 			mcr |= SC16IS7XX_MCR_LOOP_BIT;
873 		sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
874 				      SC16IS7XX_MCR_RTS_BIT |
875 				      SC16IS7XX_MCR_DTR_BIT |
876 				      SC16IS7XX_MCR_LOOP_BIT,
877 				      mcr);
878 	}
879 
880 	if (config.flags & SC16IS7XX_RECONF_IER)
881 		sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
882 				      config.ier_mask, config.ier_val);
883 
884 	if (config.flags & SC16IS7XX_RECONF_RS485)
885 		sc16is7xx_reconf_rs485(&one->port);
886 }
887 
sc16is7xx_ier_clear(struct uart_port * port,u8 bit)888 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
889 {
890 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
891 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
892 
893 	lockdep_assert_held_once(&port->lock);
894 
895 	one->config.flags |= SC16IS7XX_RECONF_IER;
896 	one->config.ier_mask |= bit;
897 	one->config.ier_val &= ~bit;
898 	kthread_queue_work(&s->kworker, &one->reg_work);
899 }
900 
sc16is7xx_ier_set(struct uart_port * port,u8 bit)901 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
902 {
903 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
904 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
905 
906 	lockdep_assert_held_once(&port->lock);
907 
908 	one->config.flags |= SC16IS7XX_RECONF_IER;
909 	one->config.ier_mask |= bit;
910 	one->config.ier_val |= bit;
911 	kthread_queue_work(&s->kworker, &one->reg_work);
912 }
913 
sc16is7xx_stop_tx(struct uart_port * port)914 static void sc16is7xx_stop_tx(struct uart_port *port)
915 {
916 	sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
917 }
918 
sc16is7xx_stop_rx(struct uart_port * port)919 static void sc16is7xx_stop_rx(struct uart_port *port)
920 {
921 	sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
922 }
923 
sc16is7xx_ms_proc(struct kthread_work * ws)924 static void sc16is7xx_ms_proc(struct kthread_work *ws)
925 {
926 	struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
927 	struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
928 
929 	if (one->port.state) {
930 		mutex_lock(&one->efr_lock);
931 		sc16is7xx_update_mlines(one);
932 		mutex_unlock(&one->efr_lock);
933 
934 		kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
935 	}
936 }
937 
sc16is7xx_enable_ms(struct uart_port * port)938 static void sc16is7xx_enable_ms(struct uart_port *port)
939 {
940 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
941 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
942 
943 	lockdep_assert_held_once(&port->lock);
944 
945 	kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
946 }
947 
sc16is7xx_start_tx(struct uart_port * port)948 static void sc16is7xx_start_tx(struct uart_port *port)
949 {
950 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
951 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
952 
953 	kthread_queue_work(&s->kworker, &one->tx_work);
954 }
955 
sc16is7xx_throttle(struct uart_port * port)956 static void sc16is7xx_throttle(struct uart_port *port)
957 {
958 	unsigned long flags;
959 
960 	/*
961 	 * Hardware flow control is enabled and thus the device ignores RTS
962 	 * value set in MCR register. Stop reading data from RX FIFO so the
963 	 * AutoRTS feature will de-activate RTS output.
964 	 */
965 	uart_port_lock_irqsave(port, &flags);
966 	sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
967 	uart_port_unlock_irqrestore(port, flags);
968 }
969 
sc16is7xx_unthrottle(struct uart_port * port)970 static void sc16is7xx_unthrottle(struct uart_port *port)
971 {
972 	unsigned long flags;
973 
974 	uart_port_lock_irqsave(port, &flags);
975 	sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
976 	uart_port_unlock_irqrestore(port, flags);
977 }
978 
sc16is7xx_tx_empty(struct uart_port * port)979 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
980 {
981 	unsigned int lsr;
982 
983 	lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
984 
985 	return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
986 }
987 
sc16is7xx_get_mctrl(struct uart_port * port)988 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
989 {
990 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
991 
992 	/* Called with port lock taken so we can only return cached value */
993 	return one->old_mctrl;
994 }
995 
sc16is7xx_set_mctrl(struct uart_port * port,unsigned int mctrl)996 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
997 {
998 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
999 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1000 
1001 	one->config.flags |= SC16IS7XX_RECONF_MD;
1002 	kthread_queue_work(&s->kworker, &one->reg_work);
1003 }
1004 
sc16is7xx_break_ctl(struct uart_port * port,int break_state)1005 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1006 {
1007 	sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1008 			      SC16IS7XX_LCR_TXBREAK_BIT,
1009 			      break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1010 }
1011 
sc16is7xx_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1012 static void sc16is7xx_set_termios(struct uart_port *port,
1013 				  struct ktermios *termios,
1014 				  const struct ktermios *old)
1015 {
1016 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1017 	unsigned int lcr, flow = 0;
1018 	int baud;
1019 	unsigned long flags;
1020 
1021 	kthread_cancel_delayed_work_sync(&one->ms_work);
1022 
1023 	/* Mask termios capabilities we don't support */
1024 	termios->c_cflag &= ~CMSPAR;
1025 
1026 	/* Word size */
1027 	switch (termios->c_cflag & CSIZE) {
1028 	case CS5:
1029 		lcr = SC16IS7XX_LCR_WORD_LEN_5;
1030 		break;
1031 	case CS6:
1032 		lcr = SC16IS7XX_LCR_WORD_LEN_6;
1033 		break;
1034 	case CS7:
1035 		lcr = SC16IS7XX_LCR_WORD_LEN_7;
1036 		break;
1037 	case CS8:
1038 		lcr = SC16IS7XX_LCR_WORD_LEN_8;
1039 		break;
1040 	default:
1041 		lcr = SC16IS7XX_LCR_WORD_LEN_8;
1042 		termios->c_cflag &= ~CSIZE;
1043 		termios->c_cflag |= CS8;
1044 		break;
1045 	}
1046 
1047 	/* Parity */
1048 	if (termios->c_cflag & PARENB) {
1049 		lcr |= SC16IS7XX_LCR_PARITY_BIT;
1050 		if (!(termios->c_cflag & PARODD))
1051 			lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1052 	}
1053 
1054 	/* Stop bits */
1055 	if (termios->c_cflag & CSTOPB)
1056 		lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1057 
1058 	/* Set read status mask */
1059 	port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1060 	if (termios->c_iflag & INPCK)
1061 		port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1062 					  SC16IS7XX_LSR_FE_BIT;
1063 	if (termios->c_iflag & (BRKINT | PARMRK))
1064 		port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1065 
1066 	/* Set status ignore mask */
1067 	port->ignore_status_mask = 0;
1068 	if (termios->c_iflag & IGNBRK)
1069 		port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1070 	if (!(termios->c_cflag & CREAD))
1071 		port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1072 
1073 	/* As above, claim the mutex while accessing the EFR. */
1074 	mutex_lock(&one->efr_lock);
1075 
1076 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1077 			     SC16IS7XX_LCR_CONF_MODE_B);
1078 
1079 	/* Configure flow control */
1080 	regcache_cache_bypass(one->regmap, true);
1081 	sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1082 	sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1083 
1084 	port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1085 	if (termios->c_cflag & CRTSCTS) {
1086 		flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1087 			SC16IS7XX_EFR_AUTORTS_BIT;
1088 		port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1089 	}
1090 	if (termios->c_iflag & IXON)
1091 		flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1092 	if (termios->c_iflag & IXOFF)
1093 		flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1094 
1095 	sc16is7xx_port_update(port,
1096 			      SC16IS7XX_EFR_REG,
1097 			      SC16IS7XX_EFR_FLOWCTRL_BITS,
1098 			      flow);
1099 	regcache_cache_bypass(one->regmap, false);
1100 
1101 	/* Update LCR register */
1102 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1103 
1104 	mutex_unlock(&one->efr_lock);
1105 
1106 	/* Get baud rate generator configuration */
1107 	baud = uart_get_baud_rate(port, termios, old,
1108 				  port->uartclk / 16 / 4 / 0xffff,
1109 				  port->uartclk / 16);
1110 
1111 	/* Setup baudrate generator */
1112 	baud = sc16is7xx_set_baud(port, baud);
1113 
1114 	uart_port_lock_irqsave(port, &flags);
1115 
1116 	/* Update timeout according to new baud rate */
1117 	uart_update_timeout(port, termios->c_cflag, baud);
1118 
1119 	if (UART_ENABLE_MS(port, termios->c_cflag))
1120 		sc16is7xx_enable_ms(port);
1121 
1122 	uart_port_unlock_irqrestore(port, flags);
1123 }
1124 
sc16is7xx_config_rs485(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1125 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1126 				  struct serial_rs485 *rs485)
1127 {
1128 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1129 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1130 
1131 	if (rs485->flags & SER_RS485_ENABLED) {
1132 		/*
1133 		 * RTS signal is handled by HW, it's timing can't be influenced.
1134 		 * However, it's sometimes useful to delay TX even without RTS
1135 		 * control therefore we try to handle .delay_rts_before_send.
1136 		 */
1137 		if (rs485->delay_rts_after_send)
1138 			return -EINVAL;
1139 	}
1140 
1141 	one->config.flags |= SC16IS7XX_RECONF_RS485;
1142 	kthread_queue_work(&s->kworker, &one->reg_work);
1143 
1144 	return 0;
1145 }
1146 
sc16is7xx_startup(struct uart_port * port)1147 static int sc16is7xx_startup(struct uart_port *port)
1148 {
1149 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1150 	unsigned int val;
1151 	unsigned long flags;
1152 
1153 	sc16is7xx_power(port, 1);
1154 
1155 	/* Reset FIFOs*/
1156 	val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1157 	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1158 	udelay(5);
1159 	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1160 			     SC16IS7XX_FCR_FIFO_BIT);
1161 
1162 	/* Enable EFR */
1163 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1164 			     SC16IS7XX_LCR_CONF_MODE_B);
1165 
1166 	regcache_cache_bypass(one->regmap, true);
1167 
1168 	/* Enable write access to enhanced features and internal clock div */
1169 	sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1170 			      SC16IS7XX_EFR_ENABLE_BIT,
1171 			      SC16IS7XX_EFR_ENABLE_BIT);
1172 
1173 	/* Enable TCR/TLR */
1174 	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1175 			      SC16IS7XX_MCR_TCRTLR_BIT,
1176 			      SC16IS7XX_MCR_TCRTLR_BIT);
1177 
1178 	/* Configure flow control levels */
1179 	/* Flow control halt level 48, resume level 24 */
1180 	sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1181 			     SC16IS7XX_TCR_RX_RESUME(24) |
1182 			     SC16IS7XX_TCR_RX_HALT(48));
1183 
1184 	regcache_cache_bypass(one->regmap, false);
1185 
1186 	/* Now, initialize the UART */
1187 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1188 
1189 	/* Enable IrDA mode if requested in DT */
1190 	/* This bit must be written with LCR[7] = 0 */
1191 	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1192 			      SC16IS7XX_MCR_IRDA_BIT,
1193 			      one->irda_mode ?
1194 				SC16IS7XX_MCR_IRDA_BIT : 0);
1195 
1196 	/* Enable the Rx and Tx FIFO */
1197 	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1198 			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1199 			      SC16IS7XX_EFCR_TXDISABLE_BIT,
1200 			      0);
1201 
1202 	/* Enable RX, CTS change and modem lines interrupts */
1203 	val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1204 	      SC16IS7XX_IER_MSI_BIT;
1205 	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1206 
1207 	/* Enable modem status polling */
1208 	uart_port_lock_irqsave(port, &flags);
1209 	sc16is7xx_enable_ms(port);
1210 	uart_port_unlock_irqrestore(port, flags);
1211 
1212 	return 0;
1213 }
1214 
sc16is7xx_shutdown(struct uart_port * port)1215 static void sc16is7xx_shutdown(struct uart_port *port)
1216 {
1217 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1218 	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1219 
1220 	kthread_cancel_delayed_work_sync(&one->ms_work);
1221 
1222 	/* Disable all interrupts */
1223 	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1224 	/* Disable TX/RX */
1225 	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1226 			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1227 			      SC16IS7XX_EFCR_TXDISABLE_BIT,
1228 			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1229 			      SC16IS7XX_EFCR_TXDISABLE_BIT);
1230 
1231 	sc16is7xx_power(port, 0);
1232 
1233 	kthread_flush_worker(&s->kworker);
1234 }
1235 
sc16is7xx_type(struct uart_port * port)1236 static const char *sc16is7xx_type(struct uart_port *port)
1237 {
1238 	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1239 
1240 	return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1241 }
1242 
sc16is7xx_request_port(struct uart_port * port)1243 static int sc16is7xx_request_port(struct uart_port *port)
1244 {
1245 	/* Do nothing */
1246 	return 0;
1247 }
1248 
sc16is7xx_config_port(struct uart_port * port,int flags)1249 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1250 {
1251 	if (flags & UART_CONFIG_TYPE)
1252 		port->type = PORT_SC16IS7XX;
1253 }
1254 
sc16is7xx_verify_port(struct uart_port * port,struct serial_struct * s)1255 static int sc16is7xx_verify_port(struct uart_port *port,
1256 				 struct serial_struct *s)
1257 {
1258 	if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1259 		return -EINVAL;
1260 	if (s->irq != port->irq)
1261 		return -EINVAL;
1262 
1263 	return 0;
1264 }
1265 
sc16is7xx_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1266 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1267 			 unsigned int oldstate)
1268 {
1269 	sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1270 }
1271 
sc16is7xx_null_void(struct uart_port * port)1272 static void sc16is7xx_null_void(struct uart_port *port)
1273 {
1274 	/* Do nothing */
1275 }
1276 
1277 static const struct uart_ops sc16is7xx_ops = {
1278 	.tx_empty	= sc16is7xx_tx_empty,
1279 	.set_mctrl	= sc16is7xx_set_mctrl,
1280 	.get_mctrl	= sc16is7xx_get_mctrl,
1281 	.stop_tx	= sc16is7xx_stop_tx,
1282 	.start_tx	= sc16is7xx_start_tx,
1283 	.throttle	= sc16is7xx_throttle,
1284 	.unthrottle	= sc16is7xx_unthrottle,
1285 	.stop_rx	= sc16is7xx_stop_rx,
1286 	.enable_ms	= sc16is7xx_enable_ms,
1287 	.break_ctl	= sc16is7xx_break_ctl,
1288 	.startup	= sc16is7xx_startup,
1289 	.shutdown	= sc16is7xx_shutdown,
1290 	.set_termios	= sc16is7xx_set_termios,
1291 	.type		= sc16is7xx_type,
1292 	.request_port	= sc16is7xx_request_port,
1293 	.release_port	= sc16is7xx_null_void,
1294 	.config_port	= sc16is7xx_config_port,
1295 	.verify_port	= sc16is7xx_verify_port,
1296 	.pm		= sc16is7xx_pm,
1297 };
1298 
1299 #ifdef CONFIG_GPIOLIB
sc16is7xx_gpio_get(struct gpio_chip * chip,unsigned offset)1300 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1301 {
1302 	unsigned int val;
1303 	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1304 	struct uart_port *port = &s->p[0].port;
1305 
1306 	val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1307 
1308 	return !!(val & BIT(offset));
1309 }
1310 
sc16is7xx_gpio_set(struct gpio_chip * chip,unsigned offset,int val)1311 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1312 {
1313 	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1314 	struct uart_port *port = &s->p[0].port;
1315 
1316 	sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1317 			      val ? BIT(offset) : 0);
1318 }
1319 
sc16is7xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1320 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1321 					  unsigned offset)
1322 {
1323 	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1324 	struct uart_port *port = &s->p[0].port;
1325 
1326 	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1327 
1328 	return 0;
1329 }
1330 
sc16is7xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1331 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1332 					   unsigned offset, int val)
1333 {
1334 	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1335 	struct uart_port *port = &s->p[0].port;
1336 	u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1337 
1338 	if (val)
1339 		state |= BIT(offset);
1340 	else
1341 		state &= ~BIT(offset);
1342 
1343 	/*
1344 	 * If we write IOSTATE first, and then IODIR, the output value is not
1345 	 * transferred to the corresponding I/O pin.
1346 	 * The datasheet states that each register bit will be transferred to
1347 	 * the corresponding I/O pin programmed as output when writing to
1348 	 * IOSTATE. Therefore, configure direction first with IODIR, and then
1349 	 * set value after with IOSTATE.
1350 	 */
1351 	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1352 			      BIT(offset));
1353 	sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1354 
1355 	return 0;
1356 }
1357 
sc16is7xx_gpio_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1358 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1359 					  unsigned long *valid_mask,
1360 					  unsigned int ngpios)
1361 {
1362 	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1363 
1364 	*valid_mask = s->gpio_valid_mask;
1365 
1366 	return 0;
1367 }
1368 
sc16is7xx_setup_gpio_chip(struct sc16is7xx_port * s)1369 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1370 {
1371 	struct device *dev = s->p[0].port.dev;
1372 
1373 	if (!s->devtype->nr_gpio)
1374 		return 0;
1375 
1376 	switch (s->mctrl_mask) {
1377 	case 0:
1378 		s->gpio_valid_mask = GENMASK(7, 0);
1379 		break;
1380 	case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1381 		s->gpio_valid_mask = GENMASK(3, 0);
1382 		break;
1383 	case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1384 		s->gpio_valid_mask = GENMASK(7, 4);
1385 		break;
1386 	default:
1387 		break;
1388 	}
1389 
1390 	if (s->gpio_valid_mask == 0)
1391 		return 0;
1392 
1393 	s->gpio.owner		 = THIS_MODULE;
1394 	s->gpio.parent		 = dev;
1395 	s->gpio.label		 = dev_name(dev);
1396 	s->gpio.init_valid_mask	 = sc16is7xx_gpio_init_valid_mask;
1397 	s->gpio.direction_input	 = sc16is7xx_gpio_direction_input;
1398 	s->gpio.get		 = sc16is7xx_gpio_get;
1399 	s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1400 	s->gpio.set		 = sc16is7xx_gpio_set;
1401 	s->gpio.base		 = -1;
1402 	s->gpio.ngpio		 = s->devtype->nr_gpio;
1403 	s->gpio.can_sleep	 = 1;
1404 
1405 	return gpiochip_add_data(&s->gpio, s);
1406 }
1407 #endif
1408 
1409 /*
1410  * Configure ports designated to operate as modem control lines.
1411  */
sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port * s,struct regmap * regmap)1412 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1413 				       struct regmap *regmap)
1414 {
1415 	int i;
1416 	int ret;
1417 	int count;
1418 	u32 mctrl_port[2];
1419 	struct device *dev = s->p[0].port.dev;
1420 
1421 	count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1422 	if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1423 		return 0;
1424 
1425 	ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1426 					     mctrl_port, count);
1427 	if (ret)
1428 		return ret;
1429 
1430 	s->mctrl_mask = 0;
1431 
1432 	for (i = 0; i < count; i++) {
1433 		/* Use GPIO lines as modem control lines */
1434 		if (mctrl_port[i] == 0)
1435 			s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1436 		else if (mctrl_port[i] == 1)
1437 			s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1438 	}
1439 
1440 	if (s->mctrl_mask)
1441 		regmap_update_bits(
1442 			regmap,
1443 			SC16IS7XX_IOCONTROL_REG,
1444 			SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1445 			SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1446 
1447 	return 0;
1448 }
1449 
1450 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1451 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,
1452 	.delay_rts_before_send = 1,
1453 	.delay_rts_after_send = 1,	/* Not supported but keep returning -EINVAL */
1454 };
1455 
sc16is7xx_probe(struct device * dev,const struct sc16is7xx_devtype * devtype,struct regmap * regmaps[],int irq)1456 static int sc16is7xx_probe(struct device *dev,
1457 			   const struct sc16is7xx_devtype *devtype,
1458 			   struct regmap *regmaps[], int irq)
1459 {
1460 	unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1461 	unsigned int val;
1462 	u32 uartclk = 0;
1463 	int i, ret;
1464 	struct sc16is7xx_port *s;
1465 
1466 	for (i = 0; i < devtype->nr_uart; i++)
1467 		if (IS_ERR(regmaps[i]))
1468 			return PTR_ERR(regmaps[i]);
1469 
1470 	/*
1471 	 * This device does not have an identification register that would
1472 	 * tell us if we are really connected to the correct device.
1473 	 * The best we can do is to check if communication is at all possible.
1474 	 *
1475 	 * Note: regmap[0] is used in the probe function to access registers
1476 	 * common to all channels/ports, as it is guaranteed to be present on
1477 	 * all variants.
1478 	 */
1479 	ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1480 	if (ret < 0)
1481 		return -EPROBE_DEFER;
1482 
1483 	/* Alloc port structure */
1484 	s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1485 	if (!s) {
1486 		dev_err(dev, "Error allocating port structure\n");
1487 		return -ENOMEM;
1488 	}
1489 
1490 	/* Always ask for fixed clock rate from a property. */
1491 	device_property_read_u32(dev, "clock-frequency", &uartclk);
1492 
1493 	s->clk = devm_clk_get_optional(dev, NULL);
1494 	if (IS_ERR(s->clk))
1495 		return PTR_ERR(s->clk);
1496 
1497 	ret = clk_prepare_enable(s->clk);
1498 	if (ret)
1499 		return ret;
1500 
1501 	freq = clk_get_rate(s->clk);
1502 	if (freq == 0) {
1503 		if (uartclk)
1504 			freq = uartclk;
1505 		if (pfreq)
1506 			freq = *pfreq;
1507 		if (freq)
1508 			dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1509 		else
1510 			return -EINVAL;
1511 	}
1512 
1513 	s->devtype = devtype;
1514 	dev_set_drvdata(dev, s);
1515 
1516 	kthread_init_worker(&s->kworker);
1517 	s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1518 				      "sc16is7xx");
1519 	if (IS_ERR(s->kworker_task)) {
1520 		ret = PTR_ERR(s->kworker_task);
1521 		goto out_clk;
1522 	}
1523 	sched_set_fifo(s->kworker_task);
1524 
1525 	/* reset device, purging any pending irq / data */
1526 	regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG,
1527 		     SC16IS7XX_IOCONTROL_SRESET_BIT);
1528 
1529 	for (i = 0; i < devtype->nr_uart; ++i) {
1530 		s->p[i].port.line = find_first_zero_bit(&sc16is7xx_lines,
1531 							SC16IS7XX_MAX_DEVS);
1532 		if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1533 			ret = -ERANGE;
1534 			goto out_ports;
1535 		}
1536 
1537 		/* Initialize port data */
1538 		s->p[i].port.dev	= dev;
1539 		s->p[i].port.irq	= irq;
1540 		s->p[i].port.type	= PORT_SC16IS7XX;
1541 		s->p[i].port.fifosize	= SC16IS7XX_FIFO_SIZE;
1542 		s->p[i].port.flags	= UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1543 		s->p[i].port.iobase	= i;
1544 		/*
1545 		 * Use all ones as membase to make sure uart_configure_port() in
1546 		 * serial_core.c does not abort for SPI/I2C devices where the
1547 		 * membase address is not applicable.
1548 		 */
1549 		s->p[i].port.membase	= (void __iomem *)~0;
1550 		s->p[i].port.iotype	= UPIO_PORT;
1551 		s->p[i].port.uartclk	= freq;
1552 		s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1553 		s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1554 		s->p[i].port.ops	= &sc16is7xx_ops;
1555 		s->p[i].old_mctrl	= 0;
1556 		s->p[i].regmap		= regmaps[i];
1557 
1558 		mutex_init(&s->p[i].efr_lock);
1559 
1560 		ret = uart_get_rs485_mode(&s->p[i].port);
1561 		if (ret)
1562 			goto out_ports;
1563 
1564 		/* Disable all interrupts */
1565 		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1566 		/* Disable TX/RX */
1567 		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1568 				     SC16IS7XX_EFCR_RXDISABLE_BIT |
1569 				     SC16IS7XX_EFCR_TXDISABLE_BIT);
1570 
1571 		/* Initialize kthread work structs */
1572 		kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1573 		kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1574 		kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1575 
1576 		/* Register port */
1577 		ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1578 		if (ret)
1579 			goto out_ports;
1580 
1581 		set_bit(s->p[i].port.line, &sc16is7xx_lines);
1582 
1583 		/* Enable EFR */
1584 		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1585 				     SC16IS7XX_LCR_CONF_MODE_B);
1586 
1587 		regcache_cache_bypass(regmaps[i], true);
1588 
1589 		/* Enable write access to enhanced features */
1590 		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1591 				     SC16IS7XX_EFR_ENABLE_BIT);
1592 
1593 		regcache_cache_bypass(regmaps[i], false);
1594 
1595 		/* Restore access to general registers */
1596 		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1597 
1598 		/* Go to suspend mode */
1599 		sc16is7xx_power(&s->p[i].port, 0);
1600 	}
1601 
1602 	if (dev->of_node) {
1603 		struct property *prop;
1604 		const __be32 *p;
1605 		u32 u;
1606 
1607 		of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1608 					 prop, p, u)
1609 			if (u < devtype->nr_uart)
1610 				s->p[u].irda_mode = true;
1611 	}
1612 
1613 	ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1614 	if (ret)
1615 		goto out_ports;
1616 
1617 #ifdef CONFIG_GPIOLIB
1618 	ret = sc16is7xx_setup_gpio_chip(s);
1619 	if (ret)
1620 		goto out_ports;
1621 #endif
1622 
1623 	/*
1624 	 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1625 	 * If that succeeds, we can allow sharing the interrupt as well.
1626 	 * In case the interrupt controller doesn't support that, we fall
1627 	 * back to a non-shared falling-edge trigger.
1628 	 */
1629 	ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1630 					IRQF_TRIGGER_LOW | IRQF_SHARED |
1631 					IRQF_ONESHOT,
1632 					dev_name(dev), s);
1633 	if (!ret)
1634 		return 0;
1635 
1636 	ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1637 					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1638 					dev_name(dev), s);
1639 	if (!ret)
1640 		return 0;
1641 
1642 #ifdef CONFIG_GPIOLIB
1643 	if (s->gpio_valid_mask)
1644 		gpiochip_remove(&s->gpio);
1645 #endif
1646 
1647 out_ports:
1648 	for (i = 0; i < devtype->nr_uart; i++)
1649 		if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines))
1650 			uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1651 
1652 	kthread_stop(s->kworker_task);
1653 
1654 out_clk:
1655 	clk_disable_unprepare(s->clk);
1656 
1657 	return ret;
1658 }
1659 
sc16is7xx_remove(struct device * dev)1660 static void sc16is7xx_remove(struct device *dev)
1661 {
1662 	struct sc16is7xx_port *s = dev_get_drvdata(dev);
1663 	int i;
1664 
1665 #ifdef CONFIG_GPIOLIB
1666 	if (s->gpio_valid_mask)
1667 		gpiochip_remove(&s->gpio);
1668 #endif
1669 
1670 	for (i = 0; i < s->devtype->nr_uart; i++) {
1671 		kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1672 		if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines))
1673 			uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1674 		sc16is7xx_power(&s->p[i].port, 0);
1675 	}
1676 
1677 	kthread_flush_worker(&s->kworker);
1678 	kthread_stop(s->kworker_task);
1679 
1680 	clk_disable_unprepare(s->clk);
1681 }
1682 
1683 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1684 	{ .compatible = "nxp,sc16is740",	.data = &sc16is74x_devtype, },
1685 	{ .compatible = "nxp,sc16is741",	.data = &sc16is74x_devtype, },
1686 	{ .compatible = "nxp,sc16is750",	.data = &sc16is750_devtype, },
1687 	{ .compatible = "nxp,sc16is752",	.data = &sc16is752_devtype, },
1688 	{ .compatible = "nxp,sc16is760",	.data = &sc16is760_devtype, },
1689 	{ .compatible = "nxp,sc16is762",	.data = &sc16is762_devtype, },
1690 	{ }
1691 };
1692 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1693 
1694 static struct regmap_config regcfg = {
1695 	.reg_bits = 5,
1696 	.pad_bits = 3,
1697 	.val_bits = 8,
1698 	.cache_type = REGCACHE_RBTREE,
1699 	.volatile_reg = sc16is7xx_regmap_volatile,
1700 	.precious_reg = sc16is7xx_regmap_precious,
1701 	.writeable_noinc_reg = sc16is7xx_regmap_noinc,
1702 	.readable_noinc_reg = sc16is7xx_regmap_noinc,
1703 	.max_raw_read = SC16IS7XX_FIFO_SIZE,
1704 	.max_raw_write = SC16IS7XX_FIFO_SIZE,
1705 	.max_register = SC16IS7XX_EFCR_REG,
1706 };
1707 
sc16is7xx_regmap_name(u8 port_id)1708 static const char *sc16is7xx_regmap_name(u8 port_id)
1709 {
1710 	switch (port_id) {
1711 	case 0:	return "port0";
1712 	case 1:	return "port1";
1713 	default:
1714 		WARN_ON(true);
1715 		return NULL;
1716 	}
1717 }
1718 
sc16is7xx_regmap_port_mask(unsigned int port_id)1719 static unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1720 {
1721 	/* CH1,CH0 are at bits 2:1. */
1722 	return port_id << 1;
1723 }
1724 
1725 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
sc16is7xx_spi_probe(struct spi_device * spi)1726 static int sc16is7xx_spi_probe(struct spi_device *spi)
1727 {
1728 	const struct sc16is7xx_devtype *devtype;
1729 	struct regmap *regmaps[2];
1730 	unsigned int i;
1731 	int ret;
1732 
1733 	/* Setup SPI bus */
1734 	spi->bits_per_word	= 8;
1735 	/* For all variants, only mode 0 is supported */
1736 	if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0)
1737 		return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n");
1738 
1739 	spi->mode		= spi->mode ? : SPI_MODE_0;
1740 	spi->max_speed_hz	= spi->max_speed_hz ? : 4 * HZ_PER_MHZ;
1741 	ret = spi_setup(spi);
1742 	if (ret)
1743 		return ret;
1744 
1745 	if (spi->dev.of_node) {
1746 		devtype = device_get_match_data(&spi->dev);
1747 		if (!devtype)
1748 			return -ENODEV;
1749 	} else {
1750 		const struct spi_device_id *id_entry = spi_get_device_id(spi);
1751 
1752 		devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1753 	}
1754 
1755 	for (i = 0; i < devtype->nr_uart; i++) {
1756 		regcfg.name = sc16is7xx_regmap_name(i);
1757 		/*
1758 		 * If read_flag_mask is 0, the regmap code sets it to a default
1759 		 * of 0x80. Since we specify our own mask, we must add the READ
1760 		 * bit ourselves:
1761 		 */
1762 		regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i) |
1763 			SC16IS7XX_SPI_READ_BIT;
1764 		regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
1765 		regmaps[i] = devm_regmap_init_spi(spi, &regcfg);
1766 	}
1767 
1768 	return sc16is7xx_probe(&spi->dev, devtype, regmaps, spi->irq);
1769 }
1770 
sc16is7xx_spi_remove(struct spi_device * spi)1771 static void sc16is7xx_spi_remove(struct spi_device *spi)
1772 {
1773 	sc16is7xx_remove(&spi->dev);
1774 }
1775 
1776 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1777 	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
1778 	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
1779 	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
1780 	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
1781 	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
1782 	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
1783 	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
1784 	{ }
1785 };
1786 
1787 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1788 
1789 static struct spi_driver sc16is7xx_spi_uart_driver = {
1790 	.driver = {
1791 		.name		= SC16IS7XX_NAME,
1792 		.of_match_table	= sc16is7xx_dt_ids,
1793 	},
1794 	.probe		= sc16is7xx_spi_probe,
1795 	.remove		= sc16is7xx_spi_remove,
1796 	.id_table	= sc16is7xx_spi_id_table,
1797 };
1798 
1799 MODULE_ALIAS("spi:sc16is7xx");
1800 #endif
1801 
1802 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
sc16is7xx_i2c_probe(struct i2c_client * i2c)1803 static int sc16is7xx_i2c_probe(struct i2c_client *i2c)
1804 {
1805 	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
1806 	const struct sc16is7xx_devtype *devtype;
1807 	struct regmap *regmaps[2];
1808 	unsigned int i;
1809 
1810 	if (i2c->dev.of_node) {
1811 		devtype = device_get_match_data(&i2c->dev);
1812 		if (!devtype)
1813 			return -ENODEV;
1814 	} else {
1815 		devtype = (struct sc16is7xx_devtype *)id->driver_data;
1816 	}
1817 
1818 	for (i = 0; i < devtype->nr_uart; i++) {
1819 		regcfg.name = sc16is7xx_regmap_name(i);
1820 		regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i);
1821 		regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
1822 		regmaps[i] = devm_regmap_init_i2c(i2c, &regcfg);
1823 	}
1824 
1825 	return sc16is7xx_probe(&i2c->dev, devtype, regmaps, i2c->irq);
1826 }
1827 
sc16is7xx_i2c_remove(struct i2c_client * client)1828 static void sc16is7xx_i2c_remove(struct i2c_client *client)
1829 {
1830 	sc16is7xx_remove(&client->dev);
1831 }
1832 
1833 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1834 	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
1835 	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
1836 	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
1837 	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
1838 	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
1839 	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
1840 	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
1841 	{ }
1842 };
1843 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1844 
1845 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1846 	.driver = {
1847 		.name		= SC16IS7XX_NAME,
1848 		.of_match_table	= sc16is7xx_dt_ids,
1849 	},
1850 	.probe		= sc16is7xx_i2c_probe,
1851 	.remove		= sc16is7xx_i2c_remove,
1852 	.id_table	= sc16is7xx_i2c_id_table,
1853 };
1854 
1855 #endif
1856 
sc16is7xx_init(void)1857 static int __init sc16is7xx_init(void)
1858 {
1859 	int ret;
1860 
1861 	ret = uart_register_driver(&sc16is7xx_uart);
1862 	if (ret) {
1863 		pr_err("Registering UART driver failed\n");
1864 		return ret;
1865 	}
1866 
1867 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1868 	ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1869 	if (ret < 0) {
1870 		pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1871 		goto err_i2c;
1872 	}
1873 #endif
1874 
1875 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1876 	ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1877 	if (ret < 0) {
1878 		pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1879 		goto err_spi;
1880 	}
1881 #endif
1882 	return ret;
1883 
1884 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1885 err_spi:
1886 #endif
1887 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1888 	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1889 err_i2c:
1890 #endif
1891 	uart_unregister_driver(&sc16is7xx_uart);
1892 	return ret;
1893 }
1894 module_init(sc16is7xx_init);
1895 
sc16is7xx_exit(void)1896 static void __exit sc16is7xx_exit(void)
1897 {
1898 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1899 	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1900 #endif
1901 
1902 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1903 	spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1904 #endif
1905 	uart_unregister_driver(&sc16is7xx_uart);
1906 }
1907 module_exit(sc16is7xx_exit);
1908 
1909 MODULE_LICENSE("GPL");
1910 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1911 MODULE_DESCRIPTION("SC16IS7XX serial driver");
1912