1 /*****************************************************************************/
2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
7 /* */
8 /* Copyright (C) 2000 IBM Corporation */
9 /* Copyright (C) 2002,2003 Adaptec, Inc. */
10 /* */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
15 /* */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
20 /* */
21 /* NO WARRANTY */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
31 /* */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40 /* */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44 /* */
45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */
46 /* ipslinux@adaptec.com */
47 /* */
48 /* For system support issues, contact your local IBM Customer support. */
49 /* Directions to find IBM Customer Support for each country can be found at: */
50 /* http://www.ibm.com/planetwide/ */
51 /* */
52 /*****************************************************************************/
53
54 /*****************************************************************************/
55 /* Change Log */
56 /* */
57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58 /* 0.99.03 - Make interrupt routine handle all completed request on the */
59 /* adapter not just the first one */
60 /* - Make sure passthru commands get woken up if we run out of */
61 /* SCBs */
62 /* - Send all of the commands on the queue at once rather than */
63 /* one at a time since the card will support it. */
64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65 /* the interface to the utilities to change */
66 /* - Fix error recovery code */
67 /* 0.99.05 - Fix an oops when we get certain passthru commands */
68 /* 1.00.00 - Initial Public Release */
69 /* Functionally equivalent to 0.99.05 */
70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71 /* - Change version to 3.60 to coincide with release numbering. */
72 /* 3.60.01 - Remove bogus error check in passthru routine */
73 /* 3.60.02 - Make DCDB direction based on lookup table */
74 /* - Only allow one DCDB command to a SCSI ID at a time */
75 /* 4.00.00 - Add support for ServeRAID 4 */
76 /* 4.00.01 - Add support for First Failure Data Capture */
77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */
78 /* 4.00.03 - Add alternative passthru interface */
79 /* - Add ability to flash BIOS */
80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81 /* 4.00.05 - Remove wish_block from init routine */
82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83 /* 2.3.18 and later */
84 /* - Sync with other changes from the 2.3 kernels */
85 /* 4.00.06 - Fix timeout with initial FFDC command */
86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87 /* 4.10.00 - Add support for ServeRAID 4M/4L */
88 /* 4.10.13 - Fix for dynamic unload and proc file system */
89 /* 4.20.03 - Rename version to coincide with new release schedules */
90 /* Performance fixes */
91 /* Fix truncation of /proc files with cat */
92 /* Merge in changes through kernel 2.4.0test1ac21 */
93 /* 4.20.13 - Fix some failure cases / reset code */
94 /* - Hook into the reboot_notifier to flush the controller cache */
95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97 /* - Add IPSSEND Flash Support */
98 /* - Set Sense Data for Unknown SCSI Command */
99 /* - Use Slot Number from NVRAM Page 5 */
100 /* - Restore caller's DCDB Structure */
101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103 /* - Don't release HA Lock in ips_next() until SC taken off queue */
104 /* - Unregister SCSI device in ips_release() */
105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107 /* Code Clean-Up for 2.4.x kernel */
108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110 /* - Don't Issue Internal FFDC Command if there are Active Commands */
111 /* - Close Window for getting too many IOCTL's active */
112 /* 4.80.00 - Make ia64 Safe */
113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114 /* - Adjustments to Device Queue Depth */
115 /* 4.80.14 - Take all semaphores off stack */
116 /* - Clean Up New_IOCTL path */
117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118 /* - 5 second delay needed after resetting an i960 adapter */
119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124 /* 4.90.11 - Don't actually RESET unless it's physically required */
125 /* - Remove unused compile options */
126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127 /* - Get rid on IOCTL_NEW_COMMAND code */
128 /* - Add Extended DCDB Commands for Tape Support in 5I */
129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130 /* 5.10.15 - remove unused code (sem, macros, etc.) */
131 /* 5.30.00 - use __devexit_p() */
132 /* 6.00.00 - Add 6x Adapters and Battery Flash */
133 /* 6.10.00 - Remove 1G Addressing Limitations */
134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136 /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138 /* - Fix sort order of 7k */
139 /* - Remove 3 unused "inline" functions */
140 /* 7.12.xx - Use STATIC functions wherever possible */
141 /* - Clean up deprecated MODULE_PARM calls */
142 /* 7.12.05 - Remove Version Matching per IBM request */
143 /*****************************************************************************/
144
145 /*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164 #include <asm/io.h>
165 #include <asm/byteorder.h>
166 #include <asm/page.h>
167 #include <linux/stddef.h>
168 #include <linux/string.h>
169 #include <linux/errno.h>
170 #include <linux/kernel.h>
171 #include <linux/ioport.h>
172 #include <linux/slab.h>
173 #include <linux/delay.h>
174 #include <linux/pci.h>
175 #include <linux/proc_fs.h>
176 #include <linux/reboot.h>
177 #include <linux/interrupt.h>
178
179 #include <linux/blkdev.h>
180 #include <linux/types.h>
181 #include <linux/dma-mapping.h>
182
183 #include <scsi/scsi.h>
184 #include <scsi/scsi_cmnd.h>
185 #include <scsi/scsi_device.h>
186 #include <scsi/scsi_eh.h>
187 #include <scsi/scsi_host.h>
188 #include <scsi/scsi_tcq.h>
189 #include <scsi/sg.h>
190
191 #include "ips.h"
192
193 #include <linux/module.h>
194
195 #include <linux/stat.h>
196
197 #include <linux/spinlock.h>
198 #include <linux/init.h>
199
200 #include <linux/smp.h>
201
202 #ifdef MODULE
203 static char *ips = NULL;
204 module_param(ips, charp, 0);
205 #endif
206
207 /*
208 * DRIVER_VER
209 */
210 #define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
211 #define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
212
213 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
214 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
215 DMA_BIDIRECTIONAL : \
216 scb->scsi_cmd->sc_data_direction)
217
218 #ifdef IPS_DEBUG
219 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
220 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
221 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
222 #else
223 #define METHOD_TRACE(s, i)
224 #define DEBUG(i, s)
225 #define DEBUG_VAR(i, s, v...)
226 #endif
227
228 /*
229 * Function prototypes
230 */
231 static int ips_eh_abort(struct scsi_cmnd *);
232 static int ips_eh_reset(struct scsi_cmnd *);
233 static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
234 static const char *ips_info(struct Scsi_Host *);
235 static irqreturn_t do_ipsintr(int, void *);
236 static int ips_hainit(ips_ha_t *);
237 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
238 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
239 static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
240 static int ips_online(ips_ha_t *, ips_scb_t *);
241 static int ips_inquiry(ips_ha_t *, ips_scb_t *);
242 static int ips_rdcap(ips_ha_t *, ips_scb_t *);
243 static int ips_msense(ips_ha_t *, ips_scb_t *);
244 static int ips_reqsen(ips_ha_t *, ips_scb_t *);
245 static int ips_deallocatescbs(ips_ha_t *, int);
246 static int ips_allocatescbs(ips_ha_t *);
247 static int ips_reset_copperhead(ips_ha_t *);
248 static int ips_reset_copperhead_memio(ips_ha_t *);
249 static int ips_reset_morpheus(ips_ha_t *);
250 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
251 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
252 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
253 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
254 static int ips_isintr_copperhead(ips_ha_t *);
255 static int ips_isintr_copperhead_memio(ips_ha_t *);
256 static int ips_isintr_morpheus(ips_ha_t *);
257 static int ips_wait(ips_ha_t *, int, int);
258 static int ips_write_driver_status(ips_ha_t *, int);
259 static int ips_read_adapter_status(ips_ha_t *, int);
260 static int ips_read_subsystem_parameters(ips_ha_t *, int);
261 static int ips_read_config(ips_ha_t *, int);
262 static int ips_clear_adapter(ips_ha_t *, int);
263 static int ips_readwrite_page5(ips_ha_t *, int, int);
264 static int ips_init_copperhead(ips_ha_t *);
265 static int ips_init_copperhead_memio(ips_ha_t *);
266 static int ips_init_morpheus(ips_ha_t *);
267 static int ips_isinit_copperhead(ips_ha_t *);
268 static int ips_isinit_copperhead_memio(ips_ha_t *);
269 static int ips_isinit_morpheus(ips_ha_t *);
270 static int ips_erase_bios(ips_ha_t *);
271 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
272 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
273 static int ips_erase_bios_memio(ips_ha_t *);
274 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
275 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
276 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
277 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
278 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
279 static void ips_free_flash_copperhead(ips_ha_t * ha);
280 static void ips_get_bios_version(ips_ha_t *, int);
281 static void ips_identify_controller(ips_ha_t *);
282 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
283 static void ips_enable_int_copperhead(ips_ha_t *);
284 static void ips_enable_int_copperhead_memio(ips_ha_t *);
285 static void ips_enable_int_morpheus(ips_ha_t *);
286 static int ips_intr_copperhead(ips_ha_t *);
287 static int ips_intr_morpheus(ips_ha_t *);
288 static void ips_next(ips_ha_t *, int);
289 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
290 static void ipsintr_done(ips_ha_t *, struct ips_scb *);
291 static void ips_done(ips_ha_t *, ips_scb_t *);
292 static void ips_free(ips_ha_t *);
293 static void ips_init_scb(ips_ha_t *, ips_scb_t *);
294 static void ips_freescb(ips_ha_t *, ips_scb_t *);
295 static void ips_setup_funclist(ips_ha_t *);
296 static void ips_statinit(ips_ha_t *);
297 static void ips_statinit_memio(ips_ha_t *);
298 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time64_t);
299 static void ips_ffdc_reset(ips_ha_t *, int);
300 static void ips_ffdc_time(ips_ha_t *);
301 static uint32_t ips_statupd_copperhead(ips_ha_t *);
302 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
303 static uint32_t ips_statupd_morpheus(ips_ha_t *);
304 static ips_scb_t *ips_getscb(ips_ha_t *);
305 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
306 static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *);
307 static void ips_putq_copp_tail(ips_copp_queue_t *,
308 ips_copp_wait_item_t *);
309 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
310 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
311 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *);
312 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *,
313 struct scsi_cmnd *);
314 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
315 ips_copp_wait_item_t *);
316 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
317
318 static int ips_is_passthru(struct scsi_cmnd *);
319 static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
320 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
321 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
322 static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
323 unsigned int count);
324 static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
325 unsigned int count);
326
327 static int ips_write_info(struct Scsi_Host *, char *, int);
328 static int ips_show_info(struct seq_file *, struct Scsi_Host *);
329 static int ips_host_info(ips_ha_t *, struct seq_file *);
330 static int ips_abort_init(ips_ha_t * ha, int index);
331 static int ips_init_phase2(int index);
332
333 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
334 static int ips_register_scsi(int index);
335
336 static int ips_poll_for_flush_complete(ips_ha_t * ha);
337 static void ips_flush_and_reset(ips_ha_t *ha);
338
339 /*
340 * global variables
341 */
342 static const char ips_name[] = "ips";
343 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
344 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
345 static unsigned int ips_next_controller;
346 static unsigned int ips_num_controllers;
347 static unsigned int ips_released_controllers;
348 static int ips_hotplug;
349 static int ips_cmd_timeout = 60;
350 static int ips_reset_timeout = 60 * 5;
351 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
352 static int ips_force_i2o = 1; /* Always use I2O command delivery */
353 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
354 static int ips_cd_boot; /* Booting from Manager CD */
355 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
356 static dma_addr_t ips_flashbusaddr;
357 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
358 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
359 static struct scsi_host_template ips_driver_template = {
360 .info = ips_info,
361 .queuecommand = ips_queue,
362 .eh_abort_handler = ips_eh_abort,
363 .eh_host_reset_handler = ips_eh_reset,
364 .proc_name = "ips",
365 .show_info = ips_show_info,
366 .write_info = ips_write_info,
367 .slave_configure = ips_slave_configure,
368 .bios_param = ips_biosparam,
369 .this_id = -1,
370 .sg_tablesize = IPS_MAX_SG,
371 .cmd_per_lun = 3,
372 .no_write_same = 1,
373 };
374
375
376 /* This table describes all ServeRAID Adapters */
377 static struct pci_device_id ips_pci_table[] = {
378 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
379 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
380 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
381 { 0, }
382 };
383
384 MODULE_DEVICE_TABLE( pci, ips_pci_table );
385
386 static char ips_hot_plug_name[] = "ips";
387
388 static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
389 static void ips_remove_device(struct pci_dev *pci_dev);
390
391 static struct pci_driver ips_pci_driver = {
392 .name = ips_hot_plug_name,
393 .id_table = ips_pci_table,
394 .probe = ips_insert_device,
395 .remove = ips_remove_device,
396 };
397
398
399 /*
400 * Necessary forward function protoypes
401 */
402 static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
403
404 #define MAX_ADAPTER_NAME 15
405
406 static char ips_adapter_name[][30] = {
407 "ServeRAID",
408 "ServeRAID II",
409 "ServeRAID on motherboard",
410 "ServeRAID on motherboard",
411 "ServeRAID 3H",
412 "ServeRAID 3L",
413 "ServeRAID 4H",
414 "ServeRAID 4M",
415 "ServeRAID 4L",
416 "ServeRAID 4Mx",
417 "ServeRAID 4Lx",
418 "ServeRAID 5i",
419 "ServeRAID 5i",
420 "ServeRAID 6M",
421 "ServeRAID 6i",
422 "ServeRAID 7t",
423 "ServeRAID 7k",
424 "ServeRAID 7M"
425 };
426
427 static struct notifier_block ips_notifier = {
428 ips_halt, NULL, 0
429 };
430
431 /*
432 * Direction table
433 */
434 static char ips_command_direction[] = {
435 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
436 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
437 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
438 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
439 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
440 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
441 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
442 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
443 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
444 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
445 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
446 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
447 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
448 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
449 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
450 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
451 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
469 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
470 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
471 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
472 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
486 };
487
488
489 /****************************************************************************/
490 /* */
491 /* Routine Name: ips_setup */
492 /* */
493 /* Routine Description: */
494 /* */
495 /* setup parameters to the driver */
496 /* */
497 /****************************************************************************/
498 static int
ips_setup(char * ips_str)499 ips_setup(char *ips_str)
500 {
501
502 int i;
503 char *key;
504 char *value;
505 static const IPS_OPTION options[] = {
506 {"noi2o", &ips_force_i2o, 0},
507 {"nommap", &ips_force_memio, 0},
508 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
509 {"cdboot", &ips_cd_boot, 0},
510 {"maxcmds", &MaxLiteCmds, 32},
511 };
512
513 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
514 /* Search for value */
515 while ((key = strsep(&ips_str, ",."))) {
516 if (!*key)
517 continue;
518 value = strchr(key, ':');
519 if (value)
520 *value++ = '\0';
521 /*
522 * We now have key/value pairs.
523 * Update the variables
524 */
525 for (i = 0; i < ARRAY_SIZE(options); i++) {
526 if (strncasecmp
527 (key, options[i].option_name,
528 strlen(options[i].option_name)) == 0) {
529 if (value)
530 *options[i].option_flag =
531 simple_strtoul(value, NULL, 0);
532 else
533 *options[i].option_flag =
534 options[i].option_value;
535 break;
536 }
537 }
538 }
539
540 return (1);
541 }
542
543 __setup("ips=", ips_setup);
544
545 /****************************************************************************/
546 /* */
547 /* Routine Name: ips_detect */
548 /* */
549 /* Routine Description: */
550 /* */
551 /* Detect and initialize the driver */
552 /* */
553 /* NOTE: this routine is called under the io_request_lock spinlock */
554 /* */
555 /****************************************************************************/
556 static int
ips_detect(struct scsi_host_template * SHT)557 ips_detect(struct scsi_host_template * SHT)
558 {
559 int i;
560
561 METHOD_TRACE("ips_detect", 1);
562
563 #ifdef MODULE
564 if (ips)
565 ips_setup(ips);
566 #endif
567
568 for (i = 0; i < ips_num_controllers; i++) {
569 if (ips_register_scsi(i))
570 ips_free(ips_ha[i]);
571 ips_released_controllers++;
572 }
573 ips_hotplug = 1;
574 return (ips_num_controllers);
575 }
576
577 /****************************************************************************/
578 /* configure the function pointers to use the functions that will work */
579 /* with the found version of the adapter */
580 /****************************************************************************/
581 static void
ips_setup_funclist(ips_ha_t * ha)582 ips_setup_funclist(ips_ha_t * ha)
583 {
584
585 /*
586 * Setup Functions
587 */
588 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
589 /* morpheus / marco / sebring */
590 ha->func.isintr = ips_isintr_morpheus;
591 ha->func.isinit = ips_isinit_morpheus;
592 ha->func.issue = ips_issue_i2o_memio;
593 ha->func.init = ips_init_morpheus;
594 ha->func.statupd = ips_statupd_morpheus;
595 ha->func.reset = ips_reset_morpheus;
596 ha->func.intr = ips_intr_morpheus;
597 ha->func.enableint = ips_enable_int_morpheus;
598 } else if (IPS_USE_MEMIO(ha)) {
599 /* copperhead w/MEMIO */
600 ha->func.isintr = ips_isintr_copperhead_memio;
601 ha->func.isinit = ips_isinit_copperhead_memio;
602 ha->func.init = ips_init_copperhead_memio;
603 ha->func.statupd = ips_statupd_copperhead_memio;
604 ha->func.statinit = ips_statinit_memio;
605 ha->func.reset = ips_reset_copperhead_memio;
606 ha->func.intr = ips_intr_copperhead;
607 ha->func.erasebios = ips_erase_bios_memio;
608 ha->func.programbios = ips_program_bios_memio;
609 ha->func.verifybios = ips_verify_bios_memio;
610 ha->func.enableint = ips_enable_int_copperhead_memio;
611 if (IPS_USE_I2O_DELIVER(ha))
612 ha->func.issue = ips_issue_i2o_memio;
613 else
614 ha->func.issue = ips_issue_copperhead_memio;
615 } else {
616 /* copperhead */
617 ha->func.isintr = ips_isintr_copperhead;
618 ha->func.isinit = ips_isinit_copperhead;
619 ha->func.init = ips_init_copperhead;
620 ha->func.statupd = ips_statupd_copperhead;
621 ha->func.statinit = ips_statinit;
622 ha->func.reset = ips_reset_copperhead;
623 ha->func.intr = ips_intr_copperhead;
624 ha->func.erasebios = ips_erase_bios;
625 ha->func.programbios = ips_program_bios;
626 ha->func.verifybios = ips_verify_bios;
627 ha->func.enableint = ips_enable_int_copperhead;
628
629 if (IPS_USE_I2O_DELIVER(ha))
630 ha->func.issue = ips_issue_i2o;
631 else
632 ha->func.issue = ips_issue_copperhead;
633 }
634 }
635
636 /****************************************************************************/
637 /* */
638 /* Routine Name: ips_release */
639 /* */
640 /* Routine Description: */
641 /* */
642 /* Remove a driver */
643 /* */
644 /****************************************************************************/
ips_release(struct Scsi_Host * sh)645 static void ips_release(struct Scsi_Host *sh)
646 {
647 ips_scb_t *scb;
648 ips_ha_t *ha;
649 int i;
650
651 METHOD_TRACE("ips_release", 1);
652
653 scsi_remove_host(sh);
654
655 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
656
657 if (i == IPS_MAX_ADAPTERS) {
658 printk(KERN_WARNING
659 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
660 BUG();
661 }
662
663 ha = IPS_HA(sh);
664
665 if (!ha)
666 return;
667
668 /* flush the cache on the controller */
669 scb = &ha->scbs[ha->max_cmds - 1];
670
671 ips_init_scb(ha, scb);
672
673 scb->timeout = ips_cmd_timeout;
674 scb->cdb[0] = IPS_CMD_FLUSH;
675
676 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
677 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
678 scb->cmd.flush_cache.state = IPS_NORM_STATE;
679 scb->cmd.flush_cache.reserved = 0;
680 scb->cmd.flush_cache.reserved2 = 0;
681 scb->cmd.flush_cache.reserved3 = 0;
682 scb->cmd.flush_cache.reserved4 = 0;
683
684 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
685
686 /* send command */
687 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
688 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
689
690 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
691
692 ips_sh[i] = NULL;
693 ips_ha[i] = NULL;
694
695 /* free extra memory */
696 ips_free(ha);
697
698 /* free IRQ */
699 free_irq(ha->pcidev->irq, ha);
700
701 scsi_host_put(sh);
702
703 ips_released_controllers++;
704 }
705
706 /****************************************************************************/
707 /* */
708 /* Routine Name: ips_halt */
709 /* */
710 /* Routine Description: */
711 /* */
712 /* Perform cleanup when the system reboots */
713 /* */
714 /****************************************************************************/
715 static int
ips_halt(struct notifier_block * nb,ulong event,void * buf)716 ips_halt(struct notifier_block *nb, ulong event, void *buf)
717 {
718 ips_scb_t *scb;
719 ips_ha_t *ha;
720 int i;
721
722 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
723 (event != SYS_POWER_OFF))
724 return (NOTIFY_DONE);
725
726 for (i = 0; i < ips_next_controller; i++) {
727 ha = (ips_ha_t *) ips_ha[i];
728
729 if (!ha)
730 continue;
731
732 if (!ha->active)
733 continue;
734
735 /* flush the cache on the controller */
736 scb = &ha->scbs[ha->max_cmds - 1];
737
738 ips_init_scb(ha, scb);
739
740 scb->timeout = ips_cmd_timeout;
741 scb->cdb[0] = IPS_CMD_FLUSH;
742
743 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
744 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
745 scb->cmd.flush_cache.state = IPS_NORM_STATE;
746 scb->cmd.flush_cache.reserved = 0;
747 scb->cmd.flush_cache.reserved2 = 0;
748 scb->cmd.flush_cache.reserved3 = 0;
749 scb->cmd.flush_cache.reserved4 = 0;
750
751 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
752
753 /* send command */
754 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
755 IPS_FAILURE)
756 IPS_PRINTK(KERN_WARNING, ha->pcidev,
757 "Incomplete Flush.\n");
758 else
759 IPS_PRINTK(KERN_WARNING, ha->pcidev,
760 "Flushing Complete.\n");
761 }
762
763 return (NOTIFY_OK);
764 }
765
766 /****************************************************************************/
767 /* */
768 /* Routine Name: ips_eh_abort */
769 /* */
770 /* Routine Description: */
771 /* */
772 /* Abort a command (using the new error code stuff) */
773 /* Note: this routine is called under the io_request_lock */
774 /****************************************************************************/
ips_eh_abort(struct scsi_cmnd * SC)775 int ips_eh_abort(struct scsi_cmnd *SC)
776 {
777 ips_ha_t *ha;
778 ips_copp_wait_item_t *item;
779 int ret;
780 struct Scsi_Host *host;
781
782 METHOD_TRACE("ips_eh_abort", 1);
783
784 if (!SC)
785 return (FAILED);
786
787 host = SC->device->host;
788 ha = (ips_ha_t *) SC->device->host->hostdata;
789
790 if (!ha)
791 return (FAILED);
792
793 if (!ha->active)
794 return (FAILED);
795
796 spin_lock(host->host_lock);
797
798 /* See if the command is on the copp queue */
799 item = ha->copp_waitlist.head;
800 while ((item) && (item->scsi_cmd != SC))
801 item = item->next;
802
803 if (item) {
804 /* Found it */
805 ips_removeq_copp(&ha->copp_waitlist, item);
806 ret = (SUCCESS);
807
808 /* See if the command is on the wait queue */
809 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
810 /* command not sent yet */
811 ret = (SUCCESS);
812 } else {
813 /* command must have already been sent */
814 ret = (FAILED);
815 }
816
817 spin_unlock(host->host_lock);
818 return ret;
819 }
820
821 /****************************************************************************/
822 /* */
823 /* Routine Name: ips_eh_reset */
824 /* */
825 /* Routine Description: */
826 /* */
827 /* Reset the controller (with new eh error code) */
828 /* */
829 /* NOTE: this routine is called under the io_request_lock spinlock */
830 /* */
831 /****************************************************************************/
__ips_eh_reset(struct scsi_cmnd * SC)832 static int __ips_eh_reset(struct scsi_cmnd *SC)
833 {
834 int ret;
835 int i;
836 ips_ha_t *ha;
837 ips_scb_t *scb;
838 ips_copp_wait_item_t *item;
839
840 METHOD_TRACE("ips_eh_reset", 1);
841
842 #ifdef NO_IPS_RESET
843 return (FAILED);
844 #else
845
846 if (!SC) {
847 DEBUG(1, "Reset called with NULL scsi command");
848
849 return (FAILED);
850 }
851
852 ha = (ips_ha_t *) SC->device->host->hostdata;
853
854 if (!ha) {
855 DEBUG(1, "Reset called with NULL ha struct");
856
857 return (FAILED);
858 }
859
860 if (!ha->active)
861 return (FAILED);
862
863 /* See if the command is on the copp queue */
864 item = ha->copp_waitlist.head;
865 while ((item) && (item->scsi_cmd != SC))
866 item = item->next;
867
868 if (item) {
869 /* Found it */
870 ips_removeq_copp(&ha->copp_waitlist, item);
871 return (SUCCESS);
872 }
873
874 /* See if the command is on the wait queue */
875 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
876 /* command not sent yet */
877 return (SUCCESS);
878 }
879
880 /* An explanation for the casual observer: */
881 /* Part of the function of a RAID controller is automatic error */
882 /* detection and recovery. As such, the only problem that physically */
883 /* resetting an adapter will ever fix is when, for some reason, */
884 /* the driver is not successfully communicating with the adapter. */
885 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
886 /* then there's no real purpose in a physical reset. This will complete */
887 /* much faster and avoids any problems that might be caused by a */
888 /* physical reset ( such as having to fail all the outstanding I/O's ). */
889
890 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
891 scb = &ha->scbs[ha->max_cmds - 1];
892
893 ips_init_scb(ha, scb);
894
895 scb->timeout = ips_cmd_timeout;
896 scb->cdb[0] = IPS_CMD_FLUSH;
897
898 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
899 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
900 scb->cmd.flush_cache.state = IPS_NORM_STATE;
901 scb->cmd.flush_cache.reserved = 0;
902 scb->cmd.flush_cache.reserved2 = 0;
903 scb->cmd.flush_cache.reserved3 = 0;
904 scb->cmd.flush_cache.reserved4 = 0;
905
906 /* Attempt the flush command */
907 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
908 if (ret == IPS_SUCCESS) {
909 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
910 "Reset Request - Flushed Cache\n");
911 return (SUCCESS);
912 }
913 }
914
915 /* Either we can't communicate with the adapter or it's an IOCTL request */
916 /* from a utility. A physical reset is needed at this point. */
917
918 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
919
920 /*
921 * command must have already been sent
922 * reset the controller
923 */
924 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
925 ret = (*ha->func.reset) (ha);
926
927 if (!ret) {
928 struct scsi_cmnd *scsi_cmd;
929
930 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
931 "Controller reset failed - controller now offline.\n");
932
933 /* Now fail all of the active commands */
934 DEBUG_VAR(1, "(%s%d) Failing active commands",
935 ips_name, ha->host_num);
936
937 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
938 scb->scsi_cmd->result = DID_ERROR << 16;
939 scsi_done(scb->scsi_cmd);
940 ips_freescb(ha, scb);
941 }
942
943 /* Now fail all of the pending commands */
944 DEBUG_VAR(1, "(%s%d) Failing pending commands",
945 ips_name, ha->host_num);
946
947 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
948 scsi_cmd->result = DID_ERROR;
949 scsi_done(scsi_cmd);
950 }
951
952 ha->active = false;
953 return (FAILED);
954 }
955
956 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
957 struct scsi_cmnd *scsi_cmd;
958
959 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
960 "Controller reset failed - controller now offline.\n");
961
962 /* Now fail all of the active commands */
963 DEBUG_VAR(1, "(%s%d) Failing active commands",
964 ips_name, ha->host_num);
965
966 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
967 scb->scsi_cmd->result = DID_ERROR << 16;
968 scsi_done(scb->scsi_cmd);
969 ips_freescb(ha, scb);
970 }
971
972 /* Now fail all of the pending commands */
973 DEBUG_VAR(1, "(%s%d) Failing pending commands",
974 ips_name, ha->host_num);
975
976 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
977 scsi_cmd->result = DID_ERROR << 16;
978 scsi_done(scsi_cmd);
979 }
980
981 ha->active = false;
982 return (FAILED);
983 }
984
985 /* FFDC */
986 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
987 ha->last_ffdc = ktime_get_real_seconds();
988 ha->reset_count++;
989 ips_ffdc_reset(ha, IPS_INTR_IORL);
990 }
991
992 /* Now fail all of the active commands */
993 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
994
995 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
996 scb->scsi_cmd->result = DID_RESET << 16;
997 scsi_done(scb->scsi_cmd);
998 ips_freescb(ha, scb);
999 }
1000
1001 /* Reset DCDB active command bits */
1002 for (i = 1; i < ha->nbus; i++)
1003 ha->dcdb_active[i - 1] = 0;
1004
1005 /* Reset the number of active IOCTLs */
1006 ha->num_ioctl = 0;
1007
1008 ips_next(ha, IPS_INTR_IORL);
1009
1010 return (SUCCESS);
1011 #endif /* NO_IPS_RESET */
1012
1013 }
1014
ips_eh_reset(struct scsi_cmnd * SC)1015 static int ips_eh_reset(struct scsi_cmnd *SC)
1016 {
1017 int rc;
1018
1019 spin_lock_irq(SC->device->host->host_lock);
1020 rc = __ips_eh_reset(SC);
1021 spin_unlock_irq(SC->device->host->host_lock);
1022
1023 return rc;
1024 }
1025
1026 /****************************************************************************/
1027 /* */
1028 /* Routine Name: ips_queue */
1029 /* */
1030 /* Routine Description: */
1031 /* */
1032 /* Send a command to the controller */
1033 /* */
1034 /* NOTE: */
1035 /* Linux obtains io_request_lock before calling this function */
1036 /* */
1037 /****************************************************************************/
ips_queue_lck(struct scsi_cmnd * SC)1038 static int ips_queue_lck(struct scsi_cmnd *SC)
1039 {
1040 void (*done)(struct scsi_cmnd *) = scsi_done;
1041 ips_ha_t *ha;
1042 ips_passthru_t *pt;
1043
1044 METHOD_TRACE("ips_queue", 1);
1045
1046 ha = (ips_ha_t *) SC->device->host->hostdata;
1047
1048 if (!ha)
1049 goto out_error;
1050
1051 if (!ha->active)
1052 goto out_error;
1053
1054 if (ips_is_passthru(SC)) {
1055 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1056 SC->result = DID_BUS_BUSY << 16;
1057 done(SC);
1058
1059 return (0);
1060 }
1061 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1062 SC->result = DID_BUS_BUSY << 16;
1063 done(SC);
1064
1065 return (0);
1066 }
1067
1068 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1069 ips_name,
1070 ha->host_num,
1071 SC->cmnd[0],
1072 SC->device->channel, SC->device->id, SC->device->lun);
1073
1074 /* Check for command to initiator IDs */
1075 if ((scmd_channel(SC) > 0)
1076 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1077 SC->result = DID_NO_CONNECT << 16;
1078 done(SC);
1079
1080 return (0);
1081 }
1082
1083 if (ips_is_passthru(SC)) {
1084
1085 ips_copp_wait_item_t *scratch;
1086
1087 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1088 /* There can never be any system activity ( network or disk ), but check */
1089 /* anyway just as a good practice. */
1090 pt = (ips_passthru_t *) scsi_sglist(SC);
1091 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1092 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1093 if (ha->scb_activelist.count != 0) {
1094 SC->result = DID_BUS_BUSY << 16;
1095 done(SC);
1096 return (0);
1097 }
1098 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1099 __ips_eh_reset(SC);
1100 SC->result = DID_OK << 16;
1101 scsi_done(SC);
1102 return (0);
1103 }
1104
1105 /* allocate space for the scribble */
1106 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1107
1108 if (!scratch) {
1109 SC->result = DID_ERROR << 16;
1110 done(SC);
1111
1112 return (0);
1113 }
1114
1115 scratch->scsi_cmd = SC;
1116 scratch->next = NULL;
1117
1118 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1119 } else {
1120 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1121 }
1122
1123 ips_next(ha, IPS_INTR_IORL);
1124
1125 return (0);
1126 out_error:
1127 SC->result = DID_ERROR << 16;
1128 done(SC);
1129
1130 return (0);
1131 }
1132
DEF_SCSI_QCMD(ips_queue)1133 static DEF_SCSI_QCMD(ips_queue)
1134
1135 /****************************************************************************/
1136 /* */
1137 /* Routine Name: ips_biosparam */
1138 /* */
1139 /* Routine Description: */
1140 /* */
1141 /* Set bios geometry for the controller */
1142 /* */
1143 /****************************************************************************/
1144 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1145 sector_t capacity, int geom[])
1146 {
1147 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1148 int heads;
1149 int sectors;
1150 int cylinders;
1151
1152 METHOD_TRACE("ips_biosparam", 1);
1153
1154 if (!ha)
1155 /* ?!?! host adater info invalid */
1156 return (0);
1157
1158 if (!ha->active)
1159 return (0);
1160
1161 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1162 /* ?!?! Enquiry command failed */
1163 return (0);
1164
1165 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1166 heads = IPS_NORM_HEADS;
1167 sectors = IPS_NORM_SECTORS;
1168 } else {
1169 heads = IPS_COMP_HEADS;
1170 sectors = IPS_COMP_SECTORS;
1171 }
1172
1173 cylinders = (unsigned long) capacity / (heads * sectors);
1174
1175 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1176 heads, sectors, cylinders);
1177
1178 geom[0] = heads;
1179 geom[1] = sectors;
1180 geom[2] = cylinders;
1181
1182 return (0);
1183 }
1184
1185 /****************************************************************************/
1186 /* */
1187 /* Routine Name: ips_slave_configure */
1188 /* */
1189 /* Routine Description: */
1190 /* */
1191 /* Set queue depths on devices once scan is complete */
1192 /* */
1193 /****************************************************************************/
1194 static int
ips_slave_configure(struct scsi_device * SDptr)1195 ips_slave_configure(struct scsi_device * SDptr)
1196 {
1197 ips_ha_t *ha;
1198 int min;
1199
1200 ha = IPS_HA(SDptr->host);
1201 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1202 min = ha->max_cmds / 2;
1203 if (ha->enq->ucLogDriveCount <= 2)
1204 min = ha->max_cmds - 1;
1205 scsi_change_queue_depth(SDptr, min);
1206 }
1207
1208 SDptr->skip_ms_page_8 = 1;
1209 SDptr->skip_ms_page_3f = 1;
1210 return 0;
1211 }
1212
1213 /****************************************************************************/
1214 /* */
1215 /* Routine Name: do_ipsintr */
1216 /* */
1217 /* Routine Description: */
1218 /* */
1219 /* Wrapper for the interrupt handler */
1220 /* */
1221 /****************************************************************************/
1222 static irqreturn_t
do_ipsintr(int irq,void * dev_id)1223 do_ipsintr(int irq, void *dev_id)
1224 {
1225 ips_ha_t *ha;
1226 struct Scsi_Host *host;
1227 int irqstatus;
1228
1229 METHOD_TRACE("do_ipsintr", 2);
1230
1231 ha = (ips_ha_t *) dev_id;
1232 if (!ha)
1233 return IRQ_NONE;
1234 host = ips_sh[ha->host_num];
1235 /* interrupt during initialization */
1236 if (!host) {
1237 (*ha->func.intr) (ha);
1238 return IRQ_HANDLED;
1239 }
1240
1241 spin_lock(host->host_lock);
1242
1243 if (!ha->active) {
1244 spin_unlock(host->host_lock);
1245 return IRQ_HANDLED;
1246 }
1247
1248 irqstatus = (*ha->func.intr) (ha);
1249
1250 spin_unlock(host->host_lock);
1251
1252 /* start the next command */
1253 ips_next(ha, IPS_INTR_ON);
1254 return IRQ_RETVAL(irqstatus);
1255 }
1256
1257 /****************************************************************************/
1258 /* */
1259 /* Routine Name: ips_intr_copperhead */
1260 /* */
1261 /* Routine Description: */
1262 /* */
1263 /* Polling interrupt handler */
1264 /* */
1265 /* ASSUMES interrupts are disabled */
1266 /* */
1267 /****************************************************************************/
1268 int
ips_intr_copperhead(ips_ha_t * ha)1269 ips_intr_copperhead(ips_ha_t * ha)
1270 {
1271 ips_stat_t *sp;
1272 ips_scb_t *scb;
1273 IPS_STATUS cstatus;
1274 int intrstatus;
1275
1276 METHOD_TRACE("ips_intr", 2);
1277
1278 if (!ha)
1279 return 0;
1280
1281 if (!ha->active)
1282 return 0;
1283
1284 intrstatus = (*ha->func.isintr) (ha);
1285
1286 if (!intrstatus) {
1287 /*
1288 * Unexpected/Shared interrupt
1289 */
1290
1291 return 0;
1292 }
1293
1294 while (true) {
1295 sp = &ha->sp;
1296
1297 intrstatus = (*ha->func.isintr) (ha);
1298
1299 if (!intrstatus)
1300 break;
1301 else
1302 cstatus.value = (*ha->func.statupd) (ha);
1303
1304 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1305 /* Spurious Interrupt ? */
1306 continue;
1307 }
1308
1309 ips_chkstatus(ha, &cstatus);
1310 scb = (ips_scb_t *) sp->scb_addr;
1311
1312 /*
1313 * use the callback function to finish things up
1314 * NOTE: interrupts are OFF for this
1315 */
1316 (*scb->callback) (ha, scb);
1317 } /* end while */
1318 return 1;
1319 }
1320
1321 /****************************************************************************/
1322 /* */
1323 /* Routine Name: ips_intr_morpheus */
1324 /* */
1325 /* Routine Description: */
1326 /* */
1327 /* Polling interrupt handler */
1328 /* */
1329 /* ASSUMES interrupts are disabled */
1330 /* */
1331 /****************************************************************************/
1332 int
ips_intr_morpheus(ips_ha_t * ha)1333 ips_intr_morpheus(ips_ha_t * ha)
1334 {
1335 ips_stat_t *sp;
1336 ips_scb_t *scb;
1337 IPS_STATUS cstatus;
1338 int intrstatus;
1339
1340 METHOD_TRACE("ips_intr_morpheus", 2);
1341
1342 if (!ha)
1343 return 0;
1344
1345 if (!ha->active)
1346 return 0;
1347
1348 intrstatus = (*ha->func.isintr) (ha);
1349
1350 if (!intrstatus) {
1351 /*
1352 * Unexpected/Shared interrupt
1353 */
1354
1355 return 0;
1356 }
1357
1358 while (true) {
1359 sp = &ha->sp;
1360
1361 intrstatus = (*ha->func.isintr) (ha);
1362
1363 if (!intrstatus)
1364 break;
1365 else
1366 cstatus.value = (*ha->func.statupd) (ha);
1367
1368 if (cstatus.value == 0xffffffff)
1369 /* No more to process */
1370 break;
1371
1372 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1373 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1374 "Spurious interrupt; no ccb.\n");
1375
1376 continue;
1377 }
1378
1379 ips_chkstatus(ha, &cstatus);
1380 scb = (ips_scb_t *) sp->scb_addr;
1381
1382 /*
1383 * use the callback function to finish things up
1384 * NOTE: interrupts are OFF for this
1385 */
1386 (*scb->callback) (ha, scb);
1387 } /* end while */
1388 return 1;
1389 }
1390
1391 /****************************************************************************/
1392 /* */
1393 /* Routine Name: ips_info */
1394 /* */
1395 /* Routine Description: */
1396 /* */
1397 /* Return info about the driver */
1398 /* */
1399 /****************************************************************************/
1400 static const char *
ips_info(struct Scsi_Host * SH)1401 ips_info(struct Scsi_Host *SH)
1402 {
1403 static char buffer[256];
1404 char *bp;
1405 ips_ha_t *ha;
1406
1407 METHOD_TRACE("ips_info", 1);
1408
1409 ha = IPS_HA(SH);
1410
1411 if (!ha)
1412 return (NULL);
1413
1414 bp = &buffer[0];
1415 memset(bp, 0, sizeof (buffer));
1416
1417 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1418 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1419
1420 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1421 strcat(bp, " <");
1422 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1423 strcat(bp, ">");
1424 }
1425
1426 return (bp);
1427 }
1428
1429 static int
ips_write_info(struct Scsi_Host * host,char * buffer,int length)1430 ips_write_info(struct Scsi_Host *host, char *buffer, int length)
1431 {
1432 int i;
1433 ips_ha_t *ha = NULL;
1434
1435 /* Find our host structure */
1436 for (i = 0; i < ips_next_controller; i++) {
1437 if (ips_sh[i]) {
1438 if (ips_sh[i] == host) {
1439 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1440 break;
1441 }
1442 }
1443 }
1444
1445 if (!ha)
1446 return (-EINVAL);
1447
1448 return 0;
1449 }
1450
1451 static int
ips_show_info(struct seq_file * m,struct Scsi_Host * host)1452 ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1453 {
1454 int i;
1455 ips_ha_t *ha = NULL;
1456
1457 /* Find our host structure */
1458 for (i = 0; i < ips_next_controller; i++) {
1459 if (ips_sh[i]) {
1460 if (ips_sh[i] == host) {
1461 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1462 break;
1463 }
1464 }
1465 }
1466
1467 if (!ha)
1468 return (-EINVAL);
1469
1470 return ips_host_info(ha, m);
1471 }
1472
1473 /*--------------------------------------------------------------------------*/
1474 /* Helper Functions */
1475 /*--------------------------------------------------------------------------*/
1476
1477 /****************************************************************************/
1478 /* */
1479 /* Routine Name: ips_is_passthru */
1480 /* */
1481 /* Routine Description: */
1482 /* */
1483 /* Determine if the specified SCSI command is really a passthru command */
1484 /* */
1485 /****************************************************************************/
ips_is_passthru(struct scsi_cmnd * SC)1486 static int ips_is_passthru(struct scsi_cmnd *SC)
1487 {
1488 unsigned long flags;
1489
1490 METHOD_TRACE("ips_is_passthru", 1);
1491
1492 if (!SC)
1493 return (0);
1494
1495 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1496 (SC->device->channel == 0) &&
1497 (SC->device->id == IPS_ADAPTER_ID) &&
1498 (SC->device->lun == 0) && scsi_sglist(SC)) {
1499 struct scatterlist *sg = scsi_sglist(SC);
1500 char *buffer;
1501
1502 /* local_irq_save() protects the KM_IRQ0 address slot. */
1503 local_irq_save(flags);
1504 buffer = kmap_local_page(sg_page(sg)) + sg->offset;
1505 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1506 buffer[2] == 'P' && buffer[3] == 'P') {
1507 kunmap_local(buffer);
1508 local_irq_restore(flags);
1509 return 1;
1510 }
1511 kunmap_local(buffer);
1512 local_irq_restore(flags);
1513 }
1514 return 0;
1515 }
1516
1517 /****************************************************************************/
1518 /* */
1519 /* Routine Name: ips_alloc_passthru_buffer */
1520 /* */
1521 /* Routine Description: */
1522 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1523 /* is too small or doesn't exist */
1524 /****************************************************************************/
1525 static int
ips_alloc_passthru_buffer(ips_ha_t * ha,int length)1526 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1527 {
1528 void *bigger_buf;
1529 dma_addr_t dma_busaddr;
1530
1531 if (ha->ioctl_data && length <= ha->ioctl_len)
1532 return 0;
1533 /* there is no buffer or it's not big enough, allocate a new one */
1534 bigger_buf = dma_alloc_coherent(&ha->pcidev->dev, length, &dma_busaddr,
1535 GFP_KERNEL);
1536 if (bigger_buf) {
1537 /* free the old memory */
1538 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
1539 ha->ioctl_data, ha->ioctl_busaddr);
1540 /* use the new memory */
1541 ha->ioctl_data = (char *) bigger_buf;
1542 ha->ioctl_len = length;
1543 ha->ioctl_busaddr = dma_busaddr;
1544 } else {
1545 return -1;
1546 }
1547 return 0;
1548 }
1549
1550 /****************************************************************************/
1551 /* */
1552 /* Routine Name: ips_make_passthru */
1553 /* */
1554 /* Routine Description: */
1555 /* */
1556 /* Make a passthru command out of the info in the Scsi block */
1557 /* */
1558 /****************************************************************************/
1559 static int
ips_make_passthru(ips_ha_t * ha,struct scsi_cmnd * SC,ips_scb_t * scb,int intr)1560 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1561 {
1562 ips_passthru_t *pt;
1563 int length = 0;
1564 int i, ret;
1565 struct scatterlist *sg = scsi_sglist(SC);
1566
1567 METHOD_TRACE("ips_make_passthru", 1);
1568
1569 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1570 length += sg->length;
1571
1572 if (length < sizeof (ips_passthru_t)) {
1573 /* wrong size */
1574 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1575 ips_name, ha->host_num);
1576 return (IPS_FAILURE);
1577 }
1578 if (ips_alloc_passthru_buffer(ha, length)) {
1579 /* allocation failure! If ha->ioctl_data exists, use it to return
1580 some error codes. Return a failed command to the scsi layer. */
1581 if (ha->ioctl_data) {
1582 pt = (ips_passthru_t *) ha->ioctl_data;
1583 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1584 pt->BasicStatus = 0x0B;
1585 pt->ExtendedStatus = 0x00;
1586 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1587 }
1588 return IPS_FAILURE;
1589 }
1590 ha->ioctl_datasize = length;
1591
1592 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1593 pt = (ips_passthru_t *) ha->ioctl_data;
1594
1595 /*
1596 * Some notes about the passthru interface used
1597 *
1598 * IF the scsi op_code == 0x0d then we assume
1599 * that the data came along with/goes with the
1600 * packet we received from the sg driver. In this
1601 * case the CmdBSize field of the pt structure is
1602 * used for the size of the buffer.
1603 */
1604
1605 switch (pt->CoppCmd) {
1606 case IPS_NUMCTRLS:
1607 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1608 &ips_num_controllers, sizeof (int));
1609 ips_scmd_buf_write(SC, ha->ioctl_data,
1610 sizeof (ips_passthru_t) + sizeof (int));
1611 SC->result = DID_OK << 16;
1612
1613 return (IPS_SUCCESS_IMM);
1614
1615 case IPS_COPPUSRCMD:
1616 case IPS_COPPIOCCMD:
1617 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1618 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1619 /* wrong size */
1620 DEBUG_VAR(1,
1621 "(%s%d) Passthru structure wrong size",
1622 ips_name, ha->host_num);
1623
1624 return (IPS_FAILURE);
1625 }
1626
1627 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1628 pt->CoppCP.cmd.flashfw.op_code ==
1629 IPS_CMD_RW_BIOSFW) {
1630 ret = ips_flash_copperhead(ha, pt, scb);
1631 ips_scmd_buf_write(SC, ha->ioctl_data,
1632 sizeof (ips_passthru_t));
1633 return ret;
1634 }
1635 if (ips_usrcmd(ha, pt, scb))
1636 return (IPS_SUCCESS);
1637 else
1638 return (IPS_FAILURE);
1639 }
1640
1641 break;
1642
1643 } /* end switch */
1644
1645 return (IPS_FAILURE);
1646 }
1647
1648 /****************************************************************************/
1649 /* Routine Name: ips_flash_copperhead */
1650 /* Routine Description: */
1651 /* Flash the BIOS/FW on a Copperhead style controller */
1652 /****************************************************************************/
1653 static int
ips_flash_copperhead(ips_ha_t * ha,ips_passthru_t * pt,ips_scb_t * scb)1654 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1655 {
1656 int datasize;
1657
1658 /* Trombone is the only copperhead that can do packet flash, but only
1659 * for firmware. No one said it had to make sense. */
1660 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1661 if (ips_usrcmd(ha, pt, scb))
1662 return IPS_SUCCESS;
1663 else
1664 return IPS_FAILURE;
1665 }
1666 pt->BasicStatus = 0x0B;
1667 pt->ExtendedStatus = 0;
1668 scb->scsi_cmd->result = DID_OK << 16;
1669 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1670 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1671 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1672 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1673 pt->BasicStatus = 0;
1674 return ips_flash_bios(ha, pt, scb);
1675 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1676 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1677 ha->flash_data = ips_FlashData;
1678 ha->flash_busaddr = ips_flashbusaddr;
1679 ha->flash_len = PAGE_SIZE << 7;
1680 ha->flash_datasize = 0;
1681 } else if (!ha->flash_data) {
1682 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1683 pt->CoppCP.cmd.flashfw.count;
1684 ha->flash_data = dma_alloc_coherent(&ha->pcidev->dev,
1685 datasize, &ha->flash_busaddr, GFP_KERNEL);
1686 if (!ha->flash_data){
1687 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1688 return IPS_FAILURE;
1689 }
1690 ha->flash_datasize = 0;
1691 ha->flash_len = datasize;
1692 } else
1693 return IPS_FAILURE;
1694 } else {
1695 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1696 ha->flash_len) {
1697 ips_free_flash_copperhead(ha);
1698 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1699 "failed size sanity check\n");
1700 return IPS_FAILURE;
1701 }
1702 }
1703 if (!ha->flash_data)
1704 return IPS_FAILURE;
1705 pt->BasicStatus = 0;
1706 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1707 pt->CoppCP.cmd.flashfw.count);
1708 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1709 if (pt->CoppCP.cmd.flashfw.packet_num ==
1710 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1711 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1712 return ips_flash_bios(ha, pt, scb);
1713 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1714 return ips_flash_firmware(ha, pt, scb);
1715 }
1716 return IPS_SUCCESS_IMM;
1717 }
1718
1719 /****************************************************************************/
1720 /* Routine Name: ips_flash_bios */
1721 /* Routine Description: */
1722 /* flashes the bios of a copperhead adapter */
1723 /****************************************************************************/
1724 static int
ips_flash_bios(ips_ha_t * ha,ips_passthru_t * pt,ips_scb_t * scb)1725 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1726 {
1727
1728 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1729 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1730 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1731 (!ha->func.verifybios))
1732 goto error;
1733 if ((*ha->func.erasebios) (ha)) {
1734 DEBUG_VAR(1,
1735 "(%s%d) flash bios failed - unable to erase flash",
1736 ips_name, ha->host_num);
1737 goto error;
1738 } else
1739 if ((*ha->func.programbios) (ha,
1740 ha->flash_data +
1741 IPS_BIOS_HEADER,
1742 ha->flash_datasize -
1743 IPS_BIOS_HEADER, 0)) {
1744 DEBUG_VAR(1,
1745 "(%s%d) flash bios failed - unable to flash",
1746 ips_name, ha->host_num);
1747 goto error;
1748 } else
1749 if ((*ha->func.verifybios) (ha,
1750 ha->flash_data +
1751 IPS_BIOS_HEADER,
1752 ha->flash_datasize -
1753 IPS_BIOS_HEADER, 0)) {
1754 DEBUG_VAR(1,
1755 "(%s%d) flash bios failed - unable to verify flash",
1756 ips_name, ha->host_num);
1757 goto error;
1758 }
1759 ips_free_flash_copperhead(ha);
1760 return IPS_SUCCESS_IMM;
1761 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1762 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1763 if (!ha->func.erasebios)
1764 goto error;
1765 if ((*ha->func.erasebios) (ha)) {
1766 DEBUG_VAR(1,
1767 "(%s%d) flash bios failed - unable to erase flash",
1768 ips_name, ha->host_num);
1769 goto error;
1770 }
1771 return IPS_SUCCESS_IMM;
1772 }
1773 error:
1774 pt->BasicStatus = 0x0B;
1775 pt->ExtendedStatus = 0x00;
1776 ips_free_flash_copperhead(ha);
1777 return IPS_FAILURE;
1778 }
1779
1780 /****************************************************************************/
1781 /* */
1782 /* Routine Name: ips_fill_scb_sg_single */
1783 /* */
1784 /* Routine Description: */
1785 /* Fill in a single scb sg_list element from an address */
1786 /* return a -1 if a breakup occurred */
1787 /****************************************************************************/
1788 static int
ips_fill_scb_sg_single(ips_ha_t * ha,dma_addr_t busaddr,ips_scb_t * scb,int indx,unsigned int e_len)1789 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1790 ips_scb_t * scb, int indx, unsigned int e_len)
1791 {
1792
1793 int ret_val = 0;
1794
1795 if ((scb->data_len + e_len) > ha->max_xfer) {
1796 e_len = ha->max_xfer - scb->data_len;
1797 scb->breakup = indx;
1798 ++scb->sg_break;
1799 ret_val = -1;
1800 } else {
1801 scb->breakup = 0;
1802 scb->sg_break = 0;
1803 }
1804 if (IPS_USE_ENH_SGLIST(ha)) {
1805 scb->sg_list.enh_list[indx].address_lo =
1806 cpu_to_le32(lower_32_bits(busaddr));
1807 scb->sg_list.enh_list[indx].address_hi =
1808 cpu_to_le32(upper_32_bits(busaddr));
1809 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1810 } else {
1811 scb->sg_list.std_list[indx].address =
1812 cpu_to_le32(lower_32_bits(busaddr));
1813 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1814 }
1815
1816 ++scb->sg_len;
1817 scb->data_len += e_len;
1818 return ret_val;
1819 }
1820
1821 /****************************************************************************/
1822 /* Routine Name: ips_flash_firmware */
1823 /* Routine Description: */
1824 /* flashes the firmware of a copperhead adapter */
1825 /****************************************************************************/
1826 static int
ips_flash_firmware(ips_ha_t * ha,ips_passthru_t * pt,ips_scb_t * scb)1827 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1828 {
1829 IPS_SG_LIST sg_list;
1830 uint32_t cmd_busaddr;
1831
1832 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1833 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1834 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1835 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1836 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1837 } else {
1838 pt->BasicStatus = 0x0B;
1839 pt->ExtendedStatus = 0x00;
1840 ips_free_flash_copperhead(ha);
1841 return IPS_FAILURE;
1842 }
1843 /* Save the S/G list pointer so it doesn't get clobbered */
1844 sg_list.list = scb->sg_list.list;
1845 cmd_busaddr = scb->scb_busaddr;
1846 /* copy in the CP */
1847 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1848 /* FIX stuff that might be wrong */
1849 scb->sg_list.list = sg_list.list;
1850 scb->scb_busaddr = cmd_busaddr;
1851 scb->bus = scb->scsi_cmd->device->channel;
1852 scb->target_id = scb->scsi_cmd->device->id;
1853 scb->lun = scb->scsi_cmd->device->lun;
1854 scb->sg_len = 0;
1855 scb->data_len = 0;
1856 scb->flags = 0;
1857 scb->op_code = 0;
1858 scb->callback = ipsintr_done;
1859 scb->timeout = ips_cmd_timeout;
1860
1861 scb->data_len = ha->flash_datasize;
1862 scb->data_busaddr =
1863 dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len,
1864 IPS_DMA_DIR(scb));
1865 scb->flags |= IPS_SCB_MAP_SINGLE;
1866 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1867 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1868 if (pt->TimeOut)
1869 scb->timeout = pt->TimeOut;
1870 scb->scsi_cmd->result = DID_OK << 16;
1871 return IPS_SUCCESS;
1872 }
1873
1874 /****************************************************************************/
1875 /* Routine Name: ips_free_flash_copperhead */
1876 /* Routine Description: */
1877 /* release the memory resources used to hold the flash image */
1878 /****************************************************************************/
1879 static void
ips_free_flash_copperhead(ips_ha_t * ha)1880 ips_free_flash_copperhead(ips_ha_t * ha)
1881 {
1882 if (ha->flash_data == ips_FlashData)
1883 test_and_clear_bit(0, &ips_FlashDataInUse);
1884 else if (ha->flash_data)
1885 dma_free_coherent(&ha->pcidev->dev, ha->flash_len,
1886 ha->flash_data, ha->flash_busaddr);
1887 ha->flash_data = NULL;
1888 }
1889
1890 /****************************************************************************/
1891 /* */
1892 /* Routine Name: ips_usrcmd */
1893 /* */
1894 /* Routine Description: */
1895 /* */
1896 /* Process a user command and make it ready to send */
1897 /* */
1898 /****************************************************************************/
1899 static int
ips_usrcmd(ips_ha_t * ha,ips_passthru_t * pt,ips_scb_t * scb)1900 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1901 {
1902 IPS_SG_LIST sg_list;
1903 uint32_t cmd_busaddr;
1904
1905 METHOD_TRACE("ips_usrcmd", 1);
1906
1907 if ((!scb) || (!pt) || (!ha))
1908 return (0);
1909
1910 /* Save the S/G list pointer so it doesn't get clobbered */
1911 sg_list.list = scb->sg_list.list;
1912 cmd_busaddr = scb->scb_busaddr;
1913 /* copy in the CP */
1914 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1915 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1916
1917 /* FIX stuff that might be wrong */
1918 scb->sg_list.list = sg_list.list;
1919 scb->scb_busaddr = cmd_busaddr;
1920 scb->bus = scb->scsi_cmd->device->channel;
1921 scb->target_id = scb->scsi_cmd->device->id;
1922 scb->lun = scb->scsi_cmd->device->lun;
1923 scb->sg_len = 0;
1924 scb->data_len = 0;
1925 scb->flags = 0;
1926 scb->op_code = 0;
1927 scb->callback = ipsintr_done;
1928 scb->timeout = ips_cmd_timeout;
1929 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1930
1931 /* we don't support DCDB/READ/WRITE Scatter Gather */
1932 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1933 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1934 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1935 return (0);
1936
1937 if (pt->CmdBSize) {
1938 scb->data_len = pt->CmdBSize;
1939 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1940 } else {
1941 scb->data_busaddr = 0L;
1942 }
1943
1944 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1945 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1946 (unsigned long) &scb->
1947 dcdb -
1948 (unsigned long) scb);
1949
1950 if (pt->CmdBSize) {
1951 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1952 scb->dcdb.buffer_pointer =
1953 cpu_to_le32(scb->data_busaddr);
1954 else
1955 scb->cmd.basic_io.sg_addr =
1956 cpu_to_le32(scb->data_busaddr);
1957 }
1958
1959 /* set timeouts */
1960 if (pt->TimeOut) {
1961 scb->timeout = pt->TimeOut;
1962
1963 if (pt->TimeOut <= 10)
1964 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1965 else if (pt->TimeOut <= 60)
1966 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1967 else
1968 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1969 }
1970
1971 /* assume success */
1972 scb->scsi_cmd->result = DID_OK << 16;
1973
1974 /* success */
1975 return (1);
1976 }
1977
1978 /****************************************************************************/
1979 /* */
1980 /* Routine Name: ips_cleanup_passthru */
1981 /* */
1982 /* Routine Description: */
1983 /* */
1984 /* Cleanup after a passthru command */
1985 /* */
1986 /****************************************************************************/
1987 static void
ips_cleanup_passthru(ips_ha_t * ha,ips_scb_t * scb)1988 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1989 {
1990 ips_passthru_t *pt;
1991
1992 METHOD_TRACE("ips_cleanup_passthru", 1);
1993
1994 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
1995 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
1996 ips_name, ha->host_num);
1997
1998 return;
1999 }
2000 pt = (ips_passthru_t *) ha->ioctl_data;
2001
2002 /* Copy data back to the user */
2003 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2004 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2005
2006 pt->BasicStatus = scb->basic_status;
2007 pt->ExtendedStatus = scb->extended_status;
2008 pt->AdapterType = ha->ad_type;
2009
2010 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2011 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2012 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2013 ips_free_flash_copperhead(ha);
2014
2015 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2016 }
2017
2018 /****************************************************************************/
2019 /* */
2020 /* Routine Name: ips_host_info */
2021 /* */
2022 /* Routine Description: */
2023 /* */
2024 /* The passthru interface for the driver */
2025 /* */
2026 /****************************************************************************/
2027 static int
ips_host_info(ips_ha_t * ha,struct seq_file * m)2028 ips_host_info(ips_ha_t *ha, struct seq_file *m)
2029 {
2030 METHOD_TRACE("ips_host_info", 1);
2031
2032 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
2033
2034 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2035 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2036 seq_printf(m, "\tController Type : %s\n",
2037 ips_adapter_name[ha->ad_type - 1]);
2038 else
2039 seq_puts(m, "\tController Type : Unknown\n");
2040
2041 if (ha->io_addr)
2042 seq_printf(m,
2043 "\tIO region : 0x%x (%d bytes)\n",
2044 ha->io_addr, ha->io_len);
2045
2046 if (ha->mem_addr) {
2047 seq_printf(m,
2048 "\tMemory region : 0x%x (%d bytes)\n",
2049 ha->mem_addr, ha->mem_len);
2050 seq_printf(m,
2051 "\tShared memory address : 0x%lx\n",
2052 (unsigned long)ha->mem_ptr);
2053 }
2054
2055 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2056
2057 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2058 /* That keeps everything happy for "text" operations on the proc file. */
2059
2060 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2061 if (ha->nvram->bios_low[3] == 0) {
2062 seq_printf(m,
2063 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2064 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2065 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2066 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2067 ha->nvram->bios_low[2]);
2068
2069 } else {
2070 seq_printf(m,
2071 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2072 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2073 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2074 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2075 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2076 }
2077
2078 }
2079
2080 if (ha->enq->CodeBlkVersion[7] == 0) {
2081 seq_printf(m,
2082 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2083 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2084 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2085 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2086 ha->enq->CodeBlkVersion[6]);
2087 } else {
2088 seq_printf(m,
2089 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2090 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2091 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2092 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2093 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2094 }
2095
2096 if (ha->enq->BootBlkVersion[7] == 0) {
2097 seq_printf(m,
2098 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2099 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2100 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2101 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2102 ha->enq->BootBlkVersion[6]);
2103 } else {
2104 seq_printf(m,
2105 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2106 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2107 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2108 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2109 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2110 }
2111
2112 seq_printf(m, "\tDriver Version : %s%s\n",
2113 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2114
2115 seq_printf(m, "\tDriver Build : %d\n",
2116 IPS_BUILD_IDENT);
2117
2118 seq_printf(m, "\tMax Physical Devices : %d\n",
2119 ha->enq->ucMaxPhysicalDevices);
2120 seq_printf(m, "\tMax Active Commands : %d\n",
2121 ha->max_cmds);
2122 seq_printf(m, "\tCurrent Queued Commands : %d\n",
2123 ha->scb_waitlist.count);
2124 seq_printf(m, "\tCurrent Active Commands : %d\n",
2125 ha->scb_activelist.count - ha->num_ioctl);
2126 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
2127 ha->copp_waitlist.count);
2128 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
2129 ha->num_ioctl);
2130
2131 seq_putc(m, '\n');
2132
2133 return 0;
2134 }
2135
2136 /****************************************************************************/
2137 /* */
2138 /* Routine Name: ips_identify_controller */
2139 /* */
2140 /* Routine Description: */
2141 /* */
2142 /* Identify this controller */
2143 /* */
2144 /****************************************************************************/
2145 static void
ips_identify_controller(ips_ha_t * ha)2146 ips_identify_controller(ips_ha_t * ha)
2147 {
2148 METHOD_TRACE("ips_identify_controller", 1);
2149
2150 switch (ha->pcidev->device) {
2151 case IPS_DEVICEID_COPPERHEAD:
2152 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2153 ha->ad_type = IPS_ADTYPE_SERVERAID;
2154 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2155 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2156 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2157 ha->ad_type = IPS_ADTYPE_NAVAJO;
2158 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2159 && (ha->slot_num == 0)) {
2160 ha->ad_type = IPS_ADTYPE_KIOWA;
2161 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2162 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2163 if (ha->enq->ucMaxPhysicalDevices == 15)
2164 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2165 else
2166 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2167 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2168 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2169 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2170 }
2171 break;
2172
2173 case IPS_DEVICEID_MORPHEUS:
2174 switch (ha->pcidev->subsystem_device) {
2175 case IPS_SUBDEVICEID_4L:
2176 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2177 break;
2178
2179 case IPS_SUBDEVICEID_4M:
2180 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2181 break;
2182
2183 case IPS_SUBDEVICEID_4MX:
2184 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2185 break;
2186
2187 case IPS_SUBDEVICEID_4LX:
2188 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2189 break;
2190
2191 case IPS_SUBDEVICEID_5I2:
2192 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2193 break;
2194
2195 case IPS_SUBDEVICEID_5I1:
2196 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2197 break;
2198 }
2199
2200 break;
2201
2202 case IPS_DEVICEID_MARCO:
2203 switch (ha->pcidev->subsystem_device) {
2204 case IPS_SUBDEVICEID_6M:
2205 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2206 break;
2207 case IPS_SUBDEVICEID_6I:
2208 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2209 break;
2210 case IPS_SUBDEVICEID_7k:
2211 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2212 break;
2213 case IPS_SUBDEVICEID_7M:
2214 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2215 break;
2216 }
2217 break;
2218 }
2219 }
2220
2221 /****************************************************************************/
2222 /* */
2223 /* Routine Name: ips_get_bios_version */
2224 /* */
2225 /* Routine Description: */
2226 /* */
2227 /* Get the BIOS revision number */
2228 /* */
2229 /****************************************************************************/
2230 static void
ips_get_bios_version(ips_ha_t * ha,int intr)2231 ips_get_bios_version(ips_ha_t * ha, int intr)
2232 {
2233 ips_scb_t *scb;
2234 int ret;
2235 uint8_t major;
2236 uint8_t minor;
2237 uint8_t subminor;
2238 uint8_t *buffer;
2239
2240 METHOD_TRACE("ips_get_bios_version", 1);
2241
2242 major = 0;
2243 minor = 0;
2244
2245 memcpy(ha->bios_version, " ?", 8);
2246
2247 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2248 if (IPS_USE_MEMIO(ha)) {
2249 /* Memory Mapped I/O */
2250
2251 /* test 1st byte */
2252 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2253 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2254 udelay(25); /* 25 us */
2255
2256 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2257 return;
2258
2259 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2260 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2261 udelay(25); /* 25 us */
2262
2263 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2264 return;
2265
2266 /* Get Major version */
2267 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2268 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2269 udelay(25); /* 25 us */
2270
2271 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2272
2273 /* Get Minor version */
2274 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2275 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2276 udelay(25); /* 25 us */
2277 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2278
2279 /* Get SubMinor version */
2280 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2281 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2282 udelay(25); /* 25 us */
2283 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2284
2285 } else {
2286 /* Programmed I/O */
2287
2288 /* test 1st byte */
2289 outl(0, ha->io_addr + IPS_REG_FLAP);
2290 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2291 udelay(25); /* 25 us */
2292
2293 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2294 return;
2295
2296 outl(1, ha->io_addr + IPS_REG_FLAP);
2297 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2298 udelay(25); /* 25 us */
2299
2300 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2301 return;
2302
2303 /* Get Major version */
2304 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2305 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2306 udelay(25); /* 25 us */
2307
2308 major = inb(ha->io_addr + IPS_REG_FLDP);
2309
2310 /* Get Minor version */
2311 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2312 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2313 udelay(25); /* 25 us */
2314
2315 minor = inb(ha->io_addr + IPS_REG_FLDP);
2316
2317 /* Get SubMinor version */
2318 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2319 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2320 udelay(25); /* 25 us */
2321
2322 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2323
2324 }
2325 } else {
2326 /* Morpheus Family - Send Command to the card */
2327
2328 buffer = ha->ioctl_data;
2329
2330 memset(buffer, 0, 0x1000);
2331
2332 scb = &ha->scbs[ha->max_cmds - 1];
2333
2334 ips_init_scb(ha, scb);
2335
2336 scb->timeout = ips_cmd_timeout;
2337 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2338
2339 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2340 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2341 scb->cmd.flashfw.type = 1;
2342 scb->cmd.flashfw.direction = 0;
2343 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2344 scb->cmd.flashfw.total_packets = 1;
2345 scb->cmd.flashfw.packet_num = 0;
2346 scb->data_len = 0x1000;
2347 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2348
2349 /* issue the command */
2350 if (((ret =
2351 ips_send_wait(ha, scb, ips_cmd_timeout,
2352 intr)) == IPS_FAILURE)
2353 || (ret == IPS_SUCCESS_IMM)
2354 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2355 /* Error occurred */
2356
2357 return;
2358 }
2359
2360 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2361 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2362 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2363 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2364 } else {
2365 return;
2366 }
2367 }
2368
2369 ha->bios_version[0] = hex_asc_upper_hi(major);
2370 ha->bios_version[1] = '.';
2371 ha->bios_version[2] = hex_asc_upper_lo(major);
2372 ha->bios_version[3] = hex_asc_upper_lo(subminor);
2373 ha->bios_version[4] = '.';
2374 ha->bios_version[5] = hex_asc_upper_hi(minor);
2375 ha->bios_version[6] = hex_asc_upper_lo(minor);
2376 ha->bios_version[7] = 0;
2377 }
2378
2379 /****************************************************************************/
2380 /* */
2381 /* Routine Name: ips_hainit */
2382 /* */
2383 /* Routine Description: */
2384 /* */
2385 /* Initialize the controller */
2386 /* */
2387 /* NOTE: Assumes to be called from with a lock */
2388 /* */
2389 /****************************************************************************/
2390 static int
ips_hainit(ips_ha_t * ha)2391 ips_hainit(ips_ha_t * ha)
2392 {
2393 int i;
2394
2395 METHOD_TRACE("ips_hainit", 1);
2396
2397 if (!ha)
2398 return (0);
2399
2400 if (ha->func.statinit)
2401 (*ha->func.statinit) (ha);
2402
2403 if (ha->func.enableint)
2404 (*ha->func.enableint) (ha);
2405
2406 /* Send FFDC */
2407 ha->reset_count = 1;
2408 ha->last_ffdc = ktime_get_real_seconds();
2409 ips_ffdc_reset(ha, IPS_INTR_IORL);
2410
2411 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2412 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2413 "unable to read config from controller.\n");
2414
2415 return (0);
2416 }
2417 /* end if */
2418 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2419 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2420 "unable to read controller status.\n");
2421
2422 return (0);
2423 }
2424
2425 /* Identify this controller */
2426 ips_identify_controller(ha);
2427
2428 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2429 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2430 "unable to read subsystem parameters.\n");
2431
2432 return (0);
2433 }
2434
2435 /* write nvram user page 5 */
2436 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2437 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2438 "unable to write driver info to controller.\n");
2439
2440 return (0);
2441 }
2442
2443 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2444 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2445 ips_clear_adapter(ha, IPS_INTR_IORL);
2446
2447 /* set limits on SID, LUN, BUS */
2448 ha->ntargets = IPS_MAX_TARGETS + 1;
2449 ha->nlun = 1;
2450 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2451
2452 switch (ha->conf->logical_drive[0].ucStripeSize) {
2453 case 4:
2454 ha->max_xfer = 0x10000;
2455 break;
2456
2457 case 5:
2458 ha->max_xfer = 0x20000;
2459 break;
2460
2461 case 6:
2462 ha->max_xfer = 0x40000;
2463 break;
2464
2465 case 7:
2466 default:
2467 ha->max_xfer = 0x80000;
2468 break;
2469 }
2470
2471 /* setup max concurrent commands */
2472 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2473 /* Use the new method */
2474 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2475 } else {
2476 /* use the old method */
2477 switch (ha->conf->logical_drive[0].ucStripeSize) {
2478 case 4:
2479 ha->max_cmds = 32;
2480 break;
2481
2482 case 5:
2483 ha->max_cmds = 16;
2484 break;
2485
2486 case 6:
2487 ha->max_cmds = 8;
2488 break;
2489
2490 case 7:
2491 default:
2492 ha->max_cmds = 4;
2493 break;
2494 }
2495 }
2496
2497 /* Limit the Active Commands on a Lite Adapter */
2498 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2499 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2500 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2501 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2502 ha->max_cmds = MaxLiteCmds;
2503 }
2504
2505 /* set controller IDs */
2506 ha->ha_id[0] = IPS_ADAPTER_ID;
2507 for (i = 1; i < ha->nbus; i++) {
2508 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2509 ha->dcdb_active[i - 1] = 0;
2510 }
2511
2512 return (1);
2513 }
2514
2515 /****************************************************************************/
2516 /* */
2517 /* Routine Name: ips_next */
2518 /* */
2519 /* Routine Description: */
2520 /* */
2521 /* Take the next command off the queue and send it to the controller */
2522 /* */
2523 /****************************************************************************/
2524 static void
ips_next(ips_ha_t * ha,int intr)2525 ips_next(ips_ha_t * ha, int intr)
2526 {
2527 ips_scb_t *scb;
2528 struct scsi_cmnd *SC;
2529 struct scsi_cmnd *p;
2530 struct scsi_cmnd *q;
2531 ips_copp_wait_item_t *item;
2532 int ret;
2533 struct Scsi_Host *host;
2534 METHOD_TRACE("ips_next", 1);
2535
2536 if (!ha)
2537 return;
2538 host = ips_sh[ha->host_num];
2539 /*
2540 * Block access to the queue function so
2541 * this command won't time out
2542 */
2543 if (intr == IPS_INTR_ON)
2544 spin_lock(host->host_lock);
2545
2546 if ((ha->subsys->param[3] & 0x300000)
2547 && (ha->scb_activelist.count == 0)) {
2548 time64_t now = ktime_get_real_seconds();
2549 if (now - ha->last_ffdc > IPS_SECS_8HOURS) {
2550 ha->last_ffdc = now;
2551 ips_ffdc_time(ha);
2552 }
2553 }
2554
2555 /*
2556 * Send passthru commands
2557 * These have priority over normal I/O
2558 * but shouldn't affect performance too much
2559 * since we limit the number that can be active
2560 * on the card at any one time
2561 */
2562 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2563 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2564
2565 item = ips_removeq_copp_head(&ha->copp_waitlist);
2566 ha->num_ioctl++;
2567 if (intr == IPS_INTR_ON)
2568 spin_unlock(host->host_lock);
2569 scb->scsi_cmd = item->scsi_cmd;
2570 kfree(item);
2571
2572 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2573
2574 if (intr == IPS_INTR_ON)
2575 spin_lock(host->host_lock);
2576 switch (ret) {
2577 case IPS_FAILURE:
2578 if (scb->scsi_cmd) {
2579 scb->scsi_cmd->result = DID_ERROR << 16;
2580 scsi_done(scb->scsi_cmd);
2581 }
2582
2583 ips_freescb(ha, scb);
2584 break;
2585 case IPS_SUCCESS_IMM:
2586 if (scb->scsi_cmd) {
2587 scb->scsi_cmd->result = DID_OK << 16;
2588 scsi_done(scb->scsi_cmd);
2589 }
2590
2591 ips_freescb(ha, scb);
2592 break;
2593 default:
2594 break;
2595 } /* end case */
2596
2597 if (ret != IPS_SUCCESS) {
2598 ha->num_ioctl--;
2599 continue;
2600 }
2601
2602 ret = ips_send_cmd(ha, scb);
2603
2604 if (ret == IPS_SUCCESS)
2605 ips_putq_scb_head(&ha->scb_activelist, scb);
2606 else
2607 ha->num_ioctl--;
2608
2609 switch (ret) {
2610 case IPS_FAILURE:
2611 if (scb->scsi_cmd) {
2612 scb->scsi_cmd->result = DID_ERROR << 16;
2613 }
2614
2615 ips_freescb(ha, scb);
2616 break;
2617 case IPS_SUCCESS_IMM:
2618 ips_freescb(ha, scb);
2619 break;
2620 default:
2621 break;
2622 } /* end case */
2623
2624 }
2625
2626 /*
2627 * Send "Normal" I/O commands
2628 */
2629
2630 p = ha->scb_waitlist.head;
2631 while ((p) && (scb = ips_getscb(ha))) {
2632 if ((scmd_channel(p) > 0)
2633 && (ha->
2634 dcdb_active[scmd_channel(p) -
2635 1] & (1 << scmd_id(p)))) {
2636 ips_freescb(ha, scb);
2637 p = (struct scsi_cmnd *) p->host_scribble;
2638 continue;
2639 }
2640
2641 q = p;
2642 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2643
2644 if (intr == IPS_INTR_ON)
2645 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2646
2647 SC->result = DID_OK;
2648 SC->host_scribble = NULL;
2649
2650 scb->target_id = SC->device->id;
2651 scb->lun = SC->device->lun;
2652 scb->bus = SC->device->channel;
2653 scb->scsi_cmd = SC;
2654 scb->breakup = 0;
2655 scb->data_len = 0;
2656 scb->callback = ipsintr_done;
2657 scb->timeout = ips_cmd_timeout;
2658 memset(&scb->cmd, 0, 16);
2659
2660 /* copy in the CDB */
2661 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2662
2663 scb->sg_count = scsi_dma_map(SC);
2664 BUG_ON(scb->sg_count < 0);
2665 if (scb->sg_count) {
2666 struct scatterlist *sg;
2667 int i;
2668
2669 scb->flags |= IPS_SCB_MAP_SG;
2670
2671 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2672 if (ips_fill_scb_sg_single
2673 (ha, sg_dma_address(sg), scb, i,
2674 sg_dma_len(sg)) < 0)
2675 break;
2676 }
2677 scb->dcdb.transfer_length = scb->data_len;
2678 } else {
2679 scb->data_busaddr = 0L;
2680 scb->sg_len = 0;
2681 scb->data_len = 0;
2682 scb->dcdb.transfer_length = 0;
2683 }
2684
2685 scb->dcdb.cmd_attribute =
2686 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2687
2688 /* Allow a WRITE BUFFER Command to Have no Data */
2689 /* This is Used by Tape Flash Utilites */
2690 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2691 (scb->data_len == 0))
2692 scb->dcdb.cmd_attribute = 0;
2693
2694 if (!(scb->dcdb.cmd_attribute & 0x3))
2695 scb->dcdb.transfer_length = 0;
2696
2697 if (scb->data_len >= IPS_MAX_XFER) {
2698 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2699 scb->dcdb.transfer_length = 0;
2700 }
2701 if (intr == IPS_INTR_ON)
2702 spin_lock(host->host_lock);
2703
2704 ret = ips_send_cmd(ha, scb);
2705
2706 switch (ret) {
2707 case IPS_SUCCESS:
2708 ips_putq_scb_head(&ha->scb_activelist, scb);
2709 break;
2710 case IPS_FAILURE:
2711 if (scb->scsi_cmd) {
2712 scb->scsi_cmd->result = DID_ERROR << 16;
2713 scsi_done(scb->scsi_cmd);
2714 }
2715
2716 if (scb->bus)
2717 ha->dcdb_active[scb->bus - 1] &=
2718 ~(1 << scb->target_id);
2719
2720 ips_freescb(ha, scb);
2721 break;
2722 case IPS_SUCCESS_IMM:
2723 if (scb->scsi_cmd)
2724 scsi_done(scb->scsi_cmd);
2725
2726 if (scb->bus)
2727 ha->dcdb_active[scb->bus - 1] &=
2728 ~(1 << scb->target_id);
2729
2730 ips_freescb(ha, scb);
2731 break;
2732 default:
2733 break;
2734 } /* end case */
2735
2736 p = (struct scsi_cmnd *) p->host_scribble;
2737
2738 } /* end while */
2739
2740 if (intr == IPS_INTR_ON)
2741 spin_unlock(host->host_lock);
2742 }
2743
2744 /****************************************************************************/
2745 /* */
2746 /* Routine Name: ips_putq_scb_head */
2747 /* */
2748 /* Routine Description: */
2749 /* */
2750 /* Add an item to the head of the queue */
2751 /* */
2752 /* ASSUMED to be called from within the HA lock */
2753 /* */
2754 /****************************************************************************/
2755 static void
ips_putq_scb_head(ips_scb_queue_t * queue,ips_scb_t * item)2756 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2757 {
2758 METHOD_TRACE("ips_putq_scb_head", 1);
2759
2760 if (!item)
2761 return;
2762
2763 item->q_next = queue->head;
2764 queue->head = item;
2765
2766 if (!queue->tail)
2767 queue->tail = item;
2768
2769 queue->count++;
2770 }
2771
2772 /****************************************************************************/
2773 /* */
2774 /* Routine Name: ips_removeq_scb_head */
2775 /* */
2776 /* Routine Description: */
2777 /* */
2778 /* Remove the head of the queue */
2779 /* */
2780 /* ASSUMED to be called from within the HA lock */
2781 /* */
2782 /****************************************************************************/
2783 static ips_scb_t *
ips_removeq_scb_head(ips_scb_queue_t * queue)2784 ips_removeq_scb_head(ips_scb_queue_t * queue)
2785 {
2786 ips_scb_t *item;
2787
2788 METHOD_TRACE("ips_removeq_scb_head", 1);
2789
2790 item = queue->head;
2791
2792 if (!item) {
2793 return (NULL);
2794 }
2795
2796 queue->head = item->q_next;
2797 item->q_next = NULL;
2798
2799 if (queue->tail == item)
2800 queue->tail = NULL;
2801
2802 queue->count--;
2803
2804 return (item);
2805 }
2806
2807 /****************************************************************************/
2808 /* */
2809 /* Routine Name: ips_removeq_scb */
2810 /* */
2811 /* Routine Description: */
2812 /* */
2813 /* Remove an item from a queue */
2814 /* */
2815 /* ASSUMED to be called from within the HA lock */
2816 /* */
2817 /****************************************************************************/
2818 static ips_scb_t *
ips_removeq_scb(ips_scb_queue_t * queue,ips_scb_t * item)2819 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2820 {
2821 ips_scb_t *p;
2822
2823 METHOD_TRACE("ips_removeq_scb", 1);
2824
2825 if (!item)
2826 return (NULL);
2827
2828 if (item == queue->head) {
2829 return (ips_removeq_scb_head(queue));
2830 }
2831
2832 p = queue->head;
2833
2834 while ((p) && (item != p->q_next))
2835 p = p->q_next;
2836
2837 if (p) {
2838 /* found a match */
2839 p->q_next = item->q_next;
2840
2841 if (!item->q_next)
2842 queue->tail = p;
2843
2844 item->q_next = NULL;
2845 queue->count--;
2846
2847 return (item);
2848 }
2849
2850 return (NULL);
2851 }
2852
2853 /****************************************************************************/
2854 /* */
2855 /* Routine Name: ips_putq_wait_tail */
2856 /* */
2857 /* Routine Description: */
2858 /* */
2859 /* Add an item to the tail of the queue */
2860 /* */
2861 /* ASSUMED to be called from within the HA lock */
2862 /* */
2863 /****************************************************************************/
ips_putq_wait_tail(ips_wait_queue_entry_t * queue,struct scsi_cmnd * item)2864 static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item)
2865 {
2866 METHOD_TRACE("ips_putq_wait_tail", 1);
2867
2868 if (!item)
2869 return;
2870
2871 item->host_scribble = NULL;
2872
2873 if (queue->tail)
2874 queue->tail->host_scribble = (char *) item;
2875
2876 queue->tail = item;
2877
2878 if (!queue->head)
2879 queue->head = item;
2880
2881 queue->count++;
2882 }
2883
2884 /****************************************************************************/
2885 /* */
2886 /* Routine Name: ips_removeq_wait_head */
2887 /* */
2888 /* Routine Description: */
2889 /* */
2890 /* Remove the head of the queue */
2891 /* */
2892 /* ASSUMED to be called from within the HA lock */
2893 /* */
2894 /****************************************************************************/
ips_removeq_wait_head(ips_wait_queue_entry_t * queue)2895 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue)
2896 {
2897 struct scsi_cmnd *item;
2898
2899 METHOD_TRACE("ips_removeq_wait_head", 1);
2900
2901 item = queue->head;
2902
2903 if (!item) {
2904 return (NULL);
2905 }
2906
2907 queue->head = (struct scsi_cmnd *) item->host_scribble;
2908 item->host_scribble = NULL;
2909
2910 if (queue->tail == item)
2911 queue->tail = NULL;
2912
2913 queue->count--;
2914
2915 return (item);
2916 }
2917
2918 /****************************************************************************/
2919 /* */
2920 /* Routine Name: ips_removeq_wait */
2921 /* */
2922 /* Routine Description: */
2923 /* */
2924 /* Remove an item from a queue */
2925 /* */
2926 /* ASSUMED to be called from within the HA lock */
2927 /* */
2928 /****************************************************************************/
ips_removeq_wait(ips_wait_queue_entry_t * queue,struct scsi_cmnd * item)2929 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue,
2930 struct scsi_cmnd *item)
2931 {
2932 struct scsi_cmnd *p;
2933
2934 METHOD_TRACE("ips_removeq_wait", 1);
2935
2936 if (!item)
2937 return (NULL);
2938
2939 if (item == queue->head) {
2940 return (ips_removeq_wait_head(queue));
2941 }
2942
2943 p = queue->head;
2944
2945 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2946 p = (struct scsi_cmnd *) p->host_scribble;
2947
2948 if (p) {
2949 /* found a match */
2950 p->host_scribble = item->host_scribble;
2951
2952 if (!item->host_scribble)
2953 queue->tail = p;
2954
2955 item->host_scribble = NULL;
2956 queue->count--;
2957
2958 return (item);
2959 }
2960
2961 return (NULL);
2962 }
2963
2964 /****************************************************************************/
2965 /* */
2966 /* Routine Name: ips_putq_copp_tail */
2967 /* */
2968 /* Routine Description: */
2969 /* */
2970 /* Add an item to the tail of the queue */
2971 /* */
2972 /* ASSUMED to be called from within the HA lock */
2973 /* */
2974 /****************************************************************************/
2975 static void
ips_putq_copp_tail(ips_copp_queue_t * queue,ips_copp_wait_item_t * item)2976 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2977 {
2978 METHOD_TRACE("ips_putq_copp_tail", 1);
2979
2980 if (!item)
2981 return;
2982
2983 item->next = NULL;
2984
2985 if (queue->tail)
2986 queue->tail->next = item;
2987
2988 queue->tail = item;
2989
2990 if (!queue->head)
2991 queue->head = item;
2992
2993 queue->count++;
2994 }
2995
2996 /****************************************************************************/
2997 /* */
2998 /* Routine Name: ips_removeq_copp_head */
2999 /* */
3000 /* Routine Description: */
3001 /* */
3002 /* Remove the head of the queue */
3003 /* */
3004 /* ASSUMED to be called from within the HA lock */
3005 /* */
3006 /****************************************************************************/
3007 static ips_copp_wait_item_t *
ips_removeq_copp_head(ips_copp_queue_t * queue)3008 ips_removeq_copp_head(ips_copp_queue_t * queue)
3009 {
3010 ips_copp_wait_item_t *item;
3011
3012 METHOD_TRACE("ips_removeq_copp_head", 1);
3013
3014 item = queue->head;
3015
3016 if (!item) {
3017 return (NULL);
3018 }
3019
3020 queue->head = item->next;
3021 item->next = NULL;
3022
3023 if (queue->tail == item)
3024 queue->tail = NULL;
3025
3026 queue->count--;
3027
3028 return (item);
3029 }
3030
3031 /****************************************************************************/
3032 /* */
3033 /* Routine Name: ips_removeq_copp */
3034 /* */
3035 /* Routine Description: */
3036 /* */
3037 /* Remove an item from a queue */
3038 /* */
3039 /* ASSUMED to be called from within the HA lock */
3040 /* */
3041 /****************************************************************************/
3042 static ips_copp_wait_item_t *
ips_removeq_copp(ips_copp_queue_t * queue,ips_copp_wait_item_t * item)3043 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3044 {
3045 ips_copp_wait_item_t *p;
3046
3047 METHOD_TRACE("ips_removeq_copp", 1);
3048
3049 if (!item)
3050 return (NULL);
3051
3052 if (item == queue->head) {
3053 return (ips_removeq_copp_head(queue));
3054 }
3055
3056 p = queue->head;
3057
3058 while ((p) && (item != p->next))
3059 p = p->next;
3060
3061 if (p) {
3062 /* found a match */
3063 p->next = item->next;
3064
3065 if (!item->next)
3066 queue->tail = p;
3067
3068 item->next = NULL;
3069 queue->count--;
3070
3071 return (item);
3072 }
3073
3074 return (NULL);
3075 }
3076
3077 /****************************************************************************/
3078 /* */
3079 /* Routine Name: ipsintr_blocking */
3080 /* */
3081 /* Routine Description: */
3082 /* */
3083 /* Finalize an interrupt for internal commands */
3084 /* */
3085 /****************************************************************************/
3086 static void
ipsintr_blocking(ips_ha_t * ha,ips_scb_t * scb)3087 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3088 {
3089 METHOD_TRACE("ipsintr_blocking", 2);
3090
3091 ips_freescb(ha, scb);
3092 if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0]) {
3093 ha->waitflag = false;
3094
3095 return;
3096 }
3097 }
3098
3099 /****************************************************************************/
3100 /* */
3101 /* Routine Name: ipsintr_done */
3102 /* */
3103 /* Routine Description: */
3104 /* */
3105 /* Finalize an interrupt for non-internal commands */
3106 /* */
3107 /****************************************************************************/
3108 static void
ipsintr_done(ips_ha_t * ha,ips_scb_t * scb)3109 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3110 {
3111 METHOD_TRACE("ipsintr_done", 2);
3112
3113 if (!scb) {
3114 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3115 "Spurious interrupt; scb NULL.\n");
3116
3117 return;
3118 }
3119
3120 if (scb->scsi_cmd == NULL) {
3121 /* unexpected interrupt */
3122 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3123 "Spurious interrupt; scsi_cmd not set.\n");
3124
3125 return;
3126 }
3127
3128 ips_done(ha, scb);
3129 }
3130
3131 /****************************************************************************/
3132 /* */
3133 /* Routine Name: ips_done */
3134 /* */
3135 /* Routine Description: */
3136 /* */
3137 /* Do housekeeping on completed commands */
3138 /* ASSUMED to be called form within the request lock */
3139 /****************************************************************************/
3140 static void
ips_done(ips_ha_t * ha,ips_scb_t * scb)3141 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3142 {
3143 int ret;
3144
3145 METHOD_TRACE("ips_done", 1);
3146
3147 if (!scb)
3148 return;
3149
3150 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3151 ips_cleanup_passthru(ha, scb);
3152 ha->num_ioctl--;
3153 } else {
3154 /*
3155 * Check to see if this command had too much
3156 * data and had to be broke up. If so, queue
3157 * the rest of the data and continue.
3158 */
3159 if ((scb->breakup) || (scb->sg_break)) {
3160 struct scatterlist *sg;
3161 int i, sg_dma_index, ips_sg_index = 0;
3162
3163 /* we had a data breakup */
3164 scb->data_len = 0;
3165
3166 sg = scsi_sglist(scb->scsi_cmd);
3167
3168 /* Spin forward to last dma chunk */
3169 sg_dma_index = scb->breakup;
3170 for (i = 0; i < scb->breakup; i++)
3171 sg = sg_next(sg);
3172
3173 /* Take care of possible partial on last chunk */
3174 ips_fill_scb_sg_single(ha,
3175 sg_dma_address(sg),
3176 scb, ips_sg_index++,
3177 sg_dma_len(sg));
3178
3179 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3180 sg_dma_index++, sg = sg_next(sg)) {
3181 if (ips_fill_scb_sg_single
3182 (ha,
3183 sg_dma_address(sg),
3184 scb, ips_sg_index++,
3185 sg_dma_len(sg)) < 0)
3186 break;
3187 }
3188
3189 scb->dcdb.transfer_length = scb->data_len;
3190 scb->dcdb.cmd_attribute |=
3191 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3192
3193 if (!(scb->dcdb.cmd_attribute & 0x3))
3194 scb->dcdb.transfer_length = 0;
3195
3196 if (scb->data_len >= IPS_MAX_XFER) {
3197 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3198 scb->dcdb.transfer_length = 0;
3199 }
3200
3201 ret = ips_send_cmd(ha, scb);
3202
3203 switch (ret) {
3204 case IPS_FAILURE:
3205 if (scb->scsi_cmd) {
3206 scb->scsi_cmd->result = DID_ERROR << 16;
3207 scsi_done(scb->scsi_cmd);
3208 }
3209
3210 ips_freescb(ha, scb);
3211 break;
3212 case IPS_SUCCESS_IMM:
3213 if (scb->scsi_cmd) {
3214 scb->scsi_cmd->result = DID_ERROR << 16;
3215 scsi_done(scb->scsi_cmd);
3216 }
3217
3218 ips_freescb(ha, scb);
3219 break;
3220 default:
3221 break;
3222 } /* end case */
3223
3224 return;
3225 }
3226 } /* end if passthru */
3227
3228 if (scb->bus) {
3229 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3230 }
3231
3232 scsi_done(scb->scsi_cmd);
3233
3234 ips_freescb(ha, scb);
3235 }
3236
3237 /****************************************************************************/
3238 /* */
3239 /* Routine Name: ips_map_status */
3240 /* */
3241 /* Routine Description: */
3242 /* */
3243 /* Map Controller Error codes to Linux Error Codes */
3244 /* */
3245 /****************************************************************************/
3246 static int
ips_map_status(ips_ha_t * ha,ips_scb_t * scb,ips_stat_t * sp)3247 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3248 {
3249 int errcode;
3250 int device_error;
3251 uint32_t transfer_len;
3252 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3253 IPS_SCSI_INQ_DATA inquiryData;
3254
3255 METHOD_TRACE("ips_map_status", 1);
3256
3257 if (scb->bus) {
3258 DEBUG_VAR(2,
3259 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3260 ips_name, ha->host_num,
3261 scb->scsi_cmd->device->channel,
3262 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3263 scb->basic_status, scb->extended_status,
3264 scb->extended_status ==
3265 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3266 scb->extended_status ==
3267 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3268 scb->extended_status ==
3269 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3270 }
3271
3272 /* default driver error */
3273 errcode = DID_ERROR;
3274 device_error = 0;
3275
3276 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3277 case IPS_CMD_TIMEOUT:
3278 errcode = DID_TIME_OUT;
3279 break;
3280
3281 case IPS_INVAL_OPCO:
3282 case IPS_INVAL_CMD_BLK:
3283 case IPS_INVAL_PARM_BLK:
3284 case IPS_LD_ERROR:
3285 case IPS_CMD_CMPLT_WERROR:
3286 break;
3287
3288 case IPS_PHYS_DRV_ERROR:
3289 switch (scb->extended_status) {
3290 case IPS_ERR_SEL_TO:
3291 if (scb->bus)
3292 errcode = DID_NO_CONNECT;
3293
3294 break;
3295
3296 case IPS_ERR_OU_RUN:
3297 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3298 (scb->cmd.dcdb.op_code ==
3299 IPS_CMD_EXTENDED_DCDB_SG)) {
3300 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3301 transfer_len = tapeDCDB->transfer_length;
3302 } else {
3303 transfer_len =
3304 (uint32_t) scb->dcdb.transfer_length;
3305 }
3306
3307 if ((scb->bus) && (transfer_len < scb->data_len)) {
3308 /* Underrun - set default to no error */
3309 errcode = DID_OK;
3310
3311 /* Restrict access to physical DASD */
3312 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3313 ips_scmd_buf_read(scb->scsi_cmd,
3314 &inquiryData, sizeof (inquiryData));
3315 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3316 errcode = DID_TIME_OUT;
3317 break;
3318 }
3319 }
3320 } else
3321 errcode = DID_ERROR;
3322
3323 break;
3324
3325 case IPS_ERR_RECOVERY:
3326 /* don't fail recovered errors */
3327 if (scb->bus)
3328 errcode = DID_OK;
3329
3330 break;
3331
3332 case IPS_ERR_HOST_RESET:
3333 case IPS_ERR_DEV_RESET:
3334 errcode = DID_RESET;
3335 break;
3336
3337 case IPS_ERR_CKCOND:
3338 if (scb->bus) {
3339 if ((scb->cmd.dcdb.op_code ==
3340 IPS_CMD_EXTENDED_DCDB)
3341 || (scb->cmd.dcdb.op_code ==
3342 IPS_CMD_EXTENDED_DCDB_SG)) {
3343 tapeDCDB =
3344 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3345 memcpy_and_pad(scb->scsi_cmd->sense_buffer,
3346 SCSI_SENSE_BUFFERSIZE,
3347 tapeDCDB->sense_info,
3348 sizeof(tapeDCDB->sense_info), 0);
3349 } else {
3350 memcpy_and_pad(scb->scsi_cmd->sense_buffer,
3351 SCSI_SENSE_BUFFERSIZE,
3352 scb->dcdb.sense_info,
3353 sizeof(scb->dcdb.sense_info), 0);
3354 }
3355 device_error = 2; /* check condition */
3356 }
3357
3358 errcode = DID_OK;
3359
3360 break;
3361
3362 default:
3363 errcode = DID_ERROR;
3364 break;
3365
3366 } /* end switch */
3367 } /* end switch */
3368
3369 scb->scsi_cmd->result = device_error | (errcode << 16);
3370
3371 return (1);
3372 }
3373
3374 /****************************************************************************/
3375 /* */
3376 /* Routine Name: ips_send_wait */
3377 /* */
3378 /* Routine Description: */
3379 /* */
3380 /* Send a command to the controller and wait for it to return */
3381 /* */
3382 /* The FFDC Time Stamp use this function for the callback, but doesn't */
3383 /* actually need to wait. */
3384 /****************************************************************************/
3385 static int
ips_send_wait(ips_ha_t * ha,ips_scb_t * scb,int timeout,int intr)3386 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3387 {
3388 int ret;
3389
3390 METHOD_TRACE("ips_send_wait", 1);
3391
3392 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3393 ha->waitflag = true;
3394 ha->cmd_in_progress = scb->cdb[0];
3395 }
3396 scb->callback = ipsintr_blocking;
3397 ret = ips_send_cmd(ha, scb);
3398
3399 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3400 return (ret);
3401
3402 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3403 ret = ips_wait(ha, timeout, intr);
3404
3405 return (ret);
3406 }
3407
3408 /****************************************************************************/
3409 /* */
3410 /* Routine Name: ips_scmd_buf_write */
3411 /* */
3412 /* Routine Description: */
3413 /* Write data to struct scsi_cmnd request_buffer at proper offsets */
3414 /****************************************************************************/
3415 static void
ips_scmd_buf_write(struct scsi_cmnd * scmd,void * data,unsigned int count)3416 ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3417 {
3418 unsigned long flags;
3419
3420 local_irq_save(flags);
3421 scsi_sg_copy_from_buffer(scmd, data, count);
3422 local_irq_restore(flags);
3423 }
3424
3425 /****************************************************************************/
3426 /* */
3427 /* Routine Name: ips_scmd_buf_read */
3428 /* */
3429 /* Routine Description: */
3430 /* Copy data from a struct scsi_cmnd to a new, linear buffer */
3431 /****************************************************************************/
3432 static void
ips_scmd_buf_read(struct scsi_cmnd * scmd,void * data,unsigned int count)3433 ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3434 {
3435 unsigned long flags;
3436
3437 local_irq_save(flags);
3438 scsi_sg_copy_to_buffer(scmd, data, count);
3439 local_irq_restore(flags);
3440 }
3441
3442 /****************************************************************************/
3443 /* */
3444 /* Routine Name: ips_send_cmd */
3445 /* */
3446 /* Routine Description: */
3447 /* */
3448 /* Map SCSI commands to ServeRAID commands for logical drives */
3449 /* */
3450 /****************************************************************************/
3451 static int
ips_send_cmd(ips_ha_t * ha,ips_scb_t * scb)3452 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3453 {
3454 int ret;
3455 char *sp;
3456 int device_error;
3457 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3458 int TimeOut;
3459
3460 METHOD_TRACE("ips_send_cmd", 1);
3461
3462 ret = IPS_SUCCESS;
3463
3464 if (!scb->scsi_cmd) {
3465 /* internal command */
3466
3467 if (scb->bus > 0) {
3468 /* Controller commands can't be issued */
3469 /* to real devices -- fail them */
3470 if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0])
3471 ha->waitflag = false;
3472
3473 return (1);
3474 }
3475 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3476 /* command to logical bus -- interpret */
3477 ret = IPS_SUCCESS_IMM;
3478
3479 switch (scb->scsi_cmd->cmnd[0]) {
3480 case ALLOW_MEDIUM_REMOVAL:
3481 case REZERO_UNIT:
3482 case ERASE:
3483 case WRITE_FILEMARKS:
3484 case SPACE:
3485 scb->scsi_cmd->result = DID_ERROR << 16;
3486 break;
3487
3488 case START_STOP:
3489 scb->scsi_cmd->result = DID_OK << 16;
3490 break;
3491
3492 case TEST_UNIT_READY:
3493 case INQUIRY:
3494 if (scb->target_id == IPS_ADAPTER_ID) {
3495 /*
3496 * Either we have a TUR
3497 * or we have a SCSI inquiry
3498 */
3499 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3500 scb->scsi_cmd->result = DID_OK << 16;
3501
3502 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3503 IPS_SCSI_INQ_DATA inquiry;
3504
3505 memset(&inquiry, 0,
3506 sizeof (IPS_SCSI_INQ_DATA));
3507
3508 inquiry.DeviceType =
3509 IPS_SCSI_INQ_TYPE_PROCESSOR;
3510 inquiry.DeviceTypeQualifier =
3511 IPS_SCSI_INQ_LU_CONNECTED;
3512 inquiry.Version = IPS_SCSI_INQ_REV2;
3513 inquiry.ResponseDataFormat =
3514 IPS_SCSI_INQ_RD_REV2;
3515 inquiry.AdditionalLength = 31;
3516 inquiry.Flags[0] =
3517 IPS_SCSI_INQ_Address16;
3518 inquiry.Flags[1] =
3519 IPS_SCSI_INQ_WBus16 |
3520 IPS_SCSI_INQ_Sync;
3521 memcpy(inquiry.VendorId, "IBM ",
3522 8);
3523 memcpy(inquiry.ProductId,
3524 "SERVERAID ", 16);
3525 memcpy(inquiry.ProductRevisionLevel,
3526 "1.00", 4);
3527
3528 ips_scmd_buf_write(scb->scsi_cmd,
3529 &inquiry,
3530 sizeof (inquiry));
3531
3532 scb->scsi_cmd->result = DID_OK << 16;
3533 }
3534 } else {
3535 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3536 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3537 scb->cmd.logical_info.reserved = 0;
3538 scb->cmd.logical_info.reserved2 = 0;
3539 scb->data_len = sizeof (IPS_LD_INFO);
3540 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3541 scb->flags = 0;
3542 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3543 ret = IPS_SUCCESS;
3544 }
3545
3546 break;
3547
3548 case REQUEST_SENSE:
3549 ips_reqsen(ha, scb);
3550 scb->scsi_cmd->result = DID_OK << 16;
3551 break;
3552
3553 case READ_6:
3554 case WRITE_6:
3555 if (!scb->sg_len) {
3556 scb->cmd.basic_io.op_code =
3557 (scb->scsi_cmd->cmnd[0] ==
3558 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3559 scb->cmd.basic_io.enhanced_sg = 0;
3560 scb->cmd.basic_io.sg_addr =
3561 cpu_to_le32(scb->data_busaddr);
3562 } else {
3563 scb->cmd.basic_io.op_code =
3564 (scb->scsi_cmd->cmnd[0] ==
3565 READ_6) ? IPS_CMD_READ_SG :
3566 IPS_CMD_WRITE_SG;
3567 scb->cmd.basic_io.enhanced_sg =
3568 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3569 scb->cmd.basic_io.sg_addr =
3570 cpu_to_le32(scb->sg_busaddr);
3571 }
3572
3573 scb->cmd.basic_io.segment_4G = 0;
3574 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3575 scb->cmd.basic_io.log_drv = scb->target_id;
3576 scb->cmd.basic_io.sg_count = scb->sg_len;
3577
3578 if (scb->cmd.basic_io.lba)
3579 le32_add_cpu(&scb->cmd.basic_io.lba,
3580 le16_to_cpu(scb->cmd.basic_io.
3581 sector_count));
3582 else
3583 scb->cmd.basic_io.lba =
3584 (((scb->scsi_cmd->
3585 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3586 cmnd[2] << 8) |
3587 (scb->scsi_cmd->cmnd[3]));
3588
3589 scb->cmd.basic_io.sector_count =
3590 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3591
3592 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3593 scb->cmd.basic_io.sector_count =
3594 cpu_to_le16(256);
3595
3596 ret = IPS_SUCCESS;
3597 break;
3598
3599 case READ_10:
3600 case WRITE_10:
3601 if (!scb->sg_len) {
3602 scb->cmd.basic_io.op_code =
3603 (scb->scsi_cmd->cmnd[0] ==
3604 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3605 scb->cmd.basic_io.enhanced_sg = 0;
3606 scb->cmd.basic_io.sg_addr =
3607 cpu_to_le32(scb->data_busaddr);
3608 } else {
3609 scb->cmd.basic_io.op_code =
3610 (scb->scsi_cmd->cmnd[0] ==
3611 READ_10) ? IPS_CMD_READ_SG :
3612 IPS_CMD_WRITE_SG;
3613 scb->cmd.basic_io.enhanced_sg =
3614 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3615 scb->cmd.basic_io.sg_addr =
3616 cpu_to_le32(scb->sg_busaddr);
3617 }
3618
3619 scb->cmd.basic_io.segment_4G = 0;
3620 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3621 scb->cmd.basic_io.log_drv = scb->target_id;
3622 scb->cmd.basic_io.sg_count = scb->sg_len;
3623
3624 if (scb->cmd.basic_io.lba)
3625 le32_add_cpu(&scb->cmd.basic_io.lba,
3626 le16_to_cpu(scb->cmd.basic_io.
3627 sector_count));
3628 else
3629 scb->cmd.basic_io.lba =
3630 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3631 scsi_cmd->
3632 cmnd[3]
3633 << 16) |
3634 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3635 scsi_cmd->cmnd[5]);
3636
3637 scb->cmd.basic_io.sector_count =
3638 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3639
3640 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3641 /*
3642 * This is a null condition
3643 * we don't have to do anything
3644 * so just return
3645 */
3646 scb->scsi_cmd->result = DID_OK << 16;
3647 } else
3648 ret = IPS_SUCCESS;
3649
3650 break;
3651
3652 case RESERVE:
3653 case RELEASE:
3654 scb->scsi_cmd->result = DID_OK << 16;
3655 break;
3656
3657 case MODE_SENSE:
3658 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3659 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3660 scb->cmd.basic_io.segment_4G = 0;
3661 scb->cmd.basic_io.enhanced_sg = 0;
3662 scb->data_len = sizeof (*ha->enq);
3663 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3664 ret = IPS_SUCCESS;
3665 break;
3666
3667 case READ_CAPACITY:
3668 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3669 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3670 scb->cmd.logical_info.reserved = 0;
3671 scb->cmd.logical_info.reserved2 = 0;
3672 scb->cmd.logical_info.reserved3 = 0;
3673 scb->data_len = sizeof (IPS_LD_INFO);
3674 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3675 scb->flags = 0;
3676 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3677 ret = IPS_SUCCESS;
3678 break;
3679
3680 case SEND_DIAGNOSTIC:
3681 case REASSIGN_BLOCKS:
3682 case FORMAT_UNIT:
3683 case SEEK_10:
3684 case VERIFY:
3685 case READ_DEFECT_DATA:
3686 case READ_BUFFER:
3687 case WRITE_BUFFER:
3688 scb->scsi_cmd->result = DID_OK << 16;
3689 break;
3690
3691 default:
3692 /* Set the Return Info to appear like the Command was */
3693 /* attempted, a Check Condition occurred, and Sense */
3694 /* Data indicating an Invalid CDB OpCode is returned. */
3695 sp = (char *) scb->scsi_cmd->sense_buffer;
3696
3697 sp[0] = 0x70; /* Error Code */
3698 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3699 sp[7] = 0x0A; /* Additional Sense Length */
3700 sp[12] = 0x20; /* ASC = Invalid OpCode */
3701 sp[13] = 0x00; /* ASCQ */
3702
3703 device_error = 2; /* Indicate Check Condition */
3704 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3705 break;
3706 } /* end switch */
3707 }
3708 /* end if */
3709 if (ret == IPS_SUCCESS_IMM)
3710 return (ret);
3711
3712 /* setup DCDB */
3713 if (scb->bus > 0) {
3714
3715 /* If we already know the Device is Not there, no need to attempt a Command */
3716 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3717 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3718 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3719 return (IPS_SUCCESS_IMM);
3720 }
3721
3722 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3723 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3724 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3725 (unsigned long) &scb->
3726 dcdb -
3727 (unsigned long) scb);
3728 scb->cmd.dcdb.reserved = 0;
3729 scb->cmd.dcdb.reserved2 = 0;
3730 scb->cmd.dcdb.reserved3 = 0;
3731 scb->cmd.dcdb.segment_4G = 0;
3732 scb->cmd.dcdb.enhanced_sg = 0;
3733
3734 TimeOut = scsi_cmd_to_rq(scb->scsi_cmd)->timeout;
3735
3736 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3737 if (!scb->sg_len) {
3738 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3739 } else {
3740 scb->cmd.dcdb.op_code =
3741 IPS_CMD_EXTENDED_DCDB_SG;
3742 scb->cmd.dcdb.enhanced_sg =
3743 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3744 }
3745
3746 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3747 tapeDCDB->device_address =
3748 ((scb->bus - 1) << 4) | scb->target_id;
3749 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3750 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3751
3752 if (TimeOut) {
3753 if (TimeOut < (10 * HZ))
3754 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3755 else if (TimeOut < (60 * HZ))
3756 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3757 else if (TimeOut < (1200 * HZ))
3758 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3759 }
3760
3761 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3762 tapeDCDB->reserved_for_LUN = 0;
3763 tapeDCDB->transfer_length = scb->data_len;
3764 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3765 tapeDCDB->buffer_pointer =
3766 cpu_to_le32(scb->sg_busaddr);
3767 else
3768 tapeDCDB->buffer_pointer =
3769 cpu_to_le32(scb->data_busaddr);
3770 tapeDCDB->sg_count = scb->sg_len;
3771 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3772 tapeDCDB->scsi_status = 0;
3773 tapeDCDB->reserved = 0;
3774 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3775 scb->scsi_cmd->cmd_len);
3776 } else {
3777 if (!scb->sg_len) {
3778 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3779 } else {
3780 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3781 scb->cmd.dcdb.enhanced_sg =
3782 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3783 }
3784
3785 scb->dcdb.device_address =
3786 ((scb->bus - 1) << 4) | scb->target_id;
3787 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3788
3789 if (TimeOut) {
3790 if (TimeOut < (10 * HZ))
3791 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3792 else if (TimeOut < (60 * HZ))
3793 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3794 else if (TimeOut < (1200 * HZ))
3795 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3796 }
3797
3798 scb->dcdb.transfer_length = scb->data_len;
3799 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3800 scb->dcdb.transfer_length = 0;
3801 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3802 scb->dcdb.buffer_pointer =
3803 cpu_to_le32(scb->sg_busaddr);
3804 else
3805 scb->dcdb.buffer_pointer =
3806 cpu_to_le32(scb->data_busaddr);
3807 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3808 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3809 scb->dcdb.sg_count = scb->sg_len;
3810 scb->dcdb.reserved = 0;
3811 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3812 scb->scsi_cmd->cmd_len);
3813 scb->dcdb.scsi_status = 0;
3814 scb->dcdb.reserved2[0] = 0;
3815 scb->dcdb.reserved2[1] = 0;
3816 scb->dcdb.reserved2[2] = 0;
3817 }
3818 }
3819
3820 return ((*ha->func.issue) (ha, scb));
3821 }
3822
3823 /****************************************************************************/
3824 /* */
3825 /* Routine Name: ips_chk_status */
3826 /* */
3827 /* Routine Description: */
3828 /* */
3829 /* Check the status of commands to logical drives */
3830 /* Assumed to be called with the HA lock */
3831 /****************************************************************************/
3832 static void
ips_chkstatus(ips_ha_t * ha,IPS_STATUS * pstatus)3833 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3834 {
3835 ips_scb_t *scb;
3836 ips_stat_t *sp;
3837 uint8_t basic_status;
3838 uint8_t ext_status;
3839 int errcode;
3840 IPS_SCSI_INQ_DATA inquiryData;
3841
3842 METHOD_TRACE("ips_chkstatus", 1);
3843
3844 scb = &ha->scbs[pstatus->fields.command_id];
3845 scb->basic_status = basic_status =
3846 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3847 scb->extended_status = ext_status = pstatus->fields.extended_status;
3848
3849 sp = &ha->sp;
3850 sp->residue_len = 0;
3851 sp->scb_addr = (void *) scb;
3852
3853 /* Remove the item from the active queue */
3854 ips_removeq_scb(&ha->scb_activelist, scb);
3855
3856 if (!scb->scsi_cmd)
3857 /* internal commands are handled in do_ipsintr */
3858 return;
3859
3860 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3861 ips_name,
3862 ha->host_num,
3863 scb->cdb[0],
3864 scb->cmd.basic_io.command_id,
3865 scb->bus, scb->target_id, scb->lun);
3866
3867 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3868 /* passthru - just returns the raw result */
3869 return;
3870
3871 errcode = DID_OK;
3872
3873 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3874 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3875
3876 if (scb->bus == 0) {
3877 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3878 IPS_CMD_RECOVERED_ERROR) {
3879 DEBUG_VAR(1,
3880 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3881 ips_name, ha->host_num,
3882 scb->cmd.basic_io.op_code,
3883 basic_status, ext_status);
3884 }
3885
3886 switch (scb->scsi_cmd->cmnd[0]) {
3887 case ALLOW_MEDIUM_REMOVAL:
3888 case REZERO_UNIT:
3889 case ERASE:
3890 case WRITE_FILEMARKS:
3891 case SPACE:
3892 errcode = DID_ERROR;
3893 break;
3894
3895 case START_STOP:
3896 break;
3897
3898 case TEST_UNIT_READY:
3899 if (!ips_online(ha, scb)) {
3900 errcode = DID_TIME_OUT;
3901 }
3902 break;
3903
3904 case INQUIRY:
3905 if (ips_online(ha, scb)) {
3906 ips_inquiry(ha, scb);
3907 } else {
3908 errcode = DID_TIME_OUT;
3909 }
3910 break;
3911
3912 case REQUEST_SENSE:
3913 ips_reqsen(ha, scb);
3914 break;
3915
3916 case READ_6:
3917 case WRITE_6:
3918 case READ_10:
3919 case WRITE_10:
3920 case RESERVE:
3921 case RELEASE:
3922 break;
3923
3924 case MODE_SENSE:
3925 if (!ips_online(ha, scb)
3926 || !ips_msense(ha, scb)) {
3927 errcode = DID_ERROR;
3928 }
3929 break;
3930
3931 case READ_CAPACITY:
3932 if (ips_online(ha, scb))
3933 ips_rdcap(ha, scb);
3934 else {
3935 errcode = DID_TIME_OUT;
3936 }
3937 break;
3938
3939 case SEND_DIAGNOSTIC:
3940 case REASSIGN_BLOCKS:
3941 break;
3942
3943 case FORMAT_UNIT:
3944 errcode = DID_ERROR;
3945 break;
3946
3947 case SEEK_10:
3948 case VERIFY:
3949 case READ_DEFECT_DATA:
3950 case READ_BUFFER:
3951 case WRITE_BUFFER:
3952 break;
3953
3954 default:
3955 errcode = DID_ERROR;
3956 } /* end switch */
3957
3958 scb->scsi_cmd->result = errcode << 16;
3959 } else { /* bus == 0 */
3960 /* restrict access to physical drives */
3961 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3962 ips_scmd_buf_read(scb->scsi_cmd,
3963 &inquiryData, sizeof (inquiryData));
3964 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
3965 scb->scsi_cmd->result = DID_TIME_OUT << 16;
3966 }
3967 } /* else */
3968 } else { /* recovered error / success */
3969 if (scb->bus == 0) {
3970 DEBUG_VAR(1,
3971 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3972 ips_name, ha->host_num,
3973 scb->cmd.basic_io.op_code, basic_status,
3974 ext_status);
3975 }
3976
3977 ips_map_status(ha, scb, sp);
3978 } /* else */
3979 }
3980
3981 /****************************************************************************/
3982 /* */
3983 /* Routine Name: ips_online */
3984 /* */
3985 /* Routine Description: */
3986 /* */
3987 /* Determine if a logical drive is online */
3988 /* */
3989 /****************************************************************************/
3990 static int
ips_online(ips_ha_t * ha,ips_scb_t * scb)3991 ips_online(ips_ha_t * ha, ips_scb_t * scb)
3992 {
3993 METHOD_TRACE("ips_online", 1);
3994
3995 if (scb->target_id >= IPS_MAX_LD)
3996 return (0);
3997
3998 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
3999 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4000 return (0);
4001 }
4002
4003 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4004 IPS_LD_OFFLINE
4005 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4006 IPS_LD_FREE
4007 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4008 IPS_LD_CRS
4009 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4010 IPS_LD_SYS)
4011 return (1);
4012 else
4013 return (0);
4014 }
4015
4016 /****************************************************************************/
4017 /* */
4018 /* Routine Name: ips_inquiry */
4019 /* */
4020 /* Routine Description: */
4021 /* */
4022 /* Simulate an inquiry command to a logical drive */
4023 /* */
4024 /****************************************************************************/
4025 static int
ips_inquiry(ips_ha_t * ha,ips_scb_t * scb)4026 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4027 {
4028 IPS_SCSI_INQ_DATA inquiry;
4029
4030 METHOD_TRACE("ips_inquiry", 1);
4031
4032 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4033
4034 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4035 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4036 inquiry.Version = IPS_SCSI_INQ_REV2;
4037 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4038 inquiry.AdditionalLength = 31;
4039 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4040 inquiry.Flags[1] =
4041 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4042 memcpy(inquiry.VendorId, "IBM ", 8);
4043 memcpy(inquiry.ProductId, "SERVERAID ", 16);
4044 memcpy(inquiry.ProductRevisionLevel, "1.00", 4);
4045
4046 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4047
4048 return (1);
4049 }
4050
4051 /****************************************************************************/
4052 /* */
4053 /* Routine Name: ips_rdcap */
4054 /* */
4055 /* Routine Description: */
4056 /* */
4057 /* Simulate a read capacity command to a logical drive */
4058 /* */
4059 /****************************************************************************/
4060 static int
ips_rdcap(ips_ha_t * ha,ips_scb_t * scb)4061 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4062 {
4063 IPS_SCSI_CAPACITY cap;
4064
4065 METHOD_TRACE("ips_rdcap", 1);
4066
4067 if (scsi_bufflen(scb->scsi_cmd) < 8)
4068 return (0);
4069
4070 cap.lba =
4071 cpu_to_be32(le32_to_cpu
4072 (ha->logical_drive_info->
4073 drive_info[scb->target_id].sector_count) - 1);
4074 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4075
4076 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4077
4078 return (1);
4079 }
4080
4081 /****************************************************************************/
4082 /* */
4083 /* Routine Name: ips_msense */
4084 /* */
4085 /* Routine Description: */
4086 /* */
4087 /* Simulate a mode sense command to a logical drive */
4088 /* */
4089 /****************************************************************************/
4090 static int
ips_msense(ips_ha_t * ha,ips_scb_t * scb)4091 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4092 {
4093 uint16_t heads;
4094 uint16_t sectors;
4095 uint32_t cylinders;
4096 IPS_SCSI_MODE_PAGE_DATA mdata;
4097
4098 METHOD_TRACE("ips_msense", 1);
4099
4100 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4101 (ha->enq->ucMiscFlag & 0x8) == 0) {
4102 heads = IPS_NORM_HEADS;
4103 sectors = IPS_NORM_SECTORS;
4104 } else {
4105 heads = IPS_COMP_HEADS;
4106 sectors = IPS_COMP_SECTORS;
4107 }
4108
4109 cylinders =
4110 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4111 1) / (heads * sectors);
4112
4113 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4114
4115 mdata.hdr.BlockDescLength = 8;
4116
4117 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4118 case 0x03: /* page 3 */
4119 mdata.pdata.pg3.PageCode = 3;
4120 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4121 mdata.hdr.DataLength =
4122 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4123 mdata.pdata.pg3.TracksPerZone = 0;
4124 mdata.pdata.pg3.AltSectorsPerZone = 0;
4125 mdata.pdata.pg3.AltTracksPerZone = 0;
4126 mdata.pdata.pg3.AltTracksPerVolume = 0;
4127 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4128 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4129 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4130 mdata.pdata.pg3.TrackSkew = 0;
4131 mdata.pdata.pg3.CylinderSkew = 0;
4132 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4133 break;
4134
4135 case 0x4:
4136 mdata.pdata.pg4.PageCode = 4;
4137 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4138 mdata.hdr.DataLength =
4139 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4140 mdata.pdata.pg4.CylindersHigh =
4141 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4142 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4143 mdata.pdata.pg4.Heads = heads;
4144 mdata.pdata.pg4.WritePrecompHigh = 0;
4145 mdata.pdata.pg4.WritePrecompLow = 0;
4146 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4147 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4148 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4149 mdata.pdata.pg4.LandingZoneHigh = 0;
4150 mdata.pdata.pg4.LandingZoneLow = 0;
4151 mdata.pdata.pg4.flags = 0;
4152 mdata.pdata.pg4.RotationalOffset = 0;
4153 mdata.pdata.pg4.MediumRotationRate = 0;
4154 break;
4155 case 0x8:
4156 mdata.pdata.pg8.PageCode = 8;
4157 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4158 mdata.hdr.DataLength =
4159 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4160 /* everything else is left set to 0 */
4161 break;
4162
4163 default:
4164 return (0);
4165 } /* end switch */
4166
4167 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4168
4169 return (1);
4170 }
4171
4172 /****************************************************************************/
4173 /* */
4174 /* Routine Name: ips_reqsen */
4175 /* */
4176 /* Routine Description: */
4177 /* */
4178 /* Simulate a request sense command to a logical drive */
4179 /* */
4180 /****************************************************************************/
4181 static int
ips_reqsen(ips_ha_t * ha,ips_scb_t * scb)4182 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4183 {
4184 IPS_SCSI_REQSEN reqsen;
4185
4186 METHOD_TRACE("ips_reqsen", 1);
4187
4188 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4189
4190 reqsen.ResponseCode =
4191 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4192 reqsen.AdditionalLength = 10;
4193 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4194 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4195
4196 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4197
4198 return (1);
4199 }
4200
4201 /****************************************************************************/
4202 /* */
4203 /* Routine Name: ips_free */
4204 /* */
4205 /* Routine Description: */
4206 /* */
4207 /* Free any allocated space for this controller */
4208 /* */
4209 /****************************************************************************/
4210 static void
ips_free(ips_ha_t * ha)4211 ips_free(ips_ha_t * ha)
4212 {
4213
4214 METHOD_TRACE("ips_free", 1);
4215
4216 if (ha) {
4217 if (ha->enq) {
4218 dma_free_coherent(&ha->pcidev->dev, sizeof(IPS_ENQ),
4219 ha->enq, ha->enq_busaddr);
4220 ha->enq = NULL;
4221 }
4222
4223 kfree(ha->conf);
4224 ha->conf = NULL;
4225
4226 if (ha->adapt) {
4227 dma_free_coherent(&ha->pcidev->dev,
4228 sizeof (IPS_ADAPTER) +
4229 sizeof (IPS_IO_CMD), ha->adapt,
4230 ha->adapt->hw_status_start);
4231 ha->adapt = NULL;
4232 }
4233
4234 if (ha->logical_drive_info) {
4235 dma_free_coherent(&ha->pcidev->dev,
4236 sizeof (IPS_LD_INFO),
4237 ha->logical_drive_info,
4238 ha->logical_drive_info_dma_addr);
4239 ha->logical_drive_info = NULL;
4240 }
4241
4242 kfree(ha->nvram);
4243 ha->nvram = NULL;
4244
4245 kfree(ha->subsys);
4246 ha->subsys = NULL;
4247
4248 if (ha->ioctl_data) {
4249 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
4250 ha->ioctl_data, ha->ioctl_busaddr);
4251 ha->ioctl_data = NULL;
4252 ha->ioctl_datasize = 0;
4253 ha->ioctl_len = 0;
4254 }
4255 ips_deallocatescbs(ha, ha->max_cmds);
4256
4257 /* free memory mapped (if applicable) */
4258 if (ha->mem_ptr) {
4259 iounmap(ha->ioremap_ptr);
4260 ha->ioremap_ptr = NULL;
4261 ha->mem_ptr = NULL;
4262 }
4263
4264 ha->mem_addr = 0;
4265
4266 }
4267 }
4268
4269 /****************************************************************************/
4270 /* */
4271 /* Routine Name: ips_deallocatescbs */
4272 /* */
4273 /* Routine Description: */
4274 /* */
4275 /* Free the command blocks */
4276 /* */
4277 /****************************************************************************/
4278 static int
ips_deallocatescbs(ips_ha_t * ha,int cmds)4279 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4280 {
4281 if (ha->scbs) {
4282 dma_free_coherent(&ha->pcidev->dev,
4283 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4284 ha->scbs->sg_list.list,
4285 ha->scbs->sg_busaddr);
4286 dma_free_coherent(&ha->pcidev->dev, sizeof (ips_scb_t) * cmds,
4287 ha->scbs, ha->scbs->scb_busaddr);
4288 ha->scbs = NULL;
4289 } /* end if */
4290 return 1;
4291 }
4292
4293 /****************************************************************************/
4294 /* */
4295 /* Routine Name: ips_allocatescbs */
4296 /* */
4297 /* Routine Description: */
4298 /* */
4299 /* Allocate the command blocks */
4300 /* */
4301 /****************************************************************************/
4302 static int
ips_allocatescbs(ips_ha_t * ha)4303 ips_allocatescbs(ips_ha_t * ha)
4304 {
4305 ips_scb_t *scb_p;
4306 IPS_SG_LIST ips_sg;
4307 int i;
4308 dma_addr_t command_dma, sg_dma;
4309
4310 METHOD_TRACE("ips_allocatescbs", 1);
4311
4312 /* Allocate memory for the SCBs */
4313 ha->scbs = dma_alloc_coherent(&ha->pcidev->dev,
4314 ha->max_cmds * sizeof (ips_scb_t),
4315 &command_dma, GFP_KERNEL);
4316 if (ha->scbs == NULL)
4317 return 0;
4318 ips_sg.list = dma_alloc_coherent(&ha->pcidev->dev,
4319 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds,
4320 &sg_dma, GFP_KERNEL);
4321 if (ips_sg.list == NULL) {
4322 dma_free_coherent(&ha->pcidev->dev,
4323 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4324 command_dma);
4325 return 0;
4326 }
4327
4328 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4329
4330 for (i = 0; i < ha->max_cmds; i++) {
4331 scb_p = &ha->scbs[i];
4332 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4333 /* set up S/G list */
4334 if (IPS_USE_ENH_SGLIST(ha)) {
4335 scb_p->sg_list.enh_list =
4336 ips_sg.enh_list + i * IPS_MAX_SG;
4337 scb_p->sg_busaddr =
4338 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4339 } else {
4340 scb_p->sg_list.std_list =
4341 ips_sg.std_list + i * IPS_MAX_SG;
4342 scb_p->sg_busaddr =
4343 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4344 }
4345
4346 /* add to the free list */
4347 if (i < ha->max_cmds - 1) {
4348 scb_p->q_next = ha->scb_freelist;
4349 ha->scb_freelist = scb_p;
4350 }
4351 }
4352
4353 /* success */
4354 return (1);
4355 }
4356
4357 /****************************************************************************/
4358 /* */
4359 /* Routine Name: ips_init_scb */
4360 /* */
4361 /* Routine Description: */
4362 /* */
4363 /* Initialize a CCB to default values */
4364 /* */
4365 /****************************************************************************/
4366 static void
ips_init_scb(ips_ha_t * ha,ips_scb_t * scb)4367 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4368 {
4369 IPS_SG_LIST sg_list;
4370 uint32_t cmd_busaddr, sg_busaddr;
4371 METHOD_TRACE("ips_init_scb", 1);
4372
4373 if (scb == NULL)
4374 return;
4375
4376 sg_list.list = scb->sg_list.list;
4377 cmd_busaddr = scb->scb_busaddr;
4378 sg_busaddr = scb->sg_busaddr;
4379 /* zero fill */
4380 memset(scb, 0, sizeof (ips_scb_t));
4381 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4382
4383 /* Initialize dummy command bucket */
4384 ha->dummy->op_code = 0xFF;
4385 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4386 + sizeof (IPS_ADAPTER));
4387 ha->dummy->command_id = IPS_MAX_CMDS;
4388
4389 /* set bus address of scb */
4390 scb->scb_busaddr = cmd_busaddr;
4391 scb->sg_busaddr = sg_busaddr;
4392 scb->sg_list.list = sg_list.list;
4393
4394 /* Neptune Fix */
4395 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4396 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4397 + sizeof (IPS_ADAPTER));
4398 }
4399
4400 /****************************************************************************/
4401 /* */
4402 /* Routine Name: ips_get_scb */
4403 /* */
4404 /* Routine Description: */
4405 /* */
4406 /* Initialize a CCB to default values */
4407 /* */
4408 /* ASSUMED to be called from within a lock */
4409 /* */
4410 /****************************************************************************/
4411 static ips_scb_t *
ips_getscb(ips_ha_t * ha)4412 ips_getscb(ips_ha_t * ha)
4413 {
4414 ips_scb_t *scb;
4415
4416 METHOD_TRACE("ips_getscb", 1);
4417
4418 if ((scb = ha->scb_freelist) == NULL) {
4419
4420 return (NULL);
4421 }
4422
4423 ha->scb_freelist = scb->q_next;
4424 scb->flags = 0;
4425 scb->q_next = NULL;
4426
4427 ips_init_scb(ha, scb);
4428
4429 return (scb);
4430 }
4431
4432 /****************************************************************************/
4433 /* */
4434 /* Routine Name: ips_free_scb */
4435 /* */
4436 /* Routine Description: */
4437 /* */
4438 /* Return an unused CCB back to the free list */
4439 /* */
4440 /* ASSUMED to be called from within a lock */
4441 /* */
4442 /****************************************************************************/
4443 static void
ips_freescb(ips_ha_t * ha,ips_scb_t * scb)4444 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4445 {
4446
4447 METHOD_TRACE("ips_freescb", 1);
4448 if (scb->flags & IPS_SCB_MAP_SG)
4449 scsi_dma_unmap(scb->scsi_cmd);
4450 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4451 dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr,
4452 scb->data_len, IPS_DMA_DIR(scb));
4453
4454 /* check to make sure this is not our "special" scb */
4455 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4456 scb->q_next = ha->scb_freelist;
4457 ha->scb_freelist = scb;
4458 }
4459 }
4460
4461 /****************************************************************************/
4462 /* */
4463 /* Routine Name: ips_isinit_copperhead */
4464 /* */
4465 /* Routine Description: */
4466 /* */
4467 /* Is controller initialized ? */
4468 /* */
4469 /****************************************************************************/
4470 static int
ips_isinit_copperhead(ips_ha_t * ha)4471 ips_isinit_copperhead(ips_ha_t * ha)
4472 {
4473 uint8_t scpr;
4474 uint8_t isr;
4475
4476 METHOD_TRACE("ips_isinit_copperhead", 1);
4477
4478 isr = inb(ha->io_addr + IPS_REG_HISR);
4479 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4480
4481 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4482 return (0);
4483 else
4484 return (1);
4485 }
4486
4487 /****************************************************************************/
4488 /* */
4489 /* Routine Name: ips_isinit_copperhead_memio */
4490 /* */
4491 /* Routine Description: */
4492 /* */
4493 /* Is controller initialized ? */
4494 /* */
4495 /****************************************************************************/
4496 static int
ips_isinit_copperhead_memio(ips_ha_t * ha)4497 ips_isinit_copperhead_memio(ips_ha_t * ha)
4498 {
4499 uint8_t isr = 0;
4500 uint8_t scpr;
4501
4502 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4503
4504 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4505 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4506
4507 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4508 return (0);
4509 else
4510 return (1);
4511 }
4512
4513 /****************************************************************************/
4514 /* */
4515 /* Routine Name: ips_isinit_morpheus */
4516 /* */
4517 /* Routine Description: */
4518 /* */
4519 /* Is controller initialized ? */
4520 /* */
4521 /****************************************************************************/
4522 static int
ips_isinit_morpheus(ips_ha_t * ha)4523 ips_isinit_morpheus(ips_ha_t * ha)
4524 {
4525 uint32_t post;
4526 uint32_t bits;
4527
4528 METHOD_TRACE("ips_is_init_morpheus", 1);
4529
4530 if (ips_isintr_morpheus(ha))
4531 ips_flush_and_reset(ha);
4532
4533 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4534 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4535
4536 if (post == 0)
4537 return (0);
4538 else if (bits & 0x3)
4539 return (0);
4540 else
4541 return (1);
4542 }
4543
4544 /****************************************************************************/
4545 /* */
4546 /* Routine Name: ips_flush_and_reset */
4547 /* */
4548 /* Routine Description: */
4549 /* */
4550 /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4551 /* state ( was trying to INIT and an interrupt was already pending ) ... */
4552 /* */
4553 /****************************************************************************/
4554 static void
ips_flush_and_reset(ips_ha_t * ha)4555 ips_flush_and_reset(ips_ha_t *ha)
4556 {
4557 ips_scb_t *scb;
4558 int ret;
4559 int time;
4560 int done;
4561 dma_addr_t command_dma;
4562
4563 /* Create a usuable SCB */
4564 scb = dma_alloc_coherent(&ha->pcidev->dev, sizeof(ips_scb_t),
4565 &command_dma, GFP_KERNEL);
4566 if (scb) {
4567 memset(scb, 0, sizeof(ips_scb_t));
4568 ips_init_scb(ha, scb);
4569 scb->scb_busaddr = command_dma;
4570
4571 scb->timeout = ips_cmd_timeout;
4572 scb->cdb[0] = IPS_CMD_FLUSH;
4573
4574 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4575 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4576 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4577 scb->cmd.flush_cache.reserved = 0;
4578 scb->cmd.flush_cache.reserved2 = 0;
4579 scb->cmd.flush_cache.reserved3 = 0;
4580 scb->cmd.flush_cache.reserved4 = 0;
4581
4582 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4583
4584 if (ret == IPS_SUCCESS) {
4585 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4586 done = 0;
4587
4588 while ((time > 0) && (!done)) {
4589 done = ips_poll_for_flush_complete(ha);
4590 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4591 udelay(1000);
4592 time--;
4593 }
4594 }
4595 }
4596
4597 /* Now RESET and INIT the adapter */
4598 (*ha->func.reset) (ha);
4599
4600 dma_free_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), scb, command_dma);
4601 return;
4602 }
4603
4604 /****************************************************************************/
4605 /* */
4606 /* Routine Name: ips_poll_for_flush_complete */
4607 /* */
4608 /* Routine Description: */
4609 /* */
4610 /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4611 /* All other responses are just taken off the queue and ignored */
4612 /* */
4613 /****************************************************************************/
4614 static int
ips_poll_for_flush_complete(ips_ha_t * ha)4615 ips_poll_for_flush_complete(ips_ha_t * ha)
4616 {
4617 IPS_STATUS cstatus;
4618
4619 while (true) {
4620 cstatus.value = (*ha->func.statupd) (ha);
4621
4622 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4623 break;
4624
4625 /* Success is when we see the Flush Command ID */
4626 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4627 return 1;
4628 }
4629
4630 return 0;
4631 }
4632
4633 /****************************************************************************/
4634 /* */
4635 /* Routine Name: ips_enable_int_copperhead */
4636 /* */
4637 /* Routine Description: */
4638 /* Turn on interrupts */
4639 /* */
4640 /****************************************************************************/
4641 static void
ips_enable_int_copperhead(ips_ha_t * ha)4642 ips_enable_int_copperhead(ips_ha_t * ha)
4643 {
4644 METHOD_TRACE("ips_enable_int_copperhead", 1);
4645
4646 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4647 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4648 }
4649
4650 /****************************************************************************/
4651 /* */
4652 /* Routine Name: ips_enable_int_copperhead_memio */
4653 /* */
4654 /* Routine Description: */
4655 /* Turn on interrupts */
4656 /* */
4657 /****************************************************************************/
4658 static void
ips_enable_int_copperhead_memio(ips_ha_t * ha)4659 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4660 {
4661 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4662
4663 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4664 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4665 }
4666
4667 /****************************************************************************/
4668 /* */
4669 /* Routine Name: ips_enable_int_morpheus */
4670 /* */
4671 /* Routine Description: */
4672 /* Turn on interrupts */
4673 /* */
4674 /****************************************************************************/
4675 static void
ips_enable_int_morpheus(ips_ha_t * ha)4676 ips_enable_int_morpheus(ips_ha_t * ha)
4677 {
4678 uint32_t Oimr;
4679
4680 METHOD_TRACE("ips_enable_int_morpheus", 1);
4681
4682 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4683 Oimr &= ~0x08;
4684 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4685 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4686 }
4687
4688 /****************************************************************************/
4689 /* */
4690 /* Routine Name: ips_init_copperhead */
4691 /* */
4692 /* Routine Description: */
4693 /* */
4694 /* Initialize a copperhead controller */
4695 /* */
4696 /****************************************************************************/
4697 static int
ips_init_copperhead(ips_ha_t * ha)4698 ips_init_copperhead(ips_ha_t * ha)
4699 {
4700 uint8_t Isr;
4701 uint8_t Cbsp;
4702 uint8_t PostByte[IPS_MAX_POST_BYTES];
4703 int i, j;
4704
4705 METHOD_TRACE("ips_init_copperhead", 1);
4706
4707 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4708 for (j = 0; j < 45; j++) {
4709 Isr = inb(ha->io_addr + IPS_REG_HISR);
4710 if (Isr & IPS_BIT_GHI)
4711 break;
4712
4713 /* Delay for 1 Second */
4714 MDELAY(IPS_ONE_SEC);
4715 }
4716
4717 if (j >= 45)
4718 /* error occurred */
4719 return (0);
4720
4721 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4722 outb(Isr, ha->io_addr + IPS_REG_HISR);
4723 }
4724
4725 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4726 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4727 "reset controller fails (post status %x %x).\n",
4728 PostByte[0], PostByte[1]);
4729
4730 return (0);
4731 }
4732
4733 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4734 for (j = 0; j < 240; j++) {
4735 Isr = inb(ha->io_addr + IPS_REG_HISR);
4736 if (Isr & IPS_BIT_GHI)
4737 break;
4738
4739 /* Delay for 1 Second */
4740 MDELAY(IPS_ONE_SEC);
4741 }
4742
4743 if (j >= 240)
4744 /* error occurred */
4745 return (0);
4746
4747 inb(ha->io_addr + IPS_REG_ISPR);
4748 outb(Isr, ha->io_addr + IPS_REG_HISR);
4749 }
4750
4751 for (i = 0; i < 240; i++) {
4752 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4753
4754 if ((Cbsp & IPS_BIT_OP) == 0)
4755 break;
4756
4757 /* Delay for 1 Second */
4758 MDELAY(IPS_ONE_SEC);
4759 }
4760
4761 if (i >= 240)
4762 /* reset failed */
4763 return (0);
4764
4765 /* setup CCCR */
4766 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4767
4768 /* Enable busmastering */
4769 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4770
4771 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4772 /* fix for anaconda64 */
4773 outl(0, ha->io_addr + IPS_REG_NDAE);
4774
4775 /* Enable interrupts */
4776 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4777
4778 return (1);
4779 }
4780
4781 /****************************************************************************/
4782 /* */
4783 /* Routine Name: ips_init_copperhead_memio */
4784 /* */
4785 /* Routine Description: */
4786 /* */
4787 /* Initialize a copperhead controller with memory mapped I/O */
4788 /* */
4789 /****************************************************************************/
4790 static int
ips_init_copperhead_memio(ips_ha_t * ha)4791 ips_init_copperhead_memio(ips_ha_t * ha)
4792 {
4793 uint8_t Isr = 0;
4794 uint8_t Cbsp;
4795 uint8_t PostByte[IPS_MAX_POST_BYTES];
4796 int i, j;
4797
4798 METHOD_TRACE("ips_init_copperhead_memio", 1);
4799
4800 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4801 for (j = 0; j < 45; j++) {
4802 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4803 if (Isr & IPS_BIT_GHI)
4804 break;
4805
4806 /* Delay for 1 Second */
4807 MDELAY(IPS_ONE_SEC);
4808 }
4809
4810 if (j >= 45)
4811 /* error occurred */
4812 return (0);
4813
4814 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4815 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4816 }
4817
4818 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4819 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4820 "reset controller fails (post status %x %x).\n",
4821 PostByte[0], PostByte[1]);
4822
4823 return (0);
4824 }
4825
4826 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4827 for (j = 0; j < 240; j++) {
4828 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4829 if (Isr & IPS_BIT_GHI)
4830 break;
4831
4832 /* Delay for 1 Second */
4833 MDELAY(IPS_ONE_SEC);
4834 }
4835
4836 if (j >= 240)
4837 /* error occurred */
4838 return (0);
4839
4840 readb(ha->mem_ptr + IPS_REG_ISPR);
4841 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4842 }
4843
4844 for (i = 0; i < 240; i++) {
4845 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4846
4847 if ((Cbsp & IPS_BIT_OP) == 0)
4848 break;
4849
4850 /* Delay for 1 Second */
4851 MDELAY(IPS_ONE_SEC);
4852 }
4853
4854 if (i >= 240)
4855 /* error occurred */
4856 return (0);
4857
4858 /* setup CCCR */
4859 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4860
4861 /* Enable busmastering */
4862 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4863
4864 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4865 /* fix for anaconda64 */
4866 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4867
4868 /* Enable interrupts */
4869 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4870
4871 /* if we get here then everything went OK */
4872 return (1);
4873 }
4874
4875 /****************************************************************************/
4876 /* */
4877 /* Routine Name: ips_init_morpheus */
4878 /* */
4879 /* Routine Description: */
4880 /* */
4881 /* Initialize a morpheus controller */
4882 /* */
4883 /****************************************************************************/
4884 static int
ips_init_morpheus(ips_ha_t * ha)4885 ips_init_morpheus(ips_ha_t * ha)
4886 {
4887 uint32_t Post;
4888 uint32_t Config;
4889 uint32_t Isr;
4890 uint32_t Oimr;
4891 int i;
4892
4893 METHOD_TRACE("ips_init_morpheus", 1);
4894
4895 /* Wait up to 45 secs for Post */
4896 for (i = 0; i < 45; i++) {
4897 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4898
4899 if (Isr & IPS_BIT_I960_MSG0I)
4900 break;
4901
4902 /* Delay for 1 Second */
4903 MDELAY(IPS_ONE_SEC);
4904 }
4905
4906 if (i >= 45) {
4907 /* error occurred */
4908 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4909 "timeout waiting for post.\n");
4910
4911 return (0);
4912 }
4913
4914 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4915
4916 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
4917 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4918 "Flashing Battery PIC, Please wait ...\n");
4919
4920 /* Clear the interrupt bit */
4921 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4922 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4923
4924 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
4925 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4926 if (Post != 0x4F00)
4927 break;
4928 /* Delay for 1 Second */
4929 MDELAY(IPS_ONE_SEC);
4930 }
4931
4932 if (i >= 120) {
4933 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4934 "timeout waiting for Battery PIC Flash\n");
4935 return (0);
4936 }
4937
4938 }
4939
4940 /* Clear the interrupt bit */
4941 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4942 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4943
4944 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4945 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4946 "reset controller fails (post status %x).\n", Post);
4947
4948 return (0);
4949 }
4950
4951 /* Wait up to 240 secs for config bytes */
4952 for (i = 0; i < 240; i++) {
4953 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4954
4955 if (Isr & IPS_BIT_I960_MSG1I)
4956 break;
4957
4958 /* Delay for 1 Second */
4959 MDELAY(IPS_ONE_SEC);
4960 }
4961
4962 if (i >= 240) {
4963 /* error occurred */
4964 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4965 "timeout waiting for config.\n");
4966
4967 return (0);
4968 }
4969
4970 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4971
4972 /* Clear interrupt bit */
4973 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4974 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4975
4976 /* Turn on the interrupts */
4977 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4978 Oimr &= ~0x8;
4979 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4980
4981 /* if we get here then everything went OK */
4982
4983 /* Since we did a RESET, an EraseStripeLock may be needed */
4984 if (Post == 0xEF10) {
4985 if ((Config == 0x000F) || (Config == 0x0009))
4986 ha->requires_esl = 1;
4987 }
4988
4989 return (1);
4990 }
4991
4992 /****************************************************************************/
4993 /* */
4994 /* Routine Name: ips_reset_copperhead */
4995 /* */
4996 /* Routine Description: */
4997 /* */
4998 /* Reset the controller */
4999 /* */
5000 /****************************************************************************/
5001 static int
ips_reset_copperhead(ips_ha_t * ha)5002 ips_reset_copperhead(ips_ha_t * ha)
5003 {
5004 int reset_counter;
5005
5006 METHOD_TRACE("ips_reset_copperhead", 1);
5007
5008 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5009 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5010
5011 reset_counter = 0;
5012
5013 while (reset_counter < 2) {
5014 reset_counter++;
5015
5016 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5017
5018 /* Delay for 1 Second */
5019 MDELAY(IPS_ONE_SEC);
5020
5021 outb(0, ha->io_addr + IPS_REG_SCPR);
5022
5023 /* Delay for 1 Second */
5024 MDELAY(IPS_ONE_SEC);
5025
5026 if ((*ha->func.init) (ha))
5027 break;
5028 else if (reset_counter >= 2) {
5029
5030 return (0);
5031 }
5032 }
5033
5034 return (1);
5035 }
5036
5037 /****************************************************************************/
5038 /* */
5039 /* Routine Name: ips_reset_copperhead_memio */
5040 /* */
5041 /* Routine Description: */
5042 /* */
5043 /* Reset the controller */
5044 /* */
5045 /****************************************************************************/
5046 static int
ips_reset_copperhead_memio(ips_ha_t * ha)5047 ips_reset_copperhead_memio(ips_ha_t * ha)
5048 {
5049 int reset_counter;
5050
5051 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5052
5053 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5054 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5055
5056 reset_counter = 0;
5057
5058 while (reset_counter < 2) {
5059 reset_counter++;
5060
5061 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5062
5063 /* Delay for 1 Second */
5064 MDELAY(IPS_ONE_SEC);
5065
5066 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5067
5068 /* Delay for 1 Second */
5069 MDELAY(IPS_ONE_SEC);
5070
5071 if ((*ha->func.init) (ha))
5072 break;
5073 else if (reset_counter >= 2) {
5074
5075 return (0);
5076 }
5077 }
5078
5079 return (1);
5080 }
5081
5082 /****************************************************************************/
5083 /* */
5084 /* Routine Name: ips_reset_morpheus */
5085 /* */
5086 /* Routine Description: */
5087 /* */
5088 /* Reset the controller */
5089 /* */
5090 /****************************************************************************/
5091 static int
ips_reset_morpheus(ips_ha_t * ha)5092 ips_reset_morpheus(ips_ha_t * ha)
5093 {
5094 int reset_counter;
5095 uint8_t junk;
5096
5097 METHOD_TRACE("ips_reset_morpheus", 1);
5098
5099 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5100 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5101
5102 reset_counter = 0;
5103
5104 while (reset_counter < 2) {
5105 reset_counter++;
5106
5107 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5108
5109 /* Delay for 5 Seconds */
5110 MDELAY(5 * IPS_ONE_SEC);
5111
5112 /* Do a PCI config read to wait for adapter */
5113 pci_read_config_byte(ha->pcidev, 4, &junk);
5114
5115 if ((*ha->func.init) (ha))
5116 break;
5117 else if (reset_counter >= 2) {
5118
5119 return (0);
5120 }
5121 }
5122
5123 return (1);
5124 }
5125
5126 /****************************************************************************/
5127 /* */
5128 /* Routine Name: ips_statinit */
5129 /* */
5130 /* Routine Description: */
5131 /* */
5132 /* Initialize the status queues on the controller */
5133 /* */
5134 /****************************************************************************/
5135 static void
ips_statinit(ips_ha_t * ha)5136 ips_statinit(ips_ha_t * ha)
5137 {
5138 uint32_t phys_status_start;
5139
5140 METHOD_TRACE("ips_statinit", 1);
5141
5142 ha->adapt->p_status_start = ha->adapt->status;
5143 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5144 ha->adapt->p_status_tail = ha->adapt->status;
5145
5146 phys_status_start = ha->adapt->hw_status_start;
5147 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5148 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5149 ha->io_addr + IPS_REG_SQER);
5150 outl(phys_status_start + IPS_STATUS_SIZE,
5151 ha->io_addr + IPS_REG_SQHR);
5152 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5153
5154 ha->adapt->hw_status_tail = phys_status_start;
5155 }
5156
5157 /****************************************************************************/
5158 /* */
5159 /* Routine Name: ips_statinit_memio */
5160 /* */
5161 /* Routine Description: */
5162 /* */
5163 /* Initialize the status queues on the controller */
5164 /* */
5165 /****************************************************************************/
5166 static void
ips_statinit_memio(ips_ha_t * ha)5167 ips_statinit_memio(ips_ha_t * ha)
5168 {
5169 uint32_t phys_status_start;
5170
5171 METHOD_TRACE("ips_statinit_memio", 1);
5172
5173 ha->adapt->p_status_start = ha->adapt->status;
5174 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5175 ha->adapt->p_status_tail = ha->adapt->status;
5176
5177 phys_status_start = ha->adapt->hw_status_start;
5178 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5179 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5180 ha->mem_ptr + IPS_REG_SQER);
5181 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5182 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5183
5184 ha->adapt->hw_status_tail = phys_status_start;
5185 }
5186
5187 /****************************************************************************/
5188 /* */
5189 /* Routine Name: ips_statupd_copperhead */
5190 /* */
5191 /* Routine Description: */
5192 /* */
5193 /* Remove an element from the status queue */
5194 /* */
5195 /****************************************************************************/
5196 static uint32_t
ips_statupd_copperhead(ips_ha_t * ha)5197 ips_statupd_copperhead(ips_ha_t * ha)
5198 {
5199 METHOD_TRACE("ips_statupd_copperhead", 1);
5200
5201 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5202 ha->adapt->p_status_tail++;
5203 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5204 } else {
5205 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5206 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5207 }
5208
5209 outl(ha->adapt->hw_status_tail,
5210 ha->io_addr + IPS_REG_SQTR);
5211
5212 return (ha->adapt->p_status_tail->value);
5213 }
5214
5215 /****************************************************************************/
5216 /* */
5217 /* Routine Name: ips_statupd_copperhead_memio */
5218 /* */
5219 /* Routine Description: */
5220 /* */
5221 /* Remove an element from the status queue */
5222 /* */
5223 /****************************************************************************/
5224 static uint32_t
ips_statupd_copperhead_memio(ips_ha_t * ha)5225 ips_statupd_copperhead_memio(ips_ha_t * ha)
5226 {
5227 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5228
5229 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5230 ha->adapt->p_status_tail++;
5231 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5232 } else {
5233 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5234 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5235 }
5236
5237 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5238
5239 return (ha->adapt->p_status_tail->value);
5240 }
5241
5242 /****************************************************************************/
5243 /* */
5244 /* Routine Name: ips_statupd_morpheus */
5245 /* */
5246 /* Routine Description: */
5247 /* */
5248 /* Remove an element from the status queue */
5249 /* */
5250 /****************************************************************************/
5251 static uint32_t
ips_statupd_morpheus(ips_ha_t * ha)5252 ips_statupd_morpheus(ips_ha_t * ha)
5253 {
5254 uint32_t val;
5255
5256 METHOD_TRACE("ips_statupd_morpheus", 1);
5257
5258 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5259
5260 return (val);
5261 }
5262
5263 /****************************************************************************/
5264 /* */
5265 /* Routine Name: ips_issue_copperhead */
5266 /* */
5267 /* Routine Description: */
5268 /* */
5269 /* Send a command down to the controller */
5270 /* */
5271 /****************************************************************************/
5272 static int
ips_issue_copperhead(ips_ha_t * ha,ips_scb_t * scb)5273 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5274 {
5275 uint32_t TimeOut;
5276 uint32_t val;
5277
5278 METHOD_TRACE("ips_issue_copperhead", 1);
5279
5280 if (scb->scsi_cmd) {
5281 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5282 ips_name,
5283 ha->host_num,
5284 scb->cdb[0],
5285 scb->cmd.basic_io.command_id,
5286 scb->bus, scb->target_id, scb->lun);
5287 } else {
5288 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5289 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5290 }
5291
5292 TimeOut = 0;
5293
5294 while ((val =
5295 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5296 udelay(1000);
5297
5298 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5299 if (!(val & IPS_BIT_START_STOP))
5300 break;
5301
5302 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5303 "ips_issue val [0x%x].\n", val);
5304 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5305 "ips_issue semaphore chk timeout.\n");
5306
5307 return (IPS_FAILURE);
5308 } /* end if */
5309 } /* end while */
5310
5311 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5312 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5313
5314 return (IPS_SUCCESS);
5315 }
5316
5317 /****************************************************************************/
5318 /* */
5319 /* Routine Name: ips_issue_copperhead_memio */
5320 /* */
5321 /* Routine Description: */
5322 /* */
5323 /* Send a command down to the controller */
5324 /* */
5325 /****************************************************************************/
5326 static int
ips_issue_copperhead_memio(ips_ha_t * ha,ips_scb_t * scb)5327 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5328 {
5329 uint32_t TimeOut;
5330 uint32_t val;
5331
5332 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5333
5334 if (scb->scsi_cmd) {
5335 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5336 ips_name,
5337 ha->host_num,
5338 scb->cdb[0],
5339 scb->cmd.basic_io.command_id,
5340 scb->bus, scb->target_id, scb->lun);
5341 } else {
5342 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5343 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5344 }
5345
5346 TimeOut = 0;
5347
5348 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5349 udelay(1000);
5350
5351 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5352 if (!(val & IPS_BIT_START_STOP))
5353 break;
5354
5355 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5356 "ips_issue val [0x%x].\n", val);
5357 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5358 "ips_issue semaphore chk timeout.\n");
5359
5360 return (IPS_FAILURE);
5361 } /* end if */
5362 } /* end while */
5363
5364 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5365 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5366
5367 return (IPS_SUCCESS);
5368 }
5369
5370 /****************************************************************************/
5371 /* */
5372 /* Routine Name: ips_issue_i2o */
5373 /* */
5374 /* Routine Description: */
5375 /* */
5376 /* Send a command down to the controller */
5377 /* */
5378 /****************************************************************************/
5379 static int
ips_issue_i2o(ips_ha_t * ha,ips_scb_t * scb)5380 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5381 {
5382
5383 METHOD_TRACE("ips_issue_i2o", 1);
5384
5385 if (scb->scsi_cmd) {
5386 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5387 ips_name,
5388 ha->host_num,
5389 scb->cdb[0],
5390 scb->cmd.basic_io.command_id,
5391 scb->bus, scb->target_id, scb->lun);
5392 } else {
5393 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5394 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5395 }
5396
5397 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5398
5399 return (IPS_SUCCESS);
5400 }
5401
5402 /****************************************************************************/
5403 /* */
5404 /* Routine Name: ips_issue_i2o_memio */
5405 /* */
5406 /* Routine Description: */
5407 /* */
5408 /* Send a command down to the controller */
5409 /* */
5410 /****************************************************************************/
5411 static int
ips_issue_i2o_memio(ips_ha_t * ha,ips_scb_t * scb)5412 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5413 {
5414
5415 METHOD_TRACE("ips_issue_i2o_memio", 1);
5416
5417 if (scb->scsi_cmd) {
5418 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5419 ips_name,
5420 ha->host_num,
5421 scb->cdb[0],
5422 scb->cmd.basic_io.command_id,
5423 scb->bus, scb->target_id, scb->lun);
5424 } else {
5425 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5426 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5427 }
5428
5429 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5430
5431 return (IPS_SUCCESS);
5432 }
5433
5434 /****************************************************************************/
5435 /* */
5436 /* Routine Name: ips_isintr_copperhead */
5437 /* */
5438 /* Routine Description: */
5439 /* */
5440 /* Test to see if an interrupt is for us */
5441 /* */
5442 /****************************************************************************/
5443 static int
ips_isintr_copperhead(ips_ha_t * ha)5444 ips_isintr_copperhead(ips_ha_t * ha)
5445 {
5446 uint8_t Isr;
5447
5448 METHOD_TRACE("ips_isintr_copperhead", 2);
5449
5450 Isr = inb(ha->io_addr + IPS_REG_HISR);
5451
5452 if (Isr == 0xFF)
5453 /* ?!?! Nothing really there */
5454 return (0);
5455
5456 if (Isr & IPS_BIT_SCE)
5457 return (1);
5458 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5459 /* status queue overflow or GHI */
5460 /* just clear the interrupt */
5461 outb(Isr, ha->io_addr + IPS_REG_HISR);
5462 }
5463
5464 return (0);
5465 }
5466
5467 /****************************************************************************/
5468 /* */
5469 /* Routine Name: ips_isintr_copperhead_memio */
5470 /* */
5471 /* Routine Description: */
5472 /* */
5473 /* Test to see if an interrupt is for us */
5474 /* */
5475 /****************************************************************************/
5476 static int
ips_isintr_copperhead_memio(ips_ha_t * ha)5477 ips_isintr_copperhead_memio(ips_ha_t * ha)
5478 {
5479 uint8_t Isr;
5480
5481 METHOD_TRACE("ips_isintr_memio", 2);
5482
5483 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5484
5485 if (Isr == 0xFF)
5486 /* ?!?! Nothing really there */
5487 return (0);
5488
5489 if (Isr & IPS_BIT_SCE)
5490 return (1);
5491 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5492 /* status queue overflow or GHI */
5493 /* just clear the interrupt */
5494 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5495 }
5496
5497 return (0);
5498 }
5499
5500 /****************************************************************************/
5501 /* */
5502 /* Routine Name: ips_isintr_morpheus */
5503 /* */
5504 /* Routine Description: */
5505 /* */
5506 /* Test to see if an interrupt is for us */
5507 /* */
5508 /****************************************************************************/
5509 static int
ips_isintr_morpheus(ips_ha_t * ha)5510 ips_isintr_morpheus(ips_ha_t * ha)
5511 {
5512 uint32_t Isr;
5513
5514 METHOD_TRACE("ips_isintr_morpheus", 2);
5515
5516 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5517
5518 if (Isr & IPS_BIT_I2O_OPQI)
5519 return (1);
5520 else
5521 return (0);
5522 }
5523
5524 /****************************************************************************/
5525 /* */
5526 /* Routine Name: ips_wait */
5527 /* */
5528 /* Routine Description: */
5529 /* */
5530 /* Wait for a command to complete */
5531 /* */
5532 /****************************************************************************/
5533 static int
ips_wait(ips_ha_t * ha,int time,int intr)5534 ips_wait(ips_ha_t * ha, int time, int intr)
5535 {
5536 int ret;
5537 int done;
5538
5539 METHOD_TRACE("ips_wait", 1);
5540
5541 ret = IPS_FAILURE;
5542 done = false;
5543
5544 time *= IPS_ONE_SEC; /* convert seconds */
5545
5546 while ((time > 0) && (!done)) {
5547 if (intr == IPS_INTR_ON) {
5548 if (!ha->waitflag) {
5549 ret = IPS_SUCCESS;
5550 done = true;
5551 break;
5552 }
5553 } else if (intr == IPS_INTR_IORL) {
5554 if (!ha->waitflag) {
5555 /*
5556 * controller generated an interrupt to
5557 * acknowledge completion of the command
5558 * and ips_intr() has serviced the interrupt.
5559 */
5560 ret = IPS_SUCCESS;
5561 done = true;
5562 break;
5563 }
5564
5565 /*
5566 * NOTE: we already have the io_request_lock so
5567 * even if we get an interrupt it won't get serviced
5568 * until after we finish.
5569 */
5570
5571 (*ha->func.intr) (ha);
5572 }
5573
5574 /* This looks like a very evil loop, but it only does this during start-up */
5575 udelay(1000);
5576 time--;
5577 }
5578
5579 return (ret);
5580 }
5581
5582 /****************************************************************************/
5583 /* */
5584 /* Routine Name: ips_write_driver_status */
5585 /* */
5586 /* Routine Description: */
5587 /* */
5588 /* Write OS/Driver version to Page 5 of the nvram on the controller */
5589 /* */
5590 /****************************************************************************/
5591 static int
ips_write_driver_status(ips_ha_t * ha,int intr)5592 ips_write_driver_status(ips_ha_t * ha, int intr)
5593 {
5594 METHOD_TRACE("ips_write_driver_status", 1);
5595
5596 if (!ips_readwrite_page5(ha, false, intr)) {
5597 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5598 "unable to read NVRAM page 5.\n");
5599
5600 return (0);
5601 }
5602
5603 /* check to make sure the page has a valid */
5604 /* signature */
5605 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5606 DEBUG_VAR(1,
5607 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5608 ips_name, ha->host_num, ha->nvram->signature);
5609 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5610 }
5611
5612 DEBUG_VAR(2,
5613 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5614 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5615 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5616 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5617 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5618 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5619 ha->nvram->bios_low[3]);
5620
5621 ips_get_bios_version(ha, intr);
5622
5623 /* change values (as needed) */
5624 ha->nvram->operating_system = IPS_OS_LINUX;
5625 ha->nvram->adapter_type = ha->ad_type;
5626 memcpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5627 memcpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5628 memcpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5629 memcpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5630
5631 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5632
5633 /* now update the page */
5634 if (!ips_readwrite_page5(ha, true, intr)) {
5635 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5636 "unable to write NVRAM page 5.\n");
5637
5638 return (0);
5639 }
5640
5641 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5642 ha->slot_num = ha->nvram->adapter_slot;
5643
5644 return (1);
5645 }
5646
5647 /****************************************************************************/
5648 /* */
5649 /* Routine Name: ips_read_adapter_status */
5650 /* */
5651 /* Routine Description: */
5652 /* */
5653 /* Do an Inquiry command to the adapter */
5654 /* */
5655 /****************************************************************************/
5656 static int
ips_read_adapter_status(ips_ha_t * ha,int intr)5657 ips_read_adapter_status(ips_ha_t * ha, int intr)
5658 {
5659 ips_scb_t *scb;
5660 int ret;
5661
5662 METHOD_TRACE("ips_read_adapter_status", 1);
5663
5664 scb = &ha->scbs[ha->max_cmds - 1];
5665
5666 ips_init_scb(ha, scb);
5667
5668 scb->timeout = ips_cmd_timeout;
5669 scb->cdb[0] = IPS_CMD_ENQUIRY;
5670
5671 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5672 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5673 scb->cmd.basic_io.sg_count = 0;
5674 scb->cmd.basic_io.lba = 0;
5675 scb->cmd.basic_io.sector_count = 0;
5676 scb->cmd.basic_io.log_drv = 0;
5677 scb->data_len = sizeof (*ha->enq);
5678 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5679
5680 /* send command */
5681 if (((ret =
5682 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5683 || (ret == IPS_SUCCESS_IMM)
5684 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5685 return (0);
5686
5687 return (1);
5688 }
5689
5690 /****************************************************************************/
5691 /* */
5692 /* Routine Name: ips_read_subsystem_parameters */
5693 /* */
5694 /* Routine Description: */
5695 /* */
5696 /* Read subsystem parameters from the adapter */
5697 /* */
5698 /****************************************************************************/
5699 static int
ips_read_subsystem_parameters(ips_ha_t * ha,int intr)5700 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5701 {
5702 ips_scb_t *scb;
5703 int ret;
5704
5705 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5706
5707 scb = &ha->scbs[ha->max_cmds - 1];
5708
5709 ips_init_scb(ha, scb);
5710
5711 scb->timeout = ips_cmd_timeout;
5712 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5713
5714 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5715 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5716 scb->cmd.basic_io.sg_count = 0;
5717 scb->cmd.basic_io.lba = 0;
5718 scb->cmd.basic_io.sector_count = 0;
5719 scb->cmd.basic_io.log_drv = 0;
5720 scb->data_len = sizeof (*ha->subsys);
5721 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5722
5723 /* send command */
5724 if (((ret =
5725 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5726 || (ret == IPS_SUCCESS_IMM)
5727 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5728 return (0);
5729
5730 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5731 return (1);
5732 }
5733
5734 /****************************************************************************/
5735 /* */
5736 /* Routine Name: ips_read_config */
5737 /* */
5738 /* Routine Description: */
5739 /* */
5740 /* Read the configuration on the adapter */
5741 /* */
5742 /****************************************************************************/
5743 static int
ips_read_config(ips_ha_t * ha,int intr)5744 ips_read_config(ips_ha_t * ha, int intr)
5745 {
5746 ips_scb_t *scb;
5747 int i;
5748 int ret;
5749
5750 METHOD_TRACE("ips_read_config", 1);
5751
5752 /* set defaults for initiator IDs */
5753 for (i = 0; i < 4; i++)
5754 ha->conf->init_id[i] = 7;
5755
5756 scb = &ha->scbs[ha->max_cmds - 1];
5757
5758 ips_init_scb(ha, scb);
5759
5760 scb->timeout = ips_cmd_timeout;
5761 scb->cdb[0] = IPS_CMD_READ_CONF;
5762
5763 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5764 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5765 scb->data_len = sizeof (*ha->conf);
5766 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5767
5768 /* send command */
5769 if (((ret =
5770 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5771 || (ret == IPS_SUCCESS_IMM)
5772 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5773
5774 memset(ha->conf, 0, sizeof (IPS_CONF));
5775
5776 /* reset initiator IDs */
5777 for (i = 0; i < 4; i++)
5778 ha->conf->init_id[i] = 7;
5779
5780 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5781 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5782 IPS_CMD_CMPLT_WERROR)
5783 return (1);
5784
5785 return (0);
5786 }
5787
5788 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5789 return (1);
5790 }
5791
5792 /****************************************************************************/
5793 /* */
5794 /* Routine Name: ips_readwrite_page5 */
5795 /* */
5796 /* Routine Description: */
5797 /* */
5798 /* Read nvram page 5 from the adapter */
5799 /* */
5800 /****************************************************************************/
5801 static int
ips_readwrite_page5(ips_ha_t * ha,int write,int intr)5802 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5803 {
5804 ips_scb_t *scb;
5805 int ret;
5806
5807 METHOD_TRACE("ips_readwrite_page5", 1);
5808
5809 scb = &ha->scbs[ha->max_cmds - 1];
5810
5811 ips_init_scb(ha, scb);
5812
5813 scb->timeout = ips_cmd_timeout;
5814 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5815
5816 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5817 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5818 scb->cmd.nvram.page = 5;
5819 scb->cmd.nvram.write = write;
5820 scb->cmd.nvram.reserved = 0;
5821 scb->cmd.nvram.reserved2 = 0;
5822 scb->data_len = sizeof (*ha->nvram);
5823 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5824 if (write)
5825 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5826
5827 /* issue the command */
5828 if (((ret =
5829 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5830 || (ret == IPS_SUCCESS_IMM)
5831 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5832
5833 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5834
5835 return (0);
5836 }
5837 if (!write)
5838 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5839 return (1);
5840 }
5841
5842 /****************************************************************************/
5843 /* */
5844 /* Routine Name: ips_clear_adapter */
5845 /* */
5846 /* Routine Description: */
5847 /* */
5848 /* Clear the stripe lock tables */
5849 /* */
5850 /****************************************************************************/
5851 static int
ips_clear_adapter(ips_ha_t * ha,int intr)5852 ips_clear_adapter(ips_ha_t * ha, int intr)
5853 {
5854 ips_scb_t *scb;
5855 int ret;
5856
5857 METHOD_TRACE("ips_clear_adapter", 1);
5858
5859 scb = &ha->scbs[ha->max_cmds - 1];
5860
5861 ips_init_scb(ha, scb);
5862
5863 scb->timeout = ips_reset_timeout;
5864 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5865
5866 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5867 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5868 scb->cmd.config_sync.channel = 0;
5869 scb->cmd.config_sync.source_target = IPS_POCL;
5870 scb->cmd.config_sync.reserved = 0;
5871 scb->cmd.config_sync.reserved2 = 0;
5872 scb->cmd.config_sync.reserved3 = 0;
5873
5874 /* issue command */
5875 if (((ret =
5876 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5877 || (ret == IPS_SUCCESS_IMM)
5878 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5879 return (0);
5880
5881 /* send unlock stripe command */
5882 ips_init_scb(ha, scb);
5883
5884 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5885 scb->timeout = ips_reset_timeout;
5886
5887 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5888 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5889 scb->cmd.unlock_stripe.log_drv = 0;
5890 scb->cmd.unlock_stripe.control = IPS_CSL;
5891 scb->cmd.unlock_stripe.reserved = 0;
5892 scb->cmd.unlock_stripe.reserved2 = 0;
5893 scb->cmd.unlock_stripe.reserved3 = 0;
5894
5895 /* issue command */
5896 if (((ret =
5897 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5898 || (ret == IPS_SUCCESS_IMM)
5899 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5900 return (0);
5901
5902 return (1);
5903 }
5904
5905 /****************************************************************************/
5906 /* */
5907 /* Routine Name: ips_ffdc_reset */
5908 /* */
5909 /* Routine Description: */
5910 /* */
5911 /* FFDC: write reset info */
5912 /* */
5913 /****************************************************************************/
5914 static void
ips_ffdc_reset(ips_ha_t * ha,int intr)5915 ips_ffdc_reset(ips_ha_t * ha, int intr)
5916 {
5917 ips_scb_t *scb;
5918
5919 METHOD_TRACE("ips_ffdc_reset", 1);
5920
5921 scb = &ha->scbs[ha->max_cmds - 1];
5922
5923 ips_init_scb(ha, scb);
5924
5925 scb->timeout = ips_cmd_timeout;
5926 scb->cdb[0] = IPS_CMD_FFDC;
5927 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5928 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5929 scb->cmd.ffdc.reset_count = ha->reset_count;
5930 scb->cmd.ffdc.reset_type = 0x80;
5931
5932 /* convert time to what the card wants */
5933 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5934
5935 /* issue command */
5936 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5937 }
5938
5939 /****************************************************************************/
5940 /* */
5941 /* Routine Name: ips_ffdc_time */
5942 /* */
5943 /* Routine Description: */
5944 /* */
5945 /* FFDC: write time info */
5946 /* */
5947 /****************************************************************************/
5948 static void
ips_ffdc_time(ips_ha_t * ha)5949 ips_ffdc_time(ips_ha_t * ha)
5950 {
5951 ips_scb_t *scb;
5952
5953 METHOD_TRACE("ips_ffdc_time", 1);
5954
5955 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5956
5957 scb = &ha->scbs[ha->max_cmds - 1];
5958
5959 ips_init_scb(ha, scb);
5960
5961 scb->timeout = ips_cmd_timeout;
5962 scb->cdb[0] = IPS_CMD_FFDC;
5963 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5964 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5965 scb->cmd.ffdc.reset_count = 0;
5966 scb->cmd.ffdc.reset_type = 0;
5967
5968 /* convert time to what the card wants */
5969 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5970
5971 /* issue command */
5972 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5973 }
5974
5975 /****************************************************************************/
5976 /* */
5977 /* Routine Name: ips_fix_ffdc_time */
5978 /* */
5979 /* Routine Description: */
5980 /* Adjust time_t to what the card wants */
5981 /* */
5982 /****************************************************************************/
5983 static void
ips_fix_ffdc_time(ips_ha_t * ha,ips_scb_t * scb,time64_t current_time)5984 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time)
5985 {
5986 struct tm tm;
5987
5988 METHOD_TRACE("ips_fix_ffdc_time", 1);
5989
5990 time64_to_tm(current_time, 0, &tm);
5991
5992 scb->cmd.ffdc.hour = tm.tm_hour;
5993 scb->cmd.ffdc.minute = tm.tm_min;
5994 scb->cmd.ffdc.second = tm.tm_sec;
5995 scb->cmd.ffdc.yearH = (tm.tm_year + 1900) / 100;
5996 scb->cmd.ffdc.yearL = tm.tm_year % 100;
5997 scb->cmd.ffdc.month = tm.tm_mon + 1;
5998 scb->cmd.ffdc.day = tm.tm_mday;
5999 }
6000
6001 /****************************************************************************
6002 * BIOS Flash Routines *
6003 ****************************************************************************/
6004
6005 /****************************************************************************/
6006 /* */
6007 /* Routine Name: ips_erase_bios */
6008 /* */
6009 /* Routine Description: */
6010 /* Erase the BIOS on the adapter */
6011 /* */
6012 /****************************************************************************/
6013 static int
ips_erase_bios(ips_ha_t * ha)6014 ips_erase_bios(ips_ha_t * ha)
6015 {
6016 int timeout;
6017 uint8_t status = 0;
6018
6019 METHOD_TRACE("ips_erase_bios", 1);
6020
6021 status = 0;
6022
6023 /* Clear the status register */
6024 outl(0, ha->io_addr + IPS_REG_FLAP);
6025 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6026 udelay(25); /* 25 us */
6027
6028 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6029 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6030 udelay(25); /* 25 us */
6031
6032 /* Erase Setup */
6033 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6034 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6035 udelay(25); /* 25 us */
6036
6037 /* Erase Confirm */
6038 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6039 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6040 udelay(25); /* 25 us */
6041
6042 /* Erase Status */
6043 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6044 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6045 udelay(25); /* 25 us */
6046
6047 timeout = 80000; /* 80 seconds */
6048
6049 while (timeout > 0) {
6050 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6051 outl(0, ha->io_addr + IPS_REG_FLAP);
6052 udelay(25); /* 25 us */
6053 }
6054
6055 status = inb(ha->io_addr + IPS_REG_FLDP);
6056
6057 if (status & 0x80)
6058 break;
6059
6060 MDELAY(1);
6061 timeout--;
6062 }
6063
6064 /* check for timeout */
6065 if (timeout <= 0) {
6066 /* timeout */
6067
6068 /* try to suspend the erase */
6069 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6070 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6071 udelay(25); /* 25 us */
6072
6073 /* wait for 10 seconds */
6074 timeout = 10000;
6075 while (timeout > 0) {
6076 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6077 outl(0, ha->io_addr + IPS_REG_FLAP);
6078 udelay(25); /* 25 us */
6079 }
6080
6081 status = inb(ha->io_addr + IPS_REG_FLDP);
6082
6083 if (status & 0xC0)
6084 break;
6085
6086 MDELAY(1);
6087 timeout--;
6088 }
6089
6090 return (1);
6091 }
6092
6093 /* check for valid VPP */
6094 if (status & 0x08)
6095 /* VPP failure */
6096 return (1);
6097
6098 /* check for successful flash */
6099 if (status & 0x30)
6100 /* sequence error */
6101 return (1);
6102
6103 /* Otherwise, we were successful */
6104 /* clear status */
6105 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6106 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6107 udelay(25); /* 25 us */
6108
6109 /* enable reads */
6110 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6111 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6112 udelay(25); /* 25 us */
6113
6114 return (0);
6115 }
6116
6117 /****************************************************************************/
6118 /* */
6119 /* Routine Name: ips_erase_bios_memio */
6120 /* */
6121 /* Routine Description: */
6122 /* Erase the BIOS on the adapter */
6123 /* */
6124 /****************************************************************************/
6125 static int
ips_erase_bios_memio(ips_ha_t * ha)6126 ips_erase_bios_memio(ips_ha_t * ha)
6127 {
6128 int timeout;
6129 uint8_t status;
6130
6131 METHOD_TRACE("ips_erase_bios_memio", 1);
6132
6133 status = 0;
6134
6135 /* Clear the status register */
6136 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6137 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6138 udelay(25); /* 25 us */
6139
6140 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6141 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6142 udelay(25); /* 25 us */
6143
6144 /* Erase Setup */
6145 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6146 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6147 udelay(25); /* 25 us */
6148
6149 /* Erase Confirm */
6150 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6151 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6152 udelay(25); /* 25 us */
6153
6154 /* Erase Status */
6155 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6156 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6157 udelay(25); /* 25 us */
6158
6159 timeout = 80000; /* 80 seconds */
6160
6161 while (timeout > 0) {
6162 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6163 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6164 udelay(25); /* 25 us */
6165 }
6166
6167 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6168
6169 if (status & 0x80)
6170 break;
6171
6172 MDELAY(1);
6173 timeout--;
6174 }
6175
6176 /* check for timeout */
6177 if (timeout <= 0) {
6178 /* timeout */
6179
6180 /* try to suspend the erase */
6181 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6182 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6183 udelay(25); /* 25 us */
6184
6185 /* wait for 10 seconds */
6186 timeout = 10000;
6187 while (timeout > 0) {
6188 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6189 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6190 udelay(25); /* 25 us */
6191 }
6192
6193 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6194
6195 if (status & 0xC0)
6196 break;
6197
6198 MDELAY(1);
6199 timeout--;
6200 }
6201
6202 return (1);
6203 }
6204
6205 /* check for valid VPP */
6206 if (status & 0x08)
6207 /* VPP failure */
6208 return (1);
6209
6210 /* check for successful flash */
6211 if (status & 0x30)
6212 /* sequence error */
6213 return (1);
6214
6215 /* Otherwise, we were successful */
6216 /* clear status */
6217 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6218 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6219 udelay(25); /* 25 us */
6220
6221 /* enable reads */
6222 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6223 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6224 udelay(25); /* 25 us */
6225
6226 return (0);
6227 }
6228
6229 /****************************************************************************/
6230 /* */
6231 /* Routine Name: ips_program_bios */
6232 /* */
6233 /* Routine Description: */
6234 /* Program the BIOS on the adapter */
6235 /* */
6236 /****************************************************************************/
6237 static int
ips_program_bios(ips_ha_t * ha,char * buffer,uint32_t buffersize,uint32_t offset)6238 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6239 uint32_t offset)
6240 {
6241 int i;
6242 int timeout;
6243 uint8_t status = 0;
6244
6245 METHOD_TRACE("ips_program_bios", 1);
6246
6247 status = 0;
6248
6249 for (i = 0; i < buffersize; i++) {
6250 /* write a byte */
6251 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6252 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6253 udelay(25); /* 25 us */
6254
6255 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6256 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6257 udelay(25); /* 25 us */
6258
6259 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6260 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6261 udelay(25); /* 25 us */
6262
6263 /* wait up to one second */
6264 timeout = 1000;
6265 while (timeout > 0) {
6266 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6267 outl(0, ha->io_addr + IPS_REG_FLAP);
6268 udelay(25); /* 25 us */
6269 }
6270
6271 status = inb(ha->io_addr + IPS_REG_FLDP);
6272
6273 if (status & 0x80)
6274 break;
6275
6276 MDELAY(1);
6277 timeout--;
6278 }
6279
6280 if (timeout == 0) {
6281 /* timeout error */
6282 outl(0, ha->io_addr + IPS_REG_FLAP);
6283 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6284 udelay(25); /* 25 us */
6285
6286 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6287 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6288 udelay(25); /* 25 us */
6289
6290 return (1);
6291 }
6292
6293 /* check the status */
6294 if (status & 0x18) {
6295 /* programming error */
6296 outl(0, ha->io_addr + IPS_REG_FLAP);
6297 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6298 udelay(25); /* 25 us */
6299
6300 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6301 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6302 udelay(25); /* 25 us */
6303
6304 return (1);
6305 }
6306 } /* end for */
6307
6308 /* Enable reading */
6309 outl(0, ha->io_addr + IPS_REG_FLAP);
6310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6311 udelay(25); /* 25 us */
6312
6313 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6314 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6315 udelay(25); /* 25 us */
6316
6317 return (0);
6318 }
6319
6320 /****************************************************************************/
6321 /* */
6322 /* Routine Name: ips_program_bios_memio */
6323 /* */
6324 /* Routine Description: */
6325 /* Program the BIOS on the adapter */
6326 /* */
6327 /****************************************************************************/
6328 static int
ips_program_bios_memio(ips_ha_t * ha,char * buffer,uint32_t buffersize,uint32_t offset)6329 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6330 uint32_t offset)
6331 {
6332 int i;
6333 int timeout;
6334 uint8_t status = 0;
6335
6336 METHOD_TRACE("ips_program_bios_memio", 1);
6337
6338 status = 0;
6339
6340 for (i = 0; i < buffersize; i++) {
6341 /* write a byte */
6342 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6343 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6344 udelay(25); /* 25 us */
6345
6346 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6347 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6348 udelay(25); /* 25 us */
6349
6350 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6351 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6352 udelay(25); /* 25 us */
6353
6354 /* wait up to one second */
6355 timeout = 1000;
6356 while (timeout > 0) {
6357 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6358 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6359 udelay(25); /* 25 us */
6360 }
6361
6362 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6363
6364 if (status & 0x80)
6365 break;
6366
6367 MDELAY(1);
6368 timeout--;
6369 }
6370
6371 if (timeout == 0) {
6372 /* timeout error */
6373 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6374 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6375 udelay(25); /* 25 us */
6376
6377 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6378 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6379 udelay(25); /* 25 us */
6380
6381 return (1);
6382 }
6383
6384 /* check the status */
6385 if (status & 0x18) {
6386 /* programming error */
6387 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6388 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6389 udelay(25); /* 25 us */
6390
6391 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6392 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6393 udelay(25); /* 25 us */
6394
6395 return (1);
6396 }
6397 } /* end for */
6398
6399 /* Enable reading */
6400 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6401 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6402 udelay(25); /* 25 us */
6403
6404 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6405 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6406 udelay(25); /* 25 us */
6407
6408 return (0);
6409 }
6410
6411 /****************************************************************************/
6412 /* */
6413 /* Routine Name: ips_verify_bios */
6414 /* */
6415 /* Routine Description: */
6416 /* Verify the BIOS on the adapter */
6417 /* */
6418 /****************************************************************************/
6419 static int
ips_verify_bios(ips_ha_t * ha,char * buffer,uint32_t buffersize,uint32_t offset)6420 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6421 uint32_t offset)
6422 {
6423 uint8_t checksum;
6424 int i;
6425
6426 METHOD_TRACE("ips_verify_bios", 1);
6427
6428 /* test 1st byte */
6429 outl(0, ha->io_addr + IPS_REG_FLAP);
6430 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6431 udelay(25); /* 25 us */
6432
6433 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6434 return (1);
6435
6436 outl(1, ha->io_addr + IPS_REG_FLAP);
6437 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6438 udelay(25); /* 25 us */
6439 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6440 return (1);
6441
6442 checksum = 0xff;
6443 for (i = 2; i < buffersize; i++) {
6444
6445 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6446 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6447 udelay(25); /* 25 us */
6448
6449 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6450 }
6451
6452 if (checksum != 0)
6453 /* failure */
6454 return (1);
6455 else
6456 /* success */
6457 return (0);
6458 }
6459
6460 /****************************************************************************/
6461 /* */
6462 /* Routine Name: ips_verify_bios_memio */
6463 /* */
6464 /* Routine Description: */
6465 /* Verify the BIOS on the adapter */
6466 /* */
6467 /****************************************************************************/
6468 static int
ips_verify_bios_memio(ips_ha_t * ha,char * buffer,uint32_t buffersize,uint32_t offset)6469 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6470 uint32_t offset)
6471 {
6472 uint8_t checksum;
6473 int i;
6474
6475 METHOD_TRACE("ips_verify_bios_memio", 1);
6476
6477 /* test 1st byte */
6478 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6479 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6480 udelay(25); /* 25 us */
6481
6482 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6483 return (1);
6484
6485 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6486 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6487 udelay(25); /* 25 us */
6488 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6489 return (1);
6490
6491 checksum = 0xff;
6492 for (i = 2; i < buffersize; i++) {
6493
6494 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6495 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6496 udelay(25); /* 25 us */
6497
6498 checksum =
6499 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6500 }
6501
6502 if (checksum != 0)
6503 /* failure */
6504 return (1);
6505 else
6506 /* success */
6507 return (0);
6508 }
6509
6510 /****************************************************************************/
6511 /* */
6512 /* Routine Name: ips_abort_init */
6513 /* */
6514 /* Routine Description: */
6515 /* cleanup routine for a failed adapter initialization */
6516 /****************************************************************************/
6517 static int
ips_abort_init(ips_ha_t * ha,int index)6518 ips_abort_init(ips_ha_t * ha, int index)
6519 {
6520 ha->active = 0;
6521 ips_free(ha);
6522 ips_ha[index] = NULL;
6523 ips_sh[index] = NULL;
6524 return -1;
6525 }
6526
6527 /****************************************************************************/
6528 /* */
6529 /* Routine Name: ips_shift_controllers */
6530 /* */
6531 /* Routine Description: */
6532 /* helper function for ordering adapters */
6533 /****************************************************************************/
6534 static void
ips_shift_controllers(int lowindex,int highindex)6535 ips_shift_controllers(int lowindex, int highindex)
6536 {
6537 ips_ha_t *ha_sav = ips_ha[highindex];
6538 struct Scsi_Host *sh_sav = ips_sh[highindex];
6539 int i;
6540
6541 for (i = highindex; i > lowindex; i--) {
6542 ips_ha[i] = ips_ha[i - 1];
6543 ips_sh[i] = ips_sh[i - 1];
6544 ips_ha[i]->host_num = i;
6545 }
6546 ha_sav->host_num = lowindex;
6547 ips_ha[lowindex] = ha_sav;
6548 ips_sh[lowindex] = sh_sav;
6549 }
6550
6551 /****************************************************************************/
6552 /* */
6553 /* Routine Name: ips_order_controllers */
6554 /* */
6555 /* Routine Description: */
6556 /* place controllers is the "proper" boot order */
6557 /****************************************************************************/
6558 static void
ips_order_controllers(void)6559 ips_order_controllers(void)
6560 {
6561 int i, j, tmp, position = 0;
6562 IPS_NVRAM_P5 *nvram;
6563 if (!ips_ha[0])
6564 return;
6565 nvram = ips_ha[0]->nvram;
6566
6567 if (nvram->adapter_order[0]) {
6568 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6569 for (j = position; j < ips_num_controllers; j++) {
6570 switch (ips_ha[j]->ad_type) {
6571 case IPS_ADTYPE_SERVERAID6M:
6572 case IPS_ADTYPE_SERVERAID7M:
6573 if (nvram->adapter_order[i] == 'M') {
6574 ips_shift_controllers(position,
6575 j);
6576 position++;
6577 }
6578 break;
6579 case IPS_ADTYPE_SERVERAID4L:
6580 case IPS_ADTYPE_SERVERAID4M:
6581 case IPS_ADTYPE_SERVERAID4MX:
6582 case IPS_ADTYPE_SERVERAID4LX:
6583 if (nvram->adapter_order[i] == 'N') {
6584 ips_shift_controllers(position,
6585 j);
6586 position++;
6587 }
6588 break;
6589 case IPS_ADTYPE_SERVERAID6I:
6590 case IPS_ADTYPE_SERVERAID5I2:
6591 case IPS_ADTYPE_SERVERAID5I1:
6592 case IPS_ADTYPE_SERVERAID7k:
6593 if (nvram->adapter_order[i] == 'S') {
6594 ips_shift_controllers(position,
6595 j);
6596 position++;
6597 }
6598 break;
6599 case IPS_ADTYPE_SERVERAID:
6600 case IPS_ADTYPE_SERVERAID2:
6601 case IPS_ADTYPE_NAVAJO:
6602 case IPS_ADTYPE_KIOWA:
6603 case IPS_ADTYPE_SERVERAID3L:
6604 case IPS_ADTYPE_SERVERAID3:
6605 case IPS_ADTYPE_SERVERAID4H:
6606 if (nvram->adapter_order[i] == 'A') {
6607 ips_shift_controllers(position,
6608 j);
6609 position++;
6610 }
6611 break;
6612 default:
6613 break;
6614 }
6615 }
6616 }
6617 /* if adapter_order[0], then ordering is complete */
6618 return;
6619 }
6620 /* old bios, use older ordering */
6621 tmp = 0;
6622 for (i = position; i < ips_num_controllers; i++) {
6623 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6624 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6625 ips_shift_controllers(position, i);
6626 position++;
6627 tmp = 1;
6628 }
6629 }
6630 /* if there were no 5I cards, then don't do any extra ordering */
6631 if (!tmp)
6632 return;
6633 for (i = position; i < ips_num_controllers; i++) {
6634 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6635 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6636 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6637 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6638 ips_shift_controllers(position, i);
6639 position++;
6640 }
6641 }
6642
6643 return;
6644 }
6645
6646 /****************************************************************************/
6647 /* */
6648 /* Routine Name: ips_register_scsi */
6649 /* */
6650 /* Routine Description: */
6651 /* perform any registration and setup with the scsi layer */
6652 /****************************************************************************/
6653 static int
ips_register_scsi(int index)6654 ips_register_scsi(int index)
6655 {
6656 struct Scsi_Host *sh;
6657 ips_ha_t *ha, *oldha = ips_ha[index];
6658 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6659 if (!sh) {
6660 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6661 "Unable to register controller with SCSI subsystem\n");
6662 return -1;
6663 }
6664 ha = IPS_HA(sh);
6665 memcpy(ha, oldha, sizeof (ips_ha_t));
6666 free_irq(oldha->pcidev->irq, oldha);
6667 /* Install the interrupt handler with the new ha */
6668 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6669 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6670 "Unable to install interrupt handler\n");
6671 goto err_out_sh;
6672 }
6673
6674 kfree(oldha);
6675
6676 /* Store away needed values for later use */
6677 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6678 sh->sg_tablesize = sh->hostt->sg_tablesize;
6679 sh->can_queue = sh->hostt->can_queue;
6680 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6681 sh->max_sectors = 128;
6682
6683 sh->max_id = ha->ntargets;
6684 sh->max_lun = ha->nlun;
6685 sh->max_channel = ha->nbus - 1;
6686 sh->can_queue = ha->max_cmds - 1;
6687
6688 if (scsi_add_host(sh, &ha->pcidev->dev))
6689 goto err_out;
6690
6691 ips_sh[index] = sh;
6692 ips_ha[index] = ha;
6693
6694 scsi_scan_host(sh);
6695
6696 return 0;
6697
6698 err_out:
6699 free_irq(ha->pcidev->irq, ha);
6700 err_out_sh:
6701 scsi_host_put(sh);
6702 return -1;
6703 }
6704
6705 /*---------------------------------------------------------------------------*/
6706 /* Routine Name: ips_remove_device */
6707 /* */
6708 /* Routine Description: */
6709 /* Remove one Adapter ( Hot Plugging ) */
6710 /*---------------------------------------------------------------------------*/
6711 static void
ips_remove_device(struct pci_dev * pci_dev)6712 ips_remove_device(struct pci_dev *pci_dev)
6713 {
6714 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6715
6716 pci_set_drvdata(pci_dev, NULL);
6717
6718 ips_release(sh);
6719
6720 pci_release_regions(pci_dev);
6721 pci_disable_device(pci_dev);
6722 }
6723
6724 /****************************************************************************/
6725 /* */
6726 /* Routine Name: ips_module_init */
6727 /* */
6728 /* Routine Description: */
6729 /* function called on module load */
6730 /****************************************************************************/
6731 static int __init
ips_module_init(void)6732 ips_module_init(void)
6733 {
6734 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6735 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6736 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6737 #endif
6738
6739 if (pci_register_driver(&ips_pci_driver) < 0)
6740 return -ENODEV;
6741 ips_driver_template.module = THIS_MODULE;
6742 ips_order_controllers();
6743 if (!ips_detect(&ips_driver_template)) {
6744 pci_unregister_driver(&ips_pci_driver);
6745 return -ENODEV;
6746 }
6747 register_reboot_notifier(&ips_notifier);
6748 return 0;
6749 }
6750
6751 /****************************************************************************/
6752 /* */
6753 /* Routine Name: ips_module_exit */
6754 /* */
6755 /* Routine Description: */
6756 /* function called on module unload */
6757 /****************************************************************************/
6758 static void __exit
ips_module_exit(void)6759 ips_module_exit(void)
6760 {
6761 pci_unregister_driver(&ips_pci_driver);
6762 unregister_reboot_notifier(&ips_notifier);
6763 }
6764
6765 module_init(ips_module_init);
6766 module_exit(ips_module_exit);
6767
6768 /*---------------------------------------------------------------------------*/
6769 /* Routine Name: ips_insert_device */
6770 /* */
6771 /* Routine Description: */
6772 /* Add One Adapter ( Hot Plug ) */
6773 /* */
6774 /* Return Value: */
6775 /* 0 if Successful, else non-zero */
6776 /*---------------------------------------------------------------------------*/
6777 static int
ips_insert_device(struct pci_dev * pci_dev,const struct pci_device_id * ent)6778 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6779 {
6780 int index = -1;
6781 int rc;
6782
6783 METHOD_TRACE("ips_insert_device", 1);
6784 rc = pci_enable_device(pci_dev);
6785 if (rc)
6786 return rc;
6787
6788 rc = pci_request_regions(pci_dev, "ips");
6789 if (rc)
6790 goto err_out;
6791
6792 rc = ips_init_phase1(pci_dev, &index);
6793 if (rc == SUCCESS)
6794 rc = ips_init_phase2(index);
6795
6796 if (ips_hotplug)
6797 if (ips_register_scsi(index)) {
6798 ips_free(ips_ha[index]);
6799 rc = -1;
6800 }
6801
6802 if (rc == SUCCESS)
6803 ips_num_controllers++;
6804
6805 ips_next_controller = ips_num_controllers;
6806
6807 if (rc < 0) {
6808 rc = -ENODEV;
6809 goto err_out_regions;
6810 }
6811
6812 pci_set_drvdata(pci_dev, ips_sh[index]);
6813 return 0;
6814
6815 err_out_regions:
6816 pci_release_regions(pci_dev);
6817 err_out:
6818 pci_disable_device(pci_dev);
6819 return rc;
6820 }
6821
6822 /*---------------------------------------------------------------------------*/
6823 /* Routine Name: ips_init_phase1 */
6824 /* */
6825 /* Routine Description: */
6826 /* Adapter Initialization */
6827 /* */
6828 /* Return Value: */
6829 /* 0 if Successful, else non-zero */
6830 /*---------------------------------------------------------------------------*/
6831 static int
ips_init_phase1(struct pci_dev * pci_dev,int * indexPtr)6832 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6833 {
6834 ips_ha_t *ha;
6835 uint32_t io_addr;
6836 uint32_t mem_addr;
6837 uint32_t io_len;
6838 uint32_t mem_len;
6839 int j;
6840 int index;
6841 dma_addr_t dma_address;
6842 char __iomem *ioremap_ptr;
6843 char __iomem *mem_ptr;
6844 uint32_t IsDead;
6845
6846 METHOD_TRACE("ips_init_phase1", 1);
6847 index = IPS_MAX_ADAPTERS;
6848 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6849 if (ips_ha[j] == NULL) {
6850 index = j;
6851 break;
6852 }
6853 }
6854
6855 if (index >= IPS_MAX_ADAPTERS)
6856 return -1;
6857
6858 /* Init MEM/IO addresses to 0 */
6859 mem_addr = 0;
6860 io_addr = 0;
6861 mem_len = 0;
6862 io_len = 0;
6863
6864 for (j = 0; j < 2; j++) {
6865 if (!pci_resource_start(pci_dev, j))
6866 break;
6867
6868 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6869 io_addr = pci_resource_start(pci_dev, j);
6870 io_len = pci_resource_len(pci_dev, j);
6871 } else {
6872 mem_addr = pci_resource_start(pci_dev, j);
6873 mem_len = pci_resource_len(pci_dev, j);
6874 }
6875 }
6876
6877 /* setup memory mapped area (if applicable) */
6878 if (mem_addr) {
6879 uint32_t base;
6880 uint32_t offs;
6881
6882 base = mem_addr & PAGE_MASK;
6883 offs = mem_addr - base;
6884 ioremap_ptr = ioremap(base, PAGE_SIZE);
6885 if (!ioremap_ptr)
6886 return -1;
6887 mem_ptr = ioremap_ptr + offs;
6888 } else {
6889 ioremap_ptr = NULL;
6890 mem_ptr = NULL;
6891 }
6892
6893 /* found a controller */
6894 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
6895 if (ha == NULL) {
6896 IPS_PRINTK(KERN_WARNING, pci_dev,
6897 "Unable to allocate temporary ha struct\n");
6898 return -1;
6899 }
6900
6901 ips_sh[index] = NULL;
6902 ips_ha[index] = ha;
6903 ha->active = 1;
6904
6905 /* Store info in HA structure */
6906 ha->io_addr = io_addr;
6907 ha->io_len = io_len;
6908 ha->mem_addr = mem_addr;
6909 ha->mem_len = mem_len;
6910 ha->mem_ptr = mem_ptr;
6911 ha->ioremap_ptr = ioremap_ptr;
6912 ha->host_num = (uint32_t) index;
6913 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6914 ha->pcidev = pci_dev;
6915
6916 /*
6917 * Set the pci_dev's dma_mask. Not all adapters support 64bit
6918 * addressing so don't enable it if the adapter can't support
6919 * it! Also, don't use 64bit addressing if dma addresses
6920 * are guaranteed to be < 4G.
6921 */
6922 if (sizeof(dma_addr_t) > 4 && IPS_HAS_ENH_SGLIST(ha) &&
6923 !dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(64))) {
6924 (ha)->flags |= IPS_HA_ENH_SG;
6925 } else {
6926 if (dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) {
6927 printk(KERN_WARNING "Unable to set DMA Mask\n");
6928 return ips_abort_init(ha, index);
6929 }
6930 }
6931 if(ips_cd_boot && !ips_FlashData){
6932 ips_FlashData = dma_alloc_coherent(&pci_dev->dev,
6933 PAGE_SIZE << 7, &ips_flashbusaddr, GFP_KERNEL);
6934 }
6935
6936 ha->enq = dma_alloc_coherent(&pci_dev->dev, sizeof (IPS_ENQ),
6937 &ha->enq_busaddr, GFP_KERNEL);
6938 if (!ha->enq) {
6939 IPS_PRINTK(KERN_WARNING, pci_dev,
6940 "Unable to allocate host inquiry structure\n");
6941 return ips_abort_init(ha, index);
6942 }
6943
6944 ha->adapt = dma_alloc_coherent(&pci_dev->dev,
6945 sizeof (IPS_ADAPTER) + sizeof (IPS_IO_CMD),
6946 &dma_address, GFP_KERNEL);
6947 if (!ha->adapt) {
6948 IPS_PRINTK(KERN_WARNING, pci_dev,
6949 "Unable to allocate host adapt & dummy structures\n");
6950 return ips_abort_init(ha, index);
6951 }
6952 ha->adapt->hw_status_start = dma_address;
6953 ha->dummy = (void *) (ha->adapt + 1);
6954
6955
6956
6957 ha->logical_drive_info = dma_alloc_coherent(&pci_dev->dev,
6958 sizeof (IPS_LD_INFO), &dma_address, GFP_KERNEL);
6959 if (!ha->logical_drive_info) {
6960 IPS_PRINTK(KERN_WARNING, pci_dev,
6961 "Unable to allocate logical drive info structure\n");
6962 return ips_abort_init(ha, index);
6963 }
6964 ha->logical_drive_info_dma_addr = dma_address;
6965
6966
6967 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
6968
6969 if (!ha->conf) {
6970 IPS_PRINTK(KERN_WARNING, pci_dev,
6971 "Unable to allocate host conf structure\n");
6972 return ips_abort_init(ha, index);
6973 }
6974
6975 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
6976
6977 if (!ha->nvram) {
6978 IPS_PRINTK(KERN_WARNING, pci_dev,
6979 "Unable to allocate host NVRAM structure\n");
6980 return ips_abort_init(ha, index);
6981 }
6982
6983 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
6984
6985 if (!ha->subsys) {
6986 IPS_PRINTK(KERN_WARNING, pci_dev,
6987 "Unable to allocate host subsystem structure\n");
6988 return ips_abort_init(ha, index);
6989 }
6990
6991 /* the ioctl buffer is now used during adapter initialization, so its
6992 * successful allocation is now required */
6993 if (ips_ioctlsize < PAGE_SIZE)
6994 ips_ioctlsize = PAGE_SIZE;
6995
6996 ha->ioctl_data = dma_alloc_coherent(&pci_dev->dev, ips_ioctlsize,
6997 &ha->ioctl_busaddr, GFP_KERNEL);
6998 ha->ioctl_len = ips_ioctlsize;
6999 if (!ha->ioctl_data) {
7000 IPS_PRINTK(KERN_WARNING, pci_dev,
7001 "Unable to allocate IOCTL data\n");
7002 return ips_abort_init(ha, index);
7003 }
7004
7005 /*
7006 * Setup Functions
7007 */
7008 ips_setup_funclist(ha);
7009
7010 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7011 /* If Morpheus appears dead, reset it */
7012 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7013 if (IsDead == 0xDEADBEEF) {
7014 ips_reset_morpheus(ha);
7015 }
7016 }
7017
7018 /*
7019 * Initialize the card if it isn't already
7020 */
7021
7022 if (!(*ha->func.isinit) (ha)) {
7023 if (!(*ha->func.init) (ha)) {
7024 /*
7025 * Initialization failed
7026 */
7027 IPS_PRINTK(KERN_WARNING, pci_dev,
7028 "Unable to initialize controller\n");
7029 return ips_abort_init(ha, index);
7030 }
7031 }
7032
7033 *indexPtr = index;
7034 return SUCCESS;
7035 }
7036
7037 /*---------------------------------------------------------------------------*/
7038 /* Routine Name: ips_init_phase2 */
7039 /* */
7040 /* Routine Description: */
7041 /* Adapter Initialization Phase 2 */
7042 /* */
7043 /* Return Value: */
7044 /* 0 if Successful, else non-zero */
7045 /*---------------------------------------------------------------------------*/
7046 static int
ips_init_phase2(int index)7047 ips_init_phase2(int index)
7048 {
7049 ips_ha_t *ha;
7050
7051 ha = ips_ha[index];
7052
7053 METHOD_TRACE("ips_init_phase2", 1);
7054 if (!ha->active) {
7055 ips_ha[index] = NULL;
7056 return -1;
7057 }
7058
7059 /* Install the interrupt handler */
7060 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7061 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7062 "Unable to install interrupt handler\n");
7063 return ips_abort_init(ha, index);
7064 }
7065
7066 /*
7067 * Allocate a temporary SCB for initialization
7068 */
7069 ha->max_cmds = 1;
7070 if (!ips_allocatescbs(ha)) {
7071 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7072 "Unable to allocate a CCB\n");
7073 free_irq(ha->pcidev->irq, ha);
7074 return ips_abort_init(ha, index);
7075 }
7076
7077 if (!ips_hainit(ha)) {
7078 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7079 "Unable to initialize controller\n");
7080 free_irq(ha->pcidev->irq, ha);
7081 return ips_abort_init(ha, index);
7082 }
7083 /* Free the temporary SCB */
7084 ips_deallocatescbs(ha, 1);
7085
7086 /* allocate CCBs */
7087 if (!ips_allocatescbs(ha)) {
7088 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7089 "Unable to allocate CCBs\n");
7090 free_irq(ha->pcidev->irq, ha);
7091 return ips_abort_init(ha, index);
7092 }
7093
7094 return SUCCESS;
7095 }
7096
7097 MODULE_LICENSE("GPL");
7098 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7099 MODULE_VERSION(IPS_VER_STRING);
7100