1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2013 Xilinx Inc.
4  */
5 
6 #ifndef _ZYNQ_CLK_H_
7 #define _ZYNQ_CLK_H_
8 
9 enum zynq_clk {
10 	armpll_clk, ddrpll_clk, iopll_clk,
11 	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
12 	ddr2x_clk, ddr3x_clk, dci_clk,
13 	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
14 	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
15 	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
16 	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
17 	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
18 	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
19 	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
20 	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
21 
22 #endif
23