1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 */
6
7 #ifndef AMD_IOMMU_H
8 #define AMD_IOMMU_H
9
10 #include <linux/iommu.h>
11
12 #include "amd_iommu_types.h"
13
14 irqreturn_t amd_iommu_int_thread(int irq, void *data);
15 irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data);
16 irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data);
17 irqreturn_t amd_iommu_int_thread_galog(int irq, void *data);
18 irqreturn_t amd_iommu_int_handler(int irq, void *data);
19 void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
20 void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
21 void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
22 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
23 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
24
25 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
26 void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
27 #else
amd_iommu_debugfs_setup(struct amd_iommu * iommu)28 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
29 #endif
30
31 /* Needed for interrupt remapping */
32 int amd_iommu_prepare(void);
33 int amd_iommu_enable(void);
34 void amd_iommu_disable(void);
35 int amd_iommu_reenable(int mode);
36 int amd_iommu_enable_faulting(void);
37 extern int amd_iommu_guest_ir;
38 extern enum io_pgtable_fmt amd_iommu_pgtable;
39 extern int amd_iommu_gpt_level;
40
41 /* IOMMUv2 specific functions */
42 struct iommu_domain;
43
44 bool amd_iommu_v2_supported(void);
45 struct amd_iommu *get_amd_iommu(unsigned int idx);
46 u8 amd_iommu_pc_get_max_banks(unsigned int idx);
47 bool amd_iommu_pc_supported(void);
48 u8 amd_iommu_pc_get_max_counters(unsigned int idx);
49 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
50 u8 fxn, u64 *value);
51 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
52 u8 fxn, u64 *value);
53
54 int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
55 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
56 void amd_iommu_domain_direct_map(struct iommu_domain *dom);
57 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
58 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);
59 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
60 void amd_iommu_domain_update(struct protection_domain *domain);
61 void amd_iommu_domain_flush_complete(struct protection_domain *domain);
62 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
63 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
64 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
65 unsigned long cr3);
66 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
67
68 #ifdef CONFIG_IRQ_REMAP
69 int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
70 #else
amd_iommu_create_irq_domain(struct amd_iommu * iommu)71 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
72 {
73 return 0;
74 }
75 #endif
76
77 #define PPR_SUCCESS 0x0
78 #define PPR_INVALID 0x1
79 #define PPR_FAILURE 0xf
80
81 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
82 int status, int tag);
83
is_rd890_iommu(struct pci_dev * pdev)84 static inline bool is_rd890_iommu(struct pci_dev *pdev)
85 {
86 return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
87 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
88 }
89
iommu_feature(struct amd_iommu * iommu,u64 mask)90 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
91 {
92 return !!(iommu->features & mask);
93 }
94
iommu_virt_to_phys(void * vaddr)95 static inline u64 iommu_virt_to_phys(void *vaddr)
96 {
97 return (u64)__sme_set(virt_to_phys(vaddr));
98 }
99
iommu_phys_to_virt(unsigned long paddr)100 static inline void *iommu_phys_to_virt(unsigned long paddr)
101 {
102 return phys_to_virt(__sme_clr(paddr));
103 }
104
105 static inline
amd_iommu_domain_set_pt_root(struct protection_domain * domain,u64 root)106 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
107 {
108 atomic64_set(&domain->iop.pt_root, root);
109 domain->iop.root = (u64 *)(root & PAGE_MASK);
110 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
111 }
112
113 static inline
amd_iommu_domain_clr_pt_root(struct protection_domain * domain)114 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
115 {
116 amd_iommu_domain_set_pt_root(domain, 0);
117 }
118
get_pci_sbdf_id(struct pci_dev * pdev)119 static inline int get_pci_sbdf_id(struct pci_dev *pdev)
120 {
121 int seg = pci_domain_nr(pdev->bus);
122 u16 devid = pci_dev_id(pdev);
123
124 return PCI_SEG_DEVID_TO_SBDF(seg, devid);
125 }
126
alloc_pgtable_page(int nid,gfp_t gfp)127 static inline void *alloc_pgtable_page(int nid, gfp_t gfp)
128 {
129 struct page *page;
130
131 page = alloc_pages_node(nid, gfp | __GFP_ZERO, 0);
132 return page ? page_address(page) : NULL;
133 }
134
135 bool translation_pre_enabled(struct amd_iommu *iommu);
136 bool amd_iommu_is_attach_deferred(struct device *dev);
137 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
138
139 #ifdef CONFIG_DMI
140 void amd_iommu_apply_ivrs_quirks(void);
141 #else
amd_iommu_apply_ivrs_quirks(void)142 static inline void amd_iommu_apply_ivrs_quirks(void) { }
143 #endif
144
145 void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
146 u64 *root, int mode);
147 struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
148
149 extern u64 amd_iommu_efr;
150 extern u64 amd_iommu_efr2;
151
152 extern bool amd_iommu_snp_en;
153 #endif
154