xref: /openbmc/qemu/hw/m68k/mcf5208.c (revision d3c79c39)
1 /*
2  * Motorola ColdFire MCF5208 SoC emulation.
3  *
4  * Copyright (c) 2007 CodeSourcery.
5  *
6  * This code is licensed under the GPL
7  */
8 
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "qemu/error-report.h"
12 #include "qemu/log.h"
13 #include "qapi/error.h"
14 #include "qemu/datadir.h"
15 #include "cpu.h"
16 #include "hw/irq.h"
17 #include "hw/m68k/mcf.h"
18 #include "hw/m68k/mcf_fec.h"
19 #include "qemu/timer.h"
20 #include "hw/ptimer.h"
21 #include "sysemu/sysemu.h"
22 #include "sysemu/qtest.h"
23 #include "net/net.h"
24 #include "hw/boards.h"
25 #include "hw/loader.h"
26 #include "hw/sysbus.h"
27 #include "elf.h"
28 
29 #define SYS_FREQ 166666666
30 
31 #define ROM_SIZE 0x200000
32 
33 #define PCSR_EN         0x0001
34 #define PCSR_RLD        0x0002
35 #define PCSR_PIF        0x0004
36 #define PCSR_PIE        0x0008
37 #define PCSR_OVW        0x0010
38 #define PCSR_DBG        0x0020
39 #define PCSR_DOZE       0x0040
40 #define PCSR_PRE_SHIFT  8
41 #define PCSR_PRE_MASK   0x0f00
42 
43 #define RCR_SOFTRST     0x80
44 
45 typedef struct {
46     MemoryRegion iomem;
47     qemu_irq irq;
48     ptimer_state *timer;
49     uint16_t pcsr;
50     uint16_t pmr;
51     uint16_t pcntr;
52 } m5208_timer_state;
53 
m5208_timer_update(m5208_timer_state * s)54 static void m5208_timer_update(m5208_timer_state *s)
55 {
56     if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
57         qemu_irq_raise(s->irq);
58     else
59         qemu_irq_lower(s->irq);
60 }
61 
m5208_timer_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)62 static void m5208_timer_write(void *opaque, hwaddr offset,
63                               uint64_t value, unsigned size)
64 {
65     m5208_timer_state *s = (m5208_timer_state *)opaque;
66     int prescale;
67     int limit;
68     switch (offset) {
69     case 0:
70         /* The PIF bit is set-to-clear.  */
71         if (value & PCSR_PIF) {
72             s->pcsr &= ~PCSR_PIF;
73             value &= ~PCSR_PIF;
74         }
75         /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
76         if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
77             s->pcsr = value;
78             m5208_timer_update(s);
79             return;
80         }
81 
82         ptimer_transaction_begin(s->timer);
83         if (s->pcsr & PCSR_EN)
84             ptimer_stop(s->timer);
85 
86         s->pcsr = value;
87 
88         prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
89         ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
90         if (s->pcsr & PCSR_RLD)
91             limit = s->pmr;
92         else
93             limit = 0xffff;
94         ptimer_set_limit(s->timer, limit, 0);
95 
96         if (s->pcsr & PCSR_EN)
97             ptimer_run(s->timer, 0);
98         ptimer_transaction_commit(s->timer);
99         break;
100     case 2:
101         ptimer_transaction_begin(s->timer);
102         s->pmr = value;
103         s->pcsr &= ~PCSR_PIF;
104         if ((s->pcsr & PCSR_RLD) == 0) {
105             if (s->pcsr & PCSR_OVW)
106                 ptimer_set_count(s->timer, value);
107         } else {
108             ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
109         }
110         ptimer_transaction_commit(s->timer);
111         break;
112     case 4:
113         break;
114     default:
115         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
116                       __func__, offset);
117         return;
118     }
119     m5208_timer_update(s);
120 }
121 
m5208_timer_trigger(void * opaque)122 static void m5208_timer_trigger(void *opaque)
123 {
124     m5208_timer_state *s = (m5208_timer_state *)opaque;
125     s->pcsr |= PCSR_PIF;
126     m5208_timer_update(s);
127 }
128 
m5208_timer_read(void * opaque,hwaddr addr,unsigned size)129 static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
130                                  unsigned size)
131 {
132     m5208_timer_state *s = (m5208_timer_state *)opaque;
133     switch (addr) {
134     case 0:
135         return s->pcsr;
136     case 2:
137         return s->pmr;
138     case 4:
139         return ptimer_get_count(s->timer);
140     default:
141         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
142                       __func__, addr);
143         return 0;
144     }
145 }
146 
147 static const MemoryRegionOps m5208_timer_ops = {
148     .read = m5208_timer_read,
149     .write = m5208_timer_write,
150     .endianness = DEVICE_NATIVE_ENDIAN,
151 };
152 
m5208_sys_read(void * opaque,hwaddr addr,unsigned size)153 static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
154                                unsigned size)
155 {
156     switch (addr) {
157     case 0x110: /* SDCS0 */
158         {
159             int n;
160             for (n = 0; n < 32; n++) {
161                 if (current_machine->ram_size < (2u << n)) {
162                     break;
163                 }
164             }
165             return (n - 1)  | 0x40000000;
166         }
167     case 0x114: /* SDCS1 */
168         return 0;
169 
170     default:
171         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
172                       __func__, addr);
173         return 0;
174     }
175 }
176 
m5208_sys_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)177 static void m5208_sys_write(void *opaque, hwaddr addr,
178                             uint64_t value, unsigned size)
179 {
180     qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
181                   __func__, addr);
182 }
183 
184 static const MemoryRegionOps m5208_sys_ops = {
185     .read = m5208_sys_read,
186     .write = m5208_sys_write,
187     .endianness = DEVICE_NATIVE_ENDIAN,
188 };
189 
m5208_rcm_read(void * opaque,hwaddr addr,unsigned size)190 static uint64_t m5208_rcm_read(void *opaque, hwaddr addr,
191                                unsigned size)
192 {
193     return 0;
194 }
195 
m5208_rcm_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)196 static void m5208_rcm_write(void *opaque, hwaddr addr,
197                             uint64_t value, unsigned size)
198 {
199     M68kCPU *cpu = opaque;
200     CPUState *cs = CPU(cpu);
201     switch (addr) {
202     case 0x0: /* RCR */
203         if (value & RCR_SOFTRST) {
204             cpu_reset(cs);
205             cpu->env.aregs[7] = ldl_phys(cs->as, 0);
206             cpu->env.pc = ldl_phys(cs->as, 4);
207         }
208         break;
209     default:
210         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
211                       __func__, addr);
212         break;
213     }
214 }
215 
216 static const MemoryRegionOps m5208_rcm_ops = {
217     .read = m5208_rcm_read,
218     .write = m5208_rcm_write,
219     .endianness = DEVICE_NATIVE_ENDIAN,
220 };
221 
mcf5208_sys_init(MemoryRegion * address_space,qemu_irq * pic,M68kCPU * cpu)222 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic,
223                              M68kCPU *cpu)
224 {
225     MemoryRegion *iomem = g_new(MemoryRegion, 1);
226     MemoryRegion *iomem_rcm = g_new(MemoryRegion, 1);
227     m5208_timer_state *s;
228     int i;
229 
230     /* RCM */
231     memory_region_init_io(iomem_rcm, NULL, &m5208_rcm_ops, cpu,
232                           "m5208-rcm", 0x00000080);
233     memory_region_add_subregion(address_space, 0xfc0a0000, iomem_rcm);
234     /* SDRAMC.  */
235     memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
236     memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
237     /* Timers.  */
238     for (i = 0; i < 2; i++) {
239         s = g_new0(m5208_timer_state, 1);
240         s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_LEGACY);
241         memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
242                               "m5208-timer", 0x00004000);
243         memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
244                                     &s->iomem);
245         s->irq = pic[4 + i];
246     }
247 }
248 
mcf_fec_init(MemoryRegion * sysmem,hwaddr base,qemu_irq * irqs)249 static void mcf_fec_init(MemoryRegion *sysmem, hwaddr base, qemu_irq *irqs)
250 {
251     DeviceState *dev;
252     SysBusDevice *s;
253     int i;
254 
255     dev = qemu_create_nic_device(TYPE_MCF_FEC_NET, true, NULL);
256     if (!dev) {
257         return;
258     }
259 
260     s = SYS_BUS_DEVICE(dev);
261     sysbus_realize_and_unref(s, &error_fatal);
262     for (i = 0; i < FEC_NUM_IRQ; i++) {
263         sysbus_connect_irq(s, i, irqs[i]);
264     }
265 
266     memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0));
267 }
268 
mcf5208evb_init(MachineState * machine)269 static void mcf5208evb_init(MachineState *machine)
270 {
271     ram_addr_t ram_size = machine->ram_size;
272     const char *kernel_filename = machine->kernel_filename;
273     M68kCPU *cpu;
274     CPUM68KState *env;
275     int kernel_size;
276     uint64_t elf_entry;
277     hwaddr entry;
278     qemu_irq *pic;
279     MemoryRegion *address_space_mem = get_system_memory();
280     MemoryRegion *rom = g_new(MemoryRegion, 1);
281     MemoryRegion *sram = g_new(MemoryRegion, 1);
282 
283     cpu = M68K_CPU(cpu_create(machine->cpu_type));
284     env = &cpu->env;
285 
286     /* Initialize CPU registers.  */
287     env->vbr = 0;
288     /* TODO: Configure BARs.  */
289 
290     /* ROM at 0x00000000 */
291     memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal);
292     memory_region_add_subregion(address_space_mem, 0x00000000, rom);
293 
294     /* DRAM at 0x40000000 */
295     memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram);
296 
297     /* Internal SRAM.  */
298     memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal);
299     memory_region_add_subregion(address_space_mem, 0x80000000, sram);
300 
301     /* Internal peripherals.  */
302     pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
303 
304     mcf_uart_create_mmap(0xfc060000, pic[26], serial_hd(0));
305     mcf_uart_create_mmap(0xfc064000, pic[27], serial_hd(1));
306     mcf_uart_create_mmap(0xfc068000, pic[28], serial_hd(2));
307 
308     mcf5208_sys_init(address_space_mem, pic, cpu);
309 
310     mcf_fec_init(address_space_mem, 0xfc030000, pic + 36);
311 
312     g_free(pic);
313 
314     /*  0xfc000000 SCM.  */
315     /*  0xfc004000 XBS.  */
316     /*  0xfc008000 FlexBus CS.  */
317     /* 0xfc030000 FEC.  */
318     /*  0xfc040000 SCM + Power management.  */
319     /*  0xfc044000 eDMA.  */
320     /* 0xfc048000 INTC.  */
321     /*  0xfc058000 I2C.  */
322     /*  0xfc05c000 QSPI.  */
323     /* 0xfc060000 UART0.  */
324     /* 0xfc064000 UART0.  */
325     /* 0xfc068000 UART0.  */
326     /*  0xfc070000 DMA timers.  */
327     /* 0xfc080000 PIT0.  */
328     /* 0xfc084000 PIT1.  */
329     /*  0xfc088000 EPORT.  */
330     /*  0xfc08c000 Watchdog.  */
331     /*  0xfc090000 clock module.  */
332     /*  0xfc0a0000 CCM + reset.  */
333     /*  0xfc0a4000 GPIO.  */
334     /* 0xfc0a8000 SDRAM controller.  */
335 
336     /* Load firmware */
337     if (machine->firmware) {
338         char *fn;
339         uint8_t *ptr;
340 
341         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
342         if (!fn) {
343             error_report("Could not find ROM image '%s'", machine->firmware);
344             exit(1);
345         }
346         if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) {
347             error_report("Could not load ROM image '%s'", machine->firmware);
348             exit(1);
349         }
350         g_free(fn);
351         /* Initial PC is always at offset 4 in firmware binaries */
352         ptr = rom_ptr(0x4, 4);
353         assert(ptr != NULL);
354         env->pc = ldl_p(ptr);
355     }
356 
357     /* Load kernel.  */
358     if (!kernel_filename) {
359         if (qtest_enabled() || machine->firmware) {
360             return;
361         }
362         error_report("Kernel image must be specified");
363         exit(1);
364     }
365 
366     kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
367                            NULL, NULL, NULL, 1, EM_68K, 0, 0);
368     entry = elf_entry;
369     if (kernel_size < 0) {
370         kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
371                                   NULL, NULL);
372     }
373     if (kernel_size < 0) {
374         kernel_size = load_image_targphys(kernel_filename, 0x40000000,
375                                           ram_size);
376         entry = 0x40000000;
377     }
378     if (kernel_size < 0) {
379         error_report("Could not load kernel '%s'", kernel_filename);
380         exit(1);
381     }
382 
383     env->pc = entry;
384 }
385 
mcf5208evb_machine_init(MachineClass * mc)386 static void mcf5208evb_machine_init(MachineClass *mc)
387 {
388     mc->desc = "MCF5208EVB";
389     mc->init = mcf5208evb_init;
390     mc->is_default = true;
391     mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208");
392     mc->default_ram_id = "mcf5208.ram";
393 }
394 
395 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init)
396