1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 *
5 */
6
7 #include "i915_drv.h"
8 #include "i915_reg.h"
9 #include "intel_de.h"
10 #include "intel_display_types.h"
11 #include "intel_vrr.h"
12
intel_vrr_is_capable(struct intel_connector * connector)13 bool intel_vrr_is_capable(struct intel_connector *connector)
14 {
15 const struct drm_display_info *info = &connector->base.display_info;
16 struct drm_i915_private *i915 = to_i915(connector->base.dev);
17 struct intel_dp *intel_dp;
18
19 /*
20 * DP Sink is capable of VRR video timings if
21 * Ignore MSA bit is set in DPCD.
22 * EDID monitor range also should be atleast 10 for reasonable
23 * Adaptive Sync or Variable Refresh Rate end user experience.
24 */
25 switch (connector->base.connector_type) {
26 case DRM_MODE_CONNECTOR_eDP:
27 if (!connector->panel.vbt.vrr)
28 return false;
29 fallthrough;
30 case DRM_MODE_CONNECTOR_DisplayPort:
31 intel_dp = intel_attached_dp(connector);
32
33 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
34 return false;
35
36 break;
37 default:
38 return false;
39 }
40
41 return HAS_VRR(i915) &&
42 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
43 }
44
45 void
intel_vrr_check_modeset(struct intel_atomic_state * state)46 intel_vrr_check_modeset(struct intel_atomic_state *state)
47 {
48 int i;
49 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
50 struct intel_crtc *crtc;
51
52 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
53 new_crtc_state, i) {
54 if (new_crtc_state->uapi.vrr_enabled !=
55 old_crtc_state->uapi.vrr_enabled)
56 new_crtc_state->uapi.mode_changed = true;
57 }
58 }
59
60 /*
61 * Without VRR registers get latched at:
62 * vblank_start
63 *
64 * With VRR the earliest registers can get latched is:
65 * intel_vrr_vmin_vblank_start(), which if we want to maintain
66 * the correct min vtotal is >=vblank_start+1
67 *
68 * The latest point registers can get latched is the vmax decision boundary:
69 * intel_vrr_vmax_vblank_start()
70 *
71 * Between those two points the vblank exit starts (and hence registers get
72 * latched) ASAP after a push is sent.
73 *
74 * framestart_delay is programmable 1-4.
75 */
intel_vrr_vblank_exit_length(const struct intel_crtc_state * crtc_state)76 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
77 {
78 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
79 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
80
81 if (DISPLAY_VER(i915) >= 13)
82 return crtc_state->vrr.guardband;
83 else
84 /* The hw imposes the extra scanline before frame start */
85 return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
86 }
87
intel_vrr_vmin_vblank_start(const struct intel_crtc_state * crtc_state)88 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
89 {
90 /* Min vblank actually determined by flipline that is always >=vmin+1 */
91 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
92 }
93
intel_vrr_vmax_vblank_start(const struct intel_crtc_state * crtc_state)94 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
95 {
96 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
97 }
98
99 void
intel_vrr_compute_config(struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)100 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
101 struct drm_connector_state *conn_state)
102 {
103 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
104 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
105 struct intel_connector *connector =
106 to_intel_connector(conn_state->connector);
107 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
108 const struct drm_display_info *info = &connector->base.display_info;
109 int vmin, vmax;
110
111 if (!intel_vrr_is_capable(connector))
112 return;
113
114 /*
115 * FIXME all joined pipes share the same transcoder.
116 * Need to account for that during VRR toggle/push/etc.
117 */
118 if (crtc_state->bigjoiner_pipes)
119 return;
120
121 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
122 return;
123
124 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
125 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
126 vmax = adjusted_mode->crtc_clock * 1000 /
127 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
128
129 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
130 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
131
132 if (vmin >= vmax)
133 return;
134
135 /*
136 * flipline determines the min vblank length the hardware will
137 * generate, and flipline>=vmin+1, hence we reduce vmin by one
138 * to make sure we can get the actual min vblank length.
139 */
140 crtc_state->vrr.vmin = vmin - 1;
141 crtc_state->vrr.vmax = vmax;
142
143 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
144
145 /*
146 * For XE_LPD+, we use guardband and pipeline override
147 * is deprecated.
148 */
149 if (DISPLAY_VER(i915) >= 13) {
150 crtc_state->vrr.guardband =
151 crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
152 } else {
153 crtc_state->vrr.pipeline_full =
154 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
155 crtc_state->framestart_delay - 1);
156 }
157
158 if (crtc_state->uapi.vrr_enabled) {
159 crtc_state->vrr.enable = true;
160 crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
161 }
162 }
163
trans_vrr_ctl(const struct intel_crtc_state * crtc_state)164 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
165 {
166 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
167
168 if (DISPLAY_VER(i915) >= 13)
169 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
170 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
171 else
172 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
173 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
174 VRR_CTL_PIPELINE_FULL_OVERRIDE;
175 }
176
intel_vrr_set_transcoder_timings(const struct intel_crtc_state * crtc_state)177 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
178 {
179 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
180 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
181
182 /*
183 * TRANS_SET_CONTEXT_LATENCY with VRR enabled
184 * requires this chicken bit on ADL/DG2.
185 */
186 if (DISPLAY_VER(dev_priv) == 13)
187 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
188 0, PIPE_VBLANK_WITH_DELAY);
189
190 if (!crtc_state->vrr.flipline) {
191 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
192 return;
193 }
194
195 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
196 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
197 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
198 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
199 }
200
intel_vrr_send_push(const struct intel_crtc_state * crtc_state)201 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
202 {
203 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
204 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
205 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
206
207 if (!crtc_state->vrr.enable)
208 return;
209
210 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
211 TRANS_PUSH_EN | TRANS_PUSH_SEND);
212 }
213
intel_vrr_is_push_sent(const struct intel_crtc_state * crtc_state)214 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
215 {
216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
218 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
219
220 if (!crtc_state->vrr.enable)
221 return false;
222
223 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND;
224 }
225
intel_vrr_enable(const struct intel_crtc_state * crtc_state)226 void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
227 {
228 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
229 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
230
231 if (!crtc_state->vrr.enable)
232 return;
233
234 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
235 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
236 VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
237 }
238
intel_vrr_disable(const struct intel_crtc_state * old_crtc_state)239 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
240 {
241 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
243 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
244
245 if (!old_crtc_state->vrr.enable)
246 return;
247
248 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
249 trans_vrr_ctl(old_crtc_state));
250 intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
251 VRR_STATUS_VRR_EN_LIVE, 1000);
252 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
253 }
254
intel_vrr_get_config(struct intel_crtc_state * crtc_state)255 void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
256 {
257 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
258 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
259 u32 trans_vrr_ctl;
260
261 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
262
263 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
264
265 if (DISPLAY_VER(dev_priv) >= 13)
266 crtc_state->vrr.guardband =
267 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
268 else
269 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
270 crtc_state->vrr.pipeline_full =
271 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
272
273 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
274 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
275 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
276 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
277 }
278
279 if (crtc_state->vrr.enable)
280 crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
281 }
282