1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #define NUM_STEPS 5
7 #define H2G_DELAY 50000
8 #define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 10000)
9 #define FREQUENCY_REQ_UNIT DIV_ROUND_CLOSEST(GT_FREQUENCY_MULTIPLIER, \
10 GEN9_FREQ_SCALER)
11 enum test_type {
12 VARY_MIN,
13 VARY_MAX,
14 MAX_GRANTED,
15 SLPC_POWER,
16 TILE_INTERACTION,
17 };
18
19 struct slpc_thread {
20 struct kthread_worker *worker;
21 struct kthread_work work;
22 struct intel_gt *gt;
23 int result;
24 };
25
slpc_set_min_freq(struct intel_guc_slpc * slpc,u32 freq)26 static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
27 {
28 int ret;
29
30 ret = intel_guc_slpc_set_min_freq(slpc, freq);
31 if (ret)
32 pr_err("Could not set min frequency to [%u]\n", freq);
33 else /* Delay to ensure h2g completes */
34 delay_for_h2g();
35
36 return ret;
37 }
38
slpc_set_max_freq(struct intel_guc_slpc * slpc,u32 freq)39 static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
40 {
41 int ret;
42
43 ret = intel_guc_slpc_set_max_freq(slpc, freq);
44 if (ret)
45 pr_err("Could not set maximum frequency [%u]\n",
46 freq);
47 else /* Delay to ensure h2g completes */
48 delay_for_h2g();
49
50 return ret;
51 }
52
slpc_set_freq(struct intel_gt * gt,u32 freq)53 static int slpc_set_freq(struct intel_gt *gt, u32 freq)
54 {
55 int err;
56 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
57
58 err = slpc_set_max_freq(slpc, freq);
59 if (err) {
60 pr_err("Unable to update max freq");
61 return err;
62 }
63
64 err = slpc_set_min_freq(slpc, freq);
65 if (err) {
66 pr_err("Unable to update min freq");
67 return err;
68 }
69
70 return err;
71 }
72
slpc_restore_freq(struct intel_guc_slpc * slpc,u32 min,u32 max)73 static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max)
74 {
75 int err;
76
77 err = slpc_set_max_freq(slpc, max);
78 if (err) {
79 pr_err("Unable to restore max freq");
80 return err;
81 }
82
83 err = slpc_set_min_freq(slpc, min);
84 if (err) {
85 pr_err("Unable to restore min freq");
86 return err;
87 }
88
89 err = intel_guc_slpc_set_ignore_eff_freq(slpc, false);
90 if (err) {
91 pr_err("Unable to restore efficient freq");
92 return err;
93 }
94
95 return 0;
96 }
97
measure_power_at_freq(struct intel_gt * gt,int * freq,u64 * power)98 static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power)
99 {
100 int err = 0;
101
102 err = slpc_set_freq(gt, *freq);
103 if (err)
104 return err;
105 *freq = intel_rps_read_actual_frequency(>->rps);
106 *power = measure_power(>->rps, freq);
107
108 return err;
109 }
110
vary_max_freq(struct intel_guc_slpc * slpc,struct intel_rps * rps,u32 * max_act_freq)111 static int vary_max_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps,
112 u32 *max_act_freq)
113 {
114 u32 step, max_freq, req_freq;
115 u32 act_freq;
116 int err = 0;
117
118 /* Go from max to min in 5 steps */
119 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS;
120 *max_act_freq = slpc->min_freq;
121 for (max_freq = slpc->rp0_freq; max_freq > slpc->min_freq;
122 max_freq -= step) {
123 err = slpc_set_max_freq(slpc, max_freq);
124 if (err)
125 break;
126
127 req_freq = intel_rps_read_punit_req_frequency(rps);
128
129 /* GuC requests freq in multiples of 50/3 MHz */
130 if (req_freq > (max_freq + FREQUENCY_REQ_UNIT)) {
131 pr_err("SWReq is %d, should be at most %d\n", req_freq,
132 max_freq + FREQUENCY_REQ_UNIT);
133 err = -EINVAL;
134 }
135
136 act_freq = intel_rps_read_actual_frequency(rps);
137 if (act_freq > *max_act_freq)
138 *max_act_freq = act_freq;
139
140 if (err)
141 break;
142 }
143
144 return err;
145 }
146
vary_min_freq(struct intel_guc_slpc * slpc,struct intel_rps * rps,u32 * max_act_freq)147 static int vary_min_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps,
148 u32 *max_act_freq)
149 {
150 u32 step, min_freq, req_freq;
151 u32 act_freq;
152 int err = 0;
153
154 /* Go from min to max in 5 steps */
155 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS;
156 *max_act_freq = slpc->min_freq;
157 for (min_freq = slpc->min_freq; min_freq < slpc->rp0_freq;
158 min_freq += step) {
159 err = slpc_set_min_freq(slpc, min_freq);
160 if (err)
161 break;
162
163 req_freq = intel_rps_read_punit_req_frequency(rps);
164
165 /* GuC requests freq in multiples of 50/3 MHz */
166 if (req_freq < (min_freq - FREQUENCY_REQ_UNIT)) {
167 pr_err("SWReq is %d, should be at least %d\n", req_freq,
168 min_freq - FREQUENCY_REQ_UNIT);
169 err = -EINVAL;
170 }
171
172 act_freq = intel_rps_read_actual_frequency(rps);
173 if (act_freq > *max_act_freq)
174 *max_act_freq = act_freq;
175
176 if (err)
177 break;
178 }
179
180 return err;
181 }
182
slpc_power(struct intel_gt * gt,struct intel_engine_cs * engine)183 static int slpc_power(struct intel_gt *gt, struct intel_engine_cs *engine)
184 {
185 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
186 struct {
187 u64 power;
188 int freq;
189 } min, max;
190 int err = 0;
191
192 /*
193 * Our fundamental assumption is that running at lower frequency
194 * actually saves power. Let's see if our RAPL measurement supports
195 * that theory.
196 */
197 if (!librapl_supported(gt->i915))
198 return 0;
199
200 min.freq = slpc->min_freq;
201 err = measure_power_at_freq(gt, &min.freq, &min.power);
202
203 if (err)
204 return err;
205
206 max.freq = slpc->rp0_freq;
207 err = measure_power_at_freq(gt, &max.freq, &max.power);
208
209 if (err)
210 return err;
211
212 pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n",
213 engine->name,
214 min.power, min.freq,
215 max.power, max.freq);
216
217 if (10 * min.freq >= 9 * max.freq) {
218 pr_notice("Could not control frequency, ran at [%uMHz, %uMhz]\n",
219 min.freq, max.freq);
220 }
221
222 if (11 * min.power > 10 * max.power) {
223 pr_err("%s: did not conserve power when setting lower frequency!\n",
224 engine->name);
225 err = -EINVAL;
226 }
227
228 /* Restore min/max frequencies */
229 slpc_set_max_freq(slpc, slpc->rp0_freq);
230 slpc_set_min_freq(slpc, slpc->min_freq);
231
232 return err;
233 }
234
max_granted_freq(struct intel_guc_slpc * slpc,struct intel_rps * rps,u32 * max_act_freq)235 static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq)
236 {
237 struct intel_gt *gt = rps_to_gt(rps);
238 u32 perf_limit_reasons;
239 int err = 0;
240
241 err = slpc_set_min_freq(slpc, slpc->rp0_freq);
242 if (err)
243 return err;
244
245 *max_act_freq = intel_rps_read_actual_frequency(rps);
246 if (*max_act_freq != slpc->rp0_freq) {
247 /* Check if there was some throttling by pcode */
248 perf_limit_reasons = intel_uncore_read(gt->uncore,
249 intel_gt_perf_limit_reasons_reg(gt));
250
251 /* If not, this is an error */
252 if (!(perf_limit_reasons & GT0_PERF_LIMIT_REASONS_MASK)) {
253 pr_err("Pcode did not grant max freq\n");
254 err = -EINVAL;
255 } else {
256 pr_info("Pcode throttled frequency 0x%x\n", perf_limit_reasons);
257 }
258 }
259
260 return err;
261 }
262
run_test(struct intel_gt * gt,int test_type)263 static int run_test(struct intel_gt *gt, int test_type)
264 {
265 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
266 struct intel_rps *rps = >->rps;
267 struct intel_engine_cs *engine;
268 enum intel_engine_id id;
269 struct igt_spinner spin;
270 u32 slpc_min_freq, slpc_max_freq;
271 int err = 0;
272
273 if (!intel_uc_uses_guc_slpc(>->uc))
274 return 0;
275
276 if (slpc->min_freq == slpc->rp0_freq) {
277 pr_err("Min/Max are fused to the same value\n");
278 return -EINVAL;
279 }
280
281 if (igt_spinner_init(&spin, gt))
282 return -ENOMEM;
283
284 if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
285 pr_err("Could not get SLPC max freq\n");
286 return -EIO;
287 }
288
289 if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
290 pr_err("Could not get SLPC min freq\n");
291 return -EIO;
292 }
293
294 /*
295 * Set min frequency to RPn so that we can test the whole
296 * range of RPn-RP0.
297 */
298 err = slpc_set_min_freq(slpc, slpc->min_freq);
299 if (err) {
300 pr_err("Unable to update min freq!");
301 return err;
302 }
303
304 /*
305 * Turn off efficient frequency so RPn/RP0 ranges are obeyed.
306 */
307 err = intel_guc_slpc_set_ignore_eff_freq(slpc, true);
308 if (err) {
309 pr_err("Unable to turn off efficient freq!");
310 return err;
311 }
312
313 intel_gt_pm_wait_for_idle(gt);
314 intel_gt_pm_get(gt);
315 for_each_engine(engine, gt, id) {
316 struct i915_request *rq;
317 u32 max_act_freq;
318
319 if (!intel_engine_can_store_dword(engine))
320 continue;
321
322 st_engine_heartbeat_disable(engine);
323
324 rq = igt_spinner_create_request(&spin,
325 engine->kernel_context,
326 MI_NOOP);
327 if (IS_ERR(rq)) {
328 err = PTR_ERR(rq);
329 st_engine_heartbeat_enable(engine);
330 break;
331 }
332
333 i915_request_add(rq);
334
335 if (!igt_wait_for_spinner(&spin, rq)) {
336 pr_err("%s: Spinner did not start\n",
337 engine->name);
338 igt_spinner_end(&spin);
339 st_engine_heartbeat_enable(engine);
340 intel_gt_set_wedged(engine->gt);
341 err = -EIO;
342 break;
343 }
344
345 switch (test_type) {
346 case VARY_MIN:
347 err = vary_min_freq(slpc, rps, &max_act_freq);
348 break;
349
350 case VARY_MAX:
351 err = vary_max_freq(slpc, rps, &max_act_freq);
352 break;
353
354 case MAX_GRANTED:
355 case TILE_INTERACTION:
356 /* Media engines have a different RP0 */
357 if (gt->type != GT_MEDIA && (engine->class == VIDEO_DECODE_CLASS ||
358 engine->class == VIDEO_ENHANCEMENT_CLASS)) {
359 igt_spinner_end(&spin);
360 st_engine_heartbeat_enable(engine);
361 err = 0;
362 continue;
363 }
364
365 err = max_granted_freq(slpc, rps, &max_act_freq);
366 break;
367
368 case SLPC_POWER:
369 err = slpc_power(gt, engine);
370 break;
371 }
372
373 if (test_type != SLPC_POWER) {
374 pr_info("Max actual frequency for %s was %d\n",
375 engine->name, max_act_freq);
376
377 /* Actual frequency should rise above min */
378 if (max_act_freq <= slpc->min_freq) {
379 pr_err("Actual freq did not rise above min\n");
380 pr_err("Perf Limit Reasons: 0x%x\n",
381 intel_uncore_read(gt->uncore,
382 intel_gt_perf_limit_reasons_reg(gt)));
383 err = -EINVAL;
384 }
385 }
386
387 igt_spinner_end(&spin);
388 st_engine_heartbeat_enable(engine);
389
390 if (err)
391 break;
392 }
393
394 /* Restore min/max/efficient frequencies */
395 err = slpc_restore_freq(slpc, slpc_min_freq, slpc_max_freq);
396
397 if (igt_flush_test(gt->i915))
398 err = -EIO;
399
400 intel_gt_pm_put(gt);
401 igt_spinner_fini(&spin);
402 intel_gt_pm_wait_for_idle(gt);
403
404 return err;
405 }
406
live_slpc_vary_min(void * arg)407 static int live_slpc_vary_min(void *arg)
408 {
409 struct drm_i915_private *i915 = arg;
410 struct intel_gt *gt;
411 unsigned int i;
412 int ret;
413
414 for_each_gt(gt, i915, i) {
415 ret = run_test(gt, VARY_MIN);
416 if (ret)
417 return ret;
418 }
419
420 return ret;
421 }
422
live_slpc_vary_max(void * arg)423 static int live_slpc_vary_max(void *arg)
424 {
425 struct drm_i915_private *i915 = arg;
426 struct intel_gt *gt;
427 unsigned int i;
428 int ret;
429
430 for_each_gt(gt, i915, i) {
431 ret = run_test(gt, VARY_MAX);
432 if (ret)
433 return ret;
434 }
435
436 return ret;
437 }
438
439 /* check if pcode can grant RP0 */
live_slpc_max_granted(void * arg)440 static int live_slpc_max_granted(void *arg)
441 {
442 struct drm_i915_private *i915 = arg;
443 struct intel_gt *gt;
444 unsigned int i;
445 int ret;
446
447 for_each_gt(gt, i915, i) {
448 ret = run_test(gt, MAX_GRANTED);
449 if (ret)
450 return ret;
451 }
452
453 return ret;
454 }
455
live_slpc_power(void * arg)456 static int live_slpc_power(void *arg)
457 {
458 struct drm_i915_private *i915 = arg;
459 struct intel_gt *gt;
460 unsigned int i;
461 int ret;
462
463 for_each_gt(gt, i915, i) {
464 ret = run_test(gt, SLPC_POWER);
465 if (ret)
466 return ret;
467 }
468
469 return ret;
470 }
471
slpc_spinner_thread(struct kthread_work * work)472 static void slpc_spinner_thread(struct kthread_work *work)
473 {
474 struct slpc_thread *thread = container_of(work, typeof(*thread), work);
475
476 thread->result = run_test(thread->gt, TILE_INTERACTION);
477 }
478
live_slpc_tile_interaction(void * arg)479 static int live_slpc_tile_interaction(void *arg)
480 {
481 struct drm_i915_private *i915 = arg;
482 struct intel_gt *gt;
483 struct slpc_thread *threads;
484 int i = 0, ret = 0;
485
486 threads = kcalloc(I915_MAX_GT, sizeof(*threads), GFP_KERNEL);
487 if (!threads)
488 return -ENOMEM;
489
490 for_each_gt(gt, i915, i) {
491 threads[i].worker = kthread_create_worker(0, "igt/slpc_parallel:%d", gt->info.id);
492
493 if (IS_ERR(threads[i].worker)) {
494 ret = PTR_ERR(threads[i].worker);
495 break;
496 }
497
498 threads[i].gt = gt;
499 kthread_init_work(&threads[i].work, slpc_spinner_thread);
500 kthread_queue_work(threads[i].worker, &threads[i].work);
501 }
502
503 for_each_gt(gt, i915, i) {
504 int status;
505
506 if (IS_ERR_OR_NULL(threads[i].worker))
507 continue;
508
509 kthread_flush_work(&threads[i].work);
510 status = READ_ONCE(threads[i].result);
511 if (status && !ret) {
512 pr_err("%s GT %d failed ", __func__, gt->info.id);
513 ret = status;
514 }
515 kthread_destroy_worker(threads[i].worker);
516 }
517
518 kfree(threads);
519 return ret;
520 }
521
intel_slpc_live_selftests(struct drm_i915_private * i915)522 int intel_slpc_live_selftests(struct drm_i915_private *i915)
523 {
524 static const struct i915_subtest tests[] = {
525 SUBTEST(live_slpc_vary_max),
526 SUBTEST(live_slpc_vary_min),
527 SUBTEST(live_slpc_max_granted),
528 SUBTEST(live_slpc_power),
529 SUBTEST(live_slpc_tile_interaction),
530 };
531
532 struct intel_gt *gt;
533 unsigned int i;
534
535 for_each_gt(gt, i915, i) {
536 if (intel_gt_is_wedged(gt))
537 return 0;
538 }
539
540 return i915_live_subtests(tests, i915);
541 }
542