xref: /openbmc/linux/arch/x86/include/asm/microcode.h (revision 098c0a373cdd51d3a735da7394acd6e57fae45a0)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MICROCODE_H
3 #define _ASM_X86_MICROCODE_H
4 
5 struct cpu_signature {
6 	unsigned int sig;
7 	unsigned int pf;
8 	unsigned int rev;
9 };
10 
11 struct ucode_cpu_info {
12 	struct cpu_signature	cpu_sig;
13 	void			*mc;
14 };
15 
16 #ifdef CONFIG_MICROCODE
17 void load_ucode_bsp(void);
18 void load_ucode_ap(void);
19 void microcode_bsp_resume(void);
20 bool __init microcode_loader_disabled(void);
21 #else
load_ucode_bsp(void)22 static inline void load_ucode_bsp(void)	{ }
load_ucode_ap(void)23 static inline void load_ucode_ap(void) { }
microcode_bsp_resume(void)24 static inline void microcode_bsp_resume(void) { }
microcode_loader_disabled(void)25 static inline bool __init microcode_loader_disabled(void) { return false; }
26 #endif
27 
28 extern unsigned long initrd_start_early;
29 
30 #ifdef CONFIG_CPU_SUP_INTEL
31 /* Intel specific microcode defines. Public for IFS */
32 struct microcode_header_intel {
33 	unsigned int	hdrver;
34 	unsigned int	rev;
35 	unsigned int	date;
36 	unsigned int	sig;
37 	unsigned int	cksum;
38 	unsigned int	ldrver;
39 	unsigned int	pf;
40 	unsigned int	datasize;
41 	unsigned int	totalsize;
42 	unsigned int	metasize;
43 	unsigned int	reserved[2];
44 };
45 
46 struct microcode_intel {
47 	struct microcode_header_intel	hdr;
48 	unsigned int			bits[];
49 };
50 
51 #define DEFAULT_UCODE_DATASIZE		(2000)
52 #define MC_HEADER_SIZE			(sizeof(struct microcode_header_intel))
53 #define MC_HEADER_TYPE_MICROCODE	1
54 #define MC_HEADER_TYPE_IFS		2
55 
intel_microcode_get_datasize(struct microcode_header_intel * hdr)56 static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr)
57 {
58 	return hdr->datasize ? : DEFAULT_UCODE_DATASIZE;
59 }
60 
intel_get_microcode_revision(void)61 static inline u32 intel_get_microcode_revision(void)
62 {
63 	u32 rev, dummy;
64 
65 	native_wrmsrl(MSR_IA32_UCODE_REV, 0);
66 
67 	/* As documented in the SDM: Do a CPUID 1 here */
68 	native_cpuid_eax(1);
69 
70 	/* get the current revision from MSR 0x8B */
71 	native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
72 
73 	return rev;
74 }
75 #endif /* !CONFIG_CPU_SUP_INTEL */
76 
77 bool microcode_nmi_handler(void);
78 void microcode_offline_nmi_handler(void);
79 
80 #ifdef CONFIG_MICROCODE_LATE_LOADING
81 DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable);
microcode_nmi_handler_enabled(void)82 static __always_inline bool microcode_nmi_handler_enabled(void)
83 {
84 	return static_branch_unlikely(&microcode_nmi_handler_enable);
85 }
86 #else
microcode_nmi_handler_enabled(void)87 static __always_inline bool microcode_nmi_handler_enabled(void) { return false; }
88 #endif
89 
90 #endif /* _ASM_X86_MICROCODE_H */
91