1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Intel CPU Microcode Update Driver for Linux
4 *
5 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
6 * 2006 Shaohua Li <shaohua.li@intel.com>
7 *
8 * Intel CPU microcode early update for Linux
9 *
10 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
11 * H Peter Anvin" <hpa@zytor.com>
12 */
13 #define pr_fmt(fmt) "microcode: " fmt
14 #include <linux/earlycpio.h>
15 #include <linux/firmware.h>
16 #include <linux/uaccess.h>
17 #include <linux/vmalloc.h>
18 #include <linux/initrd.h>
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/uio.h>
23 #include <linux/mm.h>
24
25 #include <asm/intel-family.h>
26 #include <asm/processor.h>
27 #include <asm/tlbflush.h>
28 #include <asm/setup.h>
29 #include <asm/msr.h>
30
31 #include "internal.h"
32
33 static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin";
34
35 /* Current microcode patch used in early patching on the APs. */
36 static struct microcode_intel *intel_ucode_patch;
37
38 /* last level cache size per core */
39 static int llc_size_per_core;
40
41 /* microcode format is extended from prescott processors */
42 struct extended_signature {
43 unsigned int sig;
44 unsigned int pf;
45 unsigned int cksum;
46 };
47
48 struct extended_sigtable {
49 unsigned int count;
50 unsigned int cksum;
51 unsigned int reserved[3];
52 struct extended_signature sigs[];
53 };
54
55 #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
56 #define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
57 #define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
58
get_totalsize(struct microcode_header_intel * hdr)59 static inline unsigned int get_totalsize(struct microcode_header_intel *hdr)
60 {
61 return hdr->datasize ? hdr->totalsize : DEFAULT_UCODE_TOTALSIZE;
62 }
63
exttable_size(struct extended_sigtable * et)64 static inline unsigned int exttable_size(struct extended_sigtable *et)
65 {
66 return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
67 }
68
intel_cpu_collect_info(struct ucode_cpu_info * uci)69 int intel_cpu_collect_info(struct ucode_cpu_info *uci)
70 {
71 unsigned int val[2];
72 unsigned int family, model;
73 struct cpu_signature csig = { 0 };
74 unsigned int eax, ebx, ecx, edx;
75
76 memset(uci, 0, sizeof(*uci));
77
78 eax = 0x00000001;
79 ecx = 0;
80 native_cpuid(&eax, &ebx, &ecx, &edx);
81 csig.sig = eax;
82
83 family = x86_family(eax);
84 model = x86_model(eax);
85
86 if (model >= 5 || family > 6) {
87 /* get processor flags from MSR 0x17 */
88 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
89 csig.pf = 1 << ((val[1] >> 18) & 7);
90 }
91
92 csig.rev = intel_get_microcode_revision();
93
94 uci->cpu_sig = csig;
95
96 return 0;
97 }
98 EXPORT_SYMBOL_GPL(intel_cpu_collect_info);
99
100 /*
101 * Returns 1 if update has been found, 0 otherwise.
102 */
intel_find_matching_signature(void * mc,unsigned int csig,int cpf)103 int intel_find_matching_signature(void *mc, unsigned int csig, int cpf)
104 {
105 struct microcode_header_intel *mc_hdr = mc;
106 struct extended_sigtable *ext_hdr;
107 struct extended_signature *ext_sig;
108 int i;
109
110 if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf))
111 return 1;
112
113 /* Look for ext. headers: */
114 if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE)
115 return 0;
116
117 ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE;
118 ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE;
119
120 for (i = 0; i < ext_hdr->count; i++) {
121 if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf))
122 return 1;
123 ext_sig++;
124 }
125 return 0;
126 }
127 EXPORT_SYMBOL_GPL(intel_find_matching_signature);
128
129 /**
130 * intel_microcode_sanity_check() - Sanity check microcode file.
131 * @mc: Pointer to the microcode file contents.
132 * @print_err: Display failure reason if true, silent if false.
133 * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file.
134 * Validate if the microcode header type matches with the type
135 * specified here.
136 *
137 * Validate certain header fields and verify if computed checksum matches
138 * with the one specified in the header.
139 *
140 * Return: 0 if the file passes all the checks, -EINVAL if any of the checks
141 * fail.
142 */
intel_microcode_sanity_check(void * mc,bool print_err,int hdr_type)143 int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type)
144 {
145 unsigned long total_size, data_size, ext_table_size;
146 struct microcode_header_intel *mc_header = mc;
147 struct extended_sigtable *ext_header = NULL;
148 u32 sum, orig_sum, ext_sigcount = 0, i;
149 struct extended_signature *ext_sig;
150
151 total_size = get_totalsize(mc_header);
152 data_size = intel_microcode_get_datasize(mc_header);
153
154 if (data_size + MC_HEADER_SIZE > total_size) {
155 if (print_err)
156 pr_err("Error: bad microcode data file size.\n");
157 return -EINVAL;
158 }
159
160 if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) {
161 if (print_err)
162 pr_err("Error: invalid/unknown microcode update format. Header type %d\n",
163 mc_header->hdrver);
164 return -EINVAL;
165 }
166
167 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
168 if (ext_table_size) {
169 u32 ext_table_sum = 0;
170 u32 *ext_tablep;
171
172 if (ext_table_size < EXT_HEADER_SIZE ||
173 ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
174 if (print_err)
175 pr_err("Error: truncated extended signature table.\n");
176 return -EINVAL;
177 }
178
179 ext_header = mc + MC_HEADER_SIZE + data_size;
180 if (ext_table_size != exttable_size(ext_header)) {
181 if (print_err)
182 pr_err("Error: extended signature table size mismatch.\n");
183 return -EFAULT;
184 }
185
186 ext_sigcount = ext_header->count;
187
188 /*
189 * Check extended table checksum: the sum of all dwords that
190 * comprise a valid table must be 0.
191 */
192 ext_tablep = (u32 *)ext_header;
193
194 i = ext_table_size / sizeof(u32);
195 while (i--)
196 ext_table_sum += ext_tablep[i];
197
198 if (ext_table_sum) {
199 if (print_err)
200 pr_warn("Bad extended signature table checksum, aborting.\n");
201 return -EINVAL;
202 }
203 }
204
205 /*
206 * Calculate the checksum of update data and header. The checksum of
207 * valid update data and header including the extended signature table
208 * must be 0.
209 */
210 orig_sum = 0;
211 i = (MC_HEADER_SIZE + data_size) / sizeof(u32);
212 while (i--)
213 orig_sum += ((u32 *)mc)[i];
214
215 if (orig_sum) {
216 if (print_err)
217 pr_err("Bad microcode data checksum, aborting.\n");
218 return -EINVAL;
219 }
220
221 if (!ext_table_size)
222 return 0;
223
224 /*
225 * Check extended signature checksum: 0 => valid.
226 */
227 for (i = 0; i < ext_sigcount; i++) {
228 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
229 EXT_SIGNATURE_SIZE * i;
230
231 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) -
232 (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
233 if (sum) {
234 if (print_err)
235 pr_err("Bad extended signature checksum, aborting.\n");
236 return -EINVAL;
237 }
238 }
239 return 0;
240 }
241 EXPORT_SYMBOL_GPL(intel_microcode_sanity_check);
242
243 /*
244 * Returns 1 if update has been found, 0 otherwise.
245 */
has_newer_microcode(void * mc,unsigned int csig,int cpf,int new_rev)246 static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev)
247 {
248 struct microcode_header_intel *mc_hdr = mc;
249
250 if (mc_hdr->rev <= new_rev)
251 return 0;
252
253 return intel_find_matching_signature(mc, csig, cpf);
254 }
255
memdup_patch(void * data,unsigned int size)256 static struct ucode_patch *memdup_patch(void *data, unsigned int size)
257 {
258 struct ucode_patch *p;
259
260 p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL);
261 if (!p)
262 return NULL;
263
264 p->data = kmemdup(data, size, GFP_KERNEL);
265 if (!p->data) {
266 kfree(p);
267 return NULL;
268 }
269
270 return p;
271 }
272
save_microcode_patch(struct ucode_cpu_info * uci,void * data,unsigned int size)273 static void save_microcode_patch(struct ucode_cpu_info *uci, void *data, unsigned int size)
274 {
275 struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
276 struct ucode_patch *iter, *tmp, *p = NULL;
277 bool prev_found = false;
278 unsigned int sig, pf;
279
280 mc_hdr = (struct microcode_header_intel *)data;
281
282 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) {
283 mc_saved_hdr = (struct microcode_header_intel *)iter->data;
284 sig = mc_saved_hdr->sig;
285 pf = mc_saved_hdr->pf;
286
287 if (intel_find_matching_signature(data, sig, pf)) {
288 prev_found = true;
289
290 if (mc_hdr->rev <= mc_saved_hdr->rev)
291 continue;
292
293 p = memdup_patch(data, size);
294 if (!p)
295 pr_err("Error allocating buffer %p\n", data);
296 else {
297 list_replace(&iter->plist, &p->plist);
298 kfree(iter->data);
299 kfree(iter);
300 }
301 }
302 }
303
304 /*
305 * There weren't any previous patches found in the list cache; save the
306 * newly found.
307 */
308 if (!prev_found) {
309 p = memdup_patch(data, size);
310 if (!p)
311 pr_err("Error allocating buffer for %p\n", data);
312 else
313 list_add_tail(&p->plist, µcode_cache);
314 }
315
316 if (!p)
317 return;
318
319 if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf))
320 return;
321
322 /*
323 * Save for early loading. On 32-bit, that needs to be a physical
324 * address as the APs are running from physical addresses, before
325 * paging has been enabled.
326 */
327 if (IS_ENABLED(CONFIG_X86_32))
328 intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data);
329 else
330 intel_ucode_patch = p->data;
331 }
332
333 /*
334 * Get microcode matching with BSP's model. Only CPUs with the same model as
335 * BSP can stay in the platform.
336 */
337 static struct microcode_intel *
scan_microcode(void * data,size_t size,struct ucode_cpu_info * uci,bool save)338 scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save)
339 {
340 struct microcode_header_intel *mc_header;
341 struct microcode_intel *patch = NULL;
342 unsigned int mc_size;
343
344 while (size) {
345 if (size < sizeof(struct microcode_header_intel))
346 break;
347
348 mc_header = (struct microcode_header_intel *)data;
349
350 mc_size = get_totalsize(mc_header);
351 if (!mc_size ||
352 mc_size > size ||
353 intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0)
354 break;
355
356 size -= mc_size;
357
358 if (!intel_find_matching_signature(data, uci->cpu_sig.sig,
359 uci->cpu_sig.pf)) {
360 data += mc_size;
361 continue;
362 }
363
364 if (save) {
365 save_microcode_patch(uci, data, mc_size);
366 goto next;
367 }
368
369
370 if (!patch) {
371 if (!has_newer_microcode(data,
372 uci->cpu_sig.sig,
373 uci->cpu_sig.pf,
374 uci->cpu_sig.rev))
375 goto next;
376
377 } else {
378 struct microcode_header_intel *phdr = &patch->hdr;
379
380 if (!has_newer_microcode(data,
381 phdr->sig,
382 phdr->pf,
383 phdr->rev))
384 goto next;
385 }
386
387 /* We have a newer patch, save it. */
388 patch = data;
389
390 next:
391 data += mc_size;
392 }
393
394 if (size)
395 return NULL;
396
397 return patch;
398 }
399
load_builtin_intel_microcode(struct cpio_data * cp)400 static bool load_builtin_intel_microcode(struct cpio_data *cp)
401 {
402 unsigned int eax = 1, ebx, ecx = 0, edx;
403 struct firmware fw;
404 char name[30];
405
406 if (IS_ENABLED(CONFIG_X86_32))
407 return false;
408
409 native_cpuid(&eax, &ebx, &ecx, &edx);
410
411 sprintf(name, "intel-ucode/%02x-%02x-%02x",
412 x86_family(eax), x86_model(eax), x86_stepping(eax));
413
414 if (firmware_request_builtin(&fw, name)) {
415 cp->size = fw.size;
416 cp->data = (void *)fw.data;
417 return true;
418 }
419
420 return false;
421 }
422
print_ucode_info(int old_rev,int new_rev,unsigned int date)423 static void print_ucode_info(int old_rev, int new_rev, unsigned int date)
424 {
425 pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n",
426 old_rev,
427 new_rev,
428 date & 0xffff,
429 date >> 24,
430 (date >> 16) & 0xff);
431 }
432
433 #ifdef CONFIG_X86_32
434
435 static int delay_ucode_info;
436 static int current_mc_date;
437 static int early_old_rev;
438
439 /*
440 * Print early updated ucode info after printk works. This is delayed info dump.
441 */
show_ucode_info_early(void)442 void show_ucode_info_early(void)
443 {
444 struct ucode_cpu_info uci;
445
446 if (delay_ucode_info) {
447 intel_cpu_collect_info(&uci);
448 print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date);
449 delay_ucode_info = 0;
450 }
451 }
452
453 /*
454 * At this point, we can not call printk() yet. Delay printing microcode info in
455 * show_ucode_info_early() until printk() works.
456 */
print_ucode(int old_rev,int new_rev,int date)457 static void print_ucode(int old_rev, int new_rev, int date)
458 {
459 int *delay_ucode_info_p;
460 int *current_mc_date_p;
461 int *early_old_rev_p;
462
463 delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info);
464 current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date);
465 early_old_rev_p = (int *)__pa_nodebug(&early_old_rev);
466
467 *delay_ucode_info_p = 1;
468 *current_mc_date_p = date;
469 *early_old_rev_p = old_rev;
470 }
471 #else
472
print_ucode(int old_rev,int new_rev,int date)473 static inline void print_ucode(int old_rev, int new_rev, int date)
474 {
475 print_ucode_info(old_rev, new_rev, date);
476 }
477 #endif
478
apply_microcode_early(struct ucode_cpu_info * uci,bool early)479 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
480 {
481 struct microcode_intel *mc;
482 u32 rev, old_rev;
483
484 mc = uci->mc;
485 if (!mc)
486 return 0;
487
488 /*
489 * Save us the MSR write below - which is a particular expensive
490 * operation - when the other hyperthread has updated the microcode
491 * already.
492 */
493 rev = intel_get_microcode_revision();
494 if (rev >= mc->hdr.rev) {
495 uci->cpu_sig.rev = rev;
496 return UCODE_OK;
497 }
498
499 old_rev = rev;
500
501 /*
502 * Writeback and invalidate caches before updating microcode to avoid
503 * internal issues depending on what the microcode is updating.
504 */
505 native_wbinvd();
506
507 /* write microcode via MSR 0x79 */
508 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
509
510 rev = intel_get_microcode_revision();
511 if (rev != mc->hdr.rev)
512 return -1;
513
514 uci->cpu_sig.rev = rev;
515
516 if (early)
517 print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date);
518 else
519 print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date);
520
521 return 0;
522 }
523
save_microcode_in_initrd_intel(void)524 int __init save_microcode_in_initrd_intel(void)
525 {
526 struct ucode_cpu_info uci;
527 struct cpio_data cp;
528
529 /*
530 * initrd is going away, clear patch ptr. We will scan the microcode one
531 * last time before jettisoning and save a patch, if found. Then we will
532 * update that pointer too, with a stable patch address to use when
533 * resuming the cores.
534 */
535 intel_ucode_patch = NULL;
536
537 if (!load_builtin_intel_microcode(&cp))
538 cp = find_microcode_in_initrd(ucode_path, false);
539
540 if (!(cp.data && cp.size))
541 return 0;
542
543 intel_cpu_collect_info(&uci);
544
545 scan_microcode(cp.data, cp.size, &uci, true);
546 return 0;
547 }
548
549 /*
550 * @res_patch, output: a pointer to the patch we found.
551 */
__load_ucode_intel(struct ucode_cpu_info * uci)552 static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci)
553 {
554 static const char *path;
555 struct cpio_data cp;
556 bool use_pa;
557
558 if (IS_ENABLED(CONFIG_X86_32)) {
559 path = (const char *)__pa_nodebug(ucode_path);
560 use_pa = true;
561 } else {
562 path = ucode_path;
563 use_pa = false;
564 }
565
566 /* try built-in microcode first */
567 if (!load_builtin_intel_microcode(&cp))
568 cp = find_microcode_in_initrd(path, use_pa);
569
570 if (!(cp.data && cp.size))
571 return NULL;
572
573 intel_cpu_collect_info(uci);
574
575 return scan_microcode(cp.data, cp.size, uci, false);
576 }
577
load_ucode_intel_bsp(void)578 void __init load_ucode_intel_bsp(void)
579 {
580 struct microcode_intel *patch;
581 struct ucode_cpu_info uci;
582
583 patch = __load_ucode_intel(&uci);
584 if (!patch)
585 return;
586
587 uci.mc = patch;
588
589 apply_microcode_early(&uci, true);
590 }
591
load_ucode_intel_ap(void)592 void load_ucode_intel_ap(void)
593 {
594 struct microcode_intel *patch, **iup;
595 struct ucode_cpu_info uci;
596
597 if (IS_ENABLED(CONFIG_X86_32))
598 iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch);
599 else
600 iup = &intel_ucode_patch;
601
602 if (!*iup) {
603 patch = __load_ucode_intel(&uci);
604 if (!patch)
605 return;
606
607 *iup = patch;
608 }
609
610 uci.mc = *iup;
611
612 apply_microcode_early(&uci, true);
613 }
614
find_patch(struct ucode_cpu_info * uci)615 static struct microcode_intel *find_patch(struct ucode_cpu_info *uci)
616 {
617 struct microcode_header_intel *phdr;
618 struct ucode_patch *iter, *tmp;
619
620 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) {
621
622 phdr = (struct microcode_header_intel *)iter->data;
623
624 if (phdr->rev <= uci->cpu_sig.rev)
625 continue;
626
627 if (!intel_find_matching_signature(phdr,
628 uci->cpu_sig.sig,
629 uci->cpu_sig.pf))
630 continue;
631
632 return iter->data;
633 }
634 return NULL;
635 }
636
reload_ucode_intel(void)637 void reload_ucode_intel(void)
638 {
639 struct microcode_intel *p;
640 struct ucode_cpu_info uci;
641
642 intel_cpu_collect_info(&uci);
643
644 p = find_patch(&uci);
645 if (!p)
646 return;
647
648 uci.mc = p;
649
650 apply_microcode_early(&uci, false);
651 }
652
collect_cpu_info(int cpu_num,struct cpu_signature * csig)653 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
654 {
655 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
656 unsigned int val[2];
657
658 memset(csig, 0, sizeof(*csig));
659
660 csig->sig = cpuid_eax(0x00000001);
661
662 if ((c->x86_model >= 5) || (c->x86 > 6)) {
663 /* get processor flags from MSR 0x17 */
664 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
665 csig->pf = 1 << ((val[1] >> 18) & 7);
666 }
667
668 csig->rev = c->microcode;
669
670 return 0;
671 }
672
apply_microcode_intel(int cpu)673 static enum ucode_state apply_microcode_intel(int cpu)
674 {
675 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
676 struct cpuinfo_x86 *c = &cpu_data(cpu);
677 bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
678 struct microcode_intel *mc;
679 enum ucode_state ret;
680 static int prev_rev;
681 u32 rev;
682
683 /* We should bind the task to the CPU */
684 if (WARN_ON(raw_smp_processor_id() != cpu))
685 return UCODE_ERROR;
686
687 /* Look for a newer patch in our cache: */
688 mc = find_patch(uci);
689 if (!mc) {
690 mc = uci->mc;
691 if (!mc)
692 return UCODE_NFOUND;
693 }
694
695 /*
696 * Save us the MSR write below - which is a particular expensive
697 * operation - when the other hyperthread has updated the microcode
698 * already.
699 */
700 rev = intel_get_microcode_revision();
701 if (rev >= mc->hdr.rev) {
702 ret = UCODE_OK;
703 goto out;
704 }
705
706 /*
707 * Writeback and invalidate caches before updating microcode to avoid
708 * internal issues depending on what the microcode is updating.
709 */
710 native_wbinvd();
711
712 /* write microcode via MSR 0x79 */
713 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
714
715 rev = intel_get_microcode_revision();
716
717 if (rev != mc->hdr.rev) {
718 pr_err("CPU%d update to revision 0x%x failed\n",
719 cpu, mc->hdr.rev);
720 return UCODE_ERROR;
721 }
722
723 if (bsp && rev != prev_rev) {
724 pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n",
725 rev,
726 mc->hdr.date & 0xffff,
727 mc->hdr.date >> 24,
728 (mc->hdr.date >> 16) & 0xff);
729 prev_rev = rev;
730 }
731
732 ret = UCODE_UPDATED;
733
734 out:
735 uci->cpu_sig.rev = rev;
736 c->microcode = rev;
737
738 /* Update boot_cpu_data's revision too, if we're on the BSP: */
739 if (bsp)
740 boot_cpu_data.microcode = rev;
741
742 return ret;
743 }
744
generic_load_microcode(int cpu,struct iov_iter * iter)745 static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter)
746 {
747 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
748 unsigned int curr_mc_size = 0, new_mc_size = 0;
749 enum ucode_state ret = UCODE_OK;
750 int new_rev = uci->cpu_sig.rev;
751 u8 *new_mc = NULL, *mc = NULL;
752 unsigned int csig, cpf;
753
754 while (iov_iter_count(iter)) {
755 struct microcode_header_intel mc_header;
756 unsigned int mc_size, data_size;
757 u8 *data;
758
759 if (!copy_from_iter_full(&mc_header, sizeof(mc_header), iter)) {
760 pr_err("error! Truncated or inaccessible header in microcode data file\n");
761 break;
762 }
763
764 mc_size = get_totalsize(&mc_header);
765 if (mc_size < sizeof(mc_header)) {
766 pr_err("error! Bad data in microcode data file (totalsize too small)\n");
767 break;
768 }
769 data_size = mc_size - sizeof(mc_header);
770 if (data_size > iov_iter_count(iter)) {
771 pr_err("error! Bad data in microcode data file (truncated file?)\n");
772 break;
773 }
774
775 /* For performance reasons, reuse mc area when possible */
776 if (!mc || mc_size > curr_mc_size) {
777 vfree(mc);
778 mc = vmalloc(mc_size);
779 if (!mc)
780 break;
781 curr_mc_size = mc_size;
782 }
783
784 memcpy(mc, &mc_header, sizeof(mc_header));
785 data = mc + sizeof(mc_header);
786 if (!copy_from_iter_full(data, data_size, iter) ||
787 intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) {
788 break;
789 }
790
791 csig = uci->cpu_sig.sig;
792 cpf = uci->cpu_sig.pf;
793 if (has_newer_microcode(mc, csig, cpf, new_rev)) {
794 vfree(new_mc);
795 new_rev = mc_header.rev;
796 new_mc = mc;
797 new_mc_size = mc_size;
798 mc = NULL; /* trigger new vmalloc */
799 ret = UCODE_NEW;
800 }
801 }
802
803 vfree(mc);
804
805 if (iov_iter_count(iter)) {
806 vfree(new_mc);
807 return UCODE_ERROR;
808 }
809
810 if (!new_mc)
811 return UCODE_NFOUND;
812
813 vfree(uci->mc);
814 uci->mc = (struct microcode_intel *)new_mc;
815
816 /* Save for CPU hotplug */
817 save_microcode_patch(uci, new_mc, new_mc_size);
818
819 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
820 cpu, new_rev, uci->cpu_sig.rev);
821
822 return ret;
823 }
824
is_blacklisted(unsigned int cpu)825 static bool is_blacklisted(unsigned int cpu)
826 {
827 struct cpuinfo_x86 *c = &cpu_data(cpu);
828
829 /*
830 * Late loading on model 79 with microcode revision less than 0x0b000021
831 * and LLC size per core bigger than 2.5MB may result in a system hang.
832 * This behavior is documented in item BDF90, #334165 (Intel Xeon
833 * Processor E7-8800/4800 v4 Product Family).
834 */
835 if (c->x86 == 6 &&
836 c->x86_model == INTEL_FAM6_BROADWELL_X &&
837 c->x86_stepping == 0x01 &&
838 llc_size_per_core > 2621440 &&
839 c->microcode < 0x0b000021) {
840 pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
841 pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
842 return true;
843 }
844
845 return false;
846 }
847
request_microcode_fw(int cpu,struct device * device)848 static enum ucode_state request_microcode_fw(int cpu, struct device *device)
849 {
850 struct cpuinfo_x86 *c = &cpu_data(cpu);
851 const struct firmware *firmware;
852 struct iov_iter iter;
853 enum ucode_state ret;
854 struct kvec kvec;
855 char name[30];
856
857 if (is_blacklisted(cpu))
858 return UCODE_NFOUND;
859
860 sprintf(name, "intel-ucode/%02x-%02x-%02x",
861 c->x86, c->x86_model, c->x86_stepping);
862
863 if (request_firmware_direct(&firmware, name, device)) {
864 pr_debug("data file %s load failed\n", name);
865 return UCODE_NFOUND;
866 }
867
868 kvec.iov_base = (void *)firmware->data;
869 kvec.iov_len = firmware->size;
870 iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size);
871 ret = generic_load_microcode(cpu, &iter);
872
873 release_firmware(firmware);
874
875 return ret;
876 }
877
878 static struct microcode_ops microcode_intel_ops = {
879 .request_microcode_fw = request_microcode_fw,
880 .collect_cpu_info = collect_cpu_info,
881 .apply_microcode = apply_microcode_intel,
882 };
883
calc_llc_size_per_core(struct cpuinfo_x86 * c)884 static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c)
885 {
886 u64 llc_size = c->x86_cache_size * 1024ULL;
887
888 do_div(llc_size, c->x86_max_cores);
889
890 return (int)llc_size;
891 }
892
init_intel_microcode(void)893 struct microcode_ops * __init init_intel_microcode(void)
894 {
895 struct cpuinfo_x86 *c = &boot_cpu_data;
896
897 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
898 cpu_has(c, X86_FEATURE_IA64)) {
899 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
900 return NULL;
901 }
902
903 llc_size_per_core = calc_llc_size_per_core(c);
904
905 return µcode_intel_ops;
906 }
907