1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
3 */
4
5 #include <linux/clk-provider.h>
6 #include <linux/pci.h>
7 #include <linux/dmi.h>
8 #include "dwmac-intel.h"
9 #include "dwmac4.h"
10 #include "stmmac.h"
11 #include "stmmac_ptp.h"
12
13 struct intel_priv_data {
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
15 unsigned long crossts_adj;
16 bool is_pse;
17 };
18
19 /* This struct is used to associate PCI Function of MAC controller on a board,
20 * discovered via DMI, with the address of PHY connected to the MAC. The
21 * negative value of the address means that MAC controller is not connected
22 * with PHY.
23 */
24 struct stmmac_pci_func_data {
25 unsigned int func;
26 int phy_addr;
27 };
28
29 struct stmmac_pci_dmi_data {
30 const struct stmmac_pci_func_data *func;
31 size_t nfuncs;
32 };
33
34 struct stmmac_pci_info {
35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
36 };
37
stmmac_pci_find_phy_addr(struct pci_dev * pdev,const struct dmi_system_id * dmi_list)38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
39 const struct dmi_system_id *dmi_list)
40 {
41 const struct stmmac_pci_func_data *func_data;
42 const struct stmmac_pci_dmi_data *dmi_data;
43 const struct dmi_system_id *dmi_id;
44 int func = PCI_FUNC(pdev->devfn);
45 size_t n;
46
47 dmi_id = dmi_first_match(dmi_list);
48 if (!dmi_id)
49 return -ENODEV;
50
51 dmi_data = dmi_id->driver_data;
52 func_data = dmi_data->func;
53
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
55 if (func_data->func == func)
56 return func_data->phy_addr;
57
58 return -ENODEV;
59 }
60
serdes_status_poll(struct stmmac_priv * priv,int phyaddr,int phyreg,u32 mask,u32 val)61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
62 int phyreg, u32 mask, u32 val)
63 {
64 unsigned int retries = 10;
65 int val_rd;
66
67 do {
68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
69 if ((val_rd & mask) == (val & mask))
70 return 0;
71 udelay(POLL_DELAY_US);
72 } while (--retries);
73
74 return -ETIMEDOUT;
75 }
76
intel_serdes_powerup(struct net_device * ndev,void * priv_data)77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
78 {
79 struct intel_priv_data *intel_priv = priv_data;
80 struct stmmac_priv *priv = netdev_priv(ndev);
81 int serdes_phy_addr = 0;
82 u32 data = 0;
83
84 if (!intel_priv->mdio_adhoc_addr)
85 return 0;
86
87 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
88
89 /* Set the serdes rate and the PCLK rate */
90 data = mdiobus_read(priv->mii, serdes_phy_addr,
91 SERDES_GCR0);
92
93 data &= ~SERDES_RATE_MASK;
94 data &= ~SERDES_PCLK_MASK;
95
96 if (priv->plat->max_speed == 2500)
97 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
98 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
99 else
100 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
101 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
102
103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
104
105 /* assert clk_req */
106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
107 data |= SERDES_PLL_CLK;
108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
109
110 /* check for clk_ack assertion */
111 data = serdes_status_poll(priv, serdes_phy_addr,
112 SERDES_GSR0,
113 SERDES_PLL_CLK,
114 SERDES_PLL_CLK);
115
116 if (data) {
117 dev_err(priv->device, "Serdes PLL clk request timeout\n");
118 return data;
119 }
120
121 /* assert lane reset */
122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
123 data |= SERDES_RST;
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
125
126 /* check for assert lane reset reflection */
127 data = serdes_status_poll(priv, serdes_phy_addr,
128 SERDES_GSR0,
129 SERDES_RST,
130 SERDES_RST);
131
132 if (data) {
133 dev_err(priv->device, "Serdes assert lane reset timeout\n");
134 return data;
135 }
136
137 /* move power state to P0 */
138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
139
140 data &= ~SERDES_PWR_ST_MASK;
141 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
142
143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
144
145 /* Check for P0 state */
146 data = serdes_status_poll(priv, serdes_phy_addr,
147 SERDES_GSR0,
148 SERDES_PWR_ST_MASK,
149 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
150
151 if (data) {
152 dev_err(priv->device, "Serdes power state P0 timeout.\n");
153 return data;
154 }
155
156 /* PSE only - ungate SGMII PHY Rx Clock */
157 if (intel_priv->is_pse)
158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
159 0, SERDES_PHY_RX_CLK);
160
161 return 0;
162 }
163
intel_serdes_powerdown(struct net_device * ndev,void * intel_data)164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
165 {
166 struct intel_priv_data *intel_priv = intel_data;
167 struct stmmac_priv *priv = netdev_priv(ndev);
168 int serdes_phy_addr = 0;
169 u32 data = 0;
170
171 if (!intel_priv->mdio_adhoc_addr)
172 return;
173
174 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
175
176 /* PSE only - gate SGMII PHY Rx Clock */
177 if (intel_priv->is_pse)
178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
179 SERDES_PHY_RX_CLK, 0);
180
181 /* move power state to P3 */
182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
183
184 data &= ~SERDES_PWR_ST_MASK;
185 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
186
187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
188
189 /* Check for P3 state */
190 data = serdes_status_poll(priv, serdes_phy_addr,
191 SERDES_GSR0,
192 SERDES_PWR_ST_MASK,
193 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
194
195 if (data) {
196 dev_err(priv->device, "Serdes power state P3 timeout\n");
197 return;
198 }
199
200 /* de-assert clk_req */
201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
202 data &= ~SERDES_PLL_CLK;
203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
204
205 /* check for clk_ack de-assert */
206 data = serdes_status_poll(priv, serdes_phy_addr,
207 SERDES_GSR0,
208 SERDES_PLL_CLK,
209 (u32)~SERDES_PLL_CLK);
210
211 if (data) {
212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
213 return;
214 }
215
216 /* de-assert lane reset */
217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
218 data &= ~SERDES_RST;
219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
220
221 /* check for de-assert lane reset reflection */
222 data = serdes_status_poll(priv, serdes_phy_addr,
223 SERDES_GSR0,
224 SERDES_RST,
225 (u32)~SERDES_RST);
226
227 if (data) {
228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
229 return;
230 }
231 }
232
intel_speed_mode_2500(struct net_device * ndev,void * intel_data)233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
234 {
235 struct intel_priv_data *intel_priv = intel_data;
236 struct stmmac_priv *priv = netdev_priv(ndev);
237 int serdes_phy_addr = 0;
238 u32 data = 0;
239
240 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
241
242 /* Determine the link speed mode: 2.5Gbps/1Gbps */
243 data = mdiobus_read(priv->mii, serdes_phy_addr,
244 SERDES_GCR);
245
246 if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
247 SERDES_LINK_MODE_2G5) {
248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
249 priv->plat->max_speed = 2500;
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
251 priv->plat->mdio_bus_data->xpcs_an_inband = false;
252 } else {
253 priv->plat->max_speed = 1000;
254 }
255 }
256
257 /* Program PTP Clock Frequency for different variant of
258 * Intel mGBE that has slightly different GPO mapping
259 */
intel_mgbe_ptp_clk_freq_config(struct stmmac_priv * priv)260 static void intel_mgbe_ptp_clk_freq_config(struct stmmac_priv *priv)
261 {
262 struct intel_priv_data *intel_priv;
263 u32 gpio_value;
264
265 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
266
267 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
268
269 if (intel_priv->is_pse) {
270 /* For PSE GbE, use 200MHz */
271 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
272 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
273 } else {
274 /* For PCH GbE, use 200MHz */
275 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
276 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
277 }
278
279 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
280 }
281
get_arttime(struct mii_bus * mii,int intel_adhoc_addr,u64 * art_time)282 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
283 u64 *art_time)
284 {
285 u64 ns;
286
287 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
288 ns <<= GMAC4_ART_TIME_SHIFT;
289 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
290 ns <<= GMAC4_ART_TIME_SHIFT;
291 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
292 ns <<= GMAC4_ART_TIME_SHIFT;
293 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
294
295 *art_time = ns;
296 }
297
stmmac_cross_ts_isr(struct stmmac_priv * priv)298 static int stmmac_cross_ts_isr(struct stmmac_priv *priv)
299 {
300 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE);
301 }
302
intel_crosststamp(ktime_t * device,struct system_counterval_t * system,void * ctx)303 static int intel_crosststamp(ktime_t *device,
304 struct system_counterval_t *system,
305 void *ctx)
306 {
307 struct intel_priv_data *intel_priv;
308
309 struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
310 void __iomem *ptpaddr = priv->ptpaddr;
311 void __iomem *ioaddr = priv->hw->pcsr;
312 unsigned long flags;
313 u64 art_time = 0;
314 u64 ptp_time = 0;
315 u32 num_snapshot;
316 u32 gpio_value;
317 u32 acr_value;
318 int i;
319
320 if (!boot_cpu_has(X86_FEATURE_ART))
321 return -EOPNOTSUPP;
322
323 intel_priv = priv->plat->bsp_priv;
324
325 /* Both internal crosstimestamping and external triggered event
326 * timestamping cannot be run concurrently.
327 */
328 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
329 return -EBUSY;
330
331 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN;
332
333 mutex_lock(&priv->aux_ts_lock);
334 /* Enable Internal snapshot trigger */
335 acr_value = readl(ptpaddr + PTP_ACR);
336 acr_value &= ~PTP_ACR_MASK;
337 switch (priv->plat->int_snapshot_num) {
338 case AUX_SNAPSHOT0:
339 acr_value |= PTP_ACR_ATSEN0;
340 break;
341 case AUX_SNAPSHOT1:
342 acr_value |= PTP_ACR_ATSEN1;
343 break;
344 case AUX_SNAPSHOT2:
345 acr_value |= PTP_ACR_ATSEN2;
346 break;
347 case AUX_SNAPSHOT3:
348 acr_value |= PTP_ACR_ATSEN3;
349 break;
350 default:
351 mutex_unlock(&priv->aux_ts_lock);
352 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
353 return -EINVAL;
354 }
355 writel(acr_value, ptpaddr + PTP_ACR);
356
357 /* Clear FIFO */
358 acr_value = readl(ptpaddr + PTP_ACR);
359 acr_value |= PTP_ACR_ATSFC;
360 writel(acr_value, ptpaddr + PTP_ACR);
361 /* Release the mutex */
362 mutex_unlock(&priv->aux_ts_lock);
363
364 /* Trigger Internal snapshot signal
365 * Create a rising edge by just toggle the GPO1 to low
366 * and back to high.
367 */
368 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
369 gpio_value &= ~GMAC_GPO1;
370 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
371 gpio_value |= GMAC_GPO1;
372 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
373
374 /* Time sync done Indication - Interrupt method */
375 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait,
376 stmmac_cross_ts_isr(priv),
377 HZ / 100)) {
378 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
379 return -ETIMEDOUT;
380 }
381
382 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
383 GMAC_TIMESTAMP_ATSNS_MASK) >>
384 GMAC_TIMESTAMP_ATSNS_SHIFT;
385
386 /* Repeat until the timestamps are from the FIFO last segment */
387 for (i = 0; i < num_snapshot; i++) {
388 read_lock_irqsave(&priv->ptp_lock, flags);
389 stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
390 *device = ns_to_ktime(ptp_time);
391 read_unlock_irqrestore(&priv->ptp_lock, flags);
392 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
393 *system = convert_art_to_tsc(art_time);
394 }
395
396 system->cycles *= intel_priv->crossts_adj;
397 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
398
399 return 0;
400 }
401
intel_mgbe_pse_crossts_adj(struct intel_priv_data * intel_priv,int base)402 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
403 int base)
404 {
405 if (boot_cpu_has(X86_FEATURE_ART)) {
406 unsigned int art_freq;
407
408 /* On systems that support ART, ART frequency can be obtained
409 * from ECX register of CPUID leaf (0x15).
410 */
411 art_freq = cpuid_ecx(ART_CPUID_LEAF);
412 do_div(art_freq, base);
413 intel_priv->crossts_adj = art_freq;
414 }
415 }
416
common_default_data(struct plat_stmmacenet_data * plat)417 static void common_default_data(struct plat_stmmacenet_data *plat)
418 {
419 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
420 plat->has_gmac = 1;
421 plat->force_sf_dma_mode = 1;
422
423 plat->mdio_bus_data->needs_reset = true;
424
425 /* Set default value for multicast hash bins */
426 plat->multicast_filter_bins = HASH_TABLE_SIZE;
427
428 /* Set default value for unicast filter entries */
429 plat->unicast_filter_entries = 1;
430
431 /* Set the maxmtu to a default of JUMBO_LEN */
432 plat->maxmtu = JUMBO_LEN;
433
434 /* Set default number of RX and TX queues to use */
435 plat->tx_queues_to_use = 1;
436 plat->rx_queues_to_use = 1;
437
438 /* Disable Priority config by default */
439 plat->tx_queues_cfg[0].use_prio = false;
440 plat->rx_queues_cfg[0].use_prio = false;
441
442 /* Disable RX queues routing by default */
443 plat->rx_queues_cfg[0].pkt_route = 0x0;
444 }
445
intel_mgbe_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)446 static int intel_mgbe_common_data(struct pci_dev *pdev,
447 struct plat_stmmacenet_data *plat)
448 {
449 struct fwnode_handle *fwnode;
450 char clk_name[20];
451 int ret;
452 int i;
453
454 plat->pdev = pdev;
455 plat->phy_addr = -1;
456 plat->clk_csr = 5;
457 plat->has_gmac = 0;
458 plat->has_gmac4 = 1;
459 plat->force_sf_dma_mode = 0;
460 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE);
461
462 /* Multiplying factor to the clk_eee_i clock time
463 * period to make it closer to 100 ns. This value
464 * should be programmed such that the clk_eee_time_period *
465 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
466 * clk_eee frequency is 19.2Mhz
467 * clk_eee_time_period is 52ns
468 * 52ns * (1 + 1) = 104ns
469 * MULT_FACT_100NS = 1
470 */
471 plat->mult_fact_100ns = 1;
472
473 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
474
475 for (i = 0; i < plat->rx_queues_to_use; i++) {
476 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
477 plat->rx_queues_cfg[i].chan = i;
478
479 /* Disable Priority config by default */
480 plat->rx_queues_cfg[i].use_prio = false;
481
482 /* Disable RX queues routing by default */
483 plat->rx_queues_cfg[i].pkt_route = 0x0;
484 }
485
486 for (i = 0; i < plat->tx_queues_to_use; i++) {
487 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
488
489 /* Disable Priority config by default */
490 plat->tx_queues_cfg[i].use_prio = false;
491 /* Default TX Q0 to use TSO and rest TXQ for TBS */
492 if (i > 0)
493 plat->tx_queues_cfg[i].tbs_en = 1;
494 }
495
496 /* FIFO size is 4096 bytes for 1 tx/rx queue */
497 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
498 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
499
500 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
501 plat->tx_queues_cfg[0].weight = 0x09;
502 plat->tx_queues_cfg[1].weight = 0x0A;
503 plat->tx_queues_cfg[2].weight = 0x0B;
504 plat->tx_queues_cfg[3].weight = 0x0C;
505 plat->tx_queues_cfg[4].weight = 0x0D;
506 plat->tx_queues_cfg[5].weight = 0x0E;
507 plat->tx_queues_cfg[6].weight = 0x0F;
508 plat->tx_queues_cfg[7].weight = 0x10;
509
510 plat->dma_cfg->pbl = 32;
511 plat->dma_cfg->pblx8 = true;
512 plat->dma_cfg->fixed_burst = 0;
513 plat->dma_cfg->mixed_burst = 0;
514 plat->dma_cfg->aal = 0;
515 plat->dma_cfg->dche = true;
516
517 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
518 GFP_KERNEL);
519 if (!plat->axi)
520 return -ENOMEM;
521
522 plat->axi->axi_lpi_en = 0;
523 plat->axi->axi_xit_frm = 0;
524 plat->axi->axi_wr_osr_lmt = 1;
525 plat->axi->axi_rd_osr_lmt = 1;
526 plat->axi->axi_blen[0] = 4;
527 plat->axi->axi_blen[1] = 8;
528 plat->axi->axi_blen[2] = 16;
529
530 plat->ptp_max_adj = plat->clk_ptp_rate;
531 plat->eee_usecs_rate = plat->clk_ptp_rate;
532
533 /* Set system clock */
534 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
535
536 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
537 clk_name, NULL, 0,
538 plat->clk_ptp_rate);
539
540 if (IS_ERR(plat->stmmac_clk)) {
541 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
542 plat->stmmac_clk = NULL;
543 }
544
545 ret = clk_prepare_enable(plat->stmmac_clk);
546 if (ret) {
547 clk_unregister_fixed_rate(plat->stmmac_clk);
548 return ret;
549 }
550
551 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
552
553 /* Set default value for multicast hash bins */
554 plat->multicast_filter_bins = HASH_TABLE_SIZE;
555
556 /* Set default value for unicast filter entries */
557 plat->unicast_filter_entries = 1;
558
559 /* Set the maxmtu to a default of JUMBO_LEN */
560 plat->maxmtu = JUMBO_LEN;
561
562 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN;
563
564 /* Use the last Rx queue */
565 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
566
567 /* For fixed-link setup, we allow phy-mode setting */
568 fwnode = dev_fwnode(&pdev->dev);
569 if (fwnode) {
570 int phy_mode;
571
572 /* "phy-mode" setting is optional. If it is set,
573 * we allow either sgmii or 1000base-x for now.
574 */
575 phy_mode = fwnode_get_phy_mode(fwnode);
576 if (phy_mode >= 0) {
577 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
578 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
579 plat->phy_interface = phy_mode;
580 else
581 dev_warn(&pdev->dev, "Invalid phy-mode\n");
582 }
583 }
584
585 /* Intel mgbe SGMII interface uses pcs-xcps */
586 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
587 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
588 plat->mdio_bus_data->has_xpcs = true;
589 plat->mdio_bus_data->xpcs_an_inband = true;
590 }
591
592 /* For fixed-link setup, we clear xpcs_an_inband */
593 if (fwnode) {
594 struct fwnode_handle *fixed_node;
595
596 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
597 if (fixed_node)
598 plat->mdio_bus_data->xpcs_an_inband = false;
599
600 fwnode_handle_put(fixed_node);
601 }
602
603 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
604 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
605 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
606
607 plat->int_snapshot_num = AUX_SNAPSHOT1;
608 plat->ext_snapshot_num = AUX_SNAPSHOT0;
609
610 plat->crosststamp = intel_crosststamp;
611 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
612
613 /* Setup MSI vector offset specific to Intel mGbE controller */
614 plat->msi_mac_vec = 29;
615 plat->msi_lpi_vec = 28;
616 plat->msi_sfty_ce_vec = 27;
617 plat->msi_sfty_ue_vec = 26;
618 plat->msi_rx_base_vec = 0;
619 plat->msi_tx_base_vec = 1;
620
621 return 0;
622 }
623
ehl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)624 static int ehl_common_data(struct pci_dev *pdev,
625 struct plat_stmmacenet_data *plat)
626 {
627 plat->rx_queues_to_use = 8;
628 plat->tx_queues_to_use = 8;
629 plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
630 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY;
631
632 plat->safety_feat_cfg->tsoee = 1;
633 plat->safety_feat_cfg->mrxpee = 1;
634 plat->safety_feat_cfg->mestee = 1;
635 plat->safety_feat_cfg->mrxee = 1;
636 plat->safety_feat_cfg->mtxee = 1;
637 plat->safety_feat_cfg->epsi = 0;
638 plat->safety_feat_cfg->edpp = 0;
639 plat->safety_feat_cfg->prtyen = 0;
640 plat->safety_feat_cfg->tmouten = 0;
641
642 return intel_mgbe_common_data(pdev, plat);
643 }
644
ehl_sgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)645 static int ehl_sgmii_data(struct pci_dev *pdev,
646 struct plat_stmmacenet_data *plat)
647 {
648 plat->bus_id = 1;
649 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
650 plat->speed_mode_2500 = intel_speed_mode_2500;
651 plat->serdes_powerup = intel_serdes_powerup;
652 plat->serdes_powerdown = intel_serdes_powerdown;
653
654 plat->clk_ptp_rate = 204800000;
655
656 return ehl_common_data(pdev, plat);
657 }
658
659 static struct stmmac_pci_info ehl_sgmii1g_info = {
660 .setup = ehl_sgmii_data,
661 };
662
ehl_rgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)663 static int ehl_rgmii_data(struct pci_dev *pdev,
664 struct plat_stmmacenet_data *plat)
665 {
666 plat->bus_id = 1;
667 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
668
669 plat->clk_ptp_rate = 204800000;
670
671 return ehl_common_data(pdev, plat);
672 }
673
674 static struct stmmac_pci_info ehl_rgmii1g_info = {
675 .setup = ehl_rgmii_data,
676 };
677
ehl_pse0_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)678 static int ehl_pse0_common_data(struct pci_dev *pdev,
679 struct plat_stmmacenet_data *plat)
680 {
681 struct intel_priv_data *intel_priv = plat->bsp_priv;
682
683 intel_priv->is_pse = true;
684 plat->bus_id = 2;
685 plat->host_dma_width = 32;
686
687 plat->clk_ptp_rate = 200000000;
688
689 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
690
691 return ehl_common_data(pdev, plat);
692 }
693
ehl_pse0_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)694 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
695 struct plat_stmmacenet_data *plat)
696 {
697 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
698 return ehl_pse0_common_data(pdev, plat);
699 }
700
701 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
702 .setup = ehl_pse0_rgmii1g_data,
703 };
704
ehl_pse0_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)705 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
706 struct plat_stmmacenet_data *plat)
707 {
708 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
709 plat->speed_mode_2500 = intel_speed_mode_2500;
710 plat->serdes_powerup = intel_serdes_powerup;
711 plat->serdes_powerdown = intel_serdes_powerdown;
712 return ehl_pse0_common_data(pdev, plat);
713 }
714
715 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
716 .setup = ehl_pse0_sgmii1g_data,
717 };
718
ehl_pse1_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)719 static int ehl_pse1_common_data(struct pci_dev *pdev,
720 struct plat_stmmacenet_data *plat)
721 {
722 struct intel_priv_data *intel_priv = plat->bsp_priv;
723
724 intel_priv->is_pse = true;
725 plat->bus_id = 3;
726 plat->host_dma_width = 32;
727
728 plat->clk_ptp_rate = 200000000;
729
730 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
731
732 return ehl_common_data(pdev, plat);
733 }
734
ehl_pse1_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)735 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
736 struct plat_stmmacenet_data *plat)
737 {
738 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
739 return ehl_pse1_common_data(pdev, plat);
740 }
741
742 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
743 .setup = ehl_pse1_rgmii1g_data,
744 };
745
ehl_pse1_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)746 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
747 struct plat_stmmacenet_data *plat)
748 {
749 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
750 plat->speed_mode_2500 = intel_speed_mode_2500;
751 plat->serdes_powerup = intel_serdes_powerup;
752 plat->serdes_powerdown = intel_serdes_powerdown;
753 return ehl_pse1_common_data(pdev, plat);
754 }
755
756 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
757 .setup = ehl_pse1_sgmii1g_data,
758 };
759
tgl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)760 static int tgl_common_data(struct pci_dev *pdev,
761 struct plat_stmmacenet_data *plat)
762 {
763 plat->rx_queues_to_use = 6;
764 plat->tx_queues_to_use = 4;
765 plat->clk_ptp_rate = 204800000;
766 plat->speed_mode_2500 = intel_speed_mode_2500;
767
768 plat->safety_feat_cfg->tsoee = 1;
769 plat->safety_feat_cfg->mrxpee = 0;
770 plat->safety_feat_cfg->mestee = 1;
771 plat->safety_feat_cfg->mrxee = 1;
772 plat->safety_feat_cfg->mtxee = 1;
773 plat->safety_feat_cfg->epsi = 0;
774 plat->safety_feat_cfg->edpp = 0;
775 plat->safety_feat_cfg->prtyen = 0;
776 plat->safety_feat_cfg->tmouten = 0;
777
778 return intel_mgbe_common_data(pdev, plat);
779 }
780
tgl_sgmii_phy0_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)781 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
782 struct plat_stmmacenet_data *plat)
783 {
784 plat->bus_id = 1;
785 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
786 plat->serdes_powerup = intel_serdes_powerup;
787 plat->serdes_powerdown = intel_serdes_powerdown;
788 return tgl_common_data(pdev, plat);
789 }
790
791 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
792 .setup = tgl_sgmii_phy0_data,
793 };
794
tgl_sgmii_phy1_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)795 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
796 struct plat_stmmacenet_data *plat)
797 {
798 plat->bus_id = 2;
799 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
800 plat->serdes_powerup = intel_serdes_powerup;
801 plat->serdes_powerdown = intel_serdes_powerdown;
802 return tgl_common_data(pdev, plat);
803 }
804
805 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
806 .setup = tgl_sgmii_phy1_data,
807 };
808
adls_sgmii_phy0_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)809 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
810 struct plat_stmmacenet_data *plat)
811 {
812 plat->bus_id = 1;
813 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
814
815 /* SerDes power up and power down are done in BIOS for ADL */
816
817 return tgl_common_data(pdev, plat);
818 }
819
820 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
821 .setup = adls_sgmii_phy0_data,
822 };
823
adls_sgmii_phy1_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)824 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
825 struct plat_stmmacenet_data *plat)
826 {
827 plat->bus_id = 2;
828 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
829
830 /* SerDes power up and power down are done in BIOS for ADL */
831
832 return tgl_common_data(pdev, plat);
833 }
834
835 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
836 .setup = adls_sgmii_phy1_data,
837 };
838 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
839 {
840 .func = 6,
841 .phy_addr = 1,
842 },
843 };
844
845 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
846 .func = galileo_stmmac_func_data,
847 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
848 };
849
850 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
851 {
852 .func = 6,
853 .phy_addr = 1,
854 },
855 {
856 .func = 7,
857 .phy_addr = 1,
858 },
859 };
860
861 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
862 .func = iot2040_stmmac_func_data,
863 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
864 };
865
866 static const struct dmi_system_id quark_pci_dmi[] = {
867 {
868 .matches = {
869 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
870 },
871 .driver_data = (void *)&galileo_stmmac_dmi_data,
872 },
873 {
874 .matches = {
875 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
876 },
877 .driver_data = (void *)&galileo_stmmac_dmi_data,
878 },
879 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
880 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
881 * has only one pci network device while other asset tags are
882 * for IOT2040 which has two.
883 */
884 {
885 .matches = {
886 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
887 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
888 "6ES7647-0AA00-0YA2"),
889 },
890 .driver_data = (void *)&galileo_stmmac_dmi_data,
891 },
892 {
893 .matches = {
894 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
895 },
896 .driver_data = (void *)&iot2040_stmmac_dmi_data,
897 },
898 {}
899 };
900
quark_default_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)901 static int quark_default_data(struct pci_dev *pdev,
902 struct plat_stmmacenet_data *plat)
903 {
904 int ret;
905
906 /* Set common default data first */
907 common_default_data(plat);
908
909 /* Refuse to load the driver and register net device if MAC controller
910 * does not connect to any PHY interface.
911 */
912 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
913 if (ret < 0) {
914 /* Return error to the caller on DMI enabled boards. */
915 if (dmi_get_system_info(DMI_BOARD_NAME))
916 return ret;
917
918 /* Galileo boards with old firmware don't support DMI. We always
919 * use 1 here as PHY address, so at least the first found MAC
920 * controller would be probed.
921 */
922 ret = 1;
923 }
924
925 plat->bus_id = pci_dev_id(pdev);
926 plat->phy_addr = ret;
927 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
928
929 plat->dma_cfg->pbl = 16;
930 plat->dma_cfg->pblx8 = true;
931 plat->dma_cfg->fixed_burst = 1;
932 /* AXI (TODO) */
933
934 return 0;
935 }
936
937 static const struct stmmac_pci_info quark_info = {
938 .setup = quark_default_data,
939 };
940
stmmac_config_single_msi(struct pci_dev * pdev,struct plat_stmmacenet_data * plat,struct stmmac_resources * res)941 static int stmmac_config_single_msi(struct pci_dev *pdev,
942 struct plat_stmmacenet_data *plat,
943 struct stmmac_resources *res)
944 {
945 int ret;
946
947 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
948 if (ret < 0) {
949 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
950 __func__);
951 return ret;
952 }
953
954 res->irq = pci_irq_vector(pdev, 0);
955 res->wol_irq = res->irq;
956 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN;
957 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
958 __func__);
959
960 return 0;
961 }
962
stmmac_config_multi_msi(struct pci_dev * pdev,struct plat_stmmacenet_data * plat,struct stmmac_resources * res)963 static int stmmac_config_multi_msi(struct pci_dev *pdev,
964 struct plat_stmmacenet_data *plat,
965 struct stmmac_resources *res)
966 {
967 int ret;
968 int i;
969
970 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
971 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
972 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
973 __func__);
974 return -1;
975 }
976
977 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
978 PCI_IRQ_MSI | PCI_IRQ_MSIX);
979 if (ret < 0) {
980 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
981 __func__);
982 return ret;
983 }
984
985 /* For RX MSI */
986 for (i = 0; i < plat->rx_queues_to_use; i++) {
987 res->rx_irq[i] = pci_irq_vector(pdev,
988 plat->msi_rx_base_vec + i * 2);
989 }
990
991 /* For TX MSI */
992 for (i = 0; i < plat->tx_queues_to_use; i++) {
993 res->tx_irq[i] = pci_irq_vector(pdev,
994 plat->msi_tx_base_vec + i * 2);
995 }
996
997 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
998 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
999 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
1000 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
1001 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
1002 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
1003 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
1004 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
1005 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
1006 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
1007
1008 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
1009 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
1010
1011 return 0;
1012 }
1013
1014 /**
1015 * intel_eth_pci_probe
1016 *
1017 * @pdev: pci device pointer
1018 * @id: pointer to table of device id/id's.
1019 *
1020 * Description: This probing function gets called for all PCI devices which
1021 * match the ID table and are not "owned" by other driver yet. This function
1022 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
1023 * matches the device. The probe functions returns zero when the driver choose
1024 * to take "ownership" of the device or an error code(-ve no) otherwise.
1025 */
intel_eth_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1026 static int intel_eth_pci_probe(struct pci_dev *pdev,
1027 const struct pci_device_id *id)
1028 {
1029 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
1030 struct intel_priv_data *intel_priv;
1031 struct plat_stmmacenet_data *plat;
1032 struct stmmac_resources res;
1033 int ret;
1034
1035 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
1036 if (!intel_priv)
1037 return -ENOMEM;
1038
1039 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1040 if (!plat)
1041 return -ENOMEM;
1042
1043 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1044 sizeof(*plat->mdio_bus_data),
1045 GFP_KERNEL);
1046 if (!plat->mdio_bus_data)
1047 return -ENOMEM;
1048
1049 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1050 GFP_KERNEL);
1051 if (!plat->dma_cfg)
1052 return -ENOMEM;
1053
1054 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1055 sizeof(*plat->safety_feat_cfg),
1056 GFP_KERNEL);
1057 if (!plat->safety_feat_cfg)
1058 return -ENOMEM;
1059
1060 /* Enable pci device */
1061 ret = pcim_enable_device(pdev);
1062 if (ret) {
1063 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1064 __func__);
1065 return ret;
1066 }
1067
1068 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1069 if (ret)
1070 return ret;
1071
1072 pci_set_master(pdev);
1073
1074 plat->bsp_priv = intel_priv;
1075 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1076 intel_priv->crossts_adj = 1;
1077
1078 /* Initialize all MSI vectors to invalid so that it can be set
1079 * according to platform data settings below.
1080 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1081 */
1082 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1083 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1084 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1085 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1086 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1087 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1088 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1089
1090 ret = info->setup(pdev, plat);
1091 if (ret)
1092 return ret;
1093
1094 memset(&res, 0, sizeof(res));
1095 res.addr = pcim_iomap_table(pdev)[0];
1096
1097 if (plat->eee_usecs_rate > 0) {
1098 u32 tx_lpi_usec;
1099
1100 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1101 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
1102 }
1103
1104 ret = stmmac_config_multi_msi(pdev, plat, &res);
1105 if (ret) {
1106 ret = stmmac_config_single_msi(pdev, plat, &res);
1107 if (ret) {
1108 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1109 __func__);
1110 goto err_alloc_irq;
1111 }
1112 }
1113
1114 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1115 if (ret) {
1116 goto err_alloc_irq;
1117 }
1118
1119 return 0;
1120
1121 err_alloc_irq:
1122 clk_disable_unprepare(plat->stmmac_clk);
1123 clk_unregister_fixed_rate(plat->stmmac_clk);
1124 return ret;
1125 }
1126
1127 /**
1128 * intel_eth_pci_remove
1129 *
1130 * @pdev: pci device pointer
1131 * Description: this function calls the main to free the net resources
1132 * and releases the PCI resources.
1133 */
intel_eth_pci_remove(struct pci_dev * pdev)1134 static void intel_eth_pci_remove(struct pci_dev *pdev)
1135 {
1136 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1137 struct stmmac_priv *priv = netdev_priv(ndev);
1138
1139 stmmac_dvr_remove(&pdev->dev);
1140
1141 clk_disable_unprepare(priv->plat->stmmac_clk);
1142 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1143 }
1144
intel_eth_pci_suspend(struct device * dev)1145 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
1146 {
1147 struct pci_dev *pdev = to_pci_dev(dev);
1148 int ret;
1149
1150 ret = stmmac_suspend(dev);
1151 if (ret)
1152 return ret;
1153
1154 ret = pci_save_state(pdev);
1155 if (ret)
1156 return ret;
1157
1158 pci_wake_from_d3(pdev, true);
1159 pci_set_power_state(pdev, PCI_D3hot);
1160 return 0;
1161 }
1162
intel_eth_pci_resume(struct device * dev)1163 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
1164 {
1165 struct pci_dev *pdev = to_pci_dev(dev);
1166 int ret;
1167
1168 pci_restore_state(pdev);
1169 pci_set_power_state(pdev, PCI_D0);
1170
1171 ret = pcim_enable_device(pdev);
1172 if (ret)
1173 return ret;
1174
1175 pci_set_master(pdev);
1176
1177 return stmmac_resume(dev);
1178 }
1179
1180 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
1181 intel_eth_pci_resume);
1182
1183 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937
1184 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
1185 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31
1186 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
1187 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1188 * which are named PSE0 and PSE1
1189 */
1190 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
1191 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
1192 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
1193 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
1194 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
1195 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
1196 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac
1197 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2
1198 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac
1199 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac
1200 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad
1201 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac
1202 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac
1203
1204 static const struct pci_device_id intel_eth_pci_id_table[] = {
1205 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1206 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1207 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1208 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1209 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1210 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1211 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1212 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1213 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1214 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1215 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1216 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1217 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1218 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1219 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1220 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
1221 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
1222 {}
1223 };
1224 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1225
1226 static struct pci_driver intel_eth_pci_driver = {
1227 .name = "intel-eth-pci",
1228 .id_table = intel_eth_pci_id_table,
1229 .probe = intel_eth_pci_probe,
1230 .remove = intel_eth_pci_remove,
1231 .driver = {
1232 .pm = &intel_eth_pm_ops,
1233 },
1234 };
1235
1236 module_pci_driver(intel_eth_pci_driver);
1237
1238 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1239 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1240 MODULE_LICENSE("GPL v2");
1241