1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27 
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/string_helpers.h>
33 #include <linux/timekeeping.h>
34 #include <linux/types.h>
35 
36 #include <asm/byteorder.h>
37 
38 #include <drm/display/drm_dp_helper.h>
39 #include <drm/display/drm_dsc_helper.h>
40 #include <drm/display/drm_hdmi_helper.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_probe_helper.h>
45 
46 #include "g4x_dp.h"
47 #include "i915_drv.h"
48 #include "i915_irq.h"
49 #include "i915_reg.h"
50 #include "intel_atomic.h"
51 #include "intel_audio.h"
52 #include "intel_backlight.h"
53 #include "intel_combo_phy_regs.h"
54 #include "intel_connector.h"
55 #include "intel_crtc.h"
56 #include "intel_cx0_phy.h"
57 #include "intel_ddi.h"
58 #include "intel_de.h"
59 #include "intel_display_types.h"
60 #include "intel_dp.h"
61 #include "intel_dp_aux.h"
62 #include "intel_dp_hdcp.h"
63 #include "intel_dp_link_training.h"
64 #include "intel_dp_mst.h"
65 #include "intel_dpio_phy.h"
66 #include "intel_dpll.h"
67 #include "intel_fifo_underrun.h"
68 #include "intel_hdcp.h"
69 #include "intel_hdmi.h"
70 #include "intel_hotplug.h"
71 #include "intel_hotplug_irq.h"
72 #include "intel_lspcon.h"
73 #include "intel_lvds.h"
74 #include "intel_panel.h"
75 #include "intel_pch_display.h"
76 #include "intel_pps.h"
77 #include "intel_psr.h"
78 #include "intel_tc.h"
79 #include "intel_vdsc.h"
80 #include "intel_vrr.h"
81 #include "intel_crtc_state_dump.h"
82 
83 /* DP DSC throughput values used for slice count calculations KPixels/s */
84 #define DP_DSC_PEAK_PIXEL_RATE			2720000
85 #define DP_DSC_MAX_ENC_THROUGHPUT_0		340000
86 #define DP_DSC_MAX_ENC_THROUGHPUT_1		400000
87 
88 /* DP DSC FEC Overhead factor = 1/(0.972261) */
89 #define DP_DSC_FEC_OVERHEAD_FACTOR		972261
90 
91 /* Compliance test status bits  */
92 #define INTEL_DP_RESOLUTION_SHIFT_MASK	0
93 #define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
94 #define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
95 #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
96 
97 
98 /* Constants for DP DSC configurations */
99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
100 
101 /* With Single pipe configuration, HW is capable of supporting maximum
102  * of 4 slices per line.
103  */
104 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
105 
106 /**
107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
108  * @intel_dp: DP struct
109  *
110  * If a CPU or PCH DP output is attached to an eDP panel, this function
111  * will return true, and false otherwise.
112  *
113  * This function is not safe to use prior to encoder type being set.
114  */
intel_dp_is_edp(struct intel_dp * intel_dp)115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
116 {
117 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
118 
119 	return dig_port->base.type == INTEL_OUTPUT_EDP;
120 }
121 
122 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
123 
124 /* Is link rate UHBR and thus 128b/132b? */
intel_dp_is_uhbr(const struct intel_crtc_state * crtc_state)125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
126 {
127 	return crtc_state->port_clock >= 1000000;
128 }
129 
intel_dp_set_default_sink_rates(struct intel_dp * intel_dp)130 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
131 {
132 	intel_dp->sink_rates[0] = 162000;
133 	intel_dp->num_sink_rates = 1;
134 }
135 
136 /* update sink rates from dpcd */
intel_dp_set_dpcd_sink_rates(struct intel_dp * intel_dp)137 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
138 {
139 	static const int dp_rates[] = {
140 		162000, 270000, 540000, 810000
141 	};
142 	int i, max_rate;
143 	int max_lttpr_rate;
144 
145 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
146 		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
147 		static const int quirk_rates[] = { 162000, 270000, 324000 };
148 
149 		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
150 		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
151 
152 		return;
153 	}
154 
155 	/*
156 	 * Sink rates for 8b/10b.
157 	 */
158 	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
159 	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
160 	if (max_lttpr_rate)
161 		max_rate = min(max_rate, max_lttpr_rate);
162 
163 	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
164 		if (dp_rates[i] > max_rate)
165 			break;
166 		intel_dp->sink_rates[i] = dp_rates[i];
167 	}
168 
169 	/*
170 	 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
171 	 * rates and 10 Gbps.
172 	 */
173 	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
174 		u8 uhbr_rates = 0;
175 
176 		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
177 
178 		drm_dp_dpcd_readb(&intel_dp->aux,
179 				  DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
180 
181 		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
182 			/* We have a repeater */
183 			if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
184 			    intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
185 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
186 			    DP_PHY_REPEATER_128B132B_SUPPORTED) {
187 				/* Repeater supports 128b/132b, valid UHBR rates */
188 				uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
189 									  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
190 			} else {
191 				/* Does not support 128b/132b */
192 				uhbr_rates = 0;
193 			}
194 		}
195 
196 		if (uhbr_rates & DP_UHBR10)
197 			intel_dp->sink_rates[i++] = 1000000;
198 		if (uhbr_rates & DP_UHBR13_5)
199 			intel_dp->sink_rates[i++] = 1350000;
200 		if (uhbr_rates & DP_UHBR20)
201 			intel_dp->sink_rates[i++] = 2000000;
202 	}
203 
204 	intel_dp->num_sink_rates = i;
205 }
206 
intel_dp_set_sink_rates(struct intel_dp * intel_dp)207 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
208 {
209 	struct intel_connector *connector = intel_dp->attached_connector;
210 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
211 	struct intel_encoder *encoder = &intel_dig_port->base;
212 
213 	intel_dp_set_dpcd_sink_rates(intel_dp);
214 
215 	if (intel_dp->num_sink_rates)
216 		return;
217 
218 	drm_err(&dp_to_i915(intel_dp)->drm,
219 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
220 		connector->base.base.id, connector->base.name,
221 		encoder->base.base.id, encoder->base.name);
222 
223 	intel_dp_set_default_sink_rates(intel_dp);
224 }
225 
intel_dp_set_default_max_sink_lane_count(struct intel_dp * intel_dp)226 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
227 {
228 	intel_dp->max_sink_lane_count = 1;
229 }
230 
intel_dp_set_max_sink_lane_count(struct intel_dp * intel_dp)231 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
232 {
233 	struct intel_connector *connector = intel_dp->attached_connector;
234 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
235 	struct intel_encoder *encoder = &intel_dig_port->base;
236 
237 	intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
238 
239 	switch (intel_dp->max_sink_lane_count) {
240 	case 1:
241 	case 2:
242 	case 4:
243 		return;
244 	}
245 
246 	drm_err(&dp_to_i915(intel_dp)->drm,
247 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
248 		connector->base.base.id, connector->base.name,
249 		encoder->base.base.id, encoder->base.name,
250 		intel_dp->max_sink_lane_count);
251 
252 	intel_dp_set_default_max_sink_lane_count(intel_dp);
253 }
254 
255 /* Get length of rates array potentially limited by max_rate. */
intel_dp_rate_limit_len(const int * rates,int len,int max_rate)256 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
257 {
258 	int i;
259 
260 	/* Limit results by potentially reduced max rate */
261 	for (i = 0; i < len; i++) {
262 		if (rates[len - i - 1] <= max_rate)
263 			return len - i;
264 	}
265 
266 	return 0;
267 }
268 
269 /* Get length of common rates array potentially limited by max_rate. */
intel_dp_common_len_rate_limit(const struct intel_dp * intel_dp,int max_rate)270 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
271 					  int max_rate)
272 {
273 	return intel_dp_rate_limit_len(intel_dp->common_rates,
274 				       intel_dp->num_common_rates, max_rate);
275 }
276 
intel_dp_common_rate(struct intel_dp * intel_dp,int index)277 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
278 {
279 	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
280 			index < 0 || index >= intel_dp->num_common_rates))
281 		return 162000;
282 
283 	return intel_dp->common_rates[index];
284 }
285 
286 /* Theoretical max between source and sink */
intel_dp_max_common_rate(struct intel_dp * intel_dp)287 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
288 {
289 	return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
290 }
291 
intel_dp_max_source_lane_count(struct intel_digital_port * dig_port)292 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
293 {
294 	int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
295 	int max_lanes = dig_port->max_lanes;
296 
297 	if (vbt_max_lanes)
298 		max_lanes = min(max_lanes, vbt_max_lanes);
299 
300 	return max_lanes;
301 }
302 
303 /* Theoretical max between source and sink */
intel_dp_max_common_lane_count(struct intel_dp * intel_dp)304 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
305 {
306 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
307 	int source_max = intel_dp_max_source_lane_count(dig_port);
308 	int sink_max = intel_dp->max_sink_lane_count;
309 	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
310 	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
311 
312 	if (lttpr_max)
313 		sink_max = min(sink_max, lttpr_max);
314 
315 	return min3(source_max, sink_max, fia_max);
316 }
317 
intel_dp_max_lane_count(struct intel_dp * intel_dp)318 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
319 {
320 	switch (intel_dp->max_link_lane_count) {
321 	case 1:
322 	case 2:
323 	case 4:
324 		return intel_dp->max_link_lane_count;
325 	default:
326 		MISSING_CASE(intel_dp->max_link_lane_count);
327 		return 1;
328 	}
329 }
330 
331 /*
332  * The required data bandwidth for a mode with given pixel clock and bpp. This
333  * is the required net bandwidth independent of the data bandwidth efficiency.
334  */
335 int
intel_dp_link_required(int pixel_clock,int bpp)336 intel_dp_link_required(int pixel_clock, int bpp)
337 {
338 	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
339 	return DIV_ROUND_UP(pixel_clock * bpp, 8);
340 }
341 
342 /*
343  * Given a link rate and lanes, get the data bandwidth.
344  *
345  * Data bandwidth is the actual payload rate, which depends on the data
346  * bandwidth efficiency and the link rate.
347  *
348  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
349  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
350  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
351  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
352  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
353  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
354  *
355  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
356  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
357  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
358  * does not match the symbol clock, the port clock (not even if you think in
359  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
360  * rate in units of 10000 bps.
361  */
362 int
intel_dp_max_data_rate(int max_link_rate,int max_lanes)363 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
364 {
365 	if (max_link_rate >= 1000000) {
366 		/*
367 		 * UHBR rates always use 128b/132b channel encoding, and have
368 		 * 97.71% data bandwidth efficiency. Consider max_link_rate the
369 		 * link bit rate in units of 10000 bps.
370 		 */
371 		int max_link_rate_kbps = max_link_rate * 10;
372 
373 		max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
374 		max_link_rate = max_link_rate_kbps / 8;
375 	}
376 
377 	/*
378 	 * Lower than UHBR rates always use 8b/10b channel encoding, and have
379 	 * 80% data bandwidth efficiency for SST non-FEC. However, this turns
380 	 * out to be a nop by coincidence, and can be skipped:
381 	 *
382 	 *	int max_link_rate_kbps = max_link_rate * 10;
383 	 *	max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
384 	 *	max_link_rate = max_link_rate_kbps / 8;
385 	 */
386 
387 	return max_link_rate * max_lanes;
388 }
389 
intel_dp_can_bigjoiner(struct intel_dp * intel_dp)390 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
391 {
392 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
393 	struct intel_encoder *encoder = &intel_dig_port->base;
394 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
395 
396 	/* eDP MSO is not compatible with joiner */
397 	if (intel_dp->mso_link_count)
398 		return false;
399 
400 	return DISPLAY_VER(dev_priv) >= 12 ||
401 		(DISPLAY_VER(dev_priv) == 11 &&
402 		 encoder->port != PORT_A);
403 }
404 
dg2_max_source_rate(struct intel_dp * intel_dp)405 static int dg2_max_source_rate(struct intel_dp *intel_dp)
406 {
407 	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
408 }
409 
icl_max_source_rate(struct intel_dp * intel_dp)410 static int icl_max_source_rate(struct intel_dp *intel_dp)
411 {
412 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
413 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
414 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
415 
416 	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
417 		return 540000;
418 
419 	return 810000;
420 }
421 
ehl_max_source_rate(struct intel_dp * intel_dp)422 static int ehl_max_source_rate(struct intel_dp *intel_dp)
423 {
424 	if (intel_dp_is_edp(intel_dp))
425 		return 540000;
426 
427 	return 810000;
428 }
429 
mtl_max_source_rate(struct intel_dp * intel_dp)430 static int mtl_max_source_rate(struct intel_dp *intel_dp)
431 {
432 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
433 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
434 	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
435 
436 	if (intel_is_c10phy(i915, phy))
437 		return 810000;
438 
439 	return 2000000;
440 }
441 
vbt_max_link_rate(struct intel_dp * intel_dp)442 static int vbt_max_link_rate(struct intel_dp *intel_dp)
443 {
444 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
445 	int max_rate;
446 
447 	max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
448 
449 	if (intel_dp_is_edp(intel_dp)) {
450 		struct intel_connector *connector = intel_dp->attached_connector;
451 		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
452 
453 		if (max_rate && edp_max_rate)
454 			max_rate = min(max_rate, edp_max_rate);
455 		else if (edp_max_rate)
456 			max_rate = edp_max_rate;
457 	}
458 
459 	return max_rate;
460 }
461 
462 static void
intel_dp_set_source_rates(struct intel_dp * intel_dp)463 intel_dp_set_source_rates(struct intel_dp *intel_dp)
464 {
465 	/* The values must be in increasing order */
466 	static const int mtl_rates[] = {
467 		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
468 		810000,	1000000, 1350000, 2000000,
469 	};
470 	static const int icl_rates[] = {
471 		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
472 		1000000, 1350000,
473 	};
474 	static const int bxt_rates[] = {
475 		162000, 216000, 243000, 270000, 324000, 432000, 540000
476 	};
477 	static const int skl_rates[] = {
478 		162000, 216000, 270000, 324000, 432000, 540000
479 	};
480 	static const int hsw_rates[] = {
481 		162000, 270000, 540000
482 	};
483 	static const int g4x_rates[] = {
484 		162000, 270000
485 	};
486 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
487 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
488 	const int *source_rates;
489 	int size, max_rate = 0, vbt_max_rate;
490 
491 	/* This should only be done once */
492 	drm_WARN_ON(&dev_priv->drm,
493 		    intel_dp->source_rates || intel_dp->num_source_rates);
494 
495 	if (DISPLAY_VER(dev_priv) >= 14) {
496 		source_rates = mtl_rates;
497 		size = ARRAY_SIZE(mtl_rates);
498 		max_rate = mtl_max_source_rate(intel_dp);
499 	} else if (DISPLAY_VER(dev_priv) >= 11) {
500 		source_rates = icl_rates;
501 		size = ARRAY_SIZE(icl_rates);
502 		if (IS_DG2(dev_priv))
503 			max_rate = dg2_max_source_rate(intel_dp);
504 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
505 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
506 			max_rate = 810000;
507 		else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
508 			max_rate = ehl_max_source_rate(intel_dp);
509 		else
510 			max_rate = icl_max_source_rate(intel_dp);
511 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
512 		source_rates = bxt_rates;
513 		size = ARRAY_SIZE(bxt_rates);
514 	} else if (DISPLAY_VER(dev_priv) == 9) {
515 		source_rates = skl_rates;
516 		size = ARRAY_SIZE(skl_rates);
517 	} else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
518 		   IS_BROADWELL(dev_priv)) {
519 		source_rates = hsw_rates;
520 		size = ARRAY_SIZE(hsw_rates);
521 	} else {
522 		source_rates = g4x_rates;
523 		size = ARRAY_SIZE(g4x_rates);
524 	}
525 
526 	vbt_max_rate = vbt_max_link_rate(intel_dp);
527 	if (max_rate && vbt_max_rate)
528 		max_rate = min(max_rate, vbt_max_rate);
529 	else if (vbt_max_rate)
530 		max_rate = vbt_max_rate;
531 
532 	if (max_rate)
533 		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
534 
535 	intel_dp->source_rates = source_rates;
536 	intel_dp->num_source_rates = size;
537 }
538 
intersect_rates(const int * source_rates,int source_len,const int * sink_rates,int sink_len,int * common_rates)539 static int intersect_rates(const int *source_rates, int source_len,
540 			   const int *sink_rates, int sink_len,
541 			   int *common_rates)
542 {
543 	int i = 0, j = 0, k = 0;
544 
545 	while (i < source_len && j < sink_len) {
546 		if (source_rates[i] == sink_rates[j]) {
547 			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
548 				return k;
549 			common_rates[k] = source_rates[i];
550 			++k;
551 			++i;
552 			++j;
553 		} else if (source_rates[i] < sink_rates[j]) {
554 			++i;
555 		} else {
556 			++j;
557 		}
558 	}
559 	return k;
560 }
561 
562 /* return index of rate in rates array, or -1 if not found */
intel_dp_rate_index(const int * rates,int len,int rate)563 static int intel_dp_rate_index(const int *rates, int len, int rate)
564 {
565 	int i;
566 
567 	for (i = 0; i < len; i++)
568 		if (rate == rates[i])
569 			return i;
570 
571 	return -1;
572 }
573 
intel_dp_set_common_rates(struct intel_dp * intel_dp)574 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
575 {
576 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
577 
578 	drm_WARN_ON(&i915->drm,
579 		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
580 
581 	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
582 						     intel_dp->num_source_rates,
583 						     intel_dp->sink_rates,
584 						     intel_dp->num_sink_rates,
585 						     intel_dp->common_rates);
586 
587 	/* Paranoia, there should always be something in common. */
588 	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
589 		intel_dp->common_rates[0] = 162000;
590 		intel_dp->num_common_rates = 1;
591 	}
592 }
593 
intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count)594 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
595 				       u8 lane_count)
596 {
597 	/*
598 	 * FIXME: we need to synchronize the current link parameters with
599 	 * hardware readout. Currently fast link training doesn't work on
600 	 * boot-up.
601 	 */
602 	if (link_rate == 0 ||
603 	    link_rate > intel_dp->max_link_rate)
604 		return false;
605 
606 	if (lane_count == 0 ||
607 	    lane_count > intel_dp_max_lane_count(intel_dp))
608 		return false;
609 
610 	return true;
611 }
612 
intel_dp_can_link_train_fallback_for_edp(struct intel_dp * intel_dp,int link_rate,u8 lane_count)613 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
614 						     int link_rate,
615 						     u8 lane_count)
616 {
617 	/* FIXME figure out what we actually want here */
618 	const struct drm_display_mode *fixed_mode =
619 		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
620 	int mode_rate, max_rate;
621 
622 	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
623 	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
624 	if (mode_rate > max_rate)
625 		return false;
626 
627 	return true;
628 }
629 
intel_dp_get_link_train_fallback_values(struct intel_dp * intel_dp,int link_rate,u8 lane_count)630 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
631 					    int link_rate, u8 lane_count)
632 {
633 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
634 	int index;
635 
636 	/*
637 	 * TODO: Enable fallback on MST links once MST link compute can handle
638 	 * the fallback params.
639 	 */
640 	if (intel_dp->is_mst) {
641 		drm_err(&i915->drm, "Link Training Unsuccessful\n");
642 		return -1;
643 	}
644 
645 	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
646 		drm_dbg_kms(&i915->drm,
647 			    "Retrying Link training for eDP with max parameters\n");
648 		intel_dp->use_max_params = true;
649 		return 0;
650 	}
651 
652 	index = intel_dp_rate_index(intel_dp->common_rates,
653 				    intel_dp->num_common_rates,
654 				    link_rate);
655 	if (index > 0) {
656 		if (intel_dp_is_edp(intel_dp) &&
657 		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
658 							      intel_dp_common_rate(intel_dp, index - 1),
659 							      lane_count)) {
660 			drm_dbg_kms(&i915->drm,
661 				    "Retrying Link training for eDP with same parameters\n");
662 			return 0;
663 		}
664 		intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
665 		intel_dp->max_link_lane_count = lane_count;
666 	} else if (lane_count > 1) {
667 		if (intel_dp_is_edp(intel_dp) &&
668 		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
669 							      intel_dp_max_common_rate(intel_dp),
670 							      lane_count >> 1)) {
671 			drm_dbg_kms(&i915->drm,
672 				    "Retrying Link training for eDP with same parameters\n");
673 			return 0;
674 		}
675 		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
676 		intel_dp->max_link_lane_count = lane_count >> 1;
677 	} else {
678 		drm_err(&i915->drm, "Link Training Unsuccessful\n");
679 		return -1;
680 	}
681 
682 	return 0;
683 }
684 
intel_dp_mode_to_fec_clock(u32 mode_clock)685 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
686 {
687 	return div_u64(mul_u32_u32(mode_clock, 1000000U),
688 		       DP_DSC_FEC_OVERHEAD_FACTOR);
689 }
690 
691 static int
small_joiner_ram_size_bits(struct drm_i915_private * i915)692 small_joiner_ram_size_bits(struct drm_i915_private *i915)
693 {
694 	if (DISPLAY_VER(i915) >= 13)
695 		return 17280 * 8;
696 	else if (DISPLAY_VER(i915) >= 11)
697 		return 7680 * 8;
698 	else
699 		return 6144 * 8;
700 }
701 
intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private * i915,u32 bpp,u32 pipe_bpp)702 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
703 {
704 	u32 bits_per_pixel = bpp;
705 	int i;
706 
707 	/* Error out if the max bpp is less than smallest allowed valid bpp */
708 	if (bits_per_pixel < valid_dsc_bpp[0]) {
709 		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
710 			    bits_per_pixel, valid_dsc_bpp[0]);
711 		return 0;
712 	}
713 
714 	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
715 	if (DISPLAY_VER(i915) >= 13) {
716 		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
717 
718 		/*
719 		 * According to BSpec, 27 is the max DSC output bpp,
720 		 * 8 is the min DSC output bpp.
721 		 * While we can still clamp higher bpp values to 27, saving bandwidth,
722 		 * if it is required to oompress up to bpp < 8, means we can't do
723 		 * that and probably means we can't fit the required mode, even with
724 		 * DSC enabled.
725 		 */
726 		if (bits_per_pixel < 8) {
727 			drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
728 				    bits_per_pixel);
729 			return 0;
730 		}
731 		bits_per_pixel = min_t(u32, bits_per_pixel, 27);
732 	} else {
733 		/* Find the nearest match in the array of known BPPs from VESA */
734 		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
735 			if (bits_per_pixel < valid_dsc_bpp[i + 1])
736 				break;
737 		}
738 		drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
739 			    bits_per_pixel, valid_dsc_bpp[i]);
740 
741 		bits_per_pixel = valid_dsc_bpp[i];
742 	}
743 
744 	return bits_per_pixel;
745 }
746 
intel_dp_dsc_get_output_bpp(struct drm_i915_private * i915,u32 link_clock,u32 lane_count,u32 mode_clock,u32 mode_hdisplay,bool bigjoiner,u32 pipe_bpp,u32 timeslots)747 u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
748 				u32 link_clock, u32 lane_count,
749 				u32 mode_clock, u32 mode_hdisplay,
750 				bool bigjoiner,
751 				u32 pipe_bpp,
752 				u32 timeslots)
753 {
754 	u32 bits_per_pixel, max_bpp_small_joiner_ram;
755 
756 	/*
757 	 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
758 	 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
759 	 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
760 	 * for MST -> TimeSlots has to be calculated, based on mode requirements
761 	 *
762 	 * Due to FEC overhead, the available bw is reduced to 97.2261%.
763 	 * To support the given mode:
764 	 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
765 	 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
766 	 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
767 	 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
768 	 *		       (ModeClock / FEC Overhead)
769 	 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
770 	 *		       (ModeClock / FEC Overhead * 8)
771 	 */
772 	bits_per_pixel = ((link_clock * lane_count) * timeslots) /
773 			 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
774 
775 	drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
776 				"total bw %u pixel clock %u\n",
777 				bits_per_pixel, timeslots,
778 				(link_clock * lane_count * 8),
779 				intel_dp_mode_to_fec_clock(mode_clock));
780 
781 	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
782 	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
783 		mode_hdisplay;
784 
785 	if (bigjoiner)
786 		max_bpp_small_joiner_ram *= 2;
787 
788 	/*
789 	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
790 	 * check, output bpp from small joiner RAM check)
791 	 */
792 	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
793 
794 	if (bigjoiner) {
795 		u32 max_bpp_bigjoiner =
796 			i915->display.cdclk.max_cdclk_freq * 48 /
797 			intel_dp_mode_to_fec_clock(mode_clock);
798 
799 		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
800 	}
801 
802 	bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
803 
804 	/*
805 	 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
806 	 * fractional part is 0
807 	 */
808 	return bits_per_pixel << 4;
809 }
810 
intel_dp_dsc_get_slice_count(struct intel_dp * intel_dp,int mode_clock,int mode_hdisplay,bool bigjoiner)811 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
812 				int mode_clock, int mode_hdisplay,
813 				bool bigjoiner)
814 {
815 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
816 	u8 min_slice_count, i;
817 	int max_slice_width;
818 
819 	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
820 		min_slice_count = DIV_ROUND_UP(mode_clock,
821 					       DP_DSC_MAX_ENC_THROUGHPUT_0);
822 	else
823 		min_slice_count = DIV_ROUND_UP(mode_clock,
824 					       DP_DSC_MAX_ENC_THROUGHPUT_1);
825 
826 	/*
827 	 * Due to some DSC engine BW limitations, we need to enable second
828 	 * slice and VDSC engine, whenever we approach close enough to max CDCLK
829 	 */
830 	if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
831 		min_slice_count = max_t(u8, min_slice_count, 2);
832 
833 	max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
834 	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
835 		drm_dbg_kms(&i915->drm,
836 			    "Unsupported slice width %d by DP DSC Sink device\n",
837 			    max_slice_width);
838 		return 0;
839 	}
840 	/* Also take into account max slice width */
841 	min_slice_count = max_t(u8, min_slice_count,
842 				DIV_ROUND_UP(mode_hdisplay,
843 					     max_slice_width));
844 
845 	/* Find the closest match to the valid slice count values */
846 	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
847 		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
848 
849 		if (test_slice_count >
850 		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
851 			break;
852 
853 		/* big joiner needs small joiner to be enabled */
854 		if (bigjoiner && test_slice_count < 4)
855 			continue;
856 
857 		if (min_slice_count <= test_slice_count)
858 			return test_slice_count;
859 	}
860 
861 	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
862 		    min_slice_count);
863 	return 0;
864 }
865 
source_can_output(struct intel_dp * intel_dp,enum intel_output_format format)866 static bool source_can_output(struct intel_dp *intel_dp,
867 			      enum intel_output_format format)
868 {
869 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
870 
871 	switch (format) {
872 	case INTEL_OUTPUT_FORMAT_RGB:
873 		return true;
874 
875 	case INTEL_OUTPUT_FORMAT_YCBCR444:
876 		/*
877 		 * No YCbCr output support on gmch platforms.
878 		 * Also, ILK doesn't seem capable of DP YCbCr output.
879 		 * The displayed image is severly corrupted. SNB+ is fine.
880 		 */
881 		return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
882 
883 	case INTEL_OUTPUT_FORMAT_YCBCR420:
884 		/* Platform < Gen 11 cannot output YCbCr420 format */
885 		return DISPLAY_VER(i915) >= 11;
886 
887 	default:
888 		MISSING_CASE(format);
889 		return false;
890 	}
891 }
892 
893 static bool
dfp_can_convert_from_rgb(struct intel_dp * intel_dp,enum intel_output_format sink_format)894 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
895 			 enum intel_output_format sink_format)
896 {
897 	if (!drm_dp_is_branch(intel_dp->dpcd))
898 		return false;
899 
900 	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
901 		return intel_dp->dfp.rgb_to_ycbcr;
902 
903 	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
904 		return intel_dp->dfp.rgb_to_ycbcr &&
905 			intel_dp->dfp.ycbcr_444_to_420;
906 
907 	return false;
908 }
909 
910 static bool
dfp_can_convert_from_ycbcr444(struct intel_dp * intel_dp,enum intel_output_format sink_format)911 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
912 			      enum intel_output_format sink_format)
913 {
914 	if (!drm_dp_is_branch(intel_dp->dpcd))
915 		return false;
916 
917 	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
918 		return intel_dp->dfp.ycbcr_444_to_420;
919 
920 	return false;
921 }
922 
923 static enum intel_output_format
intel_dp_output_format(struct intel_connector * connector,enum intel_output_format sink_format)924 intel_dp_output_format(struct intel_connector *connector,
925 		       enum intel_output_format sink_format)
926 {
927 	struct intel_dp *intel_dp = intel_attached_dp(connector);
928 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
929 	enum intel_output_format output_format;
930 
931 	if (intel_dp->force_dsc_output_format)
932 		return intel_dp->force_dsc_output_format;
933 
934 	if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
935 	    dfp_can_convert_from_rgb(intel_dp, sink_format))
936 		output_format = INTEL_OUTPUT_FORMAT_RGB;
937 
938 	else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
939 		 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
940 		output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
941 
942 	else
943 		output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
944 
945 	drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
946 
947 	return output_format;
948 }
949 
intel_dp_min_bpp(enum intel_output_format output_format)950 int intel_dp_min_bpp(enum intel_output_format output_format)
951 {
952 	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
953 		return 6 * 3;
954 	else
955 		return 8 * 3;
956 }
957 
intel_dp_output_bpp(enum intel_output_format output_format,int bpp)958 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
959 {
960 	/*
961 	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
962 	 * format of the number of bytes per pixel will be half the number
963 	 * of bytes of RGB pixel.
964 	 */
965 	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
966 		bpp /= 2;
967 
968 	return bpp;
969 }
970 
971 static enum intel_output_format
intel_dp_sink_format(struct intel_connector * connector,const struct drm_display_mode * mode)972 intel_dp_sink_format(struct intel_connector *connector,
973 		     const struct drm_display_mode *mode)
974 {
975 	const struct drm_display_info *info = &connector->base.display_info;
976 
977 	if (drm_mode_is_420_only(info, mode))
978 		return INTEL_OUTPUT_FORMAT_YCBCR420;
979 
980 	return INTEL_OUTPUT_FORMAT_RGB;
981 }
982 
983 static int
intel_dp_mode_min_output_bpp(struct intel_connector * connector,const struct drm_display_mode * mode)984 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
985 			     const struct drm_display_mode *mode)
986 {
987 	enum intel_output_format output_format, sink_format;
988 
989 	sink_format = intel_dp_sink_format(connector, mode);
990 
991 	output_format = intel_dp_output_format(connector, sink_format);
992 
993 	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
994 }
995 
intel_dp_hdisplay_bad(struct drm_i915_private * dev_priv,int hdisplay)996 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
997 				  int hdisplay)
998 {
999 	/*
1000 	 * Older platforms don't like hdisplay==4096 with DP.
1001 	 *
1002 	 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1003 	 * and frame counter increment), but we don't get vblank interrupts,
1004 	 * and the pipe underruns immediately. The link also doesn't seem
1005 	 * to get trained properly.
1006 	 *
1007 	 * On CHV the vblank interrupts don't seem to disappear but
1008 	 * otherwise the symptoms are similar.
1009 	 *
1010 	 * TODO: confirm the behaviour on HSW+
1011 	 */
1012 	return hdisplay == 4096 && !HAS_DDI(dev_priv);
1013 }
1014 
intel_dp_max_tmds_clock(struct intel_dp * intel_dp)1015 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1016 {
1017 	struct intel_connector *connector = intel_dp->attached_connector;
1018 	const struct drm_display_info *info = &connector->base.display_info;
1019 	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1020 
1021 	/* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1022 	if (max_tmds_clock && info->max_tmds_clock)
1023 		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1024 
1025 	return max_tmds_clock;
1026 }
1027 
1028 static enum drm_mode_status
intel_dp_tmds_clock_valid(struct intel_dp * intel_dp,int clock,int bpc,enum intel_output_format sink_format,bool respect_downstream_limits)1029 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1030 			  int clock, int bpc,
1031 			  enum intel_output_format sink_format,
1032 			  bool respect_downstream_limits)
1033 {
1034 	int tmds_clock, min_tmds_clock, max_tmds_clock;
1035 
1036 	if (!respect_downstream_limits)
1037 		return MODE_OK;
1038 
1039 	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1040 
1041 	min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1042 	max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1043 
1044 	if (min_tmds_clock && tmds_clock < min_tmds_clock)
1045 		return MODE_CLOCK_LOW;
1046 
1047 	if (max_tmds_clock && tmds_clock > max_tmds_clock)
1048 		return MODE_CLOCK_HIGH;
1049 
1050 	return MODE_OK;
1051 }
1052 
1053 static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector * connector,const struct drm_display_mode * mode,int target_clock)1054 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1055 			       const struct drm_display_mode *mode,
1056 			       int target_clock)
1057 {
1058 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1059 	const struct drm_display_info *info = &connector->base.display_info;
1060 	enum drm_mode_status status;
1061 	enum intel_output_format sink_format;
1062 
1063 	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
1064 	if (intel_dp->dfp.pcon_max_frl_bw) {
1065 		int target_bw;
1066 		int max_frl_bw;
1067 		int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1068 
1069 		target_bw = bpp * target_clock;
1070 
1071 		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1072 
1073 		/* converting bw from Gbps to Kbps*/
1074 		max_frl_bw = max_frl_bw * 1000000;
1075 
1076 		if (target_bw > max_frl_bw)
1077 			return MODE_CLOCK_HIGH;
1078 
1079 		return MODE_OK;
1080 	}
1081 
1082 	if (intel_dp->dfp.max_dotclock &&
1083 	    target_clock > intel_dp->dfp.max_dotclock)
1084 		return MODE_CLOCK_HIGH;
1085 
1086 	sink_format = intel_dp_sink_format(connector, mode);
1087 
1088 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1089 	status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1090 					   8, sink_format, true);
1091 
1092 	if (status != MODE_OK) {
1093 		if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1094 		    !connector->base.ycbcr_420_allowed ||
1095 		    !drm_mode_is_420_also(info, mode))
1096 			return status;
1097 		sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1098 		status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1099 						   8, sink_format, true);
1100 		if (status != MODE_OK)
1101 			return status;
1102 	}
1103 
1104 	return MODE_OK;
1105 }
1106 
intel_dp_need_bigjoiner(struct intel_dp * intel_dp,int hdisplay,int clock)1107 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1108 			     int hdisplay, int clock)
1109 {
1110 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1111 
1112 	if (!intel_dp_can_bigjoiner(intel_dp))
1113 		return false;
1114 
1115 	return clock > i915->max_dotclk_freq || hdisplay > 5120;
1116 }
1117 
1118 static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector * _connector,struct drm_display_mode * mode)1119 intel_dp_mode_valid(struct drm_connector *_connector,
1120 		    struct drm_display_mode *mode)
1121 {
1122 	struct intel_connector *connector = to_intel_connector(_connector);
1123 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1124 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1125 	const struct drm_display_mode *fixed_mode;
1126 	int target_clock = mode->clock;
1127 	int max_rate, mode_rate, max_lanes, max_link_clock;
1128 	int max_dotclk = dev_priv->max_dotclk_freq;
1129 	u16 dsc_max_output_bpp = 0;
1130 	u8 dsc_slice_count = 0;
1131 	enum drm_mode_status status;
1132 	bool dsc = false, bigjoiner = false;
1133 
1134 	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1135 	if (status != MODE_OK)
1136 		return status;
1137 
1138 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1139 		return MODE_H_ILLEGAL;
1140 
1141 	fixed_mode = intel_panel_fixed_mode(connector, mode);
1142 	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1143 		status = intel_panel_mode_valid(connector, mode);
1144 		if (status != MODE_OK)
1145 			return status;
1146 
1147 		target_clock = fixed_mode->clock;
1148 	}
1149 
1150 	if (mode->clock < 10000)
1151 		return MODE_CLOCK_LOW;
1152 
1153 	if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1154 		bigjoiner = true;
1155 		max_dotclk *= 2;
1156 	}
1157 	if (target_clock > max_dotclk)
1158 		return MODE_CLOCK_HIGH;
1159 
1160 	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1161 		return MODE_H_ILLEGAL;
1162 
1163 	max_link_clock = intel_dp_max_link_rate(intel_dp);
1164 	max_lanes = intel_dp_max_lane_count(intel_dp);
1165 
1166 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1167 	mode_rate = intel_dp_link_required(target_clock,
1168 					   intel_dp_mode_min_output_bpp(connector, mode));
1169 
1170 	if (HAS_DSC(dev_priv) &&
1171 	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1172 		/*
1173 		 * TBD pass the connector BPC,
1174 		 * for now U8_MAX so that max BPC on that platform would be picked
1175 		 */
1176 		int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1177 
1178 		/*
1179 		 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1180 		 * integer value since we support only integer values of bpp.
1181 		 */
1182 		if (intel_dp_is_edp(intel_dp)) {
1183 			dsc_max_output_bpp =
1184 				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1185 			dsc_slice_count =
1186 				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1187 								true);
1188 		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1189 			dsc_max_output_bpp =
1190 				intel_dp_dsc_get_output_bpp(dev_priv,
1191 							    max_link_clock,
1192 							    max_lanes,
1193 							    target_clock,
1194 							    mode->hdisplay,
1195 							    bigjoiner,
1196 							    pipe_bpp, 64) >> 4;
1197 			dsc_slice_count =
1198 				intel_dp_dsc_get_slice_count(intel_dp,
1199 							     target_clock,
1200 							     mode->hdisplay,
1201 							     bigjoiner);
1202 		}
1203 
1204 		dsc = dsc_max_output_bpp && dsc_slice_count;
1205 	}
1206 
1207 	/*
1208 	 * Big joiner configuration needs DSC for TGL which is not true for
1209 	 * XE_LPD where uncompressed joiner is supported.
1210 	 */
1211 	if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1212 		return MODE_CLOCK_HIGH;
1213 
1214 	if (mode_rate > max_rate && !dsc)
1215 		return MODE_CLOCK_HIGH;
1216 
1217 	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1218 	if (status != MODE_OK)
1219 		return status;
1220 
1221 	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1222 }
1223 
intel_dp_source_supports_tps3(struct drm_i915_private * i915)1224 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1225 {
1226 	return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1227 }
1228 
intel_dp_source_supports_tps4(struct drm_i915_private * i915)1229 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1230 {
1231 	return DISPLAY_VER(i915) >= 10;
1232 }
1233 
snprintf_int_array(char * str,size_t len,const int * array,int nelem)1234 static void snprintf_int_array(char *str, size_t len,
1235 			       const int *array, int nelem)
1236 {
1237 	int i;
1238 
1239 	str[0] = '\0';
1240 
1241 	for (i = 0; i < nelem; i++) {
1242 		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1243 		if (r >= len)
1244 			return;
1245 		str += r;
1246 		len -= r;
1247 	}
1248 }
1249 
intel_dp_print_rates(struct intel_dp * intel_dp)1250 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1251 {
1252 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1253 	char str[128]; /* FIXME: too big for stack? */
1254 
1255 	if (!drm_debug_enabled(DRM_UT_KMS))
1256 		return;
1257 
1258 	snprintf_int_array(str, sizeof(str),
1259 			   intel_dp->source_rates, intel_dp->num_source_rates);
1260 	drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1261 
1262 	snprintf_int_array(str, sizeof(str),
1263 			   intel_dp->sink_rates, intel_dp->num_sink_rates);
1264 	drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1265 
1266 	snprintf_int_array(str, sizeof(str),
1267 			   intel_dp->common_rates, intel_dp->num_common_rates);
1268 	drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1269 }
1270 
1271 int
intel_dp_max_link_rate(struct intel_dp * intel_dp)1272 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1273 {
1274 	int len;
1275 
1276 	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1277 
1278 	return intel_dp_common_rate(intel_dp, len - 1);
1279 }
1280 
intel_dp_rate_select(struct intel_dp * intel_dp,int rate)1281 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1282 {
1283 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1284 	int i = intel_dp_rate_index(intel_dp->sink_rates,
1285 				    intel_dp->num_sink_rates, rate);
1286 
1287 	if (drm_WARN_ON(&i915->drm, i < 0))
1288 		i = 0;
1289 
1290 	return i;
1291 }
1292 
intel_dp_compute_rate(struct intel_dp * intel_dp,int port_clock,u8 * link_bw,u8 * rate_select)1293 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1294 			   u8 *link_bw, u8 *rate_select)
1295 {
1296 	/* eDP 1.4 rate select method. */
1297 	if (intel_dp->use_rate_select) {
1298 		*link_bw = 0;
1299 		*rate_select =
1300 			intel_dp_rate_select(intel_dp, port_clock);
1301 	} else {
1302 		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1303 		*rate_select = 0;
1304 	}
1305 }
1306 
intel_dp_has_hdmi_sink(struct intel_dp * intel_dp)1307 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1308 {
1309 	struct intel_connector *connector = intel_dp->attached_connector;
1310 
1311 	return connector->base.display_info.is_hdmi;
1312 }
1313 
intel_dp_source_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1314 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1315 					 const struct intel_crtc_state *pipe_config)
1316 {
1317 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1318 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1319 
1320 	if (DISPLAY_VER(dev_priv) >= 12)
1321 		return true;
1322 
1323 	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1324 	    !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1325 		return true;
1326 
1327 	return false;
1328 }
1329 
intel_dp_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1330 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1331 				  const struct intel_crtc_state *pipe_config)
1332 {
1333 	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1334 		drm_dp_sink_supports_fec(intel_dp->fec_capable);
1335 }
1336 
intel_dp_supports_dsc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1337 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1338 				  const struct intel_crtc_state *crtc_state)
1339 {
1340 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1341 		return false;
1342 
1343 	return intel_dsc_source_support(crtc_state) &&
1344 		drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1345 }
1346 
intel_dp_hdmi_compute_bpc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int bpc,bool respect_downstream_limits)1347 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1348 				     const struct intel_crtc_state *crtc_state,
1349 				     int bpc, bool respect_downstream_limits)
1350 {
1351 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1352 
1353 	/*
1354 	 * Current bpc could already be below 8bpc due to
1355 	 * FDI bandwidth constraints or other limits.
1356 	 * HDMI minimum is 8bpc however.
1357 	 */
1358 	bpc = max(bpc, 8);
1359 
1360 	/*
1361 	 * We will never exceed downstream TMDS clock limits while
1362 	 * attempting deep color. If the user insists on forcing an
1363 	 * out of spec mode they will have to be satisfied with 8bpc.
1364 	 */
1365 	if (!respect_downstream_limits)
1366 		bpc = 8;
1367 
1368 	for (; bpc >= 8; bpc -= 2) {
1369 		if (intel_hdmi_bpc_possible(crtc_state, bpc,
1370 					    intel_dp_has_hdmi_sink(intel_dp)) &&
1371 		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1372 					      respect_downstream_limits) == MODE_OK)
1373 			return bpc;
1374 	}
1375 
1376 	return -EINVAL;
1377 }
1378 
intel_dp_max_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool respect_downstream_limits)1379 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1380 			    const struct intel_crtc_state *crtc_state,
1381 			    bool respect_downstream_limits)
1382 {
1383 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1384 	struct intel_connector *intel_connector = intel_dp->attached_connector;
1385 	int bpp, bpc;
1386 
1387 	bpc = crtc_state->pipe_bpp / 3;
1388 
1389 	if (intel_dp->dfp.max_bpc)
1390 		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1391 
1392 	if (intel_dp->dfp.min_tmds_clock) {
1393 		int max_hdmi_bpc;
1394 
1395 		max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1396 							 respect_downstream_limits);
1397 		if (max_hdmi_bpc < 0)
1398 			return 0;
1399 
1400 		bpc = min(bpc, max_hdmi_bpc);
1401 	}
1402 
1403 	bpp = bpc * 3;
1404 	if (intel_dp_is_edp(intel_dp)) {
1405 		/* Get bpp from vbt only for panels that dont have bpp in edid */
1406 		if (intel_connector->base.display_info.bpc == 0 &&
1407 		    intel_connector->panel.vbt.edp.bpp &&
1408 		    intel_connector->panel.vbt.edp.bpp < bpp) {
1409 			drm_dbg_kms(&dev_priv->drm,
1410 				    "clamping bpp for eDP panel to BIOS-provided %i\n",
1411 				    intel_connector->panel.vbt.edp.bpp);
1412 			bpp = intel_connector->panel.vbt.edp.bpp;
1413 		}
1414 	}
1415 
1416 	return bpp;
1417 }
1418 
1419 /* Adjust link config limits based on compliance test requests. */
1420 void
intel_dp_adjust_compliance_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct link_config_limits * limits)1421 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1422 				  struct intel_crtc_state *pipe_config,
1423 				  struct link_config_limits *limits)
1424 {
1425 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1426 
1427 	/* For DP Compliance we override the computed bpp for the pipe */
1428 	if (intel_dp->compliance.test_data.bpc != 0) {
1429 		int bpp = 3 * intel_dp->compliance.test_data.bpc;
1430 
1431 		limits->min_bpp = limits->max_bpp = bpp;
1432 		pipe_config->dither_force_disable = bpp == 6 * 3;
1433 
1434 		drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1435 	}
1436 
1437 	/* Use values requested by Compliance Test Request */
1438 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1439 		int index;
1440 
1441 		/* Validate the compliance test data since max values
1442 		 * might have changed due to link train fallback.
1443 		 */
1444 		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1445 					       intel_dp->compliance.test_lane_count)) {
1446 			index = intel_dp_rate_index(intel_dp->common_rates,
1447 						    intel_dp->num_common_rates,
1448 						    intel_dp->compliance.test_link_rate);
1449 			if (index >= 0)
1450 				limits->min_rate = limits->max_rate =
1451 					intel_dp->compliance.test_link_rate;
1452 			limits->min_lane_count = limits->max_lane_count =
1453 				intel_dp->compliance.test_lane_count;
1454 		}
1455 	}
1456 }
1457 
has_seamless_m_n(struct intel_connector * connector)1458 static bool has_seamless_m_n(struct intel_connector *connector)
1459 {
1460 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1461 
1462 	/*
1463 	 * Seamless M/N reprogramming only implemented
1464 	 * for BDW+ double buffered M/N registers so far.
1465 	 */
1466 	return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1467 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1468 }
1469 
intel_dp_mode_clock(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1470 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1471 			       const struct drm_connector_state *conn_state)
1472 {
1473 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
1474 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1475 
1476 	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
1477 	if (has_seamless_m_n(connector))
1478 		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1479 	else
1480 		return adjusted_mode->crtc_clock;
1481 }
1482 
1483 /* Optimize link config in order: max bpp, min clock, min lanes */
1484 static int
intel_dp_compute_link_config_wide(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state,const struct link_config_limits * limits)1485 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1486 				  struct intel_crtc_state *pipe_config,
1487 				  const struct drm_connector_state *conn_state,
1488 				  const struct link_config_limits *limits)
1489 {
1490 	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1491 	int mode_rate, link_rate, link_avail;
1492 
1493 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1494 		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1495 
1496 		mode_rate = intel_dp_link_required(clock, output_bpp);
1497 
1498 		for (i = 0; i < intel_dp->num_common_rates; i++) {
1499 			link_rate = intel_dp_common_rate(intel_dp, i);
1500 			if (link_rate < limits->min_rate ||
1501 			    link_rate > limits->max_rate)
1502 				continue;
1503 
1504 			for (lane_count = limits->min_lane_count;
1505 			     lane_count <= limits->max_lane_count;
1506 			     lane_count <<= 1) {
1507 				link_avail = intel_dp_max_data_rate(link_rate,
1508 								    lane_count);
1509 
1510 				if (mode_rate <= link_avail) {
1511 					pipe_config->lane_count = lane_count;
1512 					pipe_config->pipe_bpp = bpp;
1513 					pipe_config->port_clock = link_rate;
1514 
1515 					return 0;
1516 				}
1517 			}
1518 		}
1519 	}
1520 
1521 	return -EINVAL;
1522 }
1523 
intel_dp_dsc_compute_bpp(struct intel_dp * intel_dp,u8 max_req_bpc)1524 int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1525 {
1526 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1527 	int i, num_bpc;
1528 	u8 dsc_bpc[3] = {0};
1529 	u8 dsc_max_bpc;
1530 
1531 	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1532 	if (DISPLAY_VER(i915) >= 12)
1533 		dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1534 	else
1535 		dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1536 
1537 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1538 						       dsc_bpc);
1539 	for (i = 0; i < num_bpc; i++) {
1540 		if (dsc_max_bpc >= dsc_bpc[i])
1541 			return dsc_bpc[i] * 3;
1542 	}
1543 
1544 	return 0;
1545 }
1546 
intel_dp_source_dsc_version_minor(struct intel_dp * intel_dp)1547 static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1548 {
1549 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1550 
1551 	return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1552 }
1553 
intel_dp_sink_dsc_version_minor(struct intel_dp * intel_dp)1554 static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1555 {
1556 	return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1557 		DP_DSC_MINOR_SHIFT;
1558 }
1559 
intel_dp_get_slice_height(int vactive)1560 static int intel_dp_get_slice_height(int vactive)
1561 {
1562 	int slice_height;
1563 
1564 	/*
1565 	 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1566 	 * lines is an optimal slice height, but any size can be used as long as
1567 	 * vertical active integer multiple and maximum vertical slice count
1568 	 * requirements are met.
1569 	 */
1570 	for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1571 		if (vactive % slice_height == 0)
1572 			return slice_height;
1573 
1574 	/*
1575 	 * Highly unlikely we reach here as most of the resolutions will end up
1576 	 * finding appropriate slice_height in above loop but returning
1577 	 * slice_height as 2 here as it should work with all resolutions.
1578 	 */
1579 	return 2;
1580 }
1581 
intel_dp_dsc_compute_params(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1582 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1583 				       struct intel_crtc_state *crtc_state)
1584 {
1585 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1586 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1587 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1588 	u8 line_buf_depth;
1589 	int ret;
1590 
1591 	/*
1592 	 * RC_MODEL_SIZE is currently a constant across all configurations.
1593 	 *
1594 	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1595 	 * DP_DSC_RC_BUF_SIZE for this.
1596 	 */
1597 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1598 	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1599 
1600 	vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1601 
1602 	ret = intel_dsc_compute_params(crtc_state);
1603 	if (ret)
1604 		return ret;
1605 
1606 	vdsc_cfg->dsc_version_major =
1607 		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1608 		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1609 	vdsc_cfg->dsc_version_minor =
1610 		min(intel_dp_source_dsc_version_minor(intel_dp),
1611 		    intel_dp_sink_dsc_version_minor(intel_dp));
1612 	if (vdsc_cfg->convert_rgb)
1613 		vdsc_cfg->convert_rgb =
1614 			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1615 			DP_DSC_RGB;
1616 
1617 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1618 	if (!line_buf_depth) {
1619 		drm_dbg_kms(&i915->drm,
1620 			    "DSC Sink Line Buffer Depth invalid\n");
1621 		return -EINVAL;
1622 	}
1623 
1624 	if (vdsc_cfg->dsc_version_minor == 2)
1625 		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1626 			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1627 	else
1628 		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1629 			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1630 
1631 	vdsc_cfg->block_pred_enable =
1632 		intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1633 		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1634 
1635 	return drm_dsc_compute_rc_parameters(vdsc_cfg);
1636 }
1637 
intel_dp_dsc_supports_format(struct intel_dp * intel_dp,enum intel_output_format output_format)1638 static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
1639 					 enum intel_output_format output_format)
1640 {
1641 	u8 sink_dsc_format;
1642 
1643 	switch (output_format) {
1644 	case INTEL_OUTPUT_FORMAT_RGB:
1645 		sink_dsc_format = DP_DSC_RGB;
1646 		break;
1647 	case INTEL_OUTPUT_FORMAT_YCBCR444:
1648 		sink_dsc_format = DP_DSC_YCbCr444;
1649 		break;
1650 	case INTEL_OUTPUT_FORMAT_YCBCR420:
1651 		if (min(intel_dp_source_dsc_version_minor(intel_dp),
1652 			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
1653 			return false;
1654 		sink_dsc_format = DP_DSC_YCbCr420_Native;
1655 		break;
1656 	default:
1657 		return false;
1658 	}
1659 
1660 	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
1661 }
1662 
intel_dp_dsc_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,struct link_config_limits * limits,int timeslots,bool compute_pipe_bpp)1663 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1664 				struct intel_crtc_state *pipe_config,
1665 				struct drm_connector_state *conn_state,
1666 				struct link_config_limits *limits,
1667 				int timeslots,
1668 				bool compute_pipe_bpp)
1669 {
1670 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1671 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1672 	const struct drm_display_mode *adjusted_mode =
1673 		&pipe_config->hw.adjusted_mode;
1674 	int pipe_bpp;
1675 	int ret;
1676 
1677 	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1678 		intel_dp_supports_fec(intel_dp, pipe_config);
1679 
1680 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1681 		return -EINVAL;
1682 
1683 	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
1684 		return -EINVAL;
1685 
1686 	if (compute_pipe_bpp)
1687 		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1688 	else
1689 		pipe_bpp = pipe_config->pipe_bpp;
1690 
1691 	if (intel_dp->force_dsc_bpc) {
1692 		pipe_bpp = intel_dp->force_dsc_bpc * 3;
1693 		drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1694 	}
1695 
1696 	/* Min Input BPC for ICL+ is 8 */
1697 	if (pipe_bpp < 8 * 3) {
1698 		drm_dbg_kms(&dev_priv->drm,
1699 			    "No DSC support for less than 8bpc\n");
1700 		return -EINVAL;
1701 	}
1702 
1703 	/*
1704 	 * For now enable DSC for max bpp, max link rate, max lane count.
1705 	 * Optimize this later for the minimum possible link rate/lane count
1706 	 * with DSC enabled for the requested mode.
1707 	 */
1708 	pipe_config->pipe_bpp = pipe_bpp;
1709 	pipe_config->port_clock = limits->max_rate;
1710 	pipe_config->lane_count = limits->max_lane_count;
1711 
1712 	if (intel_dp_is_edp(intel_dp)) {
1713 		pipe_config->dsc.compressed_bpp =
1714 			min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1715 			      pipe_config->pipe_bpp);
1716 		pipe_config->dsc.slice_count =
1717 			drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1718 							true);
1719 		if (!pipe_config->dsc.slice_count) {
1720 			drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
1721 				    pipe_config->dsc.slice_count);
1722 			return -EINVAL;
1723 		}
1724 	} else {
1725 		u16 dsc_max_output_bpp = 0;
1726 		u8 dsc_dp_slice_count;
1727 
1728 		if (compute_pipe_bpp) {
1729 			dsc_max_output_bpp =
1730 				intel_dp_dsc_get_output_bpp(dev_priv,
1731 							    pipe_config->port_clock,
1732 							    pipe_config->lane_count,
1733 							    adjusted_mode->crtc_clock,
1734 							    adjusted_mode->crtc_hdisplay,
1735 							    pipe_config->bigjoiner_pipes,
1736 							    pipe_bpp,
1737 							    timeslots);
1738 			/*
1739 			 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
1740 			 * supported PPS value can be 63.9375 and with the further
1741 			 * mention that bpp should be programmed double the target bpp
1742 			 * restricting our target bpp to be 31.9375 at max
1743 			 */
1744 			if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1745 				dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
1746 
1747 			if (!dsc_max_output_bpp) {
1748 				drm_dbg_kms(&dev_priv->drm,
1749 					    "Compressed BPP not supported\n");
1750 				return -EINVAL;
1751 			}
1752 		}
1753 		dsc_dp_slice_count =
1754 			intel_dp_dsc_get_slice_count(intel_dp,
1755 						     adjusted_mode->crtc_clock,
1756 						     adjusted_mode->crtc_hdisplay,
1757 						     pipe_config->bigjoiner_pipes);
1758 		if (!dsc_dp_slice_count) {
1759 			drm_dbg_kms(&dev_priv->drm,
1760 				    "Compressed Slice Count not supported\n");
1761 			return -EINVAL;
1762 		}
1763 
1764 		/*
1765 		 * compute pipe bpp is set to false for DP MST DSC case
1766 		 * and compressed_bpp is calculated same time once
1767 		 * vpci timeslots are allocated, because overall bpp
1768 		 * calculation procedure is bit different for MST case.
1769 		 */
1770 		if (compute_pipe_bpp) {
1771 			pipe_config->dsc.compressed_bpp = min_t(u16,
1772 								dsc_max_output_bpp >> 4,
1773 								pipe_config->pipe_bpp);
1774 		}
1775 		pipe_config->dsc.slice_count = dsc_dp_slice_count;
1776 		drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
1777 			    pipe_config->dsc.compressed_bpp,
1778 			    pipe_config->dsc.slice_count);
1779 	}
1780 	/*
1781 	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1782 	 * is greater than the maximum Cdclock and if slice count is even
1783 	 * then we need to use 2 VDSC instances.
1784 	 */
1785 	if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
1786 		pipe_config->dsc.dsc_split = true;
1787 
1788 	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1789 	if (ret < 0) {
1790 		drm_dbg_kms(&dev_priv->drm,
1791 			    "Cannot compute valid DSC parameters for Input Bpp = %d "
1792 			    "Compressed BPP = %d\n",
1793 			    pipe_config->pipe_bpp,
1794 			    pipe_config->dsc.compressed_bpp);
1795 		return ret;
1796 	}
1797 
1798 	pipe_config->dsc.compression_enable = true;
1799 	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1800 		    "Compressed Bpp = %d Slice Count = %d\n",
1801 		    pipe_config->pipe_bpp,
1802 		    pipe_config->dsc.compressed_bpp,
1803 		    pipe_config->dsc.slice_count);
1804 
1805 	return 0;
1806 }
1807 
1808 static int
intel_dp_compute_link_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,bool respect_downstream_limits)1809 intel_dp_compute_link_config(struct intel_encoder *encoder,
1810 			     struct intel_crtc_state *pipe_config,
1811 			     struct drm_connector_state *conn_state,
1812 			     bool respect_downstream_limits)
1813 {
1814 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1815 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1816 	const struct drm_display_mode *adjusted_mode =
1817 		&pipe_config->hw.adjusted_mode;
1818 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1819 	struct link_config_limits limits;
1820 	bool joiner_needs_dsc = false;
1821 	int ret;
1822 
1823 	limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1824 	limits.max_rate = intel_dp_max_link_rate(intel_dp);
1825 
1826 	limits.min_lane_count = 1;
1827 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1828 
1829 	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1830 	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1831 
1832 	if (intel_dp->use_max_params) {
1833 		/*
1834 		 * Use the maximum clock and number of lanes the eDP panel
1835 		 * advertizes being capable of in case the initial fast
1836 		 * optimal params failed us. The panels are generally
1837 		 * designed to support only a single clock and lane
1838 		 * configuration, and typically on older panels these
1839 		 * values correspond to the native resolution of the panel.
1840 		 */
1841 		limits.min_lane_count = limits.max_lane_count;
1842 		limits.min_rate = limits.max_rate;
1843 	}
1844 
1845 	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1846 
1847 	drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1848 		    "max rate %d max bpp %d pixel clock %iKHz\n",
1849 		    limits.max_lane_count, limits.max_rate,
1850 		    limits.max_bpp, adjusted_mode->crtc_clock);
1851 
1852 	if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1853 				    adjusted_mode->crtc_clock))
1854 		pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1855 
1856 	/*
1857 	 * Pipe joiner needs compression up to display 12 due to bandwidth
1858 	 * limitation. DG2 onwards pipe joiner can be enabled without
1859 	 * compression.
1860 	 */
1861 	joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1862 
1863 	/*
1864 	 * Optimize for slow and wide for everything, because there are some
1865 	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1866 	 */
1867 	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1868 
1869 	if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1870 		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1871 			    str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1872 			    str_yes_no(intel_dp->force_dsc_en));
1873 		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1874 						  conn_state, &limits, 64, true);
1875 		if (ret < 0)
1876 			return ret;
1877 	}
1878 
1879 	if (pipe_config->dsc.compression_enable) {
1880 		drm_dbg_kms(&i915->drm,
1881 			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1882 			    pipe_config->lane_count, pipe_config->port_clock,
1883 			    pipe_config->pipe_bpp,
1884 			    pipe_config->dsc.compressed_bpp);
1885 
1886 		drm_dbg_kms(&i915->drm,
1887 			    "DP link rate required %i available %i\n",
1888 			    intel_dp_link_required(adjusted_mode->crtc_clock,
1889 						   pipe_config->dsc.compressed_bpp),
1890 			    intel_dp_max_data_rate(pipe_config->port_clock,
1891 						   pipe_config->lane_count));
1892 	} else {
1893 		drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1894 			    pipe_config->lane_count, pipe_config->port_clock,
1895 			    pipe_config->pipe_bpp);
1896 
1897 		drm_dbg_kms(&i915->drm,
1898 			    "DP link rate required %i available %i\n",
1899 			    intel_dp_link_required(adjusted_mode->crtc_clock,
1900 						   pipe_config->pipe_bpp),
1901 			    intel_dp_max_data_rate(pipe_config->port_clock,
1902 						   pipe_config->lane_count));
1903 	}
1904 	return 0;
1905 }
1906 
intel_dp_limited_color_range(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1907 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1908 				  const struct drm_connector_state *conn_state)
1909 {
1910 	const struct intel_digital_connector_state *intel_conn_state =
1911 		to_intel_digital_connector_state(conn_state);
1912 	const struct drm_display_mode *adjusted_mode =
1913 		&crtc_state->hw.adjusted_mode;
1914 
1915 	/*
1916 	 * Our YCbCr output is always limited range.
1917 	 * crtc_state->limited_color_range only applies to RGB,
1918 	 * and it must never be set for YCbCr or we risk setting
1919 	 * some conflicting bits in TRANSCONF which will mess up
1920 	 * the colors on the monitor.
1921 	 */
1922 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1923 		return false;
1924 
1925 	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1926 		/*
1927 		 * See:
1928 		 * CEA-861-E - 5.1 Default Encoding Parameters
1929 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1930 		 */
1931 		return crtc_state->pipe_bpp != 18 &&
1932 			drm_default_rgb_quant_range(adjusted_mode) ==
1933 			HDMI_QUANTIZATION_RANGE_LIMITED;
1934 	} else {
1935 		return intel_conn_state->broadcast_rgb ==
1936 			INTEL_BROADCAST_RGB_LIMITED;
1937 	}
1938 }
1939 
intel_dp_port_has_audio(struct drm_i915_private * dev_priv,enum port port)1940 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1941 				    enum port port)
1942 {
1943 	if (IS_G4X(dev_priv))
1944 		return false;
1945 	if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1946 		return false;
1947 
1948 	return true;
1949 }
1950 
intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)1951 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1952 					     const struct drm_connector_state *conn_state,
1953 					     struct drm_dp_vsc_sdp *vsc)
1954 {
1955 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1956 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1957 
1958 	/*
1959 	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1960 	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1961 	 * Colorimetry Format indication.
1962 	 */
1963 	vsc->revision = 0x5;
1964 	vsc->length = 0x13;
1965 
1966 	/* DP 1.4a spec, Table 2-120 */
1967 	switch (crtc_state->output_format) {
1968 	case INTEL_OUTPUT_FORMAT_YCBCR444:
1969 		vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1970 		break;
1971 	case INTEL_OUTPUT_FORMAT_YCBCR420:
1972 		vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1973 		break;
1974 	case INTEL_OUTPUT_FORMAT_RGB:
1975 	default:
1976 		vsc->pixelformat = DP_PIXELFORMAT_RGB;
1977 	}
1978 
1979 	switch (conn_state->colorspace) {
1980 	case DRM_MODE_COLORIMETRY_BT709_YCC:
1981 		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1982 		break;
1983 	case DRM_MODE_COLORIMETRY_XVYCC_601:
1984 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1985 		break;
1986 	case DRM_MODE_COLORIMETRY_XVYCC_709:
1987 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1988 		break;
1989 	case DRM_MODE_COLORIMETRY_SYCC_601:
1990 		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1991 		break;
1992 	case DRM_MODE_COLORIMETRY_OPYCC_601:
1993 		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1994 		break;
1995 	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1996 		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1997 		break;
1998 	case DRM_MODE_COLORIMETRY_BT2020_RGB:
1999 		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2000 		break;
2001 	case DRM_MODE_COLORIMETRY_BT2020_YCC:
2002 		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2003 		break;
2004 	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2005 	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2006 		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2007 		break;
2008 	default:
2009 		/*
2010 		 * RGB->YCBCR color conversion uses the BT.709
2011 		 * color space.
2012 		 */
2013 		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2014 			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2015 		else
2016 			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2017 		break;
2018 	}
2019 
2020 	vsc->bpc = crtc_state->pipe_bpp / 3;
2021 
2022 	/* only RGB pixelformat supports 6 bpc */
2023 	drm_WARN_ON(&dev_priv->drm,
2024 		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2025 
2026 	/* all YCbCr are always limited range */
2027 	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2028 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2029 }
2030 
intel_dp_compute_vsc_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2031 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2032 				     struct intel_crtc_state *crtc_state,
2033 				     const struct drm_connector_state *conn_state)
2034 {
2035 	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2036 
2037 	/* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2038 	if (crtc_state->has_psr)
2039 		return;
2040 
2041 	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2042 		return;
2043 
2044 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2045 	vsc->sdp_type = DP_SDP_VSC;
2046 	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2047 					 &crtc_state->infoframes.vsc);
2048 }
2049 
intel_dp_compute_psr_vsc_sdp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)2050 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2051 				  const struct intel_crtc_state *crtc_state,
2052 				  const struct drm_connector_state *conn_state,
2053 				  struct drm_dp_vsc_sdp *vsc)
2054 {
2055 	vsc->sdp_type = DP_SDP_VSC;
2056 
2057 	if (crtc_state->has_psr2) {
2058 		if (intel_dp->psr.colorimetry_support &&
2059 		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2060 			/* [PSR2, +Colorimetry] */
2061 			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2062 							 vsc);
2063 		} else {
2064 			/*
2065 			 * [PSR2, -Colorimetry]
2066 			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2067 			 * 3D stereo + PSR/PSR2 + Y-coordinate.
2068 			 */
2069 			vsc->revision = 0x4;
2070 			vsc->length = 0xe;
2071 		}
2072 	} else {
2073 		/*
2074 		 * [PSR1]
2075 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2076 		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2077 		 * higher).
2078 		 */
2079 		vsc->revision = 0x2;
2080 		vsc->length = 0x8;
2081 	}
2082 }
2083 
2084 static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2085 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2086 					    struct intel_crtc_state *crtc_state,
2087 					    const struct drm_connector_state *conn_state)
2088 {
2089 	int ret;
2090 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2091 	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2092 
2093 	if (!conn_state->hdr_output_metadata)
2094 		return;
2095 
2096 	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2097 
2098 	if (ret) {
2099 		drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2100 		return;
2101 	}
2102 
2103 	crtc_state->infoframes.enable |=
2104 		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2105 }
2106 
cpu_transcoder_has_drrs(struct drm_i915_private * i915,enum transcoder cpu_transcoder)2107 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2108 				    enum transcoder cpu_transcoder)
2109 {
2110 	if (HAS_DOUBLE_BUFFERED_M_N(i915))
2111 		return true;
2112 
2113 	return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2114 }
2115 
can_enable_drrs(struct intel_connector * connector,const struct intel_crtc_state * pipe_config,const struct drm_display_mode * downclock_mode)2116 static bool can_enable_drrs(struct intel_connector *connector,
2117 			    const struct intel_crtc_state *pipe_config,
2118 			    const struct drm_display_mode *downclock_mode)
2119 {
2120 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
2121 
2122 	if (pipe_config->vrr.enable)
2123 		return false;
2124 
2125 	/*
2126 	 * DRRS and PSR can't be enable together, so giving preference to PSR
2127 	 * as it allows more power-savings by complete shutting down display,
2128 	 * so to guarantee this, intel_drrs_compute_config() must be called
2129 	 * after intel_psr_compute_config().
2130 	 */
2131 	if (pipe_config->has_psr)
2132 		return false;
2133 
2134 	/* FIXME missing FDI M2/N2 etc. */
2135 	if (pipe_config->has_pch_encoder)
2136 		return false;
2137 
2138 	if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2139 		return false;
2140 
2141 	return downclock_mode &&
2142 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2143 }
2144 
2145 static void
intel_dp_drrs_compute_config(struct intel_connector * connector,struct intel_crtc_state * pipe_config,int output_bpp)2146 intel_dp_drrs_compute_config(struct intel_connector *connector,
2147 			     struct intel_crtc_state *pipe_config,
2148 			     int output_bpp)
2149 {
2150 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
2151 	const struct drm_display_mode *downclock_mode =
2152 		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2153 	int pixel_clock;
2154 
2155 	/*
2156 	 * FIXME all joined pipes share the same transcoder.
2157 	 * Need to account for that when updating M/N live.
2158 	 */
2159 	if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes)
2160 		pipe_config->update_m_n = true;
2161 
2162 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2163 		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2164 			intel_zero_m_n(&pipe_config->dp_m2_n2);
2165 		return;
2166 	}
2167 
2168 	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2169 		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2170 
2171 	pipe_config->has_drrs = true;
2172 
2173 	pixel_clock = downclock_mode->clock;
2174 	if (pipe_config->splitter.enable)
2175 		pixel_clock /= pipe_config->splitter.link_count;
2176 
2177 	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
2178 			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
2179 			       pipe_config->fec_enable);
2180 
2181 	/* FIXME: abstract this better */
2182 	if (pipe_config->splitter.enable)
2183 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2184 }
2185 
intel_dp_has_audio(struct intel_encoder * encoder,const struct drm_connector_state * conn_state)2186 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2187 			       const struct drm_connector_state *conn_state)
2188 {
2189 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2190 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2191 	struct intel_connector *connector = intel_dp->attached_connector;
2192 	const struct intel_digital_connector_state *intel_conn_state =
2193 		to_intel_digital_connector_state(conn_state);
2194 
2195 	if (!intel_dp_port_has_audio(i915, encoder->port))
2196 		return false;
2197 
2198 	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2199 		return connector->base.display_info.has_audio;
2200 	else
2201 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2202 }
2203 
2204 static int
intel_dp_compute_output_format(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state,bool respect_downstream_limits)2205 intel_dp_compute_output_format(struct intel_encoder *encoder,
2206 			       struct intel_crtc_state *crtc_state,
2207 			       struct drm_connector_state *conn_state,
2208 			       bool respect_downstream_limits)
2209 {
2210 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2211 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2212 	struct intel_connector *connector = intel_dp->attached_connector;
2213 	const struct drm_display_info *info = &connector->base.display_info;
2214 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2215 	bool ycbcr_420_only;
2216 	int ret;
2217 
2218 	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2219 
2220 	if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2221 		drm_dbg_kms(&i915->drm,
2222 			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2223 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2224 	} else {
2225 		crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2226 	}
2227 
2228 	crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2229 
2230 	ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2231 					   respect_downstream_limits);
2232 	if (ret) {
2233 		if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2234 		    !connector->base.ycbcr_420_allowed ||
2235 		    !drm_mode_is_420_also(info, adjusted_mode))
2236 			return ret;
2237 
2238 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2239 		crtc_state->output_format = intel_dp_output_format(connector,
2240 								   crtc_state->sink_format);
2241 		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2242 						   respect_downstream_limits);
2243 	}
2244 
2245 	return ret;
2246 }
2247 
2248 static void
intel_dp_audio_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)2249 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2250 			      struct intel_crtc_state *pipe_config,
2251 			      struct drm_connector_state *conn_state)
2252 {
2253 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2254 	struct drm_connector *connector = conn_state->connector;
2255 
2256 	pipe_config->sdp_split_enable =
2257 		intel_dp_has_audio(encoder, conn_state) &&
2258 		intel_dp_is_uhbr(pipe_config);
2259 
2260 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2261 		    connector->base.id, connector->name,
2262 		    str_yes_no(pipe_config->sdp_split_enable));
2263 }
2264 
2265 int
intel_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)2266 intel_dp_compute_config(struct intel_encoder *encoder,
2267 			struct intel_crtc_state *pipe_config,
2268 			struct drm_connector_state *conn_state)
2269 {
2270 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2271 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2272 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2273 	const struct drm_display_mode *fixed_mode;
2274 	struct intel_connector *connector = intel_dp->attached_connector;
2275 	int ret = 0, output_bpp;
2276 
2277 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2278 		pipe_config->has_pch_encoder = true;
2279 
2280 	pipe_config->has_audio =
2281 		intel_dp_has_audio(encoder, conn_state) &&
2282 		intel_audio_compute_config(encoder, pipe_config, conn_state);
2283 
2284 	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2285 	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2286 		ret = intel_panel_compute_config(connector, adjusted_mode);
2287 		if (ret)
2288 			return ret;
2289 	}
2290 
2291 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2292 		return -EINVAL;
2293 
2294 	if (!connector->base.interlace_allowed &&
2295 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2296 		return -EINVAL;
2297 
2298 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2299 		return -EINVAL;
2300 
2301 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2302 		return -EINVAL;
2303 
2304 	/*
2305 	 * Try to respect downstream TMDS clock limits first, if
2306 	 * that fails assume the user might know something we don't.
2307 	 */
2308 	ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2309 	if (ret)
2310 		ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2311 	if (ret)
2312 		return ret;
2313 
2314 	if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2315 	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2316 		ret = intel_panel_fitting(pipe_config, conn_state);
2317 		if (ret)
2318 			return ret;
2319 	}
2320 
2321 	pipe_config->limited_color_range =
2322 		intel_dp_limited_color_range(pipe_config, conn_state);
2323 
2324 	pipe_config->enhanced_framing =
2325 		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2326 
2327 	if (pipe_config->dsc.compression_enable)
2328 		output_bpp = pipe_config->dsc.compressed_bpp;
2329 	else
2330 		output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2331 						 pipe_config->pipe_bpp);
2332 
2333 	if (intel_dp->mso_link_count) {
2334 		int n = intel_dp->mso_link_count;
2335 		int overlap = intel_dp->mso_pixel_overlap;
2336 
2337 		pipe_config->splitter.enable = true;
2338 		pipe_config->splitter.link_count = n;
2339 		pipe_config->splitter.pixel_overlap = overlap;
2340 
2341 		drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2342 			    n, overlap);
2343 
2344 		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2345 		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2346 		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2347 		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2348 		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2349 		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2350 		adjusted_mode->crtc_clock /= n;
2351 	}
2352 
2353 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2354 
2355 	intel_link_compute_m_n(output_bpp,
2356 			       pipe_config->lane_count,
2357 			       adjusted_mode->crtc_clock,
2358 			       pipe_config->port_clock,
2359 			       &pipe_config->dp_m_n,
2360 			       pipe_config->fec_enable);
2361 
2362 	/* FIXME: abstract this better */
2363 	if (pipe_config->splitter.enable)
2364 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2365 
2366 	if (!HAS_DDI(dev_priv))
2367 		g4x_dp_set_clock(encoder, pipe_config);
2368 
2369 	intel_vrr_compute_config(pipe_config, conn_state);
2370 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2371 	intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2372 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2373 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2374 
2375 	return 0;
2376 }
2377 
intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count)2378 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2379 			      int link_rate, int lane_count)
2380 {
2381 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2382 	intel_dp->link_trained = false;
2383 	intel_dp->link_rate = link_rate;
2384 	intel_dp->lane_count = lane_count;
2385 }
2386 
intel_dp_reset_max_link_params(struct intel_dp * intel_dp)2387 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2388 {
2389 	intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2390 	intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2391 }
2392 
2393 /* Enable backlight PWM and backlight PP control. */
intel_edp_backlight_on(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2394 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2395 			    const struct drm_connector_state *conn_state)
2396 {
2397 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2398 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2399 
2400 	if (!intel_dp_is_edp(intel_dp))
2401 		return;
2402 
2403 	drm_dbg_kms(&i915->drm, "\n");
2404 
2405 	intel_backlight_enable(crtc_state, conn_state);
2406 	intel_pps_backlight_on(intel_dp);
2407 }
2408 
2409 /* Disable backlight PP control and backlight PWM. */
intel_edp_backlight_off(const struct drm_connector_state * old_conn_state)2410 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2411 {
2412 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2413 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2414 
2415 	if (!intel_dp_is_edp(intel_dp))
2416 		return;
2417 
2418 	drm_dbg_kms(&i915->drm, "\n");
2419 
2420 	intel_pps_backlight_off(intel_dp);
2421 	intel_backlight_disable(old_conn_state);
2422 }
2423 
downstream_hpd_needs_d0(struct intel_dp * intel_dp)2424 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2425 {
2426 	/*
2427 	 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2428 	 * be capable of signalling downstream hpd with a long pulse.
2429 	 * Whether or not that means D3 is safe to use is not clear,
2430 	 * but let's assume so until proven otherwise.
2431 	 *
2432 	 * FIXME should really check all downstream ports...
2433 	 */
2434 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2435 		drm_dp_is_branch(intel_dp->dpcd) &&
2436 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2437 }
2438 
intel_dp_sink_set_decompression_state(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)2439 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2440 					   const struct intel_crtc_state *crtc_state,
2441 					   bool enable)
2442 {
2443 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2444 	int ret;
2445 
2446 	if (!crtc_state->dsc.compression_enable)
2447 		return;
2448 
2449 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2450 				 enable ? DP_DECOMPRESSION_EN : 0);
2451 	if (ret < 0)
2452 		drm_dbg_kms(&i915->drm,
2453 			    "Failed to %s sink decompression state\n",
2454 			    str_enable_disable(enable));
2455 }
2456 
2457 static void
intel_edp_init_source_oui(struct intel_dp * intel_dp,bool careful)2458 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2459 {
2460 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2461 	u8 oui[] = { 0x00, 0xaa, 0x01 };
2462 	u8 buf[3] = { 0 };
2463 
2464 	/*
2465 	 * During driver init, we want to be careful and avoid changing the source OUI if it's
2466 	 * already set to what we want, so as to avoid clearing any state by accident
2467 	 */
2468 	if (careful) {
2469 		if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2470 			drm_err(&i915->drm, "Failed to read source OUI\n");
2471 
2472 		if (memcmp(oui, buf, sizeof(oui)) == 0)
2473 			return;
2474 	}
2475 
2476 	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2477 		drm_err(&i915->drm, "Failed to write source OUI\n");
2478 
2479 	intel_dp->last_oui_write = jiffies;
2480 }
2481 
intel_dp_wait_source_oui(struct intel_dp * intel_dp)2482 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2483 {
2484 	struct intel_connector *connector = intel_dp->attached_connector;
2485 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2486 
2487 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
2488 		    connector->base.base.id, connector->base.name,
2489 		    connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2490 
2491 	wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
2492 				       connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2493 }
2494 
2495 /* If the device supports it, try to set the power state appropriately */
intel_dp_set_power(struct intel_dp * intel_dp,u8 mode)2496 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2497 {
2498 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2499 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2500 	int ret, i;
2501 
2502 	/* Should have a valid DPCD by this point */
2503 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2504 		return;
2505 
2506 	if (mode != DP_SET_POWER_D0) {
2507 		if (downstream_hpd_needs_d0(intel_dp))
2508 			return;
2509 
2510 		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2511 	} else {
2512 		struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2513 
2514 		lspcon_resume(dp_to_dig_port(intel_dp));
2515 
2516 		/* Write the source OUI as early as possible */
2517 		if (intel_dp_is_edp(intel_dp))
2518 			intel_edp_init_source_oui(intel_dp, false);
2519 
2520 		/*
2521 		 * When turning on, we need to retry for 1ms to give the sink
2522 		 * time to wake up.
2523 		 */
2524 		for (i = 0; i < 3; i++) {
2525 			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2526 			if (ret == 1)
2527 				break;
2528 			msleep(1);
2529 		}
2530 
2531 		if (ret == 1 && lspcon->active)
2532 			lspcon_wait_pcon_mode(lspcon);
2533 	}
2534 
2535 	if (ret != 1)
2536 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2537 			    encoder->base.base.id, encoder->base.name,
2538 			    mode == DP_SET_POWER_D0 ? "D0" : "D3");
2539 }
2540 
2541 static bool
2542 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2543 
2544 /**
2545  * intel_dp_sync_state - sync the encoder state during init/resume
2546  * @encoder: intel encoder to sync
2547  * @crtc_state: state for the CRTC connected to the encoder
2548  *
2549  * Sync any state stored in the encoder wrt. HW state during driver init
2550  * and system resume.
2551  */
intel_dp_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2552 void intel_dp_sync_state(struct intel_encoder *encoder,
2553 			 const struct intel_crtc_state *crtc_state)
2554 {
2555 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2556 
2557 	if (!crtc_state)
2558 		return;
2559 
2560 	/*
2561 	 * Don't clobber DPCD if it's been already read out during output
2562 	 * setup (eDP) or detect.
2563 	 */
2564 	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2565 		intel_dp_get_dpcd(intel_dp);
2566 
2567 	intel_dp_reset_max_link_params(intel_dp);
2568 }
2569 
intel_dp_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)2570 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2571 				    struct intel_crtc_state *crtc_state)
2572 {
2573 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2574 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2575 	bool fastset = true;
2576 
2577 	/*
2578 	 * If BIOS has set an unsupported or non-standard link rate for some
2579 	 * reason force an encoder recompute and full modeset.
2580 	 */
2581 	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2582 				crtc_state->port_clock) < 0) {
2583 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
2584 			    encoder->base.base.id, encoder->base.name);
2585 		crtc_state->uapi.connectors_changed = true;
2586 		fastset = false;
2587 	}
2588 
2589 	/*
2590 	 * FIXME hack to force full modeset when DSC is being used.
2591 	 *
2592 	 * As long as we do not have full state readout and config comparison
2593 	 * of crtc_state->dsc, we have no way to ensure reliable fastset.
2594 	 * Remove once we have readout for DSC.
2595 	 */
2596 	if (crtc_state->dsc.compression_enable) {
2597 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
2598 			    encoder->base.base.id, encoder->base.name);
2599 		crtc_state->uapi.mode_changed = true;
2600 		fastset = false;
2601 	}
2602 
2603 	if (CAN_PSR(intel_dp)) {
2604 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
2605 			    encoder->base.base.id, encoder->base.name);
2606 		crtc_state->uapi.mode_changed = true;
2607 		fastset = false;
2608 	}
2609 
2610 	return fastset;
2611 }
2612 
intel_dp_get_pcon_dsc_cap(struct intel_dp * intel_dp)2613 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2614 {
2615 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2616 
2617 	/* Clear the cached register set to avoid using stale values */
2618 
2619 	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2620 
2621 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2622 			     intel_dp->pcon_dsc_dpcd,
2623 			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2624 		drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2625 			DP_PCON_DSC_ENCODER);
2626 
2627 	drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2628 		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2629 }
2630 
intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)2631 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2632 {
2633 	int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2634 	int i;
2635 
2636 	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2637 		if (frl_bw_mask & (1 << i))
2638 			return bw_gbps[i];
2639 	}
2640 	return 0;
2641 }
2642 
intel_dp_pcon_set_frl_mask(int max_frl)2643 static int intel_dp_pcon_set_frl_mask(int max_frl)
2644 {
2645 	switch (max_frl) {
2646 	case 48:
2647 		return DP_PCON_FRL_BW_MASK_48GBPS;
2648 	case 40:
2649 		return DP_PCON_FRL_BW_MASK_40GBPS;
2650 	case 32:
2651 		return DP_PCON_FRL_BW_MASK_32GBPS;
2652 	case 24:
2653 		return DP_PCON_FRL_BW_MASK_24GBPS;
2654 	case 18:
2655 		return DP_PCON_FRL_BW_MASK_18GBPS;
2656 	case 9:
2657 		return DP_PCON_FRL_BW_MASK_9GBPS;
2658 	}
2659 
2660 	return 0;
2661 }
2662 
intel_dp_hdmi_sink_max_frl(struct intel_dp * intel_dp)2663 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2664 {
2665 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2666 	struct drm_connector *connector = &intel_connector->base;
2667 	int max_frl_rate;
2668 	int max_lanes, rate_per_lane;
2669 	int max_dsc_lanes, dsc_rate_per_lane;
2670 
2671 	max_lanes = connector->display_info.hdmi.max_lanes;
2672 	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2673 	max_frl_rate = max_lanes * rate_per_lane;
2674 
2675 	if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2676 		max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2677 		dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2678 		if (max_dsc_lanes && dsc_rate_per_lane)
2679 			max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2680 	}
2681 
2682 	return max_frl_rate;
2683 }
2684 
2685 static bool
intel_dp_pcon_is_frl_trained(struct intel_dp * intel_dp,u8 max_frl_bw_mask,u8 * frl_trained_mask)2686 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2687 			     u8 max_frl_bw_mask, u8 *frl_trained_mask)
2688 {
2689 	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2690 	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2691 	    *frl_trained_mask >= max_frl_bw_mask)
2692 		return true;
2693 
2694 	return false;
2695 }
2696 
intel_dp_pcon_start_frl_training(struct intel_dp * intel_dp)2697 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2698 {
2699 #define TIMEOUT_FRL_READY_MS 500
2700 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2701 
2702 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2703 	int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2704 	u8 max_frl_bw_mask = 0, frl_trained_mask;
2705 	bool is_active;
2706 
2707 	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2708 	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2709 
2710 	max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2711 	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2712 
2713 	max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2714 
2715 	if (max_frl_bw <= 0)
2716 		return -EINVAL;
2717 
2718 	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2719 	drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2720 
2721 	if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2722 		goto frl_trained;
2723 
2724 	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2725 	if (ret < 0)
2726 		return ret;
2727 	/* Wait for PCON to be FRL Ready */
2728 	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2729 
2730 	if (!is_active)
2731 		return -ETIMEDOUT;
2732 
2733 	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2734 					  DP_PCON_ENABLE_SEQUENTIAL_LINK);
2735 	if (ret < 0)
2736 		return ret;
2737 	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2738 					  DP_PCON_FRL_LINK_TRAIN_NORMAL);
2739 	if (ret < 0)
2740 		return ret;
2741 	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2742 	if (ret < 0)
2743 		return ret;
2744 	/*
2745 	 * Wait for FRL to be completed
2746 	 * Check if the HDMI Link is up and active.
2747 	 */
2748 	wait_for(is_active =
2749 		 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2750 		 TIMEOUT_HDMI_LINK_ACTIVE_MS);
2751 
2752 	if (!is_active)
2753 		return -ETIMEDOUT;
2754 
2755 frl_trained:
2756 	drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2757 	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2758 	intel_dp->frl.is_trained = true;
2759 	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2760 
2761 	return 0;
2762 }
2763 
intel_dp_is_hdmi_2_1_sink(struct intel_dp * intel_dp)2764 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2765 {
2766 	if (drm_dp_is_branch(intel_dp->dpcd) &&
2767 	    intel_dp_has_hdmi_sink(intel_dp) &&
2768 	    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2769 		return true;
2770 
2771 	return false;
2772 }
2773 
2774 static
intel_dp_pcon_set_tmds_mode(struct intel_dp * intel_dp)2775 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2776 {
2777 	int ret;
2778 	u8 buf = 0;
2779 
2780 	/* Set PCON source control mode */
2781 	buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2782 
2783 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2784 	if (ret < 0)
2785 		return ret;
2786 
2787 	/* Set HDMI LINK ENABLE */
2788 	buf |= DP_PCON_ENABLE_HDMI_LINK;
2789 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2790 	if (ret < 0)
2791 		return ret;
2792 
2793 	return 0;
2794 }
2795 
intel_dp_check_frl_training(struct intel_dp * intel_dp)2796 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2797 {
2798 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2799 
2800 	/*
2801 	 * Always go for FRL training if:
2802 	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2803 	 * -sink is HDMI2.1
2804 	 */
2805 	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2806 	    !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2807 	    intel_dp->frl.is_trained)
2808 		return;
2809 
2810 	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2811 		int ret, mode;
2812 
2813 		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2814 		ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2815 		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2816 
2817 		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2818 			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2819 	} else {
2820 		drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2821 	}
2822 }
2823 
2824 static int
intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state * crtc_state)2825 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2826 {
2827 	int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2828 
2829 	return intel_hdmi_dsc_get_slice_height(vactive);
2830 }
2831 
2832 static int
intel_dp_pcon_dsc_enc_slices(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2833 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2834 			     const struct intel_crtc_state *crtc_state)
2835 {
2836 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2837 	struct drm_connector *connector = &intel_connector->base;
2838 	int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2839 	int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2840 	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2841 	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2842 
2843 	return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2844 					     pcon_max_slice_width,
2845 					     hdmi_max_slices, hdmi_throughput);
2846 }
2847 
2848 static int
intel_dp_pcon_dsc_enc_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int num_slices,int slice_width)2849 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2850 			  const struct intel_crtc_state *crtc_state,
2851 			  int num_slices, int slice_width)
2852 {
2853 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2854 	struct drm_connector *connector = &intel_connector->base;
2855 	int output_format = crtc_state->output_format;
2856 	bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2857 	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2858 	int hdmi_max_chunk_bytes =
2859 		connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2860 
2861 	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2862 				      num_slices, output_format, hdmi_all_bpp,
2863 				      hdmi_max_chunk_bytes);
2864 }
2865 
2866 void
intel_dp_pcon_dsc_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2867 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2868 			    const struct intel_crtc_state *crtc_state)
2869 {
2870 	u8 pps_param[6];
2871 	int slice_height;
2872 	int slice_width;
2873 	int num_slices;
2874 	int bits_per_pixel;
2875 	int ret;
2876 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2877 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2878 	struct drm_connector *connector;
2879 	bool hdmi_is_dsc_1_2;
2880 
2881 	if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2882 		return;
2883 
2884 	if (!intel_connector)
2885 		return;
2886 	connector = &intel_connector->base;
2887 	hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2888 
2889 	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2890 	    !hdmi_is_dsc_1_2)
2891 		return;
2892 
2893 	slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2894 	if (!slice_height)
2895 		return;
2896 
2897 	num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2898 	if (!num_slices)
2899 		return;
2900 
2901 	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2902 				   num_slices);
2903 
2904 	bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2905 						   num_slices, slice_width);
2906 	if (!bits_per_pixel)
2907 		return;
2908 
2909 	pps_param[0] = slice_height & 0xFF;
2910 	pps_param[1] = slice_height >> 8;
2911 	pps_param[2] = slice_width & 0xFF;
2912 	pps_param[3] = slice_width >> 8;
2913 	pps_param[4] = bits_per_pixel & 0xFF;
2914 	pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2915 
2916 	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2917 	if (ret < 0)
2918 		drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2919 }
2920 
intel_dp_configure_protocol_converter(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2921 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2922 					   const struct intel_crtc_state *crtc_state)
2923 {
2924 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2925 	bool ycbcr444_to_420 = false;
2926 	bool rgb_to_ycbcr = false;
2927 	u8 tmp;
2928 
2929 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2930 		return;
2931 
2932 	if (!drm_dp_is_branch(intel_dp->dpcd))
2933 		return;
2934 
2935 	tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2936 
2937 	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2938 			       DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2939 		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2940 			    str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
2941 
2942 	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2943 		switch (crtc_state->output_format) {
2944 		case INTEL_OUTPUT_FORMAT_YCBCR420:
2945 			break;
2946 		case INTEL_OUTPUT_FORMAT_YCBCR444:
2947 			ycbcr444_to_420 = true;
2948 			break;
2949 		case INTEL_OUTPUT_FORMAT_RGB:
2950 			rgb_to_ycbcr = true;
2951 			ycbcr444_to_420 = true;
2952 			break;
2953 		default:
2954 			MISSING_CASE(crtc_state->output_format);
2955 			break;
2956 		}
2957 	} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
2958 		switch (crtc_state->output_format) {
2959 		case INTEL_OUTPUT_FORMAT_YCBCR444:
2960 			break;
2961 		case INTEL_OUTPUT_FORMAT_RGB:
2962 			rgb_to_ycbcr = true;
2963 			break;
2964 		default:
2965 			MISSING_CASE(crtc_state->output_format);
2966 			break;
2967 		}
2968 	}
2969 
2970 	tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2971 
2972 	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2973 			       DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2974 		drm_dbg_kms(&i915->drm,
2975 			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2976 			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2977 
2978 	tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2979 
2980 	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2981 		drm_dbg_kms(&i915->drm,
2982 			    "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2983 			    str_enable_disable(tmp));
2984 }
2985 
intel_dp_get_colorimetry_status(struct intel_dp * intel_dp)2986 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2987 {
2988 	u8 dprx = 0;
2989 
2990 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2991 			      &dprx) != 1)
2992 		return false;
2993 	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2994 }
2995 
intel_dp_get_dsc_sink_cap(struct intel_dp * intel_dp)2996 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2997 {
2998 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2999 
3000 	/*
3001 	 * Clear the cached register set to avoid using stale values
3002 	 * for the sinks that do not support DSC.
3003 	 */
3004 	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
3005 
3006 	/* Clear fec_capable to avoid using stale values */
3007 	intel_dp->fec_capable = 0;
3008 
3009 	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
3010 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
3011 	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3012 		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
3013 				     intel_dp->dsc_dpcd,
3014 				     sizeof(intel_dp->dsc_dpcd)) < 0)
3015 			drm_err(&i915->drm,
3016 				"Failed to read DPCD register 0x%x\n",
3017 				DP_DSC_SUPPORT);
3018 
3019 		drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
3020 			    (int)sizeof(intel_dp->dsc_dpcd),
3021 			    intel_dp->dsc_dpcd);
3022 
3023 		/* FEC is supported only on DP 1.4 */
3024 		if (!intel_dp_is_edp(intel_dp) &&
3025 		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
3026 				      &intel_dp->fec_capable) < 0)
3027 			drm_err(&i915->drm,
3028 				"Failed to read FEC DPCD register\n");
3029 
3030 		drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3031 			    intel_dp->fec_capable);
3032 	}
3033 }
3034 
intel_edp_mso_mode_fixup(struct intel_connector * connector,struct drm_display_mode * mode)3035 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3036 				     struct drm_display_mode *mode)
3037 {
3038 	struct intel_dp *intel_dp = intel_attached_dp(connector);
3039 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
3040 	int n = intel_dp->mso_link_count;
3041 	int overlap = intel_dp->mso_pixel_overlap;
3042 
3043 	if (!mode || !n)
3044 		return;
3045 
3046 	mode->hdisplay = (mode->hdisplay - overlap) * n;
3047 	mode->hsync_start = (mode->hsync_start - overlap) * n;
3048 	mode->hsync_end = (mode->hsync_end - overlap) * n;
3049 	mode->htotal = (mode->htotal - overlap) * n;
3050 	mode->clock *= n;
3051 
3052 	drm_mode_set_name(mode);
3053 
3054 	drm_dbg_kms(&i915->drm,
3055 		    "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3056 		    connector->base.base.id, connector->base.name,
3057 		    DRM_MODE_ARG(mode));
3058 }
3059 
intel_edp_fixup_vbt_bpp(struct intel_encoder * encoder,int pipe_bpp)3060 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3061 {
3062 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3063 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3064 	struct intel_connector *connector = intel_dp->attached_connector;
3065 
3066 	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3067 		/*
3068 		 * This is a big fat ugly hack.
3069 		 *
3070 		 * Some machines in UEFI boot mode provide us a VBT that has 18
3071 		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3072 		 * unknown we fail to light up. Yet the same BIOS boots up with
3073 		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3074 		 * max, not what it tells us to use.
3075 		 *
3076 		 * Note: This will still be broken if the eDP panel is not lit
3077 		 * up by the BIOS, and thus we can't get the mode at module
3078 		 * load.
3079 		 */
3080 		drm_dbg_kms(&dev_priv->drm,
3081 			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3082 			    pipe_bpp, connector->panel.vbt.edp.bpp);
3083 		connector->panel.vbt.edp.bpp = pipe_bpp;
3084 	}
3085 }
3086 
intel_edp_mso_init(struct intel_dp * intel_dp)3087 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3088 {
3089 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3090 	struct intel_connector *connector = intel_dp->attached_connector;
3091 	struct drm_display_info *info = &connector->base.display_info;
3092 	u8 mso;
3093 
3094 	if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3095 		return;
3096 
3097 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3098 		drm_err(&i915->drm, "Failed to read MSO cap\n");
3099 		return;
3100 	}
3101 
3102 	/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3103 	mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3104 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3105 		drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3106 		mso = 0;
3107 	}
3108 
3109 	if (mso) {
3110 		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3111 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3112 			    info->mso_pixel_overlap);
3113 		if (!HAS_MSO(i915)) {
3114 			drm_err(&i915->drm, "No source MSO support, disabling\n");
3115 			mso = 0;
3116 		}
3117 	}
3118 
3119 	intel_dp->mso_link_count = mso;
3120 	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3121 }
3122 
3123 static bool
intel_edp_init_dpcd(struct intel_dp * intel_dp)3124 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3125 {
3126 	struct drm_i915_private *dev_priv =
3127 		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3128 
3129 	/* this function is meant to be called only once */
3130 	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3131 
3132 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3133 		return false;
3134 
3135 	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3136 			 drm_dp_is_branch(intel_dp->dpcd));
3137 
3138 	/*
3139 	 * Read the eDP display control registers.
3140 	 *
3141 	 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3142 	 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3143 	 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3144 	 * method). The display control registers should read zero if they're
3145 	 * not supported anyway.
3146 	 */
3147 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3148 			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3149 			     sizeof(intel_dp->edp_dpcd)) {
3150 		drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3151 			    (int)sizeof(intel_dp->edp_dpcd),
3152 			    intel_dp->edp_dpcd);
3153 
3154 		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3155 	}
3156 
3157 	/*
3158 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3159 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3160 	 */
3161 	intel_psr_init_dpcd(intel_dp);
3162 
3163 	/* Clear the default sink rates */
3164 	intel_dp->num_sink_rates = 0;
3165 
3166 	/* Read the eDP 1.4+ supported link rates. */
3167 	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3168 		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3169 		int i;
3170 
3171 		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3172 				sink_rates, sizeof(sink_rates));
3173 
3174 		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3175 			int val = le16_to_cpu(sink_rates[i]);
3176 
3177 			if (val == 0)
3178 				break;
3179 
3180 			/* Value read multiplied by 200kHz gives the per-lane
3181 			 * link rate in kHz. The source rates are, however,
3182 			 * stored in terms of LS_Clk kHz. The full conversion
3183 			 * back to symbols is
3184 			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3185 			 */
3186 			intel_dp->sink_rates[i] = (val * 200) / 10;
3187 		}
3188 		intel_dp->num_sink_rates = i;
3189 	}
3190 
3191 	/*
3192 	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3193 	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3194 	 */
3195 	if (intel_dp->num_sink_rates)
3196 		intel_dp->use_rate_select = true;
3197 	else
3198 		intel_dp_set_sink_rates(intel_dp);
3199 	intel_dp_set_max_sink_lane_count(intel_dp);
3200 
3201 	/* Read the eDP DSC DPCD registers */
3202 	if (HAS_DSC(dev_priv))
3203 		intel_dp_get_dsc_sink_cap(intel_dp);
3204 
3205 	/*
3206 	 * If needed, program our source OUI so we can make various Intel-specific AUX services
3207 	 * available (such as HDR backlight controls)
3208 	 */
3209 	intel_edp_init_source_oui(intel_dp, true);
3210 
3211 	return true;
3212 }
3213 
3214 static bool
intel_dp_has_sink_count(struct intel_dp * intel_dp)3215 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3216 {
3217 	if (!intel_dp->attached_connector)
3218 		return false;
3219 
3220 	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3221 					  intel_dp->dpcd,
3222 					  &intel_dp->desc);
3223 }
3224 
3225 static bool
intel_dp_get_dpcd(struct intel_dp * intel_dp)3226 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3227 {
3228 	int ret;
3229 
3230 	if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3231 		return false;
3232 
3233 	/*
3234 	 * Don't clobber cached eDP rates. Also skip re-reading
3235 	 * the OUI/ID since we know it won't change.
3236 	 */
3237 	if (!intel_dp_is_edp(intel_dp)) {
3238 		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3239 				 drm_dp_is_branch(intel_dp->dpcd));
3240 
3241 		intel_dp_set_sink_rates(intel_dp);
3242 		intel_dp_set_max_sink_lane_count(intel_dp);
3243 		intel_dp_set_common_rates(intel_dp);
3244 	}
3245 
3246 	if (intel_dp_has_sink_count(intel_dp)) {
3247 		ret = drm_dp_read_sink_count(&intel_dp->aux);
3248 		if (ret < 0)
3249 			return false;
3250 
3251 		/*
3252 		 * Sink count can change between short pulse hpd hence
3253 		 * a member variable in intel_dp will track any changes
3254 		 * between short pulse interrupts.
3255 		 */
3256 		intel_dp->sink_count = ret;
3257 
3258 		/*
3259 		 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3260 		 * a dongle is present but no display. Unless we require to know
3261 		 * if a dongle is present or not, we don't need to update
3262 		 * downstream port information. So, an early return here saves
3263 		 * time from performing other operations which are not required.
3264 		 */
3265 		if (!intel_dp->sink_count)
3266 			return false;
3267 	}
3268 
3269 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3270 					   intel_dp->downstream_ports) == 0;
3271 }
3272 
3273 static bool
intel_dp_can_mst(struct intel_dp * intel_dp)3274 intel_dp_can_mst(struct intel_dp *intel_dp)
3275 {
3276 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3277 
3278 	return i915->params.enable_dp_mst &&
3279 		intel_dp_mst_source_support(intel_dp) &&
3280 		drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3281 }
3282 
3283 static void
intel_dp_configure_mst(struct intel_dp * intel_dp)3284 intel_dp_configure_mst(struct intel_dp *intel_dp)
3285 {
3286 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3287 	struct intel_encoder *encoder =
3288 		&dp_to_dig_port(intel_dp)->base;
3289 	bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3290 
3291 	drm_dbg_kms(&i915->drm,
3292 		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3293 		    encoder->base.base.id, encoder->base.name,
3294 		    str_yes_no(intel_dp_mst_source_support(intel_dp)),
3295 		    str_yes_no(sink_can_mst),
3296 		    str_yes_no(i915->params.enable_dp_mst));
3297 
3298 	if (!intel_dp_mst_source_support(intel_dp))
3299 		return;
3300 
3301 	intel_dp->is_mst = sink_can_mst &&
3302 		i915->params.enable_dp_mst;
3303 
3304 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3305 					intel_dp->is_mst);
3306 }
3307 
3308 static bool
intel_dp_get_sink_irq_esi(struct intel_dp * intel_dp,u8 * esi)3309 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3310 {
3311 	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3312 }
3313 
intel_dp_ack_sink_irq_esi(struct intel_dp * intel_dp,u8 esi[4])3314 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3315 {
3316 	int retry;
3317 
3318 	for (retry = 0; retry < 3; retry++) {
3319 		if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3320 				      &esi[1], 3) == 3)
3321 			return true;
3322 	}
3323 
3324 	return false;
3325 }
3326 
3327 bool
intel_dp_needs_vsc_sdp(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3328 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3329 		       const struct drm_connector_state *conn_state)
3330 {
3331 	/*
3332 	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3333 	 * of Color Encoding Format and Content Color Gamut], in order to
3334 	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3335 	 */
3336 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3337 		return true;
3338 
3339 	switch (conn_state->colorspace) {
3340 	case DRM_MODE_COLORIMETRY_SYCC_601:
3341 	case DRM_MODE_COLORIMETRY_OPYCC_601:
3342 	case DRM_MODE_COLORIMETRY_BT2020_YCC:
3343 	case DRM_MODE_COLORIMETRY_BT2020_RGB:
3344 	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3345 		return true;
3346 	default:
3347 		break;
3348 	}
3349 
3350 	return false;
3351 }
3352 
intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp * vsc,struct dp_sdp * sdp,size_t size)3353 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3354 				     struct dp_sdp *sdp, size_t size)
3355 {
3356 	size_t length = sizeof(struct dp_sdp);
3357 
3358 	if (size < length)
3359 		return -ENOSPC;
3360 
3361 	memset(sdp, 0, size);
3362 
3363 	/*
3364 	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3365 	 * VSC SDP Header Bytes
3366 	 */
3367 	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3368 	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3369 	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3370 	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3371 
3372 	/*
3373 	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3374 	 * per DP 1.4a spec.
3375 	 */
3376 	if (vsc->revision != 0x5)
3377 		goto out;
3378 
3379 	/* VSC SDP Payload for DB16 through DB18 */
3380 	/* Pixel Encoding and Colorimetry Formats  */
3381 	sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3382 	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3383 
3384 	switch (vsc->bpc) {
3385 	case 6:
3386 		/* 6bpc: 0x0 */
3387 		break;
3388 	case 8:
3389 		sdp->db[17] = 0x1; /* DB17[3:0] */
3390 		break;
3391 	case 10:
3392 		sdp->db[17] = 0x2;
3393 		break;
3394 	case 12:
3395 		sdp->db[17] = 0x3;
3396 		break;
3397 	case 16:
3398 		sdp->db[17] = 0x4;
3399 		break;
3400 	default:
3401 		MISSING_CASE(vsc->bpc);
3402 		break;
3403 	}
3404 	/* Dynamic Range and Component Bit Depth */
3405 	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3406 		sdp->db[17] |= 0x80;  /* DB17[7] */
3407 
3408 	/* Content Type */
3409 	sdp->db[18] = vsc->content_type & 0x7;
3410 
3411 out:
3412 	return length;
3413 }
3414 
3415 static ssize_t
intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private * i915,const struct hdmi_drm_infoframe * drm_infoframe,struct dp_sdp * sdp,size_t size)3416 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3417 					 const struct hdmi_drm_infoframe *drm_infoframe,
3418 					 struct dp_sdp *sdp,
3419 					 size_t size)
3420 {
3421 	size_t length = sizeof(struct dp_sdp);
3422 	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3423 	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3424 	ssize_t len;
3425 
3426 	if (size < length)
3427 		return -ENOSPC;
3428 
3429 	memset(sdp, 0, size);
3430 
3431 	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3432 	if (len < 0) {
3433 		drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3434 		return -ENOSPC;
3435 	}
3436 
3437 	if (len != infoframe_size) {
3438 		drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3439 		return -ENOSPC;
3440 	}
3441 
3442 	/*
3443 	 * Set up the infoframe sdp packet for HDR static metadata.
3444 	 * Prepare VSC Header for SU as per DP 1.4a spec,
3445 	 * Table 2-100 and Table 2-101
3446 	 */
3447 
3448 	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3449 	sdp->sdp_header.HB0 = 0;
3450 	/*
3451 	 * Packet Type 80h + Non-audio INFOFRAME Type value
3452 	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
3453 	 * - 80h + Non-audio INFOFRAME Type value
3454 	 * - InfoFrame Type: 0x07
3455 	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3456 	 */
3457 	sdp->sdp_header.HB1 = drm_infoframe->type;
3458 	/*
3459 	 * Least Significant Eight Bits of (Data Byte Count – 1)
3460 	 * infoframe_size - 1
3461 	 */
3462 	sdp->sdp_header.HB2 = 0x1D;
3463 	/* INFOFRAME SDP Version Number */
3464 	sdp->sdp_header.HB3 = (0x13 << 2);
3465 	/* CTA Header Byte 2 (INFOFRAME Version Number) */
3466 	sdp->db[0] = drm_infoframe->version;
3467 	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3468 	sdp->db[1] = drm_infoframe->length;
3469 	/*
3470 	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3471 	 * HDMI_INFOFRAME_HEADER_SIZE
3472 	 */
3473 	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3474 	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3475 	       HDMI_DRM_INFOFRAME_SIZE);
3476 
3477 	/*
3478 	 * Size of DP infoframe sdp packet for HDR static metadata consists of
3479 	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
3480 	 * - Two Data Blocks: 2 bytes
3481 	 *    CTA Header Byte2 (INFOFRAME Version Number)
3482 	 *    CTA Header Byte3 (Length of INFOFRAME)
3483 	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3484 	 *
3485 	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3486 	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
3487 	 * will pad rest of the size.
3488 	 */
3489 	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3490 }
3491 
intel_write_dp_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type)3492 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3493 			       const struct intel_crtc_state *crtc_state,
3494 			       unsigned int type)
3495 {
3496 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3497 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3498 	struct dp_sdp sdp = {};
3499 	ssize_t len;
3500 
3501 	if ((crtc_state->infoframes.enable &
3502 	     intel_hdmi_infoframe_enable(type)) == 0)
3503 		return;
3504 
3505 	switch (type) {
3506 	case DP_SDP_VSC:
3507 		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3508 					    sizeof(sdp));
3509 		break;
3510 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
3511 		len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3512 							       &crtc_state->infoframes.drm.drm,
3513 							       &sdp, sizeof(sdp));
3514 		break;
3515 	default:
3516 		MISSING_CASE(type);
3517 		return;
3518 	}
3519 
3520 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
3521 		return;
3522 
3523 	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3524 }
3525 
intel_write_dp_vsc_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_dp_vsc_sdp * vsc)3526 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3527 			    const struct intel_crtc_state *crtc_state,
3528 			    const struct drm_dp_vsc_sdp *vsc)
3529 {
3530 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3531 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3532 	struct dp_sdp sdp = {};
3533 	ssize_t len;
3534 
3535 	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3536 
3537 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
3538 		return;
3539 
3540 	dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3541 					&sdp, len);
3542 }
3543 
intel_dp_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3544 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3545 			     bool enable,
3546 			     const struct intel_crtc_state *crtc_state,
3547 			     const struct drm_connector_state *conn_state)
3548 {
3549 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3550 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3551 	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3552 			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3553 			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3554 	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3555 
3556 	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
3557 	/* When PSR is enabled, this routine doesn't disable VSC DIP */
3558 	if (!crtc_state->has_psr)
3559 		val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3560 
3561 	intel_de_write(dev_priv, reg, val);
3562 	intel_de_posting_read(dev_priv, reg);
3563 
3564 	if (!enable)
3565 		return;
3566 
3567 	/* When PSR is enabled, VSC SDP is handled by PSR routine */
3568 	if (!crtc_state->has_psr)
3569 		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3570 
3571 	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3572 }
3573 
intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp * vsc,const void * buffer,size_t size)3574 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3575 				   const void *buffer, size_t size)
3576 {
3577 	const struct dp_sdp *sdp = buffer;
3578 
3579 	if (size < sizeof(struct dp_sdp))
3580 		return -EINVAL;
3581 
3582 	memset(vsc, 0, sizeof(*vsc));
3583 
3584 	if (sdp->sdp_header.HB0 != 0)
3585 		return -EINVAL;
3586 
3587 	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3588 		return -EINVAL;
3589 
3590 	vsc->sdp_type = sdp->sdp_header.HB1;
3591 	vsc->revision = sdp->sdp_header.HB2;
3592 	vsc->length = sdp->sdp_header.HB3;
3593 
3594 	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3595 	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3596 		/*
3597 		 * - HB2 = 0x2, HB3 = 0x8
3598 		 *   VSC SDP supporting 3D stereo + PSR
3599 		 * - HB2 = 0x4, HB3 = 0xe
3600 		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3601 		 *   first scan line of the SU region (applies to eDP v1.4b
3602 		 *   and higher).
3603 		 */
3604 		return 0;
3605 	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3606 		/*
3607 		 * - HB2 = 0x5, HB3 = 0x13
3608 		 *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3609 		 *   Format.
3610 		 */
3611 		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3612 		vsc->colorimetry = sdp->db[16] & 0xf;
3613 		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3614 
3615 		switch (sdp->db[17] & 0x7) {
3616 		case 0x0:
3617 			vsc->bpc = 6;
3618 			break;
3619 		case 0x1:
3620 			vsc->bpc = 8;
3621 			break;
3622 		case 0x2:
3623 			vsc->bpc = 10;
3624 			break;
3625 		case 0x3:
3626 			vsc->bpc = 12;
3627 			break;
3628 		case 0x4:
3629 			vsc->bpc = 16;
3630 			break;
3631 		default:
3632 			MISSING_CASE(sdp->db[17] & 0x7);
3633 			return -EINVAL;
3634 		}
3635 
3636 		vsc->content_type = sdp->db[18] & 0x7;
3637 	} else {
3638 		return -EINVAL;
3639 	}
3640 
3641 	return 0;
3642 }
3643 
3644 static int
intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe * drm_infoframe,const void * buffer,size_t size)3645 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3646 					   const void *buffer, size_t size)
3647 {
3648 	int ret;
3649 
3650 	const struct dp_sdp *sdp = buffer;
3651 
3652 	if (size < sizeof(struct dp_sdp))
3653 		return -EINVAL;
3654 
3655 	if (sdp->sdp_header.HB0 != 0)
3656 		return -EINVAL;
3657 
3658 	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3659 		return -EINVAL;
3660 
3661 	/*
3662 	 * Least Significant Eight Bits of (Data Byte Count – 1)
3663 	 * 1Dh (i.e., Data Byte Count = 30 bytes).
3664 	 */
3665 	if (sdp->sdp_header.HB2 != 0x1D)
3666 		return -EINVAL;
3667 
3668 	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3669 	if ((sdp->sdp_header.HB3 & 0x3) != 0)
3670 		return -EINVAL;
3671 
3672 	/* INFOFRAME SDP Version Number */
3673 	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3674 		return -EINVAL;
3675 
3676 	/* CTA Header Byte 2 (INFOFRAME Version Number) */
3677 	if (sdp->db[0] != 1)
3678 		return -EINVAL;
3679 
3680 	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3681 	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3682 		return -EINVAL;
3683 
3684 	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3685 					     HDMI_DRM_INFOFRAME_SIZE);
3686 
3687 	return ret;
3688 }
3689 
intel_read_dp_vsc_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_dp_vsc_sdp * vsc)3690 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3691 				  struct intel_crtc_state *crtc_state,
3692 				  struct drm_dp_vsc_sdp *vsc)
3693 {
3694 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3695 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3696 	unsigned int type = DP_SDP_VSC;
3697 	struct dp_sdp sdp = {};
3698 	int ret;
3699 
3700 	/* When PSR is enabled, VSC SDP is handled by PSR routine */
3701 	if (crtc_state->has_psr)
3702 		return;
3703 
3704 	if ((crtc_state->infoframes.enable &
3705 	     intel_hdmi_infoframe_enable(type)) == 0)
3706 		return;
3707 
3708 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3709 
3710 	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3711 
3712 	if (ret)
3713 		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3714 }
3715 
intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct hdmi_drm_infoframe * drm_infoframe)3716 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3717 						     struct intel_crtc_state *crtc_state,
3718 						     struct hdmi_drm_infoframe *drm_infoframe)
3719 {
3720 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3721 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3722 	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3723 	struct dp_sdp sdp = {};
3724 	int ret;
3725 
3726 	if ((crtc_state->infoframes.enable &
3727 	    intel_hdmi_infoframe_enable(type)) == 0)
3728 		return;
3729 
3730 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3731 				 sizeof(sdp));
3732 
3733 	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3734 							 sizeof(sdp));
3735 
3736 	if (ret)
3737 		drm_dbg_kms(&dev_priv->drm,
3738 			    "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3739 }
3740 
intel_read_dp_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,unsigned int type)3741 void intel_read_dp_sdp(struct intel_encoder *encoder,
3742 		       struct intel_crtc_state *crtc_state,
3743 		       unsigned int type)
3744 {
3745 	switch (type) {
3746 	case DP_SDP_VSC:
3747 		intel_read_dp_vsc_sdp(encoder, crtc_state,
3748 				      &crtc_state->infoframes.vsc);
3749 		break;
3750 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
3751 		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3752 							 &crtc_state->infoframes.drm.drm);
3753 		break;
3754 	default:
3755 		MISSING_CASE(type);
3756 		break;
3757 	}
3758 }
3759 
intel_dp_autotest_link_training(struct intel_dp * intel_dp)3760 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3761 {
3762 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3763 	int status = 0;
3764 	int test_link_rate;
3765 	u8 test_lane_count, test_link_bw;
3766 	/* (DP CTS 1.2)
3767 	 * 4.3.1.11
3768 	 */
3769 	/* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3770 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3771 				   &test_lane_count);
3772 
3773 	if (status <= 0) {
3774 		drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3775 		return DP_TEST_NAK;
3776 	}
3777 	test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3778 
3779 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3780 				   &test_link_bw);
3781 	if (status <= 0) {
3782 		drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3783 		return DP_TEST_NAK;
3784 	}
3785 	test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3786 
3787 	/* Validate the requested link rate and lane count */
3788 	if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3789 					test_lane_count))
3790 		return DP_TEST_NAK;
3791 
3792 	intel_dp->compliance.test_lane_count = test_lane_count;
3793 	intel_dp->compliance.test_link_rate = test_link_rate;
3794 
3795 	return DP_TEST_ACK;
3796 }
3797 
intel_dp_autotest_video_pattern(struct intel_dp * intel_dp)3798 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3799 {
3800 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3801 	u8 test_pattern;
3802 	u8 test_misc;
3803 	__be16 h_width, v_height;
3804 	int status = 0;
3805 
3806 	/* Read the TEST_PATTERN (DP CTS 3.1.5) */
3807 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3808 				   &test_pattern);
3809 	if (status <= 0) {
3810 		drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3811 		return DP_TEST_NAK;
3812 	}
3813 	if (test_pattern != DP_COLOR_RAMP)
3814 		return DP_TEST_NAK;
3815 
3816 	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3817 				  &h_width, 2);
3818 	if (status <= 0) {
3819 		drm_dbg_kms(&i915->drm, "H Width read failed\n");
3820 		return DP_TEST_NAK;
3821 	}
3822 
3823 	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3824 				  &v_height, 2);
3825 	if (status <= 0) {
3826 		drm_dbg_kms(&i915->drm, "V Height read failed\n");
3827 		return DP_TEST_NAK;
3828 	}
3829 
3830 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3831 				   &test_misc);
3832 	if (status <= 0) {
3833 		drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3834 		return DP_TEST_NAK;
3835 	}
3836 	if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3837 		return DP_TEST_NAK;
3838 	if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3839 		return DP_TEST_NAK;
3840 	switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3841 	case DP_TEST_BIT_DEPTH_6:
3842 		intel_dp->compliance.test_data.bpc = 6;
3843 		break;
3844 	case DP_TEST_BIT_DEPTH_8:
3845 		intel_dp->compliance.test_data.bpc = 8;
3846 		break;
3847 	default:
3848 		return DP_TEST_NAK;
3849 	}
3850 
3851 	intel_dp->compliance.test_data.video_pattern = test_pattern;
3852 	intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3853 	intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3854 	/* Set test active flag here so userspace doesn't interrupt things */
3855 	intel_dp->compliance.test_active = true;
3856 
3857 	return DP_TEST_ACK;
3858 }
3859 
intel_dp_autotest_edid(struct intel_dp * intel_dp)3860 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3861 {
3862 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3863 	u8 test_result = DP_TEST_ACK;
3864 	struct intel_connector *intel_connector = intel_dp->attached_connector;
3865 	struct drm_connector *connector = &intel_connector->base;
3866 
3867 	if (intel_connector->detect_edid == NULL ||
3868 	    connector->edid_corrupt ||
3869 	    intel_dp->aux.i2c_defer_count > 6) {
3870 		/* Check EDID read for NACKs, DEFERs and corruption
3871 		 * (DP CTS 1.2 Core r1.1)
3872 		 *    4.2.2.4 : Failed EDID read, I2C_NAK
3873 		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
3874 		 *    4.2.2.6 : EDID corruption detected
3875 		 * Use failsafe mode for all cases
3876 		 */
3877 		if (intel_dp->aux.i2c_nack_count > 0 ||
3878 			intel_dp->aux.i2c_defer_count > 0)
3879 			drm_dbg_kms(&i915->drm,
3880 				    "EDID read had %d NACKs, %d DEFERs\n",
3881 				    intel_dp->aux.i2c_nack_count,
3882 				    intel_dp->aux.i2c_defer_count);
3883 		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3884 	} else {
3885 		/* FIXME: Get rid of drm_edid_raw() */
3886 		const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
3887 
3888 		/* We have to write the checksum of the last block read */
3889 		block += block->extensions;
3890 
3891 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3892 				       block->checksum) <= 0)
3893 			drm_dbg_kms(&i915->drm,
3894 				    "Failed to write EDID checksum\n");
3895 
3896 		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3897 		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3898 	}
3899 
3900 	/* Set test active flag here so userspace doesn't interrupt things */
3901 	intel_dp->compliance.test_active = true;
3902 
3903 	return test_result;
3904 }
3905 
intel_dp_phy_pattern_update(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3906 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3907 					const struct intel_crtc_state *crtc_state)
3908 {
3909 	struct drm_i915_private *dev_priv =
3910 			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3911 	struct drm_dp_phy_test_params *data =
3912 			&intel_dp->compliance.test_data.phytest;
3913 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3914 	enum pipe pipe = crtc->pipe;
3915 	u32 pattern_val;
3916 
3917 	switch (data->phy_pattern) {
3918 	case DP_PHY_TEST_PATTERN_NONE:
3919 		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3920 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3921 		break;
3922 	case DP_PHY_TEST_PATTERN_D10_2:
3923 		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3924 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3925 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3926 		break;
3927 	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3928 		drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3929 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3930 			       DDI_DP_COMP_CTL_ENABLE |
3931 			       DDI_DP_COMP_CTL_SCRAMBLED_0);
3932 		break;
3933 	case DP_PHY_TEST_PATTERN_PRBS7:
3934 		drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3935 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3936 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3937 		break;
3938 	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3939 		/*
3940 		 * FIXME: Ideally pattern should come from DPCD 0x250. As
3941 		 * current firmware of DPR-100 could not set it, so hardcoding
3942 		 * now for complaince test.
3943 		 */
3944 		drm_dbg_kms(&dev_priv->drm,
3945 			    "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3946 		pattern_val = 0x3e0f83e0;
3947 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3948 		pattern_val = 0x0f83e0f8;
3949 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3950 		pattern_val = 0x0000f83e;
3951 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3952 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3953 			       DDI_DP_COMP_CTL_ENABLE |
3954 			       DDI_DP_COMP_CTL_CUSTOM80);
3955 		break;
3956 	case DP_PHY_TEST_PATTERN_CP2520:
3957 		/*
3958 		 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3959 		 * current firmware of DPR-100 could not set it, so hardcoding
3960 		 * now for complaince test.
3961 		 */
3962 		drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3963 		pattern_val = 0xFB;
3964 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3965 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3966 			       pattern_val);
3967 		break;
3968 	default:
3969 		WARN(1, "Invalid Phy Test Pattern\n");
3970 	}
3971 }
3972 
intel_dp_process_phy_request(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3973 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3974 					 const struct intel_crtc_state *crtc_state)
3975 {
3976 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3977 	struct drm_dp_phy_test_params *data =
3978 		&intel_dp->compliance.test_data.phytest;
3979 	u8 link_status[DP_LINK_STATUS_SIZE];
3980 
3981 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3982 					     link_status) < 0) {
3983 		drm_dbg_kms(&i915->drm, "failed to get link status\n");
3984 		return;
3985 	}
3986 
3987 	/* retrieve vswing & pre-emphasis setting */
3988 	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3989 				  link_status);
3990 
3991 	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3992 
3993 	intel_dp_phy_pattern_update(intel_dp, crtc_state);
3994 
3995 	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3996 			  intel_dp->train_set, crtc_state->lane_count);
3997 
3998 	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3999 				    intel_dp->dpcd[DP_DPCD_REV]);
4000 }
4001 
intel_dp_autotest_phy_pattern(struct intel_dp * intel_dp)4002 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4003 {
4004 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4005 	struct drm_dp_phy_test_params *data =
4006 		&intel_dp->compliance.test_data.phytest;
4007 
4008 	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4009 		drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4010 		return DP_TEST_NAK;
4011 	}
4012 
4013 	/* Set test active flag here so userspace doesn't interrupt things */
4014 	intel_dp->compliance.test_active = true;
4015 
4016 	return DP_TEST_ACK;
4017 }
4018 
intel_dp_handle_test_request(struct intel_dp * intel_dp)4019 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4020 {
4021 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4022 	u8 response = DP_TEST_NAK;
4023 	u8 request = 0;
4024 	int status;
4025 
4026 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4027 	if (status <= 0) {
4028 		drm_dbg_kms(&i915->drm,
4029 			    "Could not read test request from sink\n");
4030 		goto update_status;
4031 	}
4032 
4033 	switch (request) {
4034 	case DP_TEST_LINK_TRAINING:
4035 		drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4036 		response = intel_dp_autotest_link_training(intel_dp);
4037 		break;
4038 	case DP_TEST_LINK_VIDEO_PATTERN:
4039 		drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4040 		response = intel_dp_autotest_video_pattern(intel_dp);
4041 		break;
4042 	case DP_TEST_LINK_EDID_READ:
4043 		drm_dbg_kms(&i915->drm, "EDID test requested\n");
4044 		response = intel_dp_autotest_edid(intel_dp);
4045 		break;
4046 	case DP_TEST_LINK_PHY_TEST_PATTERN:
4047 		drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4048 		response = intel_dp_autotest_phy_pattern(intel_dp);
4049 		break;
4050 	default:
4051 		drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4052 			    request);
4053 		break;
4054 	}
4055 
4056 	if (response & DP_TEST_ACK)
4057 		intel_dp->compliance.test_type = request;
4058 
4059 update_status:
4060 	status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4061 	if (status <= 0)
4062 		drm_dbg_kms(&i915->drm,
4063 			    "Could not write test response to sink\n");
4064 }
4065 
intel_dp_link_ok(struct intel_dp * intel_dp,u8 link_status[DP_LINK_STATUS_SIZE])4066 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4067 			     u8 link_status[DP_LINK_STATUS_SIZE])
4068 {
4069 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4070 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4071 	bool uhbr = intel_dp->link_rate >= 1000000;
4072 	bool ok;
4073 
4074 	if (uhbr)
4075 		ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4076 							  intel_dp->lane_count);
4077 	else
4078 		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4079 
4080 	if (ok)
4081 		return true;
4082 
4083 	intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4084 	drm_dbg_kms(&i915->drm,
4085 		    "[ENCODER:%d:%s] %s link not ok, retraining\n",
4086 		    encoder->base.base.id, encoder->base.name,
4087 		    uhbr ? "128b/132b" : "8b/10b");
4088 
4089 	return false;
4090 }
4091 
4092 static void
intel_dp_mst_hpd_irq(struct intel_dp * intel_dp,u8 * esi,u8 * ack)4093 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4094 {
4095 	bool handled = false;
4096 
4097 	drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4098 
4099 	if (esi[1] & DP_CP_IRQ) {
4100 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4101 		ack[1] |= DP_CP_IRQ;
4102 	}
4103 }
4104 
intel_dp_mst_link_status(struct intel_dp * intel_dp)4105 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4106 {
4107 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4108 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4109 	u8 link_status[DP_LINK_STATUS_SIZE] = {};
4110 	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4111 
4112 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4113 			     esi_link_status_size) != esi_link_status_size) {
4114 		drm_err(&i915->drm,
4115 			"[ENCODER:%d:%s] Failed to read link status\n",
4116 			encoder->base.base.id, encoder->base.name);
4117 		return false;
4118 	}
4119 
4120 	return intel_dp_link_ok(intel_dp, link_status);
4121 }
4122 
4123 /**
4124  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4125  * @intel_dp: Intel DP struct
4126  *
4127  * Read any pending MST interrupts, call MST core to handle these and ack the
4128  * interrupts. Check if the main and AUX link state is ok.
4129  *
4130  * Returns:
4131  * - %true if pending interrupts were serviced (or no interrupts were
4132  *   pending) w/o detecting an error condition.
4133  * - %false if an error condition - like AUX failure or a loss of link - is
4134  *   detected, which needs servicing from the hotplug work.
4135  */
4136 static bool
intel_dp_check_mst_status(struct intel_dp * intel_dp)4137 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4138 {
4139 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4140 	bool link_ok = true;
4141 
4142 	drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4143 
4144 	for (;;) {
4145 		u8 esi[4] = {};
4146 		u8 ack[4] = {};
4147 
4148 		if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4149 			drm_dbg_kms(&i915->drm,
4150 				    "failed to get ESI - device may have failed\n");
4151 			link_ok = false;
4152 
4153 			break;
4154 		}
4155 
4156 		drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4157 
4158 		if (intel_dp->active_mst_links > 0 && link_ok &&
4159 		    esi[3] & LINK_STATUS_CHANGED) {
4160 			if (!intel_dp_mst_link_status(intel_dp))
4161 				link_ok = false;
4162 			ack[3] |= LINK_STATUS_CHANGED;
4163 		}
4164 
4165 		intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4166 
4167 		if (!memchr_inv(ack, 0, sizeof(ack)))
4168 			break;
4169 
4170 		if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4171 			drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4172 
4173 		if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4174 			drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4175 	}
4176 
4177 	return link_ok;
4178 }
4179 
4180 static void
intel_dp_handle_hdmi_link_status_change(struct intel_dp * intel_dp)4181 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4182 {
4183 	bool is_active;
4184 	u8 buf = 0;
4185 
4186 	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4187 	if (intel_dp->frl.is_trained && !is_active) {
4188 		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4189 			return;
4190 
4191 		buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4192 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4193 			return;
4194 
4195 		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4196 
4197 		intel_dp->frl.is_trained = false;
4198 
4199 		/* Restart FRL training or fall back to TMDS mode */
4200 		intel_dp_check_frl_training(intel_dp);
4201 	}
4202 }
4203 
4204 static bool
intel_dp_needs_link_retrain(struct intel_dp * intel_dp)4205 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4206 {
4207 	u8 link_status[DP_LINK_STATUS_SIZE];
4208 
4209 	if (!intel_dp->link_trained)
4210 		return false;
4211 
4212 	/*
4213 	 * While PSR source HW is enabled, it will control main-link sending
4214 	 * frames, enabling and disabling it so trying to do a retrain will fail
4215 	 * as the link would or not be on or it could mix training patterns
4216 	 * and frame data at the same time causing retrain to fail.
4217 	 * Also when exiting PSR, HW will retrain the link anyways fixing
4218 	 * any link status error.
4219 	 */
4220 	if (intel_psr_enabled(intel_dp))
4221 		return false;
4222 
4223 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4224 					     link_status) < 0)
4225 		return false;
4226 
4227 	/*
4228 	 * Validate the cached values of intel_dp->link_rate and
4229 	 * intel_dp->lane_count before attempting to retrain.
4230 	 *
4231 	 * FIXME would be nice to user the crtc state here, but since
4232 	 * we need to call this from the short HPD handler that seems
4233 	 * a bit hard.
4234 	 */
4235 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4236 					intel_dp->lane_count))
4237 		return false;
4238 
4239 	/* Retrain if link not ok */
4240 	return !intel_dp_link_ok(intel_dp, link_status);
4241 }
4242 
intel_dp_has_connector(struct intel_dp * intel_dp,const struct drm_connector_state * conn_state)4243 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4244 				   const struct drm_connector_state *conn_state)
4245 {
4246 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4247 	struct intel_encoder *encoder;
4248 	enum pipe pipe;
4249 
4250 	if (!conn_state->best_encoder)
4251 		return false;
4252 
4253 	/* SST */
4254 	encoder = &dp_to_dig_port(intel_dp)->base;
4255 	if (conn_state->best_encoder == &encoder->base)
4256 		return true;
4257 
4258 	/* MST */
4259 	for_each_pipe(i915, pipe) {
4260 		encoder = &intel_dp->mst_encoders[pipe]->base;
4261 		if (conn_state->best_encoder == &encoder->base)
4262 			return true;
4263 	}
4264 
4265 	return false;
4266 }
4267 
intel_dp_get_active_pipes(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u8 * pipe_mask)4268 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
4269 			      struct drm_modeset_acquire_ctx *ctx,
4270 			      u8 *pipe_mask)
4271 {
4272 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4273 	struct drm_connector_list_iter conn_iter;
4274 	struct intel_connector *connector;
4275 	int ret = 0;
4276 
4277 	*pipe_mask = 0;
4278 
4279 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4280 	for_each_intel_connector_iter(connector, &conn_iter) {
4281 		struct drm_connector_state *conn_state =
4282 			connector->base.state;
4283 		struct intel_crtc_state *crtc_state;
4284 		struct intel_crtc *crtc;
4285 
4286 		if (!intel_dp_has_connector(intel_dp, conn_state))
4287 			continue;
4288 
4289 		crtc = to_intel_crtc(conn_state->crtc);
4290 		if (!crtc)
4291 			continue;
4292 
4293 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4294 		if (ret)
4295 			break;
4296 
4297 		crtc_state = to_intel_crtc_state(crtc->base.state);
4298 
4299 		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4300 
4301 		if (!crtc_state->hw.active)
4302 			continue;
4303 
4304 		if (conn_state->commit &&
4305 		    !try_wait_for_completion(&conn_state->commit->hw_done))
4306 			continue;
4307 
4308 		*pipe_mask |= BIT(crtc->pipe);
4309 	}
4310 	drm_connector_list_iter_end(&conn_iter);
4311 
4312 	return ret;
4313 }
4314 
intel_dp_is_connected(struct intel_dp * intel_dp)4315 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4316 {
4317 	struct intel_connector *connector = intel_dp->attached_connector;
4318 
4319 	return connector->base.status == connector_status_connected ||
4320 		intel_dp->is_mst;
4321 }
4322 
intel_dp_retrain_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4323 int intel_dp_retrain_link(struct intel_encoder *encoder,
4324 			  struct drm_modeset_acquire_ctx *ctx)
4325 {
4326 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4327 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4328 	struct intel_crtc *crtc;
4329 	u8 pipe_mask;
4330 	int ret;
4331 
4332 	if (!intel_dp_is_connected(intel_dp))
4333 		return 0;
4334 
4335 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4336 			       ctx);
4337 	if (ret)
4338 		return ret;
4339 
4340 	if (!intel_dp_needs_link_retrain(intel_dp))
4341 		return 0;
4342 
4343 	ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
4344 	if (ret)
4345 		return ret;
4346 
4347 	if (pipe_mask == 0)
4348 		return 0;
4349 
4350 	if (!intel_dp_needs_link_retrain(intel_dp))
4351 		return 0;
4352 
4353 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4354 		    encoder->base.base.id, encoder->base.name);
4355 
4356 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4357 		const struct intel_crtc_state *crtc_state =
4358 			to_intel_crtc_state(crtc->base.state);
4359 
4360 		/* Suppress underruns caused by re-training */
4361 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4362 		if (crtc_state->has_pch_encoder)
4363 			intel_set_pch_fifo_underrun_reporting(dev_priv,
4364 							      intel_crtc_pch_transcoder(crtc), false);
4365 	}
4366 
4367 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4368 		const struct intel_crtc_state *crtc_state =
4369 			to_intel_crtc_state(crtc->base.state);
4370 
4371 		/* retrain on the MST master transcoder */
4372 		if (DISPLAY_VER(dev_priv) >= 12 &&
4373 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4374 		    !intel_dp_mst_is_master_trans(crtc_state))
4375 			continue;
4376 
4377 		intel_dp->link_trained = false;
4378 
4379 		intel_dp_check_frl_training(intel_dp);
4380 		intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4381 		intel_dp_start_link_train(intel_dp, crtc_state);
4382 		intel_dp_stop_link_train(intel_dp, crtc_state);
4383 		break;
4384 	}
4385 
4386 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4387 		const struct intel_crtc_state *crtc_state =
4388 			to_intel_crtc_state(crtc->base.state);
4389 
4390 		/* Keep underrun reporting disabled until things are stable */
4391 		intel_crtc_wait_for_next_vblank(crtc);
4392 
4393 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4394 		if (crtc_state->has_pch_encoder)
4395 			intel_set_pch_fifo_underrun_reporting(dev_priv,
4396 							      intel_crtc_pch_transcoder(crtc), true);
4397 	}
4398 
4399 	return 0;
4400 }
4401 
intel_dp_prep_phy_test(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u8 * pipe_mask)4402 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4403 				  struct drm_modeset_acquire_ctx *ctx,
4404 				  u8 *pipe_mask)
4405 {
4406 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4407 	struct drm_connector_list_iter conn_iter;
4408 	struct intel_connector *connector;
4409 	int ret = 0;
4410 
4411 	*pipe_mask = 0;
4412 
4413 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4414 	for_each_intel_connector_iter(connector, &conn_iter) {
4415 		struct drm_connector_state *conn_state =
4416 			connector->base.state;
4417 		struct intel_crtc_state *crtc_state;
4418 		struct intel_crtc *crtc;
4419 
4420 		if (!intel_dp_has_connector(intel_dp, conn_state))
4421 			continue;
4422 
4423 		crtc = to_intel_crtc(conn_state->crtc);
4424 		if (!crtc)
4425 			continue;
4426 
4427 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4428 		if (ret)
4429 			break;
4430 
4431 		crtc_state = to_intel_crtc_state(crtc->base.state);
4432 
4433 		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4434 
4435 		if (!crtc_state->hw.active)
4436 			continue;
4437 
4438 		if (conn_state->commit &&
4439 		    !try_wait_for_completion(&conn_state->commit->hw_done))
4440 			continue;
4441 
4442 		*pipe_mask |= BIT(crtc->pipe);
4443 	}
4444 	drm_connector_list_iter_end(&conn_iter);
4445 
4446 	return ret;
4447 }
4448 
intel_dp_do_phy_test(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4449 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4450 				struct drm_modeset_acquire_ctx *ctx)
4451 {
4452 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4453 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4454 	struct intel_crtc *crtc;
4455 	u8 pipe_mask;
4456 	int ret;
4457 
4458 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4459 			       ctx);
4460 	if (ret)
4461 		return ret;
4462 
4463 	ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4464 	if (ret)
4465 		return ret;
4466 
4467 	if (pipe_mask == 0)
4468 		return 0;
4469 
4470 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4471 		    encoder->base.base.id, encoder->base.name);
4472 
4473 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4474 		const struct intel_crtc_state *crtc_state =
4475 			to_intel_crtc_state(crtc->base.state);
4476 
4477 		/* test on the MST master transcoder */
4478 		if (DISPLAY_VER(dev_priv) >= 12 &&
4479 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4480 		    !intel_dp_mst_is_master_trans(crtc_state))
4481 			continue;
4482 
4483 		intel_dp_process_phy_request(intel_dp, crtc_state);
4484 		break;
4485 	}
4486 
4487 	return 0;
4488 }
4489 
intel_dp_phy_test(struct intel_encoder * encoder)4490 void intel_dp_phy_test(struct intel_encoder *encoder)
4491 {
4492 	struct drm_modeset_acquire_ctx ctx;
4493 	int ret;
4494 
4495 	drm_modeset_acquire_init(&ctx, 0);
4496 
4497 	for (;;) {
4498 		ret = intel_dp_do_phy_test(encoder, &ctx);
4499 
4500 		if (ret == -EDEADLK) {
4501 			drm_modeset_backoff(&ctx);
4502 			continue;
4503 		}
4504 
4505 		break;
4506 	}
4507 
4508 	drm_modeset_drop_locks(&ctx);
4509 	drm_modeset_acquire_fini(&ctx);
4510 	drm_WARN(encoder->base.dev, ret,
4511 		 "Acquiring modeset locks failed with %i\n", ret);
4512 }
4513 
intel_dp_check_device_service_irq(struct intel_dp * intel_dp)4514 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4515 {
4516 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4517 	u8 val;
4518 
4519 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4520 		return;
4521 
4522 	if (drm_dp_dpcd_readb(&intel_dp->aux,
4523 			      DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4524 		return;
4525 
4526 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4527 
4528 	if (val & DP_AUTOMATED_TEST_REQUEST)
4529 		intel_dp_handle_test_request(intel_dp);
4530 
4531 	if (val & DP_CP_IRQ)
4532 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4533 
4534 	if (val & DP_SINK_SPECIFIC_IRQ)
4535 		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4536 }
4537 
intel_dp_check_link_service_irq(struct intel_dp * intel_dp)4538 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4539 {
4540 	u8 val;
4541 
4542 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4543 		return;
4544 
4545 	if (drm_dp_dpcd_readb(&intel_dp->aux,
4546 			      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4547 		return;
4548 
4549 	if (drm_dp_dpcd_writeb(&intel_dp->aux,
4550 			       DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4551 		return;
4552 
4553 	if (val & HDMI_LINK_STATUS_CHANGED)
4554 		intel_dp_handle_hdmi_link_status_change(intel_dp);
4555 }
4556 
4557 /*
4558  * According to DP spec
4559  * 5.1.2:
4560  *  1. Read DPCD
4561  *  2. Configure link according to Receiver Capabilities
4562  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4563  *  4. Check link status on receipt of hot-plug interrupt
4564  *
4565  * intel_dp_short_pulse -  handles short pulse interrupts
4566  * when full detection is not required.
4567  * Returns %true if short pulse is handled and full detection
4568  * is NOT required and %false otherwise.
4569  */
4570 static bool
intel_dp_short_pulse(struct intel_dp * intel_dp)4571 intel_dp_short_pulse(struct intel_dp *intel_dp)
4572 {
4573 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4574 	u8 old_sink_count = intel_dp->sink_count;
4575 	bool ret;
4576 
4577 	/*
4578 	 * Clearing compliance test variables to allow capturing
4579 	 * of values for next automated test request.
4580 	 */
4581 	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4582 
4583 	/*
4584 	 * Now read the DPCD to see if it's actually running
4585 	 * If the current value of sink count doesn't match with
4586 	 * the value that was stored earlier or dpcd read failed
4587 	 * we need to do full detection
4588 	 */
4589 	ret = intel_dp_get_dpcd(intel_dp);
4590 
4591 	if ((old_sink_count != intel_dp->sink_count) || !ret) {
4592 		/* No need to proceed if we are going to do full detect */
4593 		return false;
4594 	}
4595 
4596 	intel_dp_check_device_service_irq(intel_dp);
4597 	intel_dp_check_link_service_irq(intel_dp);
4598 
4599 	/* Handle CEC interrupts, if any */
4600 	drm_dp_cec_irq(&intel_dp->aux);
4601 
4602 	/* defer to the hotplug work for link retraining if needed */
4603 	if (intel_dp_needs_link_retrain(intel_dp))
4604 		return false;
4605 
4606 	intel_psr_short_pulse(intel_dp);
4607 
4608 	switch (intel_dp->compliance.test_type) {
4609 	case DP_TEST_LINK_TRAINING:
4610 		drm_dbg_kms(&dev_priv->drm,
4611 			    "Link Training Compliance Test requested\n");
4612 		/* Send a Hotplug Uevent to userspace to start modeset */
4613 		drm_kms_helper_hotplug_event(&dev_priv->drm);
4614 		break;
4615 	case DP_TEST_LINK_PHY_TEST_PATTERN:
4616 		drm_dbg_kms(&dev_priv->drm,
4617 			    "PHY test pattern Compliance Test requested\n");
4618 		/*
4619 		 * Schedule long hpd to do the test
4620 		 *
4621 		 * FIXME get rid of the ad-hoc phy test modeset code
4622 		 * and properly incorporate it into the normal modeset.
4623 		 */
4624 		return false;
4625 	}
4626 
4627 	return true;
4628 }
4629 
4630 /* XXX this is probably wrong for multiple downstream ports */
4631 static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp * intel_dp)4632 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4633 {
4634 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4635 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4636 	u8 *dpcd = intel_dp->dpcd;
4637 	u8 type;
4638 
4639 	if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4640 		return connector_status_connected;
4641 
4642 	lspcon_resume(dig_port);
4643 
4644 	if (!intel_dp_get_dpcd(intel_dp))
4645 		return connector_status_disconnected;
4646 
4647 	/* if there's no downstream port, we're done */
4648 	if (!drm_dp_is_branch(dpcd))
4649 		return connector_status_connected;
4650 
4651 	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4652 	if (intel_dp_has_sink_count(intel_dp) &&
4653 	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4654 		return intel_dp->sink_count ?
4655 		connector_status_connected : connector_status_disconnected;
4656 	}
4657 
4658 	if (intel_dp_can_mst(intel_dp))
4659 		return connector_status_connected;
4660 
4661 	/* If no HPD, poke DDC gently */
4662 	if (drm_probe_ddc(&intel_dp->aux.ddc))
4663 		return connector_status_connected;
4664 
4665 	/* Well we tried, say unknown for unreliable port types */
4666 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4667 		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4668 		if (type == DP_DS_PORT_TYPE_VGA ||
4669 		    type == DP_DS_PORT_TYPE_NON_EDID)
4670 			return connector_status_unknown;
4671 	} else {
4672 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4673 			DP_DWN_STRM_PORT_TYPE_MASK;
4674 		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4675 		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
4676 			return connector_status_unknown;
4677 	}
4678 
4679 	/* Anything else is out of spec, warn and ignore */
4680 	drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4681 	return connector_status_disconnected;
4682 }
4683 
4684 static enum drm_connector_status
edp_detect(struct intel_dp * intel_dp)4685 edp_detect(struct intel_dp *intel_dp)
4686 {
4687 	return connector_status_connected;
4688 }
4689 
4690 /*
4691  * intel_digital_port_connected - is the specified port connected?
4692  * @encoder: intel_encoder
4693  *
4694  * In cases where there's a connector physically connected but it can't be used
4695  * by our hardware we also return false, since the rest of the driver should
4696  * pretty much treat the port as disconnected. This is relevant for type-C
4697  * (starting on ICL) where there's ownership involved.
4698  *
4699  * Return %true if port is connected, %false otherwise.
4700  */
intel_digital_port_connected(struct intel_encoder * encoder)4701 bool intel_digital_port_connected(struct intel_encoder *encoder)
4702 {
4703 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4704 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4705 	bool is_connected = false;
4706 	intel_wakeref_t wakeref;
4707 
4708 	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4709 		is_connected = dig_port->connected(encoder);
4710 
4711 	return is_connected;
4712 }
4713 
4714 static const struct drm_edid *
intel_dp_get_edid(struct intel_dp * intel_dp)4715 intel_dp_get_edid(struct intel_dp *intel_dp)
4716 {
4717 	struct intel_connector *connector = intel_dp->attached_connector;
4718 	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
4719 
4720 	/* Use panel fixed edid if we have one */
4721 	if (fixed_edid) {
4722 		/* invalid edid */
4723 		if (IS_ERR(fixed_edid))
4724 			return NULL;
4725 
4726 		return drm_edid_dup(fixed_edid);
4727 	}
4728 
4729 	return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
4730 }
4731 
4732 static void
intel_dp_update_dfp(struct intel_dp * intel_dp,const struct drm_edid * drm_edid)4733 intel_dp_update_dfp(struct intel_dp *intel_dp,
4734 		    const struct drm_edid *drm_edid)
4735 {
4736 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4737 	struct intel_connector *connector = intel_dp->attached_connector;
4738 	const struct edid *edid;
4739 
4740 	/* FIXME: Get rid of drm_edid_raw() */
4741 	edid = drm_edid_raw(drm_edid);
4742 
4743 	intel_dp->dfp.max_bpc =
4744 		drm_dp_downstream_max_bpc(intel_dp->dpcd,
4745 					  intel_dp->downstream_ports, edid);
4746 
4747 	intel_dp->dfp.max_dotclock =
4748 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4749 					       intel_dp->downstream_ports);
4750 
4751 	intel_dp->dfp.min_tmds_clock =
4752 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4753 						 intel_dp->downstream_ports,
4754 						 edid);
4755 	intel_dp->dfp.max_tmds_clock =
4756 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4757 						 intel_dp->downstream_ports,
4758 						 edid);
4759 
4760 	intel_dp->dfp.pcon_max_frl_bw =
4761 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4762 					   intel_dp->downstream_ports);
4763 
4764 	drm_dbg_kms(&i915->drm,
4765 		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4766 		    connector->base.base.id, connector->base.name,
4767 		    intel_dp->dfp.max_bpc,
4768 		    intel_dp->dfp.max_dotclock,
4769 		    intel_dp->dfp.min_tmds_clock,
4770 		    intel_dp->dfp.max_tmds_clock,
4771 		    intel_dp->dfp.pcon_max_frl_bw);
4772 
4773 	intel_dp_get_pcon_dsc_cap(intel_dp);
4774 }
4775 
4776 static bool
intel_dp_can_ycbcr420(struct intel_dp * intel_dp)4777 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
4778 {
4779 	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
4780 	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
4781 		return true;
4782 
4783 	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
4784 	    dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4785 		return true;
4786 
4787 	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
4788 	    dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4789 		return true;
4790 
4791 	return false;
4792 }
4793 
4794 static void
intel_dp_update_420(struct intel_dp * intel_dp)4795 intel_dp_update_420(struct intel_dp *intel_dp)
4796 {
4797 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4798 	struct intel_connector *connector = intel_dp->attached_connector;
4799 
4800 	intel_dp->dfp.ycbcr420_passthrough =
4801 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4802 						  intel_dp->downstream_ports);
4803 	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4804 	intel_dp->dfp.ycbcr_444_to_420 =
4805 		dp_to_dig_port(intel_dp)->lspcon.active ||
4806 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4807 							intel_dp->downstream_ports);
4808 	intel_dp->dfp.rgb_to_ycbcr =
4809 		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4810 							  intel_dp->downstream_ports,
4811 							  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4812 
4813 	connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
4814 
4815 	drm_dbg_kms(&i915->drm,
4816 		    "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4817 		    connector->base.base.id, connector->base.name,
4818 		    str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4819 		    str_yes_no(connector->base.ycbcr_420_allowed),
4820 		    str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4821 }
4822 
4823 static void
intel_dp_set_edid(struct intel_dp * intel_dp)4824 intel_dp_set_edid(struct intel_dp *intel_dp)
4825 {
4826 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4827 	struct intel_connector *connector = intel_dp->attached_connector;
4828 	const struct drm_edid *drm_edid;
4829 	const struct edid *edid;
4830 	bool vrr_capable;
4831 
4832 	intel_dp_unset_edid(intel_dp);
4833 	drm_edid = intel_dp_get_edid(intel_dp);
4834 	connector->detect_edid = drm_edid;
4835 
4836 	/* Below we depend on display info having been updated */
4837 	drm_edid_connector_update(&connector->base, drm_edid);
4838 
4839 	vrr_capable = intel_vrr_is_capable(connector);
4840 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4841 		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4842 	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4843 
4844 	intel_dp_update_dfp(intel_dp, drm_edid);
4845 	intel_dp_update_420(intel_dp);
4846 
4847 	/* FIXME: Get rid of drm_edid_raw() */
4848 	edid = drm_edid_raw(drm_edid);
4849 
4850 	drm_dp_cec_set_edid(&intel_dp->aux, edid);
4851 }
4852 
4853 static void
intel_dp_unset_edid(struct intel_dp * intel_dp)4854 intel_dp_unset_edid(struct intel_dp *intel_dp)
4855 {
4856 	struct intel_connector *connector = intel_dp->attached_connector;
4857 
4858 	drm_dp_cec_unset_edid(&intel_dp->aux);
4859 	drm_edid_free(connector->detect_edid);
4860 	connector->detect_edid = NULL;
4861 
4862 	intel_dp->dfp.max_bpc = 0;
4863 	intel_dp->dfp.max_dotclock = 0;
4864 	intel_dp->dfp.min_tmds_clock = 0;
4865 	intel_dp->dfp.max_tmds_clock = 0;
4866 
4867 	intel_dp->dfp.pcon_max_frl_bw = 0;
4868 
4869 	intel_dp->dfp.ycbcr_444_to_420 = false;
4870 	connector->base.ycbcr_420_allowed = false;
4871 
4872 	drm_connector_set_vrr_capable_property(&connector->base,
4873 					       false);
4874 }
4875 
4876 static int
intel_dp_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)4877 intel_dp_detect(struct drm_connector *connector,
4878 		struct drm_modeset_acquire_ctx *ctx,
4879 		bool force)
4880 {
4881 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
4882 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4883 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4884 	struct intel_encoder *encoder = &dig_port->base;
4885 	enum drm_connector_status status;
4886 
4887 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4888 		    connector->base.id, connector->name);
4889 	drm_WARN_ON(&dev_priv->drm,
4890 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4891 
4892 	if (!INTEL_DISPLAY_ENABLED(dev_priv))
4893 		return connector_status_disconnected;
4894 
4895 	/* Can't disconnect eDP */
4896 	if (intel_dp_is_edp(intel_dp))
4897 		status = edp_detect(intel_dp);
4898 	else if (intel_digital_port_connected(encoder))
4899 		status = intel_dp_detect_dpcd(intel_dp);
4900 	else
4901 		status = connector_status_disconnected;
4902 
4903 	if (status == connector_status_disconnected) {
4904 		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4905 		memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4906 
4907 		if (intel_dp->is_mst) {
4908 			drm_dbg_kms(&dev_priv->drm,
4909 				    "MST device may have disappeared %d vs %d\n",
4910 				    intel_dp->is_mst,
4911 				    intel_dp->mst_mgr.mst_state);
4912 			intel_dp->is_mst = false;
4913 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4914 							intel_dp->is_mst);
4915 		}
4916 
4917 		goto out;
4918 	}
4919 
4920 	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4921 	if (HAS_DSC(dev_priv))
4922 		intel_dp_get_dsc_sink_cap(intel_dp);
4923 
4924 	intel_dp_configure_mst(intel_dp);
4925 
4926 	/*
4927 	 * TODO: Reset link params when switching to MST mode, until MST
4928 	 * supports link training fallback params.
4929 	 */
4930 	if (intel_dp->reset_link_params || intel_dp->is_mst) {
4931 		intel_dp_reset_max_link_params(intel_dp);
4932 		intel_dp->reset_link_params = false;
4933 	}
4934 
4935 	intel_dp_print_rates(intel_dp);
4936 
4937 	if (intel_dp->is_mst) {
4938 		/*
4939 		 * If we are in MST mode then this connector
4940 		 * won't appear connected or have anything
4941 		 * with EDID on it
4942 		 */
4943 		status = connector_status_disconnected;
4944 		goto out;
4945 	}
4946 
4947 	/*
4948 	 * Some external monitors do not signal loss of link synchronization
4949 	 * with an IRQ_HPD, so force a link status check.
4950 	 */
4951 	if (!intel_dp_is_edp(intel_dp)) {
4952 		int ret;
4953 
4954 		ret = intel_dp_retrain_link(encoder, ctx);
4955 		if (ret)
4956 			return ret;
4957 	}
4958 
4959 	/*
4960 	 * Clearing NACK and defer counts to get their exact values
4961 	 * while reading EDID which are required by Compliance tests
4962 	 * 4.2.2.4 and 4.2.2.5
4963 	 */
4964 	intel_dp->aux.i2c_nack_count = 0;
4965 	intel_dp->aux.i2c_defer_count = 0;
4966 
4967 	intel_dp_set_edid(intel_dp);
4968 	if (intel_dp_is_edp(intel_dp) ||
4969 	    to_intel_connector(connector)->detect_edid)
4970 		status = connector_status_connected;
4971 
4972 	intel_dp_check_device_service_irq(intel_dp);
4973 
4974 out:
4975 	if (status != connector_status_connected && !intel_dp->is_mst)
4976 		intel_dp_unset_edid(intel_dp);
4977 
4978 	/*
4979 	 * Make sure the refs for power wells enabled during detect are
4980 	 * dropped to avoid a new detect cycle triggered by HPD polling.
4981 	 */
4982 	intel_display_power_flush_work(dev_priv);
4983 
4984 	if (!intel_dp_is_edp(intel_dp))
4985 		drm_dp_set_subconnector_property(connector,
4986 						 status,
4987 						 intel_dp->dpcd,
4988 						 intel_dp->downstream_ports);
4989 	return status;
4990 }
4991 
4992 static void
intel_dp_force(struct drm_connector * connector)4993 intel_dp_force(struct drm_connector *connector)
4994 {
4995 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4996 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4997 	struct intel_encoder *intel_encoder = &dig_port->base;
4998 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4999 	enum intel_display_power_domain aux_domain =
5000 		intel_aux_power_domain(dig_port);
5001 	intel_wakeref_t wakeref;
5002 
5003 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5004 		    connector->base.id, connector->name);
5005 	intel_dp_unset_edid(intel_dp);
5006 
5007 	if (connector->status != connector_status_connected)
5008 		return;
5009 
5010 	wakeref = intel_display_power_get(dev_priv, aux_domain);
5011 
5012 	intel_dp_set_edid(intel_dp);
5013 
5014 	intel_display_power_put(dev_priv, aux_domain, wakeref);
5015 }
5016 
intel_dp_get_modes(struct drm_connector * connector)5017 static int intel_dp_get_modes(struct drm_connector *connector)
5018 {
5019 	struct intel_connector *intel_connector = to_intel_connector(connector);
5020 	int num_modes;
5021 
5022 	/* drm_edid_connector_update() done in ->detect() or ->force() */
5023 	num_modes = drm_edid_connector_add_modes(connector);
5024 
5025 	/* Also add fixed mode, which may or may not be present in EDID */
5026 	if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5027 		num_modes += intel_panel_get_modes(intel_connector);
5028 
5029 	if (num_modes)
5030 		return num_modes;
5031 
5032 	if (!intel_connector->detect_edid) {
5033 		struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5034 		struct drm_display_mode *mode;
5035 
5036 		mode = drm_dp_downstream_mode(connector->dev,
5037 					      intel_dp->dpcd,
5038 					      intel_dp->downstream_ports);
5039 		if (mode) {
5040 			drm_mode_probed_add(connector, mode);
5041 			num_modes++;
5042 		}
5043 	}
5044 
5045 	return num_modes;
5046 }
5047 
5048 static int
intel_dp_connector_register(struct drm_connector * connector)5049 intel_dp_connector_register(struct drm_connector *connector)
5050 {
5051 	struct drm_i915_private *i915 = to_i915(connector->dev);
5052 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5053 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5054 	struct intel_lspcon *lspcon = &dig_port->lspcon;
5055 	int ret;
5056 
5057 	ret = intel_connector_register(connector);
5058 	if (ret)
5059 		return ret;
5060 
5061 	drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5062 		    intel_dp->aux.name, connector->kdev->kobj.name);
5063 
5064 	intel_dp->aux.dev = connector->kdev;
5065 	ret = drm_dp_aux_register(&intel_dp->aux);
5066 	if (!ret)
5067 		drm_dp_cec_register_connector(&intel_dp->aux, connector);
5068 
5069 	if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5070 		return ret;
5071 
5072 	/*
5073 	 * ToDo: Clean this up to handle lspcon init and resume more
5074 	 * efficiently and streamlined.
5075 	 */
5076 	if (lspcon_init(dig_port)) {
5077 		lspcon_detect_hdr_capability(lspcon);
5078 		if (lspcon->hdr_supported)
5079 			drm_connector_attach_hdr_output_metadata_property(connector);
5080 	}
5081 
5082 	return ret;
5083 }
5084 
5085 static void
intel_dp_connector_unregister(struct drm_connector * connector)5086 intel_dp_connector_unregister(struct drm_connector *connector)
5087 {
5088 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5089 
5090 	drm_dp_cec_unregister_connector(&intel_dp->aux);
5091 	drm_dp_aux_unregister(&intel_dp->aux);
5092 	intel_connector_unregister(connector);
5093 }
5094 
intel_dp_encoder_flush_work(struct drm_encoder * encoder)5095 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5096 {
5097 	struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5098 	struct intel_dp *intel_dp = &dig_port->dp;
5099 
5100 	intel_dp_mst_encoder_cleanup(dig_port);
5101 
5102 	intel_pps_vdd_off_sync(intel_dp);
5103 
5104 	/*
5105 	 * Ensure power off delay is respected on module remove, so that we can
5106 	 * reduce delays at driver probe. See pps_init_timestamps().
5107 	 */
5108 	intel_pps_wait_power_cycle(intel_dp);
5109 
5110 	intel_dp_aux_fini(intel_dp);
5111 }
5112 
intel_dp_encoder_suspend(struct intel_encoder * intel_encoder)5113 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5114 {
5115 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5116 
5117 	intel_pps_vdd_off_sync(intel_dp);
5118 }
5119 
intel_dp_encoder_shutdown(struct intel_encoder * intel_encoder)5120 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5121 {
5122 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5123 
5124 	intel_pps_wait_power_cycle(intel_dp);
5125 }
5126 
intel_modeset_tile_group(struct intel_atomic_state * state,int tile_group_id)5127 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5128 				    int tile_group_id)
5129 {
5130 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5131 	struct drm_connector_list_iter conn_iter;
5132 	struct drm_connector *connector;
5133 	int ret = 0;
5134 
5135 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5136 	drm_for_each_connector_iter(connector, &conn_iter) {
5137 		struct drm_connector_state *conn_state;
5138 		struct intel_crtc_state *crtc_state;
5139 		struct intel_crtc *crtc;
5140 
5141 		if (!connector->has_tile ||
5142 		    connector->tile_group->id != tile_group_id)
5143 			continue;
5144 
5145 		conn_state = drm_atomic_get_connector_state(&state->base,
5146 							    connector);
5147 		if (IS_ERR(conn_state)) {
5148 			ret = PTR_ERR(conn_state);
5149 			break;
5150 		}
5151 
5152 		crtc = to_intel_crtc(conn_state->crtc);
5153 
5154 		if (!crtc)
5155 			continue;
5156 
5157 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5158 		crtc_state->uapi.mode_changed = true;
5159 
5160 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5161 		if (ret)
5162 			break;
5163 	}
5164 	drm_connector_list_iter_end(&conn_iter);
5165 
5166 	return ret;
5167 }
5168 
intel_modeset_affected_transcoders(struct intel_atomic_state * state,u8 transcoders)5169 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5170 {
5171 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5172 	struct intel_crtc *crtc;
5173 
5174 	if (transcoders == 0)
5175 		return 0;
5176 
5177 	for_each_intel_crtc(&dev_priv->drm, crtc) {
5178 		struct intel_crtc_state *crtc_state;
5179 		int ret;
5180 
5181 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5182 		if (IS_ERR(crtc_state))
5183 			return PTR_ERR(crtc_state);
5184 
5185 		if (!crtc_state->hw.enable)
5186 			continue;
5187 
5188 		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5189 			continue;
5190 
5191 		crtc_state->uapi.mode_changed = true;
5192 
5193 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5194 		if (ret)
5195 			return ret;
5196 
5197 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5198 		if (ret)
5199 			return ret;
5200 
5201 		transcoders &= ~BIT(crtc_state->cpu_transcoder);
5202 	}
5203 
5204 	drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5205 
5206 	return 0;
5207 }
5208 
intel_modeset_synced_crtcs(struct intel_atomic_state * state,struct drm_connector * connector)5209 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5210 				      struct drm_connector *connector)
5211 {
5212 	const struct drm_connector_state *old_conn_state =
5213 		drm_atomic_get_old_connector_state(&state->base, connector);
5214 	const struct intel_crtc_state *old_crtc_state;
5215 	struct intel_crtc *crtc;
5216 	u8 transcoders;
5217 
5218 	crtc = to_intel_crtc(old_conn_state->crtc);
5219 	if (!crtc)
5220 		return 0;
5221 
5222 	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5223 
5224 	if (!old_crtc_state->hw.active)
5225 		return 0;
5226 
5227 	transcoders = old_crtc_state->sync_mode_slaves_mask;
5228 	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5229 		transcoders |= BIT(old_crtc_state->master_transcoder);
5230 
5231 	return intel_modeset_affected_transcoders(state,
5232 						  transcoders);
5233 }
5234 
intel_dp_connector_atomic_check(struct drm_connector * conn,struct drm_atomic_state * _state)5235 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5236 					   struct drm_atomic_state *_state)
5237 {
5238 	struct drm_i915_private *dev_priv = to_i915(conn->dev);
5239 	struct intel_atomic_state *state = to_intel_atomic_state(_state);
5240 	struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
5241 	struct intel_connector *intel_conn = to_intel_connector(conn);
5242 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
5243 	int ret;
5244 
5245 	ret = intel_digital_connector_atomic_check(conn, &state->base);
5246 	if (ret)
5247 		return ret;
5248 
5249 	if (intel_dp_mst_source_support(intel_dp)) {
5250 		ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
5251 		if (ret)
5252 			return ret;
5253 	}
5254 
5255 	/*
5256 	 * We don't enable port sync on BDW due to missing w/as and
5257 	 * due to not having adjusted the modeset sequence appropriately.
5258 	 */
5259 	if (DISPLAY_VER(dev_priv) < 9)
5260 		return 0;
5261 
5262 	if (!intel_connector_needs_modeset(state, conn))
5263 		return 0;
5264 
5265 	if (conn->has_tile) {
5266 		ret = intel_modeset_tile_group(state, conn->tile_group->id);
5267 		if (ret)
5268 			return ret;
5269 	}
5270 
5271 	return intel_modeset_synced_crtcs(state, conn);
5272 }
5273 
intel_dp_oob_hotplug_event(struct drm_connector * connector)5274 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5275 {
5276 	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5277 	struct drm_i915_private *i915 = to_i915(connector->dev);
5278 
5279 	spin_lock_irq(&i915->irq_lock);
5280 	i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
5281 	spin_unlock_irq(&i915->irq_lock);
5282 	queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0);
5283 }
5284 
5285 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5286 	.force = intel_dp_force,
5287 	.fill_modes = drm_helper_probe_single_connector_modes,
5288 	.atomic_get_property = intel_digital_connector_atomic_get_property,
5289 	.atomic_set_property = intel_digital_connector_atomic_set_property,
5290 	.late_register = intel_dp_connector_register,
5291 	.early_unregister = intel_dp_connector_unregister,
5292 	.destroy = intel_connector_destroy,
5293 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5294 	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
5295 	.oob_hotplug_event = intel_dp_oob_hotplug_event,
5296 };
5297 
5298 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5299 	.detect_ctx = intel_dp_detect,
5300 	.get_modes = intel_dp_get_modes,
5301 	.mode_valid = intel_dp_mode_valid,
5302 	.atomic_check = intel_dp_connector_atomic_check,
5303 };
5304 
5305 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port * dig_port,bool long_hpd)5306 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5307 {
5308 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5309 	struct intel_dp *intel_dp = &dig_port->dp;
5310 
5311 	if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5312 	    (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5313 		/*
5314 		 * vdd off can generate a long/short pulse on eDP which
5315 		 * would require vdd on to handle it, and thus we
5316 		 * would end up in an endless cycle of
5317 		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5318 		 */
5319 		drm_dbg_kms(&i915->drm,
5320 			    "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5321 			    long_hpd ? "long" : "short",
5322 			    dig_port->base.base.base.id,
5323 			    dig_port->base.base.name);
5324 		return IRQ_HANDLED;
5325 	}
5326 
5327 	drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5328 		    dig_port->base.base.base.id,
5329 		    dig_port->base.base.name,
5330 		    long_hpd ? "long" : "short");
5331 
5332 	if (long_hpd) {
5333 		intel_dp->reset_link_params = true;
5334 		return IRQ_NONE;
5335 	}
5336 
5337 	if (intel_dp->is_mst) {
5338 		if (!intel_dp_check_mst_status(intel_dp))
5339 			return IRQ_NONE;
5340 	} else if (!intel_dp_short_pulse(intel_dp)) {
5341 		return IRQ_NONE;
5342 	}
5343 
5344 	return IRQ_HANDLED;
5345 }
5346 
_intel_dp_is_port_edp(struct drm_i915_private * dev_priv,const struct intel_bios_encoder_data * devdata,enum port port)5347 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
5348 				  const struct intel_bios_encoder_data *devdata,
5349 				  enum port port)
5350 {
5351 	/*
5352 	 * eDP not supported on g4x. so bail out early just
5353 	 * for a bit extra safety in case the VBT is bonkers.
5354 	 */
5355 	if (DISPLAY_VER(dev_priv) < 5)
5356 		return false;
5357 
5358 	if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5359 		return true;
5360 
5361 	return devdata && intel_bios_encoder_supports_edp(devdata);
5362 }
5363 
intel_dp_is_port_edp(struct drm_i915_private * i915,enum port port)5364 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
5365 {
5366 	const struct intel_bios_encoder_data *devdata =
5367 		intel_bios_encoder_data_lookup(i915, port);
5368 
5369 	return _intel_dp_is_port_edp(i915, devdata, port);
5370 }
5371 
5372 static bool
has_gamut_metadata_dip(struct intel_encoder * encoder)5373 has_gamut_metadata_dip(struct intel_encoder *encoder)
5374 {
5375 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5376 	enum port port = encoder->port;
5377 
5378 	if (intel_bios_encoder_is_lspcon(encoder->devdata))
5379 		return false;
5380 
5381 	if (DISPLAY_VER(i915) >= 11)
5382 		return true;
5383 
5384 	if (port == PORT_A)
5385 		return false;
5386 
5387 	if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5388 	    DISPLAY_VER(i915) >= 9)
5389 		return true;
5390 
5391 	return false;
5392 }
5393 
5394 static void
intel_dp_add_properties(struct intel_dp * intel_dp,struct drm_connector * connector)5395 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5396 {
5397 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
5398 	enum port port = dp_to_dig_port(intel_dp)->base.port;
5399 
5400 	if (!intel_dp_is_edp(intel_dp))
5401 		drm_connector_attach_dp_subconnector_property(connector);
5402 
5403 	if (!IS_G4X(dev_priv) && port != PORT_A)
5404 		intel_attach_force_audio_property(connector);
5405 
5406 	intel_attach_broadcast_rgb_property(connector);
5407 	if (HAS_GMCH(dev_priv))
5408 		drm_connector_attach_max_bpc_property(connector, 6, 10);
5409 	else if (DISPLAY_VER(dev_priv) >= 5)
5410 		drm_connector_attach_max_bpc_property(connector, 6, 12);
5411 
5412 	/* Register HDMI colorspace for case of lspcon */
5413 	if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
5414 		drm_connector_attach_content_type_property(connector);
5415 		intel_attach_hdmi_colorspace_property(connector);
5416 	} else {
5417 		intel_attach_dp_colorspace_property(connector);
5418 	}
5419 
5420 	if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
5421 		drm_connector_attach_hdr_output_metadata_property(connector);
5422 
5423 	if (HAS_VRR(dev_priv))
5424 		drm_connector_attach_vrr_capable_property(connector);
5425 }
5426 
5427 static void
intel_edp_add_properties(struct intel_dp * intel_dp)5428 intel_edp_add_properties(struct intel_dp *intel_dp)
5429 {
5430 	struct intel_connector *connector = intel_dp->attached_connector;
5431 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
5432 	const struct drm_display_mode *fixed_mode =
5433 		intel_panel_preferred_fixed_mode(connector);
5434 
5435 	intel_attach_scaling_mode_property(&connector->base);
5436 
5437 	drm_connector_set_panel_orientation_with_quirk(&connector->base,
5438 						       i915->display.vbt.orientation,
5439 						       fixed_mode->hdisplay,
5440 						       fixed_mode->vdisplay);
5441 }
5442 
intel_edp_backlight_setup(struct intel_dp * intel_dp,struct intel_connector * connector)5443 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
5444 				      struct intel_connector *connector)
5445 {
5446 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5447 	enum pipe pipe = INVALID_PIPE;
5448 
5449 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
5450 		/*
5451 		 * Figure out the current pipe for the initial backlight setup.
5452 		 * If the current pipe isn't valid, try the PPS pipe, and if that
5453 		 * fails just assume pipe A.
5454 		 */
5455 		pipe = vlv_active_pipe(intel_dp);
5456 
5457 		if (pipe != PIPE_A && pipe != PIPE_B)
5458 			pipe = intel_dp->pps.pps_pipe;
5459 
5460 		if (pipe != PIPE_A && pipe != PIPE_B)
5461 			pipe = PIPE_A;
5462 	}
5463 
5464 	intel_backlight_setup(connector, pipe);
5465 }
5466 
intel_edp_init_connector(struct intel_dp * intel_dp,struct intel_connector * intel_connector)5467 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5468 				     struct intel_connector *intel_connector)
5469 {
5470 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5471 	struct drm_connector *connector = &intel_connector->base;
5472 	struct drm_display_mode *fixed_mode;
5473 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5474 	bool has_dpcd;
5475 	const struct drm_edid *drm_edid;
5476 
5477 	if (!intel_dp_is_edp(intel_dp))
5478 		return true;
5479 
5480 	/*
5481 	 * On IBX/CPT we may get here with LVDS already registered. Since the
5482 	 * driver uses the only internal power sequencer available for both
5483 	 * eDP and LVDS bail out early in this case to prevent interfering
5484 	 * with an already powered-on LVDS power sequencer.
5485 	 */
5486 	if (intel_get_lvds_encoder(dev_priv)) {
5487 		drm_WARN_ON(&dev_priv->drm,
5488 			    !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5489 		drm_info(&dev_priv->drm,
5490 			 "LVDS was detected, not registering eDP\n");
5491 
5492 		return false;
5493 	}
5494 
5495 	intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
5496 				    encoder->devdata);
5497 
5498 	if (!intel_pps_init(intel_dp)) {
5499 		drm_info(&dev_priv->drm,
5500 			 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
5501 			 encoder->base.base.id, encoder->base.name);
5502 		/*
5503 		 * The BIOS may have still enabled VDD on the PPS even
5504 		 * though it's unusable. Make sure we turn it back off
5505 		 * and to release the power domain references/etc.
5506 		 */
5507 		goto out_vdd_off;
5508 	}
5509 
5510 	/*
5511 	 * Enable HPD sense for live status check.
5512 	 * intel_hpd_irq_setup() will turn it off again
5513 	 * if it's no longer needed later.
5514 	 *
5515 	 * The DPCD probe below will make sure VDD is on.
5516 	 */
5517 	intel_hpd_enable_detection(encoder);
5518 
5519 	/* Cache DPCD and EDID for edp. */
5520 	has_dpcd = intel_edp_init_dpcd(intel_dp);
5521 
5522 	if (!has_dpcd) {
5523 		/* if this fails, presume the device is a ghost */
5524 		drm_info(&dev_priv->drm,
5525 			 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
5526 			 encoder->base.base.id, encoder->base.name);
5527 		goto out_vdd_off;
5528 	}
5529 
5530 	/*
5531 	 * VBT and straps are liars. Also check HPD as that seems
5532 	 * to be the most reliable piece of information available.
5533 	 *
5534 	 * ... expect on devices that forgot to hook HPD up for eDP
5535 	 * (eg. Acer Chromebook C710), so we'll check it only if multiple
5536 	 * ports are attempting to use the same AUX CH, according to VBT.
5537 	 */
5538 	if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
5539 		/*
5540 		 * If this fails, presume the DPCD answer came
5541 		 * from some other port using the same AUX CH.
5542 		 *
5543 		 * FIXME maybe cleaner to check this before the
5544 		 * DPCD read? Would need sort out the VDD handling...
5545 		 */
5546 		if (!intel_digital_port_connected(encoder)) {
5547 			drm_info(&dev_priv->drm,
5548 				 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
5549 				 encoder->base.base.id, encoder->base.name);
5550 			goto out_vdd_off;
5551 		}
5552 
5553 		/*
5554 		 * Unfortunately even the HPD based detection fails on
5555 		 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
5556 		 * back to checking for a VGA branch device. Only do this
5557 		 * on known affected platforms to minimize false positives.
5558 		 */
5559 		if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
5560 		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
5561 		    DP_DWN_STRM_PORT_TYPE_ANALOG) {
5562 			drm_info(&dev_priv->drm,
5563 				 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
5564 				 encoder->base.base.id, encoder->base.name);
5565 			goto out_vdd_off;
5566 		}
5567 	}
5568 
5569 	mutex_lock(&dev_priv->drm.mode_config.mutex);
5570 	drm_edid = drm_edid_read_ddc(connector, &intel_dp->aux.ddc);
5571 	if (!drm_edid) {
5572 		/* Fallback to EDID from ACPI OpRegion, if any */
5573 		drm_edid = intel_opregion_get_edid(intel_connector);
5574 		if (drm_edid)
5575 			drm_dbg_kms(&dev_priv->drm,
5576 				    "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5577 				    connector->base.id, connector->name);
5578 	}
5579 	if (drm_edid) {
5580 		if (drm_edid_connector_update(connector, drm_edid) ||
5581 		    !drm_edid_connector_add_modes(connector)) {
5582 			drm_edid_connector_update(connector, NULL);
5583 			drm_edid_free(drm_edid);
5584 			drm_edid = ERR_PTR(-EINVAL);
5585 		}
5586 	} else {
5587 		drm_edid = ERR_PTR(-ENOENT);
5588 	}
5589 
5590 	intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
5591 				   IS_ERR(drm_edid) ? NULL : drm_edid);
5592 
5593 	intel_panel_add_edid_fixed_modes(intel_connector, true);
5594 
5595 	/* MSO requires information from the EDID */
5596 	intel_edp_mso_init(intel_dp);
5597 
5598 	/* multiply the mode clock and horizontal timings for MSO */
5599 	list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5600 		intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5601 
5602 	/* fallback to VBT if available for eDP */
5603 	if (!intel_panel_preferred_fixed_mode(intel_connector))
5604 		intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5605 
5606 	mutex_unlock(&dev_priv->drm.mode_config.mutex);
5607 
5608 	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
5609 		drm_info(&dev_priv->drm,
5610 			 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
5611 			 encoder->base.base.id, encoder->base.name);
5612 		goto out_vdd_off;
5613 	}
5614 
5615 	intel_panel_init(intel_connector, drm_edid);
5616 
5617 	intel_edp_backlight_setup(intel_dp, intel_connector);
5618 
5619 	intel_edp_add_properties(intel_dp);
5620 
5621 	intel_pps_init_late(intel_dp);
5622 
5623 	return true;
5624 
5625 out_vdd_off:
5626 	intel_pps_vdd_off_sync(intel_dp);
5627 
5628 	return false;
5629 }
5630 
intel_dp_modeset_retry_work_fn(struct work_struct * work)5631 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5632 {
5633 	struct intel_connector *intel_connector;
5634 	struct drm_connector *connector;
5635 
5636 	intel_connector = container_of(work, typeof(*intel_connector),
5637 				       modeset_retry_work);
5638 	connector = &intel_connector->base;
5639 	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5640 		    connector->name);
5641 
5642 	/* Grab the locks before changing connector property*/
5643 	mutex_lock(&connector->dev->mode_config.mutex);
5644 	/* Set connector link status to BAD and send a Uevent to notify
5645 	 * userspace to do a modeset.
5646 	 */
5647 	drm_connector_set_link_status_property(connector,
5648 					       DRM_MODE_LINK_STATUS_BAD);
5649 	mutex_unlock(&connector->dev->mode_config.mutex);
5650 	/* Send Hotplug uevent so userspace can reprobe */
5651 	drm_kms_helper_connector_hotplug_event(connector);
5652 }
5653 
5654 bool
intel_dp_init_connector(struct intel_digital_port * dig_port,struct intel_connector * intel_connector)5655 intel_dp_init_connector(struct intel_digital_port *dig_port,
5656 			struct intel_connector *intel_connector)
5657 {
5658 	struct drm_connector *connector = &intel_connector->base;
5659 	struct intel_dp *intel_dp = &dig_port->dp;
5660 	struct intel_encoder *intel_encoder = &dig_port->base;
5661 	struct drm_device *dev = intel_encoder->base.dev;
5662 	struct drm_i915_private *dev_priv = to_i915(dev);
5663 	enum port port = intel_encoder->port;
5664 	enum phy phy = intel_port_to_phy(dev_priv, port);
5665 	int type;
5666 
5667 	/* Initialize the work for modeset in case of link train failure */
5668 	INIT_WORK(&intel_connector->modeset_retry_work,
5669 		  intel_dp_modeset_retry_work_fn);
5670 
5671 	if (drm_WARN(dev, dig_port->max_lanes < 1,
5672 		     "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5673 		     dig_port->max_lanes, intel_encoder->base.base.id,
5674 		     intel_encoder->base.name))
5675 		return false;
5676 
5677 	intel_dp->reset_link_params = true;
5678 	intel_dp->pps.pps_pipe = INVALID_PIPE;
5679 	intel_dp->pps.active_pipe = INVALID_PIPE;
5680 
5681 	/* Preserve the current hw state. */
5682 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5683 	intel_dp->attached_connector = intel_connector;
5684 
5685 	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
5686 		/*
5687 		 * Currently we don't support eDP on TypeC ports, although in
5688 		 * theory it could work on TypeC legacy ports.
5689 		 */
5690 		drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5691 		type = DRM_MODE_CONNECTOR_eDP;
5692 		intel_encoder->type = INTEL_OUTPUT_EDP;
5693 
5694 		/* eDP only on port B and/or C on vlv/chv */
5695 		if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5696 				      IS_CHERRYVIEW(dev_priv)) &&
5697 				port != PORT_B && port != PORT_C))
5698 			return false;
5699 	} else {
5700 		type = DRM_MODE_CONNECTOR_DisplayPort;
5701 	}
5702 
5703 	intel_dp_set_default_sink_rates(intel_dp);
5704 	intel_dp_set_default_max_sink_lane_count(intel_dp);
5705 
5706 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5707 		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5708 
5709 	drm_dbg_kms(&dev_priv->drm,
5710 		    "Adding %s connector on [ENCODER:%d:%s]\n",
5711 		    type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5712 		    intel_encoder->base.base.id, intel_encoder->base.name);
5713 
5714 	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5715 	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5716 
5717 	if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
5718 		connector->interlace_allowed = true;
5719 
5720 	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5721 
5722 	intel_dp_aux_init(intel_dp);
5723 
5724 	intel_connector_attach_encoder(intel_connector, intel_encoder);
5725 
5726 	if (HAS_DDI(dev_priv))
5727 		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5728 	else
5729 		intel_connector->get_hw_state = intel_connector_get_hw_state;
5730 
5731 	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5732 		intel_dp_aux_fini(intel_dp);
5733 		goto fail;
5734 	}
5735 
5736 	intel_dp_set_source_rates(intel_dp);
5737 	intel_dp_set_common_rates(intel_dp);
5738 	intel_dp_reset_max_link_params(intel_dp);
5739 
5740 	/* init MST on ports that can support it */
5741 	intel_dp_mst_encoder_init(dig_port,
5742 				  intel_connector->base.base.id);
5743 
5744 	intel_dp_add_properties(intel_dp, connector);
5745 
5746 	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5747 		int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5748 		if (ret)
5749 			drm_dbg_kms(&dev_priv->drm,
5750 				    "HDCP init failed, skipping.\n");
5751 	}
5752 
5753 	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5754 	 * 0xd.  Failure to do so will result in spurious interrupts being
5755 	 * generated on the port when a cable is not attached.
5756 	 */
5757 	if (IS_G45(dev_priv)) {
5758 		u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5759 		intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5760 			       (temp & ~0xf) | 0xd);
5761 	}
5762 
5763 	intel_dp->frl.is_trained = false;
5764 	intel_dp->frl.trained_rate_gbps = 0;
5765 
5766 	intel_psr_init(intel_dp);
5767 
5768 	return true;
5769 
5770 fail:
5771 	intel_display_power_flush_work(dev_priv);
5772 	drm_connector_cleanup(connector);
5773 
5774 	return false;
5775 }
5776 
intel_dp_mst_suspend(struct drm_i915_private * dev_priv)5777 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5778 {
5779 	struct intel_encoder *encoder;
5780 
5781 	if (!HAS_DISPLAY(dev_priv))
5782 		return;
5783 
5784 	for_each_intel_encoder(&dev_priv->drm, encoder) {
5785 		struct intel_dp *intel_dp;
5786 
5787 		if (encoder->type != INTEL_OUTPUT_DDI)
5788 			continue;
5789 
5790 		intel_dp = enc_to_intel_dp(encoder);
5791 
5792 		if (!intel_dp_mst_source_support(intel_dp))
5793 			continue;
5794 
5795 		if (intel_dp->is_mst)
5796 			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5797 	}
5798 }
5799 
intel_dp_mst_resume(struct drm_i915_private * dev_priv)5800 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5801 {
5802 	struct intel_encoder *encoder;
5803 
5804 	if (!HAS_DISPLAY(dev_priv))
5805 		return;
5806 
5807 	for_each_intel_encoder(&dev_priv->drm, encoder) {
5808 		struct intel_dp *intel_dp;
5809 		int ret;
5810 
5811 		if (encoder->type != INTEL_OUTPUT_DDI)
5812 			continue;
5813 
5814 		intel_dp = enc_to_intel_dp(encoder);
5815 
5816 		if (!intel_dp_mst_source_support(intel_dp))
5817 			continue;
5818 
5819 		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5820 						     true);
5821 		if (ret) {
5822 			intel_dp->is_mst = false;
5823 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5824 							false);
5825 		}
5826 	}
5827 }
5828