xref: /openbmc/linux/drivers/video/fbdev/da8xx-fb.c (revision 1e9fd9d5)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2008-2009 MontaVista Software Inc.
4  * Copyright (C) 2008-2009 Texas Instruments Inc
5  *
6  * Based on the LCD driver for TI Avalanche processors written by
7  * Ajay Singh and Shalom Hai.
8  */
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/fb.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/device.h>
14 #include <linux/platform_device.h>
15 #include <linux/uaccess.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
18 #include <linux/wait.h>
19 #include <linux/clk.h>
20 #include <linux/cpufreq.h>
21 #include <linux/console.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/lcm.h>
27 #include <video/da8xx-fb.h>
28 #include <asm/div64.h>
29 
30 #define DRIVER_NAME "da8xx_lcdc"
31 
32 #define LCD_VERSION_1	1
33 #define LCD_VERSION_2	2
34 
35 /* LCD Status Register */
36 #define LCD_END_OF_FRAME1		BIT(9)
37 #define LCD_END_OF_FRAME0		BIT(8)
38 #define LCD_PL_LOAD_DONE		BIT(6)
39 #define LCD_FIFO_UNDERFLOW		BIT(5)
40 #define LCD_SYNC_LOST			BIT(2)
41 #define LCD_FRAME_DONE			BIT(0)
42 
43 /* LCD DMA Control Register */
44 #define LCD_DMA_BURST_SIZE(x)		((x) << 4)
45 #define LCD_DMA_BURST_1			0x0
46 #define LCD_DMA_BURST_2			0x1
47 #define LCD_DMA_BURST_4			0x2
48 #define LCD_DMA_BURST_8			0x3
49 #define LCD_DMA_BURST_16		0x4
50 #define LCD_V1_END_OF_FRAME_INT_ENA	BIT(2)
51 #define LCD_V2_END_OF_FRAME0_INT_ENA	BIT(8)
52 #define LCD_V2_END_OF_FRAME1_INT_ENA	BIT(9)
53 #define LCD_DUAL_FRAME_BUFFER_ENABLE	BIT(0)
54 
55 /* LCD Control Register */
56 #define LCD_CLK_DIVISOR(x)		((x) << 8)
57 #define LCD_RASTER_MODE			0x01
58 
59 /* LCD Raster Control Register */
60 #define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
61 #define PALETTE_AND_DATA		0x00
62 #define PALETTE_ONLY			0x01
63 #define DATA_ONLY			0x02
64 
65 #define LCD_MONO_8BIT_MODE		BIT(9)
66 #define LCD_RASTER_ORDER		BIT(8)
67 #define LCD_TFT_MODE			BIT(7)
68 #define LCD_V1_UNDERFLOW_INT_ENA	BIT(6)
69 #define LCD_V2_UNDERFLOW_INT_ENA	BIT(5)
70 #define LCD_V1_PL_INT_ENA		BIT(4)
71 #define LCD_V2_PL_INT_ENA		BIT(6)
72 #define LCD_MONOCHROME_MODE		BIT(1)
73 #define LCD_RASTER_ENABLE		BIT(0)
74 #define LCD_TFT_ALT_ENABLE		BIT(23)
75 #define LCD_STN_565_ENABLE		BIT(24)
76 #define LCD_V2_DMA_CLK_EN		BIT(2)
77 #define LCD_V2_LIDD_CLK_EN		BIT(1)
78 #define LCD_V2_CORE_CLK_EN		BIT(0)
79 #define LCD_V2_LPP_B10			26
80 #define LCD_V2_TFT_24BPP_MODE		BIT(25)
81 #define LCD_V2_TFT_24BPP_UNPACK		BIT(26)
82 
83 /* LCD Raster Timing 2 Register */
84 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
85 #define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
86 #define LCD_SYNC_CTRL				BIT(25)
87 #define LCD_SYNC_EDGE				BIT(24)
88 #define LCD_INVERT_PIXEL_CLOCK			BIT(22)
89 #define LCD_INVERT_LINE_CLOCK			BIT(21)
90 #define LCD_INVERT_FRAME_CLOCK			BIT(20)
91 
92 /* LCD Block */
93 #define  LCD_PID_REG				0x0
94 #define  LCD_CTRL_REG				0x4
95 #define  LCD_STAT_REG				0x8
96 #define  LCD_RASTER_CTRL_REG			0x28
97 #define  LCD_RASTER_TIMING_0_REG		0x2C
98 #define  LCD_RASTER_TIMING_1_REG		0x30
99 #define  LCD_RASTER_TIMING_2_REG		0x34
100 #define  LCD_DMA_CTRL_REG			0x40
101 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG	0x44
102 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG	0x48
103 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG	0x4C
104 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG	0x50
105 
106 /* Interrupt Registers available only in Version 2 */
107 #define  LCD_RAW_STAT_REG			0x58
108 #define  LCD_MASKED_STAT_REG			0x5c
109 #define  LCD_INT_ENABLE_SET_REG			0x60
110 #define  LCD_INT_ENABLE_CLR_REG			0x64
111 #define  LCD_END_OF_INT_IND_REG			0x68
112 
113 /* Clock registers available only on Version 2 */
114 #define  LCD_CLK_ENABLE_REG			0x6c
115 #define  LCD_CLK_RESET_REG			0x70
116 #define  LCD_CLK_MAIN_RESET			BIT(3)
117 
118 #define LCD_NUM_BUFFERS	2
119 
120 #define PALETTE_SIZE	256
121 
122 #define	CLK_MIN_DIV	2
123 #define	CLK_MAX_DIV	255
124 
125 static void __iomem *da8xx_fb_reg_base;
126 static unsigned int lcd_revision;
127 static irq_handler_t lcdc_irq_handler;
128 static wait_queue_head_t frame_done_wq;
129 static int frame_done_flag;
130 
lcdc_read(unsigned int addr)131 static unsigned int lcdc_read(unsigned int addr)
132 {
133 	return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
134 }
135 
lcdc_write(unsigned int val,unsigned int addr)136 static void lcdc_write(unsigned int val, unsigned int addr)
137 {
138 	__raw_writel(val, da8xx_fb_reg_base + (addr));
139 }
140 
141 struct da8xx_fb_par {
142 	struct device		*dev;
143 	dma_addr_t		p_palette_base;
144 	unsigned char *v_palette_base;
145 	dma_addr_t		vram_phys;
146 	unsigned long		vram_size;
147 	void			*vram_virt;
148 	unsigned int		dma_start;
149 	unsigned int		dma_end;
150 	struct clk *lcdc_clk;
151 	int irq;
152 	unsigned int palette_sz;
153 	int blank;
154 	wait_queue_head_t	vsync_wait;
155 	int			vsync_flag;
156 	int			vsync_timeout;
157 	spinlock_t		lock_for_chan_update;
158 
159 	/*
160 	 * LCDC has 2 ping pong DMA channels, channel 0
161 	 * and channel 1.
162 	 */
163 	unsigned int		which_dma_channel_done;
164 #ifdef CONFIG_CPU_FREQ
165 	struct notifier_block	freq_transition;
166 #endif
167 	unsigned int		lcdc_clk_rate;
168 	struct regulator	*lcd_supply;
169 	u32 pseudo_palette[16];
170 	struct fb_videomode	mode;
171 	struct lcd_ctrl_config	cfg;
172 };
173 
174 static struct fb_var_screeninfo da8xx_fb_var;
175 
176 static struct fb_fix_screeninfo da8xx_fb_fix = {
177 	.id = "DA8xx FB Drv",
178 	.type = FB_TYPE_PACKED_PIXELS,
179 	.type_aux = 0,
180 	.visual = FB_VISUAL_PSEUDOCOLOR,
181 	.xpanstep = 0,
182 	.ypanstep = 1,
183 	.ywrapstep = 0,
184 	.accel = FB_ACCEL_NONE
185 };
186 
187 static struct fb_videomode known_lcd_panels[] = {
188 	/* Sharp LCD035Q3DG01 */
189 	[0] = {
190 		.name           = "Sharp_LCD035Q3DG01",
191 		.xres           = 320,
192 		.yres           = 240,
193 		.pixclock       = KHZ2PICOS(4607),
194 		.left_margin    = 6,
195 		.right_margin   = 8,
196 		.upper_margin   = 2,
197 		.lower_margin   = 2,
198 		.hsync_len      = 0,
199 		.vsync_len      = 0,
200 		.sync           = FB_SYNC_CLK_INVERT,
201 	},
202 	/* Sharp LK043T1DG01 */
203 	[1] = {
204 		.name           = "Sharp_LK043T1DG01",
205 		.xres           = 480,
206 		.yres           = 272,
207 		.pixclock       = KHZ2PICOS(7833),
208 		.left_margin    = 2,
209 		.right_margin   = 2,
210 		.upper_margin   = 2,
211 		.lower_margin   = 2,
212 		.hsync_len      = 41,
213 		.vsync_len      = 10,
214 		.sync           = 0,
215 		.flag           = 0,
216 	},
217 	[2] = {
218 		/* Hitachi SP10Q010 */
219 		.name           = "SP10Q010",
220 		.xres           = 320,
221 		.yres           = 240,
222 		.pixclock       = KHZ2PICOS(7833),
223 		.left_margin    = 10,
224 		.right_margin   = 10,
225 		.upper_margin   = 10,
226 		.lower_margin   = 10,
227 		.hsync_len      = 10,
228 		.vsync_len      = 10,
229 		.sync           = 0,
230 		.flag           = 0,
231 	},
232 	[3] = {
233 		/* Densitron 84-0023-001T */
234 		.name           = "Densitron_84-0023-001T",
235 		.xres           = 320,
236 		.yres           = 240,
237 		.pixclock       = KHZ2PICOS(6400),
238 		.left_margin    = 0,
239 		.right_margin   = 0,
240 		.upper_margin   = 0,
241 		.lower_margin   = 0,
242 		.hsync_len      = 30,
243 		.vsync_len      = 3,
244 		.sync           = 0,
245 	},
246 };
247 
da8xx_fb_is_raster_enabled(void)248 static bool da8xx_fb_is_raster_enabled(void)
249 {
250 	return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
251 }
252 
253 /* Enable the Raster Engine of the LCD Controller */
lcd_enable_raster(void)254 static void lcd_enable_raster(void)
255 {
256 	u32 reg;
257 
258 	/* Put LCDC in reset for several cycles */
259 	if (lcd_revision == LCD_VERSION_2)
260 		/* Write 1 to reset LCDC */
261 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
262 	mdelay(1);
263 
264 	/* Bring LCDC out of reset */
265 	if (lcd_revision == LCD_VERSION_2)
266 		lcdc_write(0, LCD_CLK_RESET_REG);
267 	mdelay(1);
268 
269 	/* Above reset sequence doesnot reset register context */
270 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
271 	if (!(reg & LCD_RASTER_ENABLE))
272 		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
273 }
274 
275 /* Disable the Raster Engine of the LCD Controller */
lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)276 static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)
277 {
278 	u32 reg;
279 	int ret;
280 
281 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
282 	if (reg & LCD_RASTER_ENABLE)
283 		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
284 	else
285 		/* return if already disabled */
286 		return;
287 
288 	if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
289 			(lcd_revision == LCD_VERSION_2)) {
290 		frame_done_flag = 0;
291 		ret = wait_event_interruptible_timeout(frame_done_wq,
292 				frame_done_flag != 0,
293 				msecs_to_jiffies(50));
294 		if (ret == 0)
295 			pr_err("LCD Controller timed out\n");
296 	}
297 }
298 
lcd_blit(int load_mode,struct da8xx_fb_par * par)299 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
300 {
301 	u32 start;
302 	u32 end;
303 	u32 reg_ras;
304 	u32 reg_dma;
305 	u32 reg_int;
306 
307 	/* init reg to clear PLM (loading mode) fields */
308 	reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
309 	reg_ras &= ~(3 << 20);
310 
311 	reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
312 
313 	if (load_mode == LOAD_DATA) {
314 		start    = par->dma_start;
315 		end      = par->dma_end;
316 
317 		reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
318 		if (lcd_revision == LCD_VERSION_1) {
319 			reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
320 		} else {
321 			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
322 				LCD_V2_END_OF_FRAME0_INT_ENA |
323 				LCD_V2_END_OF_FRAME1_INT_ENA |
324 				LCD_FRAME_DONE | LCD_SYNC_LOST;
325 			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
326 		}
327 		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
328 
329 		lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
330 		lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
331 		lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
332 		lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
333 	} else if (load_mode == LOAD_PALETTE) {
334 		start    = par->p_palette_base;
335 		end      = start + par->palette_sz - 1;
336 
337 		reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
338 
339 		if (lcd_revision == LCD_VERSION_1) {
340 			reg_ras |= LCD_V1_PL_INT_ENA;
341 		} else {
342 			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
343 				LCD_V2_PL_INT_ENA;
344 			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
345 		}
346 
347 		lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
348 		lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
349 	}
350 
351 	lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
352 	lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
353 
354 	/*
355 	 * The Raster enable bit must be set after all other control fields are
356 	 * set.
357 	 */
358 	lcd_enable_raster();
359 }
360 
361 /* Configure the Burst Size and fifo threhold of DMA */
lcd_cfg_dma(int burst_size,int fifo_th)362 static int lcd_cfg_dma(int burst_size, int fifo_th)
363 {
364 	u32 reg;
365 
366 	reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
367 	switch (burst_size) {
368 	case 1:
369 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
370 		break;
371 	case 2:
372 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
373 		break;
374 	case 4:
375 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
376 		break;
377 	case 8:
378 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
379 		break;
380 	case 16:
381 	default:
382 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
383 		break;
384 	}
385 
386 	reg |= (fifo_th << 8);
387 
388 	lcdc_write(reg, LCD_DMA_CTRL_REG);
389 
390 	return 0;
391 }
392 
lcd_cfg_ac_bias(int period,int transitions_per_int)393 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
394 {
395 	u32 reg;
396 
397 	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
398 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
399 	reg |= LCD_AC_BIAS_FREQUENCY(period) |
400 		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
401 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
402 }
403 
lcd_cfg_horizontal_sync(int back_porch,int pulse_width,int front_porch)404 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
405 		int front_porch)
406 {
407 	u32 reg;
408 
409 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
410 	reg |= (((back_porch-1) & 0xff) << 24)
411 	    | (((front_porch-1) & 0xff) << 16)
412 	    | (((pulse_width-1) & 0x3f) << 10);
413 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
414 
415 	/*
416 	 * LCDC Version 2 adds some extra bits that increase the allowable
417 	 * size of the horizontal timing registers.
418 	 * remember that the registers use 0 to represent 1 so all values
419 	 * that get set into register need to be decremented by 1
420 	 */
421 	if (lcd_revision == LCD_VERSION_2) {
422 		/* Mask off the bits we want to change */
423 		reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff;
424 		reg |= ((front_porch-1) & 0x300) >> 8;
425 		reg |= ((back_porch-1) & 0x300) >> 4;
426 		reg |= ((pulse_width-1) & 0x3c0) << 21;
427 		lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
428 	}
429 }
430 
lcd_cfg_vertical_sync(int back_porch,int pulse_width,int front_porch)431 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
432 		int front_porch)
433 {
434 	u32 reg;
435 
436 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
437 	reg |= ((back_porch & 0xff) << 24)
438 	    | ((front_porch & 0xff) << 16)
439 	    | (((pulse_width-1) & 0x3f) << 10);
440 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
441 }
442 
lcd_cfg_display(const struct lcd_ctrl_config * cfg,struct fb_videomode * panel)443 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
444 		struct fb_videomode *panel)
445 {
446 	u32 reg;
447 	u32 reg_int;
448 
449 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
450 						LCD_MONO_8BIT_MODE |
451 						LCD_MONOCHROME_MODE);
452 
453 	switch (cfg->panel_shade) {
454 	case MONOCHROME:
455 		reg |= LCD_MONOCHROME_MODE;
456 		if (cfg->mono_8bit_mode)
457 			reg |= LCD_MONO_8BIT_MODE;
458 		break;
459 	case COLOR_ACTIVE:
460 		reg |= LCD_TFT_MODE;
461 		if (cfg->tft_alt_mode)
462 			reg |= LCD_TFT_ALT_ENABLE;
463 		break;
464 
465 	case COLOR_PASSIVE:
466 		/* AC bias applicable only for Pasive panels */
467 		lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
468 		if (cfg->bpp == 12 && cfg->stn_565_mode)
469 			reg |= LCD_STN_565_ENABLE;
470 		break;
471 
472 	default:
473 		return -EINVAL;
474 	}
475 
476 	/* enable additional interrupts here */
477 	if (lcd_revision == LCD_VERSION_1) {
478 		reg |= LCD_V1_UNDERFLOW_INT_ENA;
479 	} else {
480 		reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
481 			LCD_V2_UNDERFLOW_INT_ENA;
482 		lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
483 	}
484 
485 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
486 
487 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
488 
489 	reg |= LCD_SYNC_CTRL;
490 
491 	if (cfg->sync_edge)
492 		reg |= LCD_SYNC_EDGE;
493 	else
494 		reg &= ~LCD_SYNC_EDGE;
495 
496 	if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
497 		reg |= LCD_INVERT_LINE_CLOCK;
498 	else
499 		reg &= ~LCD_INVERT_LINE_CLOCK;
500 
501 	if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
502 		reg |= LCD_INVERT_FRAME_CLOCK;
503 	else
504 		reg &= ~LCD_INVERT_FRAME_CLOCK;
505 
506 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
507 
508 	return 0;
509 }
510 
lcd_cfg_frame_buffer(struct da8xx_fb_par * par,u32 width,u32 height,u32 bpp,u32 raster_order)511 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
512 		u32 bpp, u32 raster_order)
513 {
514 	u32 reg;
515 
516 	if (bpp > 16 && lcd_revision == LCD_VERSION_1)
517 		return -EINVAL;
518 
519 	/* Set the Panel Width */
520 	/* Pixels per line = (PPL + 1)*16 */
521 	if (lcd_revision == LCD_VERSION_1) {
522 		/*
523 		 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
524 		 * pixels.
525 		 */
526 		width &= 0x3f0;
527 	} else {
528 		/*
529 		 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
530 		 * pixels.
531 		 */
532 		width &= 0x7f0;
533 	}
534 
535 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
536 	reg &= 0xfffffc00;
537 	if (lcd_revision == LCD_VERSION_1) {
538 		reg |= ((width >> 4) - 1) << 4;
539 	} else {
540 		width = (width >> 4) - 1;
541 		reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
542 	}
543 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
544 
545 	/* Set the Panel Height */
546 	/* Set bits 9:0 of Lines Per Pixel */
547 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
548 	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
549 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
550 
551 	/* Set bit 10 of Lines Per Pixel */
552 	if (lcd_revision == LCD_VERSION_2) {
553 		reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
554 		reg |= ((height - 1) & 0x400) << 16;
555 		lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
556 	}
557 
558 	/* Set the Raster Order of the Frame Buffer */
559 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
560 	if (raster_order)
561 		reg |= LCD_RASTER_ORDER;
562 
563 	par->palette_sz = 16 * 2;
564 
565 	switch (bpp) {
566 	case 1:
567 	case 2:
568 	case 4:
569 	case 16:
570 		break;
571 	case 24:
572 		reg |= LCD_V2_TFT_24BPP_MODE;
573 		break;
574 	case 32:
575 		reg |= LCD_V2_TFT_24BPP_MODE;
576 		reg |= LCD_V2_TFT_24BPP_UNPACK;
577 		break;
578 	case 8:
579 		par->palette_sz = 256 * 2;
580 		break;
581 
582 	default:
583 		return -EINVAL;
584 	}
585 
586 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
587 
588 	return 0;
589 }
590 
591 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
fb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)592 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
593 			      unsigned blue, unsigned transp,
594 			      struct fb_info *info)
595 {
596 	struct da8xx_fb_par *par = info->par;
597 	unsigned short *palette = (unsigned short *) par->v_palette_base;
598 	u_short pal;
599 	int update_hw = 0;
600 
601 	if (regno > 255)
602 		return 1;
603 
604 	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
605 		return 1;
606 
607 	if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
608 		return -EINVAL;
609 
610 	switch (info->fix.visual) {
611 	case FB_VISUAL_TRUECOLOR:
612 		red = CNVT_TOHW(red, info->var.red.length);
613 		green = CNVT_TOHW(green, info->var.green.length);
614 		blue = CNVT_TOHW(blue, info->var.blue.length);
615 		break;
616 	case FB_VISUAL_PSEUDOCOLOR:
617 		switch (info->var.bits_per_pixel) {
618 		case 4:
619 			if (regno > 15)
620 				return -EINVAL;
621 
622 			if (info->var.grayscale) {
623 				pal = regno;
624 			} else {
625 				red >>= 4;
626 				green >>= 8;
627 				blue >>= 12;
628 
629 				pal = red & 0x0f00;
630 				pal |= green & 0x00f0;
631 				pal |= blue & 0x000f;
632 			}
633 			if (regno == 0)
634 				pal |= 0x2000;
635 			palette[regno] = pal;
636 			break;
637 
638 		case 8:
639 			red >>= 4;
640 			green >>= 8;
641 			blue >>= 12;
642 
643 			pal = (red & 0x0f00);
644 			pal |= (green & 0x00f0);
645 			pal |= (blue & 0x000f);
646 
647 			if (palette[regno] != pal) {
648 				update_hw = 1;
649 				palette[regno] = pal;
650 			}
651 			break;
652 		}
653 		break;
654 	}
655 
656 	/* Truecolor has hardware independent palette */
657 	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
658 		u32 v;
659 
660 		if (regno > 15)
661 			return -EINVAL;
662 
663 		v = (red << info->var.red.offset) |
664 			(green << info->var.green.offset) |
665 			(blue << info->var.blue.offset);
666 
667 		((u32 *) (info->pseudo_palette))[regno] = v;
668 		if (palette[0] != 0x4000) {
669 			update_hw = 1;
670 			palette[0] = 0x4000;
671 		}
672 	}
673 
674 	/* Update the palette in the h/w as needed. */
675 	if (update_hw)
676 		lcd_blit(LOAD_PALETTE, par);
677 
678 	return 0;
679 }
680 #undef CNVT_TOHW
681 
da8xx_fb_lcd_reset(void)682 static void da8xx_fb_lcd_reset(void)
683 {
684 	/* DMA has to be disabled */
685 	lcdc_write(0, LCD_DMA_CTRL_REG);
686 	lcdc_write(0, LCD_RASTER_CTRL_REG);
687 
688 	if (lcd_revision == LCD_VERSION_2) {
689 		lcdc_write(0, LCD_INT_ENABLE_SET_REG);
690 		/* Write 1 to reset */
691 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
692 		lcdc_write(0, LCD_CLK_RESET_REG);
693 	}
694 }
695 
da8xx_fb_config_clk_divider(struct da8xx_fb_par * par,unsigned lcdc_clk_div,unsigned lcdc_clk_rate)696 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
697 					      unsigned lcdc_clk_div,
698 					      unsigned lcdc_clk_rate)
699 {
700 	int ret;
701 
702 	if (par->lcdc_clk_rate != lcdc_clk_rate) {
703 		ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
704 		if (ret) {
705 			dev_err(par->dev,
706 				"unable to set clock rate at %u\n",
707 				lcdc_clk_rate);
708 			return ret;
709 		}
710 		par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
711 	}
712 
713 	/* Configure the LCD clock divisor. */
714 	lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) |
715 			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
716 
717 	if (lcd_revision == LCD_VERSION_2)
718 		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
719 				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
720 
721 	return 0;
722 }
723 
da8xx_fb_calc_clk_divider(struct da8xx_fb_par * par,unsigned pixclock,unsigned * lcdc_clk_rate)724 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
725 					      unsigned pixclock,
726 					      unsigned *lcdc_clk_rate)
727 {
728 	unsigned lcdc_clk_div;
729 
730 	pixclock = PICOS2KHZ(pixclock) * 1000;
731 
732 	*lcdc_clk_rate = par->lcdc_clk_rate;
733 
734 	if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) {
735 		*lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
736 						pixclock * CLK_MAX_DIV);
737 		lcdc_clk_div = CLK_MAX_DIV;
738 	} else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) {
739 		*lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
740 						pixclock * CLK_MIN_DIV);
741 		lcdc_clk_div = CLK_MIN_DIV;
742 	} else {
743 		lcdc_clk_div = *lcdc_clk_rate / pixclock;
744 	}
745 
746 	return lcdc_clk_div;
747 }
748 
da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par * par,struct fb_videomode * mode)749 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
750 					    struct fb_videomode *mode)
751 {
752 	unsigned lcdc_clk_rate;
753 	unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
754 							  &lcdc_clk_rate);
755 
756 	return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
757 }
758 
da8xx_fb_round_clk(struct da8xx_fb_par * par,unsigned pixclock)759 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
760 					  unsigned pixclock)
761 {
762 	unsigned lcdc_clk_div, lcdc_clk_rate;
763 
764 	lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
765 	return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div));
766 }
767 
lcd_init(struct da8xx_fb_par * par,const struct lcd_ctrl_config * cfg,struct fb_videomode * panel)768 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
769 		struct fb_videomode *panel)
770 {
771 	u32 bpp;
772 	int ret = 0;
773 
774 	ret = da8xx_fb_calc_config_clk_divider(par, panel);
775 	if (ret) {
776 		dev_err(par->dev, "unable to configure clock\n");
777 		return ret;
778 	}
779 
780 	if (panel->sync & FB_SYNC_CLK_INVERT)
781 		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
782 			LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
783 	else
784 		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
785 			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
786 
787 	/* Configure the DMA burst size and fifo threshold. */
788 	ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
789 	if (ret < 0)
790 		return ret;
791 
792 	/* Configure the vertical and horizontal sync properties. */
793 	lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len,
794 			panel->lower_margin);
795 	lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len,
796 			panel->right_margin);
797 
798 	/* Configure for disply */
799 	ret = lcd_cfg_display(cfg, panel);
800 	if (ret < 0)
801 		return ret;
802 
803 	bpp = cfg->bpp;
804 
805 	if (bpp == 12)
806 		bpp = 16;
807 	ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
808 				(unsigned int)panel->yres, bpp,
809 				cfg->raster_order);
810 	if (ret < 0)
811 		return ret;
812 
813 	/* Configure FDD */
814 	lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
815 		       (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
816 
817 	return 0;
818 }
819 
820 /* IRQ handler for version 2 of LCDC */
lcdc_irq_handler_rev02(int irq,void * arg)821 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
822 {
823 	struct da8xx_fb_par *par = arg;
824 	u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
825 
826 	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
827 		lcd_disable_raster(DA8XX_FRAME_NOWAIT);
828 		lcdc_write(stat, LCD_MASKED_STAT_REG);
829 		lcd_enable_raster();
830 	} else if (stat & LCD_PL_LOAD_DONE) {
831 		/*
832 		 * Must disable raster before changing state of any control bit.
833 		 * And also must be disabled before clearing the PL loading
834 		 * interrupt via the following write to the status register. If
835 		 * this is done after then one gets multiple PL done interrupts.
836 		 */
837 		lcd_disable_raster(DA8XX_FRAME_NOWAIT);
838 
839 		lcdc_write(stat, LCD_MASKED_STAT_REG);
840 
841 		/* Disable PL completion interrupt */
842 		lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
843 
844 		/* Setup and start data loading mode */
845 		lcd_blit(LOAD_DATA, par);
846 	} else {
847 		lcdc_write(stat, LCD_MASKED_STAT_REG);
848 
849 		if (stat & LCD_END_OF_FRAME0) {
850 			par->which_dma_channel_done = 0;
851 			lcdc_write(par->dma_start,
852 				   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
853 			lcdc_write(par->dma_end,
854 				   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
855 			par->vsync_flag = 1;
856 			wake_up_interruptible(&par->vsync_wait);
857 		}
858 
859 		if (stat & LCD_END_OF_FRAME1) {
860 			par->which_dma_channel_done = 1;
861 			lcdc_write(par->dma_start,
862 				   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
863 			lcdc_write(par->dma_end,
864 				   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
865 			par->vsync_flag = 1;
866 			wake_up_interruptible(&par->vsync_wait);
867 		}
868 
869 		/* Set only when controller is disabled and at the end of
870 		 * active frame
871 		 */
872 		if (stat & BIT(0)) {
873 			frame_done_flag = 1;
874 			wake_up_interruptible(&frame_done_wq);
875 		}
876 	}
877 
878 	lcdc_write(0, LCD_END_OF_INT_IND_REG);
879 	return IRQ_HANDLED;
880 }
881 
882 /* IRQ handler for version 1 LCDC */
lcdc_irq_handler_rev01(int irq,void * arg)883 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
884 {
885 	struct da8xx_fb_par *par = arg;
886 	u32 stat = lcdc_read(LCD_STAT_REG);
887 	u32 reg_ras;
888 
889 	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
890 		lcd_disable_raster(DA8XX_FRAME_NOWAIT);
891 		lcdc_write(stat, LCD_STAT_REG);
892 		lcd_enable_raster();
893 	} else if (stat & LCD_PL_LOAD_DONE) {
894 		/*
895 		 * Must disable raster before changing state of any control bit.
896 		 * And also must be disabled before clearing the PL loading
897 		 * interrupt via the following write to the status register. If
898 		 * this is done after then one gets multiple PL done interrupts.
899 		 */
900 		lcd_disable_raster(DA8XX_FRAME_NOWAIT);
901 
902 		lcdc_write(stat, LCD_STAT_REG);
903 
904 		/* Disable PL completion inerrupt */
905 		reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
906 		reg_ras &= ~LCD_V1_PL_INT_ENA;
907 		lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
908 
909 		/* Setup and start data loading mode */
910 		lcd_blit(LOAD_DATA, par);
911 	} else {
912 		lcdc_write(stat, LCD_STAT_REG);
913 
914 		if (stat & LCD_END_OF_FRAME0) {
915 			par->which_dma_channel_done = 0;
916 			lcdc_write(par->dma_start,
917 				   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
918 			lcdc_write(par->dma_end,
919 				   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
920 			par->vsync_flag = 1;
921 			wake_up_interruptible(&par->vsync_wait);
922 		}
923 
924 		if (stat & LCD_END_OF_FRAME1) {
925 			par->which_dma_channel_done = 1;
926 			lcdc_write(par->dma_start,
927 				   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
928 			lcdc_write(par->dma_end,
929 				   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
930 			par->vsync_flag = 1;
931 			wake_up_interruptible(&par->vsync_wait);
932 		}
933 	}
934 
935 	return IRQ_HANDLED;
936 }
937 
fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)938 static int fb_check_var(struct fb_var_screeninfo *var,
939 			struct fb_info *info)
940 {
941 	int err = 0;
942 	struct da8xx_fb_par *par = info->par;
943 	int bpp = var->bits_per_pixel >> 3;
944 	unsigned long line_size = var->xres_virtual * bpp;
945 
946 	if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
947 		return -EINVAL;
948 
949 	switch (var->bits_per_pixel) {
950 	case 1:
951 	case 8:
952 		var->red.offset = 0;
953 		var->red.length = 8;
954 		var->green.offset = 0;
955 		var->green.length = 8;
956 		var->blue.offset = 0;
957 		var->blue.length = 8;
958 		var->transp.offset = 0;
959 		var->transp.length = 0;
960 		var->nonstd = 0;
961 		break;
962 	case 4:
963 		var->red.offset = 0;
964 		var->red.length = 4;
965 		var->green.offset = 0;
966 		var->green.length = 4;
967 		var->blue.offset = 0;
968 		var->blue.length = 4;
969 		var->transp.offset = 0;
970 		var->transp.length = 0;
971 		var->nonstd = FB_NONSTD_REV_PIX_IN_B;
972 		break;
973 	case 16:		/* RGB 565 */
974 		var->red.offset = 11;
975 		var->red.length = 5;
976 		var->green.offset = 5;
977 		var->green.length = 6;
978 		var->blue.offset = 0;
979 		var->blue.length = 5;
980 		var->transp.offset = 0;
981 		var->transp.length = 0;
982 		var->nonstd = 0;
983 		break;
984 	case 24:
985 		var->red.offset = 16;
986 		var->red.length = 8;
987 		var->green.offset = 8;
988 		var->green.length = 8;
989 		var->blue.offset = 0;
990 		var->blue.length = 8;
991 		var->nonstd = 0;
992 		break;
993 	case 32:
994 		var->transp.offset = 24;
995 		var->transp.length = 8;
996 		var->red.offset = 16;
997 		var->red.length = 8;
998 		var->green.offset = 8;
999 		var->green.length = 8;
1000 		var->blue.offset = 0;
1001 		var->blue.length = 8;
1002 		var->nonstd = 0;
1003 		break;
1004 	default:
1005 		err = -EINVAL;
1006 	}
1007 
1008 	var->red.msb_right = 0;
1009 	var->green.msb_right = 0;
1010 	var->blue.msb_right = 0;
1011 	var->transp.msb_right = 0;
1012 
1013 	if (line_size * var->yres_virtual > par->vram_size)
1014 		var->yres_virtual = par->vram_size / line_size;
1015 
1016 	if (var->yres > var->yres_virtual)
1017 		var->yres = var->yres_virtual;
1018 
1019 	if (var->xres > var->xres_virtual)
1020 		var->xres = var->xres_virtual;
1021 
1022 	if (var->xres + var->xoffset > var->xres_virtual)
1023 		var->xoffset = var->xres_virtual - var->xres;
1024 	if (var->yres + var->yoffset > var->yres_virtual)
1025 		var->yoffset = var->yres_virtual - var->yres;
1026 
1027 	var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
1028 
1029 	return err;
1030 }
1031 
1032 #ifdef CONFIG_CPU_FREQ
lcd_da8xx_cpufreq_transition(struct notifier_block * nb,unsigned long val,void * data)1033 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
1034 				     unsigned long val, void *data)
1035 {
1036 	struct da8xx_fb_par *par;
1037 
1038 	par = container_of(nb, struct da8xx_fb_par, freq_transition);
1039 	if (val == CPUFREQ_POSTCHANGE) {
1040 		if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
1041 			par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1042 			lcd_disable_raster(DA8XX_FRAME_WAIT);
1043 			da8xx_fb_calc_config_clk_divider(par, &par->mode);
1044 			if (par->blank == FB_BLANK_UNBLANK)
1045 				lcd_enable_raster();
1046 		}
1047 	}
1048 
1049 	return 0;
1050 }
1051 
lcd_da8xx_cpufreq_register(struct da8xx_fb_par * par)1052 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1053 {
1054 	par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1055 
1056 	return cpufreq_register_notifier(&par->freq_transition,
1057 					 CPUFREQ_TRANSITION_NOTIFIER);
1058 }
1059 
lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par * par)1060 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1061 {
1062 	cpufreq_unregister_notifier(&par->freq_transition,
1063 				    CPUFREQ_TRANSITION_NOTIFIER);
1064 }
1065 #endif
1066 
fb_remove(struct platform_device * dev)1067 static void fb_remove(struct platform_device *dev)
1068 {
1069 	struct fb_info *info = platform_get_drvdata(dev);
1070 	struct da8xx_fb_par *par = info->par;
1071 	int ret;
1072 
1073 #ifdef CONFIG_CPU_FREQ
1074 	lcd_da8xx_cpufreq_deregister(par);
1075 #endif
1076 	if (par->lcd_supply) {
1077 		ret = regulator_disable(par->lcd_supply);
1078 		if (ret)
1079 			dev_warn(&dev->dev, "Failed to disable regulator (%pe)\n",
1080 				 ERR_PTR(ret));
1081 	}
1082 
1083 	lcd_disable_raster(DA8XX_FRAME_WAIT);
1084 	lcdc_write(0, LCD_RASTER_CTRL_REG);
1085 
1086 	/* disable DMA  */
1087 	lcdc_write(0, LCD_DMA_CTRL_REG);
1088 
1089 	unregister_framebuffer(info);
1090 	fb_dealloc_cmap(&info->cmap);
1091 	pm_runtime_put_sync(&dev->dev);
1092 	pm_runtime_disable(&dev->dev);
1093 	framebuffer_release(info);
1094 }
1095 
1096 /*
1097  * Function to wait for vertical sync which for this LCD peripheral
1098  * translates into waiting for the current raster frame to complete.
1099  */
fb_wait_for_vsync(struct fb_info * info)1100 static int fb_wait_for_vsync(struct fb_info *info)
1101 {
1102 	struct da8xx_fb_par *par = info->par;
1103 	int ret;
1104 
1105 	/*
1106 	 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1107 	 * race condition here where the ISR could have occurred just before or
1108 	 * just after this set. But since we are just coarsely waiting for
1109 	 * a frame to complete then that's OK. i.e. if the frame completed
1110 	 * just before this code executed then we have to wait another full
1111 	 * frame time but there is no way to avoid such a situation. On the
1112 	 * other hand if the frame completed just after then we don't need
1113 	 * to wait long at all. Either way we are guaranteed to return to the
1114 	 * user immediately after a frame completion which is all that is
1115 	 * required.
1116 	 */
1117 	par->vsync_flag = 0;
1118 	ret = wait_event_interruptible_timeout(par->vsync_wait,
1119 					       par->vsync_flag != 0,
1120 					       par->vsync_timeout);
1121 	if (ret < 0)
1122 		return ret;
1123 	if (ret == 0)
1124 		return -ETIMEDOUT;
1125 
1126 	return 0;
1127 }
1128 
fb_ioctl(struct fb_info * info,unsigned int cmd,unsigned long arg)1129 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1130 			  unsigned long arg)
1131 {
1132 	struct lcd_sync_arg sync_arg;
1133 
1134 	switch (cmd) {
1135 	case FBIOGET_CONTRAST:
1136 	case FBIOPUT_CONTRAST:
1137 	case FBIGET_BRIGHTNESS:
1138 	case FBIPUT_BRIGHTNESS:
1139 	case FBIGET_COLOR:
1140 	case FBIPUT_COLOR:
1141 		return -ENOTTY;
1142 	case FBIPUT_HSYNC:
1143 		if (copy_from_user(&sync_arg, (char *)arg,
1144 				sizeof(struct lcd_sync_arg)))
1145 			return -EFAULT;
1146 		lcd_cfg_horizontal_sync(sync_arg.back_porch,
1147 					sync_arg.pulse_width,
1148 					sync_arg.front_porch);
1149 		break;
1150 	case FBIPUT_VSYNC:
1151 		if (copy_from_user(&sync_arg, (char *)arg,
1152 				sizeof(struct lcd_sync_arg)))
1153 			return -EFAULT;
1154 		lcd_cfg_vertical_sync(sync_arg.back_porch,
1155 					sync_arg.pulse_width,
1156 					sync_arg.front_porch);
1157 		break;
1158 	case FBIO_WAITFORVSYNC:
1159 		return fb_wait_for_vsync(info);
1160 	default:
1161 		return -EINVAL;
1162 	}
1163 	return 0;
1164 }
1165 
cfb_blank(int blank,struct fb_info * info)1166 static int cfb_blank(int blank, struct fb_info *info)
1167 {
1168 	struct da8xx_fb_par *par = info->par;
1169 	int ret = 0;
1170 
1171 	if (par->blank == blank)
1172 		return 0;
1173 
1174 	par->blank = blank;
1175 	switch (blank) {
1176 	case FB_BLANK_UNBLANK:
1177 		lcd_enable_raster();
1178 
1179 		if (par->lcd_supply) {
1180 			ret = regulator_enable(par->lcd_supply);
1181 			if (ret)
1182 				return ret;
1183 		}
1184 		break;
1185 	case FB_BLANK_NORMAL:
1186 	case FB_BLANK_VSYNC_SUSPEND:
1187 	case FB_BLANK_HSYNC_SUSPEND:
1188 	case FB_BLANK_POWERDOWN:
1189 		if (par->lcd_supply) {
1190 			ret = regulator_disable(par->lcd_supply);
1191 			if (ret)
1192 				return ret;
1193 		}
1194 
1195 		lcd_disable_raster(DA8XX_FRAME_WAIT);
1196 		break;
1197 	default:
1198 		ret = -EINVAL;
1199 	}
1200 
1201 	return ret;
1202 }
1203 
1204 /*
1205  * Set new x,y offsets in the virtual display for the visible area and switch
1206  * to the new mode.
1207  */
da8xx_pan_display(struct fb_var_screeninfo * var,struct fb_info * fbi)1208 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1209 			     struct fb_info *fbi)
1210 {
1211 	int ret = 0;
1212 	struct fb_var_screeninfo new_var;
1213 	struct da8xx_fb_par         *par = fbi->par;
1214 	struct fb_fix_screeninfo    *fix = &fbi->fix;
1215 	unsigned int end;
1216 	unsigned int start;
1217 	unsigned long irq_flags;
1218 
1219 	if (var->xoffset != fbi->var.xoffset ||
1220 			var->yoffset != fbi->var.yoffset) {
1221 		memcpy(&new_var, &fbi->var, sizeof(new_var));
1222 		new_var.xoffset = var->xoffset;
1223 		new_var.yoffset = var->yoffset;
1224 		if (fb_check_var(&new_var, fbi))
1225 			ret = -EINVAL;
1226 		else {
1227 			memcpy(&fbi->var, &new_var, sizeof(new_var));
1228 
1229 			start	= fix->smem_start +
1230 				new_var.yoffset * fix->line_length +
1231 				new_var.xoffset * fbi->var.bits_per_pixel / 8;
1232 			end	= start + fbi->var.yres * fix->line_length - 1;
1233 			par->dma_start	= start;
1234 			par->dma_end	= end;
1235 			spin_lock_irqsave(&par->lock_for_chan_update,
1236 					irq_flags);
1237 			if (par->which_dma_channel_done == 0) {
1238 				lcdc_write(par->dma_start,
1239 					   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1240 				lcdc_write(par->dma_end,
1241 					   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1242 			} else if (par->which_dma_channel_done == 1) {
1243 				lcdc_write(par->dma_start,
1244 					   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1245 				lcdc_write(par->dma_end,
1246 					   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1247 			}
1248 			spin_unlock_irqrestore(&par->lock_for_chan_update,
1249 					irq_flags);
1250 		}
1251 	}
1252 
1253 	return ret;
1254 }
1255 
da8xxfb_set_par(struct fb_info * info)1256 static int da8xxfb_set_par(struct fb_info *info)
1257 {
1258 	struct da8xx_fb_par *par = info->par;
1259 	int ret;
1260 	bool raster = da8xx_fb_is_raster_enabled();
1261 
1262 	if (raster)
1263 		lcd_disable_raster(DA8XX_FRAME_WAIT);
1264 
1265 	fb_var_to_videomode(&par->mode, &info->var);
1266 
1267 	par->cfg.bpp = info->var.bits_per_pixel;
1268 
1269 	info->fix.visual = (par->cfg.bpp <= 8) ?
1270 				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1271 	info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1272 
1273 	ret = lcd_init(par, &par->cfg, &par->mode);
1274 	if (ret < 0) {
1275 		dev_err(par->dev, "lcd init failed\n");
1276 		return ret;
1277 	}
1278 
1279 	par->dma_start = info->fix.smem_start +
1280 			 info->var.yoffset * info->fix.line_length +
1281 			 info->var.xoffset * info->var.bits_per_pixel / 8;
1282 	par->dma_end   = par->dma_start +
1283 			 info->var.yres * info->fix.line_length - 1;
1284 
1285 	lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1286 	lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1287 	lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1288 	lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1289 
1290 	if (raster)
1291 		lcd_enable_raster();
1292 
1293 	return 0;
1294 }
1295 
1296 static const struct fb_ops da8xx_fb_ops = {
1297 	.owner = THIS_MODULE,
1298 	FB_DEFAULT_IOMEM_OPS,
1299 	.fb_check_var = fb_check_var,
1300 	.fb_set_par = da8xxfb_set_par,
1301 	.fb_setcolreg = fb_setcolreg,
1302 	.fb_pan_display = da8xx_pan_display,
1303 	.fb_ioctl = fb_ioctl,
1304 	.fb_blank = cfb_blank,
1305 };
1306 
da8xx_fb_get_videomode(struct platform_device * dev)1307 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
1308 {
1309 	struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev);
1310 	struct fb_videomode *lcdc_info;
1311 	int i;
1312 
1313 	for (i = 0, lcdc_info = known_lcd_panels;
1314 		i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
1315 		if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1316 			break;
1317 	}
1318 
1319 	if (i == ARRAY_SIZE(known_lcd_panels)) {
1320 		dev_err(&dev->dev, "no panel found\n");
1321 		return NULL;
1322 	}
1323 	dev_info(&dev->dev, "found %s panel\n", lcdc_info->name);
1324 
1325 	return lcdc_info;
1326 }
1327 
fb_probe(struct platform_device * device)1328 static int fb_probe(struct platform_device *device)
1329 {
1330 	struct da8xx_lcdc_platform_data *fb_pdata =
1331 						dev_get_platdata(&device->dev);
1332 	struct lcd_ctrl_config *lcd_cfg;
1333 	struct fb_videomode *lcdc_info;
1334 	struct fb_info *da8xx_fb_info;
1335 	struct da8xx_fb_par *par;
1336 	struct clk *tmp_lcdc_clk;
1337 	int ret;
1338 	unsigned long ulcm;
1339 
1340 	if (fb_pdata == NULL) {
1341 		dev_err(&device->dev, "Can not get platform data\n");
1342 		return -ENOENT;
1343 	}
1344 
1345 	lcdc_info = da8xx_fb_get_videomode(device);
1346 	if (lcdc_info == NULL)
1347 		return -ENODEV;
1348 
1349 	da8xx_fb_reg_base = devm_platform_ioremap_resource(device, 0);
1350 	if (IS_ERR(da8xx_fb_reg_base))
1351 		return PTR_ERR(da8xx_fb_reg_base);
1352 
1353 	tmp_lcdc_clk = devm_clk_get(&device->dev, "fck");
1354 	if (IS_ERR(tmp_lcdc_clk))
1355 		return dev_err_probe(&device->dev, PTR_ERR(tmp_lcdc_clk),
1356 				     "Can not get device clock\n");
1357 
1358 	pm_runtime_enable(&device->dev);
1359 	pm_runtime_get_sync(&device->dev);
1360 
1361 	/* Determine LCD IP Version */
1362 	switch (lcdc_read(LCD_PID_REG)) {
1363 	case 0x4C100102:
1364 		lcd_revision = LCD_VERSION_1;
1365 		break;
1366 	case 0x4F200800:
1367 	case 0x4F201000:
1368 		lcd_revision = LCD_VERSION_2;
1369 		break;
1370 	default:
1371 		dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1372 				"defaulting to LCD revision 1\n",
1373 				lcdc_read(LCD_PID_REG));
1374 		lcd_revision = LCD_VERSION_1;
1375 		break;
1376 	}
1377 
1378 	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1379 
1380 	if (!lcd_cfg) {
1381 		ret = -EINVAL;
1382 		goto err_pm_runtime_disable;
1383 	}
1384 
1385 	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1386 					&device->dev);
1387 	if (!da8xx_fb_info) {
1388 		ret = -ENOMEM;
1389 		goto err_pm_runtime_disable;
1390 	}
1391 
1392 	par = da8xx_fb_info->par;
1393 	par->dev = &device->dev;
1394 	par->lcdc_clk = tmp_lcdc_clk;
1395 	par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1396 
1397 	par->lcd_supply = devm_regulator_get_optional(&device->dev, "lcd");
1398 	if (IS_ERR(par->lcd_supply)) {
1399 		if (PTR_ERR(par->lcd_supply) == -EPROBE_DEFER) {
1400 			ret = -EPROBE_DEFER;
1401 			goto err_release_fb;
1402 		}
1403 
1404 		par->lcd_supply = NULL;
1405 	} else {
1406 		ret = regulator_enable(par->lcd_supply);
1407 		if (ret)
1408 			goto err_release_fb;
1409 	}
1410 
1411 	fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
1412 	par->cfg = *lcd_cfg;
1413 
1414 	da8xx_fb_lcd_reset();
1415 
1416 	/* allocate frame buffer */
1417 	par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1418 	ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
1419 	par->vram_size = roundup(par->vram_size/8, ulcm);
1420 	par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1421 
1422 	par->vram_virt = dmam_alloc_coherent(par->dev,
1423 					     par->vram_size,
1424 					     &par->vram_phys,
1425 					     GFP_KERNEL | GFP_DMA);
1426 	if (!par->vram_virt) {
1427 		dev_err(&device->dev,
1428 			"GLCD: kmalloc for frame buffer failed\n");
1429 		ret = -EINVAL;
1430 		goto err_disable_reg;
1431 	}
1432 
1433 	da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1434 	da8xx_fb_fix.smem_start    = par->vram_phys;
1435 	da8xx_fb_fix.smem_len      = par->vram_size;
1436 	da8xx_fb_fix.line_length   = (lcdc_info->xres * lcd_cfg->bpp) / 8;
1437 
1438 	par->dma_start = par->vram_phys;
1439 	par->dma_end   = par->dma_start + lcdc_info->yres *
1440 		da8xx_fb_fix.line_length - 1;
1441 
1442 	/* allocate palette buffer */
1443 	par->v_palette_base = dmam_alloc_coherent(par->dev, PALETTE_SIZE,
1444 						  &par->p_palette_base,
1445 						  GFP_KERNEL | GFP_DMA);
1446 	if (!par->v_palette_base) {
1447 		dev_err(&device->dev,
1448 			"GLCD: kmalloc for palette buffer failed\n");
1449 		ret = -EINVAL;
1450 		goto err_release_fb;
1451 	}
1452 
1453 	par->irq = platform_get_irq(device, 0);
1454 	if (par->irq < 0) {
1455 		ret = -ENOENT;
1456 		goto err_release_fb;
1457 	}
1458 
1459 	da8xx_fb_var.grayscale =
1460 	    lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
1461 	da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1462 
1463 	/* Initialize fbinfo */
1464 	da8xx_fb_info->fix = da8xx_fb_fix;
1465 	da8xx_fb_info->var = da8xx_fb_var;
1466 	da8xx_fb_info->fbops = &da8xx_fb_ops;
1467 	da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1468 	da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1469 				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1470 
1471 	ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1472 	if (ret)
1473 		goto err_disable_reg;
1474 	da8xx_fb_info->cmap.len = par->palette_sz;
1475 
1476 	/* initialize var_screeninfo */
1477 	da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1478 	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1479 
1480 	platform_set_drvdata(device, da8xx_fb_info);
1481 
1482 	/* initialize the vsync wait queue */
1483 	init_waitqueue_head(&par->vsync_wait);
1484 	par->vsync_timeout = HZ / 5;
1485 	par->which_dma_channel_done = -1;
1486 	spin_lock_init(&par->lock_for_chan_update);
1487 
1488 	/* Register the Frame Buffer  */
1489 	if (register_framebuffer(da8xx_fb_info) < 0) {
1490 		dev_err(&device->dev,
1491 			"GLCD: Frame Buffer Registration Failed!\n");
1492 		ret = -EINVAL;
1493 		goto err_dealloc_cmap;
1494 	}
1495 
1496 #ifdef CONFIG_CPU_FREQ
1497 	ret = lcd_da8xx_cpufreq_register(par);
1498 	if (ret) {
1499 		dev_err(&device->dev, "failed to register cpufreq\n");
1500 		goto err_cpu_freq;
1501 	}
1502 #endif
1503 
1504 	if (lcd_revision == LCD_VERSION_1)
1505 		lcdc_irq_handler = lcdc_irq_handler_rev01;
1506 	else {
1507 		init_waitqueue_head(&frame_done_wq);
1508 		lcdc_irq_handler = lcdc_irq_handler_rev02;
1509 	}
1510 
1511 	ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
1512 			       DRIVER_NAME, par);
1513 	if (ret)
1514 		goto irq_freq;
1515 	return 0;
1516 
1517 irq_freq:
1518 #ifdef CONFIG_CPU_FREQ
1519 	lcd_da8xx_cpufreq_deregister(par);
1520 err_cpu_freq:
1521 #endif
1522 	unregister_framebuffer(da8xx_fb_info);
1523 
1524 err_dealloc_cmap:
1525 	fb_dealloc_cmap(&da8xx_fb_info->cmap);
1526 
1527 err_disable_reg:
1528 	if (par->lcd_supply)
1529 		regulator_disable(par->lcd_supply);
1530 err_release_fb:
1531 	framebuffer_release(da8xx_fb_info);
1532 
1533 err_pm_runtime_disable:
1534 	pm_runtime_put_sync(&device->dev);
1535 	pm_runtime_disable(&device->dev);
1536 
1537 	return ret;
1538 }
1539 
1540 #ifdef CONFIG_PM_SLEEP
1541 static struct lcdc_context {
1542 	u32 clk_enable;
1543 	u32 ctrl;
1544 	u32 dma_ctrl;
1545 	u32 raster_timing_0;
1546 	u32 raster_timing_1;
1547 	u32 raster_timing_2;
1548 	u32 int_enable_set;
1549 	u32 dma_frm_buf_base_addr_0;
1550 	u32 dma_frm_buf_ceiling_addr_0;
1551 	u32 dma_frm_buf_base_addr_1;
1552 	u32 dma_frm_buf_ceiling_addr_1;
1553 	u32 raster_ctrl;
1554 } reg_context;
1555 
lcd_context_save(void)1556 static void lcd_context_save(void)
1557 {
1558 	if (lcd_revision == LCD_VERSION_2) {
1559 		reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1560 		reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1561 	}
1562 
1563 	reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1564 	reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1565 	reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1566 	reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1567 	reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1568 	reg_context.dma_frm_buf_base_addr_0 =
1569 		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1570 	reg_context.dma_frm_buf_ceiling_addr_0 =
1571 		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1572 	reg_context.dma_frm_buf_base_addr_1 =
1573 		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1574 	reg_context.dma_frm_buf_ceiling_addr_1 =
1575 		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1576 	reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1577 	return;
1578 }
1579 
lcd_context_restore(void)1580 static void lcd_context_restore(void)
1581 {
1582 	if (lcd_revision == LCD_VERSION_2) {
1583 		lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1584 		lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1585 	}
1586 
1587 	lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1588 	lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1589 	lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1590 	lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1591 	lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1592 	lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1593 			LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1594 	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1595 			LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1596 	lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1597 			LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1598 	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1599 			LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1600 	lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1601 	return;
1602 }
1603 
fb_suspend(struct device * dev)1604 static int fb_suspend(struct device *dev)
1605 {
1606 	struct fb_info *info = dev_get_drvdata(dev);
1607 	struct da8xx_fb_par *par = info->par;
1608 	int ret;
1609 
1610 	console_lock();
1611 	if (par->lcd_supply) {
1612 		ret = regulator_disable(par->lcd_supply);
1613 		if (ret)
1614 			return ret;
1615 	}
1616 
1617 	fb_set_suspend(info, 1);
1618 	lcd_disable_raster(DA8XX_FRAME_WAIT);
1619 	lcd_context_save();
1620 	pm_runtime_put_sync(dev);
1621 	console_unlock();
1622 
1623 	return 0;
1624 }
fb_resume(struct device * dev)1625 static int fb_resume(struct device *dev)
1626 {
1627 	struct fb_info *info = dev_get_drvdata(dev);
1628 	struct da8xx_fb_par *par = info->par;
1629 	int ret;
1630 
1631 	console_lock();
1632 	pm_runtime_get_sync(dev);
1633 	lcd_context_restore();
1634 	if (par->blank == FB_BLANK_UNBLANK) {
1635 		lcd_enable_raster();
1636 
1637 		if (par->lcd_supply) {
1638 			ret = regulator_enable(par->lcd_supply);
1639 			if (ret)
1640 				return ret;
1641 		}
1642 	}
1643 
1644 	fb_set_suspend(info, 0);
1645 	console_unlock();
1646 
1647 	return 0;
1648 }
1649 #endif
1650 
1651 static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume);
1652 
1653 static struct platform_driver da8xx_fb_driver = {
1654 	.probe = fb_probe,
1655 	.remove_new = fb_remove,
1656 	.driver = {
1657 		   .name = DRIVER_NAME,
1658 		   .pm	= &fb_pm_ops,
1659 		   },
1660 };
1661 module_platform_driver(da8xx_fb_driver);
1662 
1663 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1664 MODULE_AUTHOR("Texas Instruments");
1665 MODULE_LICENSE("GPL");
1666