1 /*
2 * qemu user cpu loop
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu.h"
22 #include "user-internals.h"
23 #include "elf.h"
24 #include "cpu_loop-common.h"
25 #include "signal-common.h"
26 #include "semihosting/common-semi.h"
27 #include "exec/page-protection.h"
28 #include "target/arm/syndrome.h"
29
30 #define get_user_code_u32(x, gaddr, env) \
31 ({ abi_long __r = get_user_u32((x), (gaddr)); \
32 if (!__r && bswap_code(arm_sctlr_b(env))) { \
33 (x) = bswap32(x); \
34 } \
35 __r; \
36 })
37
38 #define get_user_code_u16(x, gaddr, env) \
39 ({ abi_long __r = get_user_u16((x), (gaddr)); \
40 if (!__r && bswap_code(arm_sctlr_b(env))) { \
41 (x) = bswap16(x); \
42 } \
43 __r; \
44 })
45
46 #define get_user_data_u32(x, gaddr, env) \
47 ({ abi_long __r = get_user_u32((x), (gaddr)); \
48 if (!__r && arm_cpu_bswap_data(env)) { \
49 (x) = bswap32(x); \
50 } \
51 __r; \
52 })
53
54 #define get_user_data_u16(x, gaddr, env) \
55 ({ abi_long __r = get_user_u16((x), (gaddr)); \
56 if (!__r && arm_cpu_bswap_data(env)) { \
57 (x) = bswap16(x); \
58 } \
59 __r; \
60 })
61
62 #define put_user_data_u32(x, gaddr, env) \
63 ({ typeof(x) __x = (x); \
64 if (arm_cpu_bswap_data(env)) { \
65 __x = bswap32(__x); \
66 } \
67 put_user_u32(__x, (gaddr)); \
68 })
69
70 #define put_user_data_u16(x, gaddr, env) \
71 ({ typeof(x) __x = (x); \
72 if (arm_cpu_bswap_data(env)) { \
73 __x = bswap16(__x); \
74 } \
75 put_user_u16(__x, (gaddr)); \
76 })
77
78 /*
79 * Similar to code in accel/tcg/user-exec.c, but outside the execution loop.
80 * Must be called with mmap_lock.
81 * We get the PC of the entry address - which is as good as anything,
82 * on a real kernel what you get depends on which mode it uses.
83 */
atomic_mmu_lookup(CPUArchState * env,uint32_t addr,int size)84 static void *atomic_mmu_lookup(CPUArchState *env, uint32_t addr, int size)
85 {
86 int need_flags = PAGE_READ | PAGE_WRITE_ORG | PAGE_VALID;
87 int page_flags;
88
89 /* Enforce guest required alignment. */
90 if (unlikely(addr & (size - 1))) {
91 force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr);
92 return NULL;
93 }
94
95 page_flags = page_get_flags(addr);
96 if (unlikely((page_flags & need_flags) != need_flags)) {
97 force_sig_fault(TARGET_SIGSEGV,
98 page_flags & PAGE_VALID ?
99 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
100 return NULL;
101 }
102
103 return g2h(env_cpu(env), addr);
104 }
105
106 /*
107 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
108 * Input:
109 * r0 = oldval
110 * r1 = newval
111 * r2 = pointer to target value
112 *
113 * Output:
114 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
115 * C set if *ptr was changed, clear if no exchange happened
116 */
arm_kernel_cmpxchg32_helper(CPUARMState * env)117 static void arm_kernel_cmpxchg32_helper(CPUARMState *env)
118 {
119 uint32_t oldval, newval, val, addr, cpsr, *host_addr;
120
121 /* Swap if host != guest endianness, for the host cmpxchg below */
122 oldval = tswap32(env->regs[0]);
123 newval = tswap32(env->regs[1]);
124 addr = env->regs[2];
125
126 mmap_lock();
127 host_addr = atomic_mmu_lookup(env, addr, 4);
128 if (!host_addr) {
129 mmap_unlock();
130 return;
131 }
132
133 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
134 mmap_unlock();
135
136 cpsr = (val == oldval) * CPSR_C;
137 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
138 env->regs[0] = cpsr ? 0 : -1;
139 }
140
141 /*
142 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
143 * Input:
144 * r0 = pointer to oldval
145 * r1 = pointer to newval
146 * r2 = pointer to target value
147 *
148 * Output:
149 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
150 * C set if *ptr was changed, clear if no exchange happened
151 *
152 * Note segv's in kernel helpers are a bit tricky, we can set the
153 * data address sensibly but the PC address is just the entry point.
154 */
arm_kernel_cmpxchg64_helper(CPUARMState * env)155 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
156 {
157 uint64_t oldval, newval, val;
158 uint32_t addr, cpsr;
159 uint64_t *host_addr;
160
161 addr = env->regs[0];
162 if (get_user_u64(oldval, addr)) {
163 goto segv;
164 }
165
166 addr = env->regs[1];
167 if (get_user_u64(newval, addr)) {
168 goto segv;
169 }
170
171 mmap_lock();
172 addr = env->regs[2];
173 host_addr = atomic_mmu_lookup(env, addr, 8);
174 if (!host_addr) {
175 mmap_unlock();
176 return;
177 }
178
179 /* Swap if host != guest endianness, for the host cmpxchg below */
180 oldval = tswap64(oldval);
181 newval = tswap64(newval);
182
183 #ifdef CONFIG_ATOMIC64
184 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
185 cpsr = (val == oldval) * CPSR_C;
186 #else
187 /*
188 * This only works between threads, not between processes, but since
189 * the host has no 64-bit cmpxchg, it is the best that we can do.
190 */
191 start_exclusive();
192 val = *host_addr;
193 if (val == oldval) {
194 *host_addr = newval;
195 cpsr = CPSR_C;
196 } else {
197 cpsr = 0;
198 }
199 end_exclusive();
200 #endif
201 mmap_unlock();
202
203 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
204 env->regs[0] = cpsr ? 0 : -1;
205 return;
206
207 segv:
208 force_sig_fault(TARGET_SIGSEGV,
209 page_get_flags(addr) & PAGE_VALID ?
210 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
211 }
212
213 /* Handle a jump to the kernel code page. */
214 static int
do_kernel_trap(CPUARMState * env)215 do_kernel_trap(CPUARMState *env)
216 {
217 uint32_t addr;
218
219 switch (env->regs[15]) {
220 case 0xffff0fa0: /* __kernel_memory_barrier */
221 smp_mb();
222 break;
223 case 0xffff0fc0: /* __kernel_cmpxchg */
224 arm_kernel_cmpxchg32_helper(env);
225 break;
226 case 0xffff0fe0: /* __kernel_get_tls */
227 env->regs[0] = cpu_get_tls(env);
228 break;
229 case 0xffff0f60: /* __kernel_cmpxchg64 */
230 arm_kernel_cmpxchg64_helper(env);
231 break;
232
233 default:
234 return 1;
235 }
236 /* Jump back to the caller. */
237 addr = env->regs[14];
238 if (addr & 1) {
239 env->thumb = true;
240 addr &= ~1;
241 }
242 env->regs[15] = addr;
243
244 return 0;
245 }
246
insn_is_linux_bkpt(uint32_t opcode,bool is_thumb)247 static bool insn_is_linux_bkpt(uint32_t opcode, bool is_thumb)
248 {
249 /*
250 * Return true if this insn is one of the three magic UDF insns
251 * which the kernel treats as breakpoint insns.
252 */
253 if (!is_thumb) {
254 return (opcode & 0x0fffffff) == 0x07f001f0;
255 } else {
256 /*
257 * Note that we get the two halves of the 32-bit T32 insn
258 * in the opposite order to the value the kernel uses in
259 * its undef_hook struct.
260 */
261 return ((opcode & 0xffff) == 0xde01) || (opcode == 0xa000f7f0);
262 }
263 }
264
emulate_arm_fpa11(CPUARMState * env,uint32_t opcode)265 static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode)
266 {
267 TaskState *ts = get_task_state(env_cpu(env));
268 int rc = EmulateAll(opcode, &ts->fpa, env);
269 int raise, enabled;
270
271 if (rc == 0) {
272 /* Illegal instruction */
273 return false;
274 }
275 if (rc > 0) {
276 /* Everything ok. */
277 env->regs[15] += 4;
278 return true;
279 }
280
281 /* FP exception */
282 rc = -rc;
283 raise = 0;
284
285 /* Translate softfloat flags to FPSR flags */
286 if (rc & float_flag_invalid) {
287 raise |= BIT_IOC;
288 }
289 if (rc & float_flag_divbyzero) {
290 raise |= BIT_DZC;
291 }
292 if (rc & float_flag_overflow) {
293 raise |= BIT_OFC;
294 }
295 if (rc & float_flag_underflow) {
296 raise |= BIT_UFC;
297 }
298 if (rc & float_flag_inexact) {
299 raise |= BIT_IXC;
300 }
301
302 /* Accumulate unenabled exceptions */
303 enabled = ts->fpa.fpsr >> 16;
304 ts->fpa.fpsr |= raise & ~enabled;
305
306 if (raise & enabled) {
307 /*
308 * The kernel's nwfpe emulator does not pass a real si_code.
309 * It merely uses send_sig(SIGFPE, current, 1), which results in
310 * __send_signal() filling out SI_KERNEL with pid and uid 0 (under
311 * the "SEND_SIG_PRIV" case). That's what our force_sig() does.
312 */
313 force_sig(TARGET_SIGFPE);
314 } else {
315 env->regs[15] += 4;
316 }
317 return true;
318 }
319
cpu_loop(CPUARMState * env)320 void cpu_loop(CPUARMState *env)
321 {
322 CPUState *cs = env_cpu(env);
323 int trapnr, si_signo, si_code;
324 unsigned int n, insn;
325 abi_ulong ret;
326
327 for(;;) {
328 cpu_exec_start(cs);
329 trapnr = cpu_exec(cs);
330 cpu_exec_end(cs);
331 process_queued_cpu_work(cs);
332
333 switch(trapnr) {
334 case EXCP_UDEF:
335 case EXCP_NOCP:
336 case EXCP_INVSTATE:
337 {
338 uint32_t opcode;
339
340 /* we handle the FPU emulation here, as Linux */
341 /* we get the opcode */
342 /* FIXME - what to do if get_user() fails? */
343 get_user_code_u32(opcode, env->regs[15], env);
344
345 /*
346 * The Linux kernel treats some UDF patterns specially
347 * to use as breakpoints (instead of the architectural
348 * bkpt insn). These should trigger a SIGTRAP rather
349 * than SIGILL.
350 */
351 if (insn_is_linux_bkpt(opcode, env->thumb)) {
352 goto excp_debug;
353 }
354
355 if (!env->thumb && emulate_arm_fpa11(env, opcode)) {
356 break;
357 }
358
359 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN,
360 env->regs[15]);
361 }
362 break;
363 case EXCP_SWI:
364 {
365 env->eabi = true;
366 /* system call */
367 if (env->thumb) {
368 /* Thumb is always EABI style with syscall number in r7 */
369 n = env->regs[7];
370 } else {
371 /*
372 * Equivalent of kernel CONFIG_OABI_COMPAT: read the
373 * Arm SVC insn to extract the immediate, which is the
374 * syscall number in OABI.
375 */
376 /* FIXME - what to do if get_user() fails? */
377 get_user_code_u32(insn, env->regs[15] - 4, env);
378 n = insn & 0xffffff;
379 if (n == 0) {
380 /* zero immediate: EABI, syscall number in r7 */
381 n = env->regs[7];
382 } else {
383 /*
384 * This XOR matches the kernel code: an immediate
385 * in the valid range (0x900000 .. 0x9fffff) is
386 * converted into the correct EABI-style syscall
387 * number; invalid immediates end up as values
388 * > 0xfffff and are handled below as out-of-range.
389 */
390 n ^= ARM_SYSCALL_BASE;
391 env->eabi = false;
392 }
393 }
394
395 if (n > ARM_NR_BASE) {
396 switch (n) {
397 case ARM_NR_cacheflush:
398 /* nop */
399 break;
400 case ARM_NR_set_tls:
401 cpu_set_tls(env, env->regs[0]);
402 env->regs[0] = 0;
403 break;
404 case ARM_NR_breakpoint:
405 env->regs[15] -= env->thumb ? 2 : 4;
406 goto excp_debug;
407 case ARM_NR_get_tls:
408 env->regs[0] = cpu_get_tls(env);
409 break;
410 default:
411 if (n < 0xf0800) {
412 /*
413 * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
414 * 0x9f07ff in OABI numbering) are defined
415 * to return -ENOSYS rather than raising
416 * SIGILL. Note that we have already
417 * removed the 0x900000 prefix.
418 */
419 qemu_log_mask(LOG_UNIMP,
420 "qemu: Unsupported ARM syscall: 0x%x\n",
421 n);
422 env->regs[0] = -TARGET_ENOSYS;
423 } else {
424 /*
425 * Otherwise SIGILL. This includes any SWI with
426 * immediate not originally 0x9fxxxx, because
427 * of the earlier XOR.
428 * Like the real kernel, we report the addr of the
429 * SWI in the siginfo si_addr but leave the PC
430 * pointing at the insn after the SWI.
431 */
432 abi_ulong faultaddr = env->regs[15];
433 faultaddr -= env->thumb ? 2 : 4;
434 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP,
435 faultaddr);
436 }
437 break;
438 }
439 } else {
440 ret = do_syscall(env,
441 n,
442 env->regs[0],
443 env->regs[1],
444 env->regs[2],
445 env->regs[3],
446 env->regs[4],
447 env->regs[5],
448 0, 0);
449 if (ret == -QEMU_ERESTARTSYS) {
450 env->regs[15] -= env->thumb ? 2 : 4;
451 } else if (ret != -QEMU_ESIGRETURN) {
452 env->regs[0] = ret;
453 }
454 }
455 }
456 break;
457 case EXCP_SEMIHOST:
458 do_common_semihosting(cs);
459 env->regs[15] += env->thumb ? 2 : 4;
460 break;
461 case EXCP_INTERRUPT:
462 /* just indicate that signals should be handled asap */
463 break;
464 case EXCP_PREFETCH_ABORT:
465 case EXCP_DATA_ABORT:
466 /* For user-only we don't set TTBCR_EAE, so look at the FSR. */
467 switch (env->exception.fsr & 0x1f) {
468 case 0x1: /* Alignment */
469 si_signo = TARGET_SIGBUS;
470 si_code = TARGET_BUS_ADRALN;
471 break;
472 case 0x3: /* Access flag fault, level 1 */
473 case 0x6: /* Access flag fault, level 2 */
474 case 0x9: /* Domain fault, level 1 */
475 case 0xb: /* Domain fault, level 2 */
476 case 0xd: /* Permission fault, level 1 */
477 case 0xf: /* Permission fault, level 2 */
478 si_signo = TARGET_SIGSEGV;
479 si_code = TARGET_SEGV_ACCERR;
480 break;
481 case 0x5: /* Translation fault, level 1 */
482 case 0x7: /* Translation fault, level 2 */
483 si_signo = TARGET_SIGSEGV;
484 si_code = TARGET_SEGV_MAPERR;
485 break;
486 default:
487 g_assert_not_reached();
488 }
489 force_sig_fault(si_signo, si_code, env->exception.vaddress);
490 break;
491 case EXCP_DEBUG:
492 case EXCP_BKPT:
493 excp_debug:
494 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[15]);
495 break;
496 case EXCP_KERNEL_TRAP:
497 if (do_kernel_trap(env))
498 goto error;
499 break;
500 case EXCP_YIELD:
501 /* nothing to do here for user-mode, just resume guest code */
502 break;
503 case EXCP_ATOMIC:
504 cpu_exec_step_atomic(cs);
505 break;
506 default:
507 error:
508 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
509 abort();
510 }
511 process_pending_signals(env);
512 }
513 }
514
target_cpu_copy_regs(CPUArchState * env,struct target_pt_regs * regs)515 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
516 {
517 CPUState *cpu = env_cpu(env);
518 TaskState *ts = get_task_state(cpu);
519 struct image_info *info = ts->info;
520 int i;
521
522 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
523 CPSRWriteByInstr);
524 for(i = 0; i < 16; i++) {
525 env->regs[i] = regs->uregs[i];
526 }
527 #if TARGET_BIG_ENDIAN
528 /* Enable BE8. */
529 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
530 && (info->elf_flags & EF_ARM_BE8)) {
531 env->uncached_cpsr |= CPSR_E;
532 env->cp15.sctlr_el[1] |= SCTLR_E0E;
533 } else {
534 env->cp15.sctlr_el[1] |= SCTLR_B;
535 }
536 arm_rebuild_hflags(env);
537 #endif
538
539 ts->stack_base = info->start_stack;
540 ts->heap_base = info->brk;
541 /* This will be filled in on the first SYS_HEAPINFO call. */
542 ts->heap_limit = 0;
543 }
544